WO2019109284A1 - 调试器以及芯片调试方法 - Google Patents

调试器以及芯片调试方法 Download PDF

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Publication number
WO2019109284A1
WO2019109284A1 PCT/CN2017/114925 CN2017114925W WO2019109284A1 WO 2019109284 A1 WO2019109284 A1 WO 2019109284A1 CN 2017114925 W CN2017114925 W CN 2017114925W WO 2019109284 A1 WO2019109284 A1 WO 2019109284A1
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Prior art keywords
test
peripheral interface
chip
test item
debugger
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PCT/CN2017/114925
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English (en)
French (fr)
Inventor
冯守川
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201780002028.0A priority Critical patent/CN110249316A/zh
Priority to PCT/CN2017/114925 priority patent/WO2019109284A1/zh
Publication of WO2019109284A1 publication Critical patent/WO2019109284A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Definitions

  • the present application relates to the field of testing technologies, and in particular, to a debugger and a chip debugging method.
  • the debugger is connected to the host computer through a Universal Serial Bus (USB) interface, and communicates with the chip through the debug interface, and the host computer passes the debugger. Test the chip.
  • USB Universal Serial Bus
  • the inventor has found that at least the following problems exist in the prior art: when the existing debugger tests the chip, some test items need external peripherals to complete, and during the test, the tester needs to manually replace the corresponding peripheral; even, Some test items require the cooperation of testers, and the test efficiency is low; for example, when verifying the fingerprint algorithm, after the tester manually connects the fingerprint acquisition device (peripheral), in order to simulate the real scene, the tester needs to pass the fingerprint collection device. Various techniques continue to press the fingerprint. In addition, when the chip is a peripheral controller, when testing it, it is necessary to purchase peripherals of various characteristics to verify whether the chip is perfectly supported and costly.
  • a part of the embodiments of the present application is to provide a debugger, in the process of testing a chip, It can simulate different peripherals to transmit test data to the tested chip without the manual operation of the tester, which improves the test efficiency. At the same time, the peripheral-related test can be completed without purchasing peripherals, which reduces the test cost.
  • the embodiment of the present application provides a debugger for debugging a chip under test under the control of a host computer
  • the debugger includes at least one emulation peripheral interface;
  • the emulation peripheral interface is connected to the microprocessor of the debugger, and
  • the emulation peripheral interface is configured to have a function of supporting a test item for testing;
  • the microprocessor tests the test item through the emulation peripheral interface during the test item test process The corresponding test data is transmitted to the chip under test.
  • the embodiment of the present application further provides a chip debugging method, which is applied to a host computer that debugs a chip under test by a debugger; the debugger includes at least one emulation peripheral interface, and the emulation peripheral interface is used for at least one of the tested chips.
  • a peripheral interface is connected; the method comprises: configuring the emulation peripheral interface to have a function of supporting a test item for testing; and transmitting the test data corresponding to the test item to the tested by the emulation peripheral interface during the test item test process; chip.
  • the embodiment of the present application simulates different peripherals to transmit test data to the tested chip through the simulation peripheral interface during the test of the chip, without the manual operation of the tester, thereby improving the test efficiency; By eliminating the need to purchase peripherals, peripheral-related tests can be completed, reducing test costs.
  • the debugger further includes a memory connected to the microprocessor; the memory is configured to pre-store the test data corresponding to the test item; and the microprocessor corresponds the test item in the memory during the test of the test item.
  • the test data is transmitted to the chip under test. A specific transmission mode of one type of test data is provided in this embodiment.
  • the microprocessor will receive from the host computer during the test of the test item.
  • the test data corresponding to the test item is transmitted to the chip under test.
  • This embodiment provides another specific transmission method of test data.
  • the emulation peripheral interface is configured to have one or any combination of the following functions: serial peripheral interface SPI function, serial communication bus I2C function, general-purpose input/output GPIO function, pulse width modulation PWM function.
  • serial peripheral interface SPI function serial peripheral interface SPI function
  • serial communication bus I2C function serial communication bus I2C function
  • general-purpose input/output GPIO function pulse width modulation PWM function.
  • test items belong to peripheral controller tests or algorithm tests. This embodiment provides a specific type of test item.
  • the test item belongs to the algorithm test, and the test item is a fingerprint algorithm test.
  • the emulation peripheral interface is configured to have the following functions: SPI slave device function and GPIO function. This embodiment provides a specific configuration of the emulation peripheral interface when testing the fingerprint algorithm.
  • the method before configuring the emulation peripheral interface to have a function of supporting a test item for testing, the method further includes: detecting whether the test item starts testing; if detecting the test item to start testing, entering the emulating peripheral interface Configured to have the ability to support a test item for testing.
  • the test is started to test whether the test item starts to perform automatic continuous test of multiple test items.
  • the method further includes: receiving the feedback data obtained by the debugger from the tested chip, and obtaining the test result corresponding to the test item according to the feedback data.
  • the feedback data is data generated by the tested chip during the test of the test item.
  • the debugger sends the feedback data to the upper computer, so that the upper computer analyzes the feedback data to obtain a test result.
  • FIG. 1 is a block schematic diagram of a debugger in accordance with a first embodiment of the present application
  • FIG. 2 is a block schematic diagram of a debugger in a second embodiment of the present application.
  • FIG. 3 is a specific flowchart of a chip debugging method according to a third embodiment of the present application.
  • FIG. 4 is a specific flowchart of a chip debugging method according to a fourth embodiment of the present application.
  • the first embodiment of the present application relates to a debugger.
  • the debugger is configured to debug a chip under test under the control of a host computer, and the debugger includes at least one emulated peripheral interface;
  • the emulation peripheral interface is connected to a microprocessor of the debugger, and configured to be connected to at least one peripheral interface of the tested chip, the emulation peripheral interface is configured to have a function of supporting a test item for testing; during the testing of the test item by the microprocessor, The test data corresponding to the test item is transmitted to the chip under test through the emulation peripheral interface.
  • the simulation peripheral interface simulates different peripherals to transmit test data to the tested chip without manual operation by the tester, thereby improving the test efficiency; Reduces test costs by eliminating peripheral-related tests without the need to purchase peripherals.
  • the implementation details of the debugger of this embodiment are specifically described below. The following content is only It is not necessary to implement this solution to facilitate the understanding of the implementation details provided.
  • the debugger 10 includes a microprocessor 1 and at least one emulated peripheral interface 2 (one in the figure is taken as an example, but not limited thereto).
  • the debugger 10 further includes a communication interface 3 (for example, a USB interface) and a debug interface 4 (the one in FIG. 1 is taken as an example, but not limited thereto), and the microprocessor 1 is respectively connected to the communication interface 3 and the debug interface. 4.
  • the debug interface 4 is connected to the debug interface 6 of the chip under test 5, the communication interface 3 is connected to the host computer 7, and the host computer 7 controls the debugger 10 to debug the chip under test 5 through the debug interface 4.
  • the debug interface 4 can be a standard JTAG (Joint Test Action Group) interface, a standard SWD (serial debug) interface, and the like.
  • the tested chip 5 is mounted on a circuit board, and the circuit board is provided with a plurality of interfaces connected to the tested chip 5, and a plurality of interfaces are connected with the tested chip 5 through a trace on the circuit board; the plurality of interfaces include at least The debug interface 6 of the tested chip 5 and the at least one peripheral interface 8 (the one in the figure is taken as an example, but not limited thereto).
  • the emulation peripheral interface 2 is connected to the microprocessor 1 and is connected to the peripheral interface 8 of the chip under test 5, and the emulated peripheral interface 2 is configured to have a function of supporting the test item for testing.
  • the host computer 7 controls the debugger 10 to debug the chip under test 5, and when the test chip 5 performs a test item (test item involving the peripheral device), the external peripheral device is required for the test, and the peripheral device interface 2 is simulated.
  • the function configured to support the test item for testing that is, the debugger 10 simulates the required peripheral to transmit the test data corresponding to the test item to the chip under test 5 through the emulation peripheral interface 2.
  • the configuration of the emulation peripheral interface 2 may be: pre-stored at least one test item corresponding firmware in the host computer 7, and the test chip 5 burns the firmware from the host computer 7 when performing the test of the test item. Configure the emulation peripheral interface 2. In addition, when the test chip 5 performs the test of the test item, the host computer 7 also configures the peripheral interface 8 of the tested chip 5 through the debugger 10, so that the peripheral interface 8 has a corresponding test function.
  • the test data corresponding to the test item is stored in the host computer 7, and the debugger 10 Communicating with the host computer 7 through the communication interface 3, during the test of the test item, that is, when the test chip 5 performs the test of the test item, the host computer 7 sends the test data corresponding to the test item to the microprocessor 1.
  • the microprocessor 1 receives the test data corresponding to the test item from the host computer 7 through the communication interface 3, and transmits the test data to the device under test 5 through the emulation peripheral interface 2.
  • the emulation peripheral interface 2 can be understood to include N general-purpose input/output GPIO interfaces led out by the microprocessor 1, and test items tested according to the tested chip 5, at least part of the N GPIO interfaces.
  • the interface is configured to have one or any combination of the following: serial peripheral interface SPI function, serial communication bus I2C function, general purpose input/output GPIO function, pulse width modulation PWM function.
  • the size of N may be the maximum number of pins required for the peripheral interface 8 used by the plurality of test items of the tested chip 5.
  • the tested chip 5 has three peripheral interfaces 8 corresponding to three test items.
  • the number of pins of the three peripheral interfaces 8 is 3, 4, and 5, respectively, and the number of Ns may be 5 (may be greater than 5).
  • the N GPIO interfaces of the emulation peripheral interface 2 can lead to multiple interfaces, and the multiple interfaces are adapted to the plurality of peripheral interfaces 8 of the tested chip 5, so that the emulated peripheral interface 2 is connected to the tested chip 5
  • the plurality of peripheral interfaces 8 are used to test the plurality of test items.
  • the simulation peripheral interface 2 leads to multiple interfaces to be used in turn.
  • this embodiment does not impose any limitation on this, and can be set according to specific test requirements.
  • the debugger 10 can also obtain feedback data from the tested chip 5 through the debug interface 4, and upload the feedback data to the upper computer 7, so that the host computer 7 analyzes the feedback data to obtain a test result.
  • the feedback data is data generated by the tested chip 5 during the test of the test item.
  • the types of test items to be tested by the tested chip 5 can be classified according to specific test requirements.
  • the test items are divided into two categories, namely, algorithm test and peripheral controller test.
  • the algorithm test is, for example, a fingerprint algorithm test, an image algorithm test, etc.; a peripheral controller
  • the test is, for example, the verification of the SPI master controller.
  • the verification of the SPI master controller includes the following test items: test clock various duty cycles, testing various serial peripheral interface SPI modes, test standards (Standard), 2-bit (Dual) or 4-bit (Quad) serial peripheral interface SPI.
  • test standards Standard
  • 2-bit Two
  • 4-bit Quality of Serial peripheral interface SPI
  • the test item is a fingerprint algorithm test.
  • the specific test process is as follows: the microprocessor 1 debugs the chip under test 5 through the debug interface 4, and during the debugging process, when the test chip 5 performs the test of the fingerprint algorithm test item, Using the fingerprint algorithm to test the corresponding firmware to configure the emulation peripheral interface 2, that is, the firmware corresponding to the fingerprint algorithm test is burned into the debugger 10, and the emulation peripheral interface 2 is configured to have the SPI slave device function and the GPIO function, specifically Four GPIO interfaces are multiplexed into SPI slave interface (serial peripheral interface SPI function), one GPIO interface is used for analog interrupt (general-purpose input/output GPIO function), and peripheral interface 8 of the tested chip 5 is also available.
  • SPI slave interface serial peripheral interface SPI function
  • one GPIO interface is used for analog interrupt (general-purpose input/output GPIO function)
  • peripheral interface 8 of the tested chip 5 is also available.
  • the configuration is performed to have the function of receiving the fingerprint test data, and the host computer 7 transmits the fingerprint test data to the device under test 5 through the SPI from the device interface, and the fingerprint test data includes at least one fingerprint data of the test case, when the GPIO interface is detected.
  • the analog interrupt signal is output, the fingerprint data of the test example is transmitted from the device interface to the device under test 5 through the SPI, and the tested chip 5 performs the fingerprint data of the test example.
  • the microprocessor 1 acquires the verification result (ie, feedback data) of the fingerprint test data from the device under test 5 through the debug interface 4, and uploads the feedback data to the host computer 7 through the communication interface 3, so that the host computer 7 analyzes the verification result. , get the test results of the fingerprint algorithm test.
  • the verification result ie, feedback data
  • the microprocessor 1 acquires the verification result (ie, feedback data) of the fingerprint test data from the device under test 5 through the debug interface 4, and uploads the feedback data to the host computer 7 through the communication interface 3, so that the host computer 7 analyzes the verification result. , get the test results of the fingerprint algorithm test.
  • the test item is the SPI master device verification of the tested chip 5.
  • the specific test process is as follows: the microprocessor 1 debugs the chip under test 5 through the debug interface 4, and performs SPI master on the tested chip 5 during the debugging process. When verifying the device, use the SPI master device to verify the corresponding firmware pair emulation peripheral interface 2 For configuration, the emulation peripheral interface 2 is configured to have the SPI slave device function, and the host computer 7 configures the peripheral interface 8 of the chip under test 5 to have the SPI master device function, and the host computer 7 verifies the SPI master device.
  • the corresponding test data (the test data corresponding to the SPI master device verification may be referred to as SPI slave device data) is transmitted to the chip under test 5 through the emulation peripheral interface 2, and the chip under test 5 receives and stores the SPI slave device data to the device under test 5
  • the host computer 7 reads the SPI slave device data stored by the chip under test 5 from the memory 9 of the chip under test 5 through the debugger 10, and compares it with the local SPI slave device data to judge from the simulation. It is determined whether the interface 2 transmits the SPI slave device data to the tested chip 5 successfully. When the comparison result is the same, it is determined that the transmission of the SPI slave device data from the emulation peripheral interface 2 to the device under test 5 is successful; otherwise, the transmission of the SPI slave device is indicated. The data failed.
  • the host computer 7 can store test data corresponding to a plurality of test items and firmware.
  • each test item is tested in a preset order, and the simulation peripheral interface 2 follows the
  • the firmware is installed or burned in a preset order to be configured to have different functions, and the test data corresponding to the plurality of test items is sequentially transmitted to the chip under test 5 in the preset order.
  • the simulation peripheral interface simulates different peripherals to transmit test data to the tested chip without manual operation by the tester, thereby improving the test efficiency; Reduces test costs by eliminating peripheral-related tests without the need to purchase peripherals.
  • the second embodiment of the present application relates to a debugger.
  • This embodiment is a refinement of the first embodiment.
  • the main refinement is that, referring to FIG. 2, the debugger 10 further includes a memory 11.
  • the microprocessor 1 is connected to the memory 11, and the memory 11 is configured to pre-store test data corresponding to the test item; for example, the test item is a fingerprint algorithm test, and the fingerprint test data corresponding to the fingerprint algorithm test is pre-stored in the memory 11. .
  • Microprocessor 1 during the test of the test item ie, When the test chip 5 performs the test of the test item, the microprocessor 1 transmits the test data corresponding to the test item in the memory 11 to the test chip 5 through the emulation peripheral interface 2.
  • the test data corresponding to the plurality of test items may be pre-stored in the memory 9 of the debugger 10.
  • the test sequence of a plurality of test items is set in the host computer 7.
  • each test item is tested in a preset order, and the simulation peripheral interface 2 is configured differently according to the preset order.
  • the function of the test data corresponding to the plurality of test items is sequentially transmitted to the chip under test 5 in the preset order.
  • This embodiment provides another specific transmission method of test data with respect to the first embodiment.
  • the third embodiment of the present invention relates to a chip debugging method, which is applied to a host computer 7 for debugging a chip under test 5 by a debugger 10; wherein the debugger 10 is a debugger in the first embodiment or the second embodiment. 10.
  • FIG. 3 The specific process of the chip debugging method in this embodiment is shown in FIG. 3.
  • the debugger 10 is connected to the host computer 7 through a communication interface 3 connected to the microprocessor 1.
  • the host computer 7 controls the debugger 10 to debug the chip under test 5 through the debug interface 4.
  • the chip under test 5 is mounted on a circuit board, and the circuit board is provided with a plurality of interfaces connected to the chip under test 5 .
  • test data corresponding to the test item is stored in the host computer 7, but the test data corresponding to the test item may be stored in the memory 9 of the debugger 10.
  • the emulation peripheral interface is configured to have a function of supporting a test item for testing.
  • the host computer 7 can be specific according to the specific The test requirement configures the emulation peripheral interface 2 to have a function of supporting a test item for testing; at the same time, the host computer 7 also configures the peripheral interface 8 of the tested chip 5 through the debugger 10 to make the peripheral interface 8 has the corresponding test function. Specifically, the host computer 7 controls the debugger 10 to debug the chip under test 5, and the tested chip 5 needs external peripherals when testing a test item (test item involving peripherals). At this time, the host computer 7 The emulation peripheral interface 2 is configured to support the test item for testing.
  • the configuration of the emulation peripheral interface 2 may be: storing firmware corresponding to at least one test item in the host computer 7, and when the test chip 5 performs the test of the test item, the firmware is burned from the host computer 7 to Configure the emulation peripheral interface 2.
  • the emulation peripheral interface 2 can be understood to include N general-purpose input/output GPIO interfaces led out by the microprocessor 1, and test items tested according to the tested chip 5, at least part of the N GPIO interfaces.
  • the interface is configured to have one or any combination of the following: serial peripheral interface SPI function, serial communication bus I2C function, general purpose input/output GPIO function, pulse width modulation PWM function.
  • the size of N may be the maximum number of pins required for the peripheral interface 8 used by the plurality of test items of the tested chip 5.
  • the tested chip 5 has three peripheral interfaces 8 corresponding to three test items.
  • the number of pins of the three peripheral interfaces 8 is 3, 4, and 5, respectively, and the number of Ns may be 5 (may be greater than 5).
  • the N GPIO interfaces of the emulation peripheral interface 2 can lead to multiple interfaces, and the multiple interfaces are adapted to the plurality of peripheral interfaces 8 of the tested chip 5, so that the emulated peripheral interface 2 is connected to the tested chip 5
  • the plurality of peripheral interfaces 8 are used to test the plurality of test items.
  • the simulation peripheral interface 2 leads to multiple interfaces to be used in turn.
  • this embodiment does not impose any limitation on this, and can be set according to specific test requirements.
  • the test item as the fingerprint algorithm test as an example
  • the fingerprint algorithm is used to test the corresponding firmware to match the simulation peripheral interface 2
  • the firmware corresponding to the fingerprint algorithm test is programmed into the debugger 10.
  • the emulation peripheral interface 2 is configured to have the SPI slave function and the GPIO function, specifically, the four GPIO interfaces are multiplexed into the SPI slave interface (string Line peripheral interface SPI function), one GPIO interface is used for analog interrupt (general-purpose input/output GPIO function); at the same time, the peripheral interface 8 of the tested chip 5 is configured to have the function of receiving fingerprint test data.
  • Step 102 During the test of the test item, the test data corresponding to the test item is transmitted to the chip under test through the emulation peripheral interface.
  • the debugger 10 simulates the required peripheral to transmit the test data corresponding to the test item to the chip under test 5 through the configured emulation peripheral interface 2.
  • the host computer 7 transmits the fingerprint test data to the device under test 5 through the SPI slave device interface, and the fingerprint test data includes at least one test case fingerprint data.
  • the fingerprint data of the test instance is transmitted from the device interface to the tested chip 5 through the SPI, and the tested chip 5 performs fingerprint algorithm verification using the fingerprint data of the test example, and verifies The result is stored in the memory 9 on the chip under test 5; if the fingerprint test data includes fingerprint data of a plurality of test cases, the above process is repeated.
  • the debugger 10 simulates the required peripherals to transmit the test data corresponding to the test item to the tested chip 5 through the emulation peripheral interface 2, wherein the two transmission modes of the test data are as follows:
  • the test data corresponding to the test item is stored in the host computer 7, and the debugger 10 communicates with the host computer 7 through the communication interface 3, and the microprocessor 1 is in the test process of the test item, that is, When the test chip 5 performs the test of the test item, the microprocessor 1 receives the test data corresponding to the test item from the host computer 7 through the communication interface 7, and transmits the test data to the test chip 5.
  • the memory 11 is used to pre-store the number of tests corresponding to the test item.
  • the test item is a fingerprint algorithm test
  • the fingerprint test data corresponding to the fingerprint algorithm test is stored in the memory 11 .
  • the microprocessor 1 transmits the test data corresponding to the test item in the memory 11 to the measured device through the simulation peripheral interface 2 Chip 5.
  • Step 103 Receive feedback data obtained by the debugger from the tested chip, and obtain a test result corresponding to the test item according to the feedback data.
  • the debug interface 4 of the debugger 10 is communicatively coupled to the debug interface 6 on the chip under test 5, and the test item is a fingerprint algorithm test as an example.
  • the feedback data is that the microprocessor 1 passes the debug interface 4 from the chip under test 5 Obtaining the verification result of the fingerprint test data, the verification result data of the fingerprint test data is stored in the memory 9 of the tested chip 5, and therefore, the microprocessor 1 of the debugger 10 obtains the verification result from the memory 9 through the debug interface 4, and micro-processing
  • the device 1 obtains the verification result (ie, feedback data) of the fingerprint test data from the device under test 5 through the debug interface 4, and uploads the feedback data to the host computer 7 through the communication interface 3, and the host computer 7 analyzes the verification result to obtain a fingerprint algorithm. Test results of the test.
  • the test item belongs to the algorithm test
  • the algorithm test is a fingerprint algorithm test as an example.
  • the specific type of the test item is not limited in this embodiment.
  • the simulation peripheral interface simulates different peripherals to transmit test data to the tested chip without manual operation by the tester, thereby improving the test efficiency; Reduces test costs by eliminating peripheral-related tests without the need to purchase peripherals.
  • the fourth embodiment of the present application relates to a chip debugging method, which is substantially the same as the third embodiment, and the main difference is that in the third embodiment, one test item of the tested chip 5 is separately tested. In this embodiment, multiple test items of the tested chip 5 are continuously tested, and it is necessary to test whether the test item starts testing to identify the test item currently to be tested.
  • the present embodiment is applied to continuous testing of a plurality of test items of the chip under test 5, and the test program stored in the host computer 7 can sequentially perform testing of the plurality of test items on the tested chip 5, that is, implement multiple tests. Automatic testing of items.
  • the test data corresponding to the plurality of test items is stored in the host computer 7.
  • the test data corresponding to the plurality of test items may be stored in the memory 9 of the test chip 5 in the test data.
  • Steps 202 to 204 are substantially the same as steps 101 to 103, and are not described here.
  • the main difference is that in the embodiment, step 201 is added, as follows:
  • Step 201 Detect whether the test item starts testing.
  • the host computer 7 can detect the test item being tested by the tested chip 5 to determine the test data corresponding to the test item, and then proceeds to step 202 (same as step 101 in the third embodiment) to simulate the peripheral interface 2 It is configured to have the function of supporting a test item for testing, and then proceeds to step 203 (same as step 102 in the third embodiment).
  • step 202 (same as step 101 in the third embodiment) to simulate the peripheral interface 2 It is configured to have the function of supporting a test item for testing, and then proceeds to step 203 (same as step 102 in the third embodiment).
  • the test data corresponding to the test item is transmitted through the emulation peripheral interface 2. Go to the chip under test 5 to complete the test of the test item.
  • step 201 when the plurality of test items of the tested chip 5 are continuously tested, after the test of one test item is completed, the process returns to step 201 to re-detect whether the next test item starts the test until all the test items are tested.
  • This embodiment can realize automatic continuous testing of a plurality of test items with respect to the third embodiment.

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Abstract

一种调试器（10）以及芯片调试方法。调试器（10）包括至少一仿真外设接口（2）；仿真外设接口（2）连接于调试器（10）的微处理器（1），且用于与被测芯片（5）的至少一外设接口连接（8），仿真外设接口（2）被配置为具有支持一测试项进行测试的功能（101）；在测试项的测试过程中，通过仿真外设接口（2）将测试项对应的测试数据传输至被测芯片（5）（102）。该方法无需测试人员手动操作，提升了测试效率；无需购买外设便能完成与外设相关的测试，降低了测试成本。

Description

调试器以及芯片调试方法 技术领域
本申请涉及测试技术领域，特别涉及一种调试器以及芯片调试方法。
背景技术
在芯片的开发过程中，需要使用调试器进行相关测试，调试器通过通用串行总线(Universal Serial Bus,USB)接口与上位机连接，并通过调试接口与芯片进行通讯连接，上位机通过调试器对芯片进行测试。
发明人发现现有技术至少存在以下问题：现有的调试器在对芯片进行测试时，有些测试项目需要外接外设才能完成，在测试过程中，需要测试人员手动更换相应的外设；甚至，有些测试项目需要测试人员的配合，测试效率低；例如，在验证指纹算法时，测试人员手动连接指纹采集设备(外设)后，为了模拟真实的场景，还需要测试人员在指纹采集设备上通过各种手法不断按压指纹。另外，当芯片为外设控制器，在对其进行测试时，需要购买各种特性的外设来验证芯片是否都完美支持，成本较高。
发明内容
本申请部分实施例的目的在于提供一种调试器，在对芯片测试过程中， 能够模拟不同的外设向被测芯片传输测试数据，而无需测试人员手动操作，提升了测试效率；同时，由于无需购买外设便能完成与外设相关的测试，降低了测试成本。
本申请实施例提供了一种调试器，用于在上位机的控制下对被测芯片进行调试，调试器包括至少一仿真外设接口；仿真外设接口连接于调试器的微处理器，且用于与被测芯片的至少一外设接口连接，仿真外设接口被配置为具有支持一测试项进行测试的功能；微处理器在测试项的测试过程中，通过仿真外设接口将测试项对应的测试数据传输至被测芯片。
本申请实施例还提供了一种芯片调试方法，应用于通过调试器对被测芯片进行调试的上位机；调试器包括至少一仿真外设接口，仿真外设接口用于与被测芯片的至少一外设接口连接；方法包括：将仿真外设接口配置为具有支持一测试项进行测试的功能；在测试项的测试过程中，通过仿真外设接口将测试项对应的测试数据传输至被测芯片。
本申请实施例相对于现有技术而言，在对芯片测试过程中，通过仿真外设接口模拟不同的外设向被测芯片传输测试数据，而无需测试人员手动操作，提升了测试效率；同时，由于无需购买外设便能完成与外设相关的测试，降低了测试成本。
另外，在调试器中，调试器还包括连接于微处理器的存储器；存储器用于预先储存测试项对应的测试数据；微处理器在测试项的测试过程中，将存储器中的测试项对应的测试数据传输至被测芯片。本实施例中提供了测试数据的一种的具体传输方式。
另外，在调试器中，微处理器在测试项的测试过程中，将从上位机接收 的测试项对应的测试数据传输至被测芯片。本实施例提供了测试数据的另一种具体传输方式。
另外，在调试器中，仿真外设接口被配置为具有以下功能的其中之一或任意组合：串行外设接口SPI功能、串行通讯总线I2C功能、通用输入/输出GPIO功能、脉冲宽度调制PWM功能。本实施例提供了仿真外设接口的具体类型。
另外，测试项属于外设控制器测试或算法测试。本实施例提供了测试项的具体类型。
另外，在调试器中，测试项属于算法测试，且测试项为指纹算法测试，仿真外设接口被配置为具有以下功能：SPI从设备功能和GPIO功能。本实施例提供了对指纹算法进行测试时，仿真外设接口的具体配置情况。
另外，在芯片调试方法中，将仿真外设接口配置为具有支持一测试项进行测试的功能之前，还包括：检测测试项是否开始测试；若检测到测试项开始测试，进入将仿真外设接口配置为具有支持一测试项进行测试的功能的步骤。本实施例中，对测试项是否开始测试进行检测，以进行多个测试项的自动连续测试。
另外，在通过仿真外设接口将测试项对应的测试数据传输至被测芯片之后，方法还包括：接收调试器从被测芯片获取的反馈数据，并根据反馈数据得出测试项对应的测试结果；其中，反馈数据为被测芯片在测试项的测试过程中产生的数据。本实施例中，调试器将反馈数据发送到上位机，以便于上位机对反馈数据进行分析，得出测试结果。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据本申请第一实施例中的调试器的方框示意图；
图2是根据本申请第二实施例中的调试器的方框示意图；
图3是根据本申请第三实施例中的芯片调试方法的具体流程图；
图4是根据本申请第四实施例中的芯片调试方法的具体流程图。
具体实施例
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请的第一实施例涉及一种调试器，本实施例中，调试器用于在上位机的控制下对被测芯片进行调试，调试器包括至少一仿真外设接口；仿真外设接口连接于调试器的微处理器，且用于与被测芯片的至少一外设接口连接，仿真外设接口被配置为具有支持一测试项进行测试的功能；微处理器在测试项的测试过程中，通过仿真外设接口将测试项对应的测试数据传输至被测芯片。
本实施例相对于现有技术而言，在对芯片测试过程中，通过仿真外设接口模拟不同的外设向被测芯片传输测试数据，而无需测试人员手动操作，提升了测试效率；同时，由于无需购买外设便能完成与外设相关的测试，降低了测试成本。下面对本实施例的调试器的实现细节进行具体的说明，以下内容仅为 方便理解提供的实现细节，并非实施本方案的必须。
请参考图1，调试器10包括微处理器1以及至少一仿真外设接口2(图中以1个为例，然不以此为限)。另外，调试器10还包括通信接口3(例如为USB接口)与调试接口4(图1中以一个为例，然不以此为限)，微处理器1分别连接于通信接口3以及调试接口4，调试接口4与被测芯片5的调试接口6连接，通信接口3与上位机7连接，上位机7控制调试器10通过调试接口4对被测芯片5进行调试。其中，调试接口4可以为标准的JTAG(Joint Test Action Group，联合测试行动小组)接口、标准SWD(串行调试)接口等。其中，被测芯片5安装在电路板上，电路板上设有与被测芯片5连接的多种接口且多种接口与被测芯片5通过电路板上的走线连接；多种接口至少包括被测芯片5的调试接口6和至少一外设接口8(图中以1个为例，然不以此为限)。
仿真外设接口2连接于微处理器1，且连接于被测芯片5的外设接口8，仿真外设接口2被配置为具有支持该测试项进行测试的功能。具体来说，上位机7控制调试器10对被测芯片5进行调试，当被测芯片5进行某一测试项(涉及外设的测试项)的测试需要外接外设时，仿真外设接口2被配置为支持该测试项进行测试的功能，即，调试器10模拟所需外设通过仿真外设接口2向被测芯片5传输该测试项对应的测试数据。其中，仿真外设接口2的配置方式可以为：在上位机7中预先存储至少一测试项对应的固件，被测芯片5在进行该测试项的测试时，从上位机7烧录该固件，以对仿真外设接口2进行配置。另外，在被测芯片5进行测试项的测试时，上位机7也会通过调试器10对被测芯片5的外设接口8进行配置，以使外设接口8具有相应的测试功能。
在一个例子中，测试项对应的测试数据存储在上位机7中，调试器10 通过通信接口3与上位机7通讯，在测试项的测试过程中，即，被测芯片5进行该测试项的测试时，上位机7将该测试项对应的测试数据发送至微处理器1，微处理器1通过通讯接口3从上位机7中接收测试项对应的测试数据，并将该测试数据通过仿真外设接口2传输至被测芯片5。
本实施例中，仿真外设接口2可以理解为包括由微处理器1上引出的N个通用输入/输出GPIO接口，根据被测芯片5进行测试的测试项，N个GPIO接口中的至少部分接口被配置为具有以下功能的其中之一或任意组合：串行外设接口SPI功能、串行通讯总线I2C功能、通用输入/输出GPIO功能、脉冲宽度调制PWM功能。其中，N的大小可以为被测芯片5的多个测试项所用的外设接口8的所需的最大引脚数目，例如，被测芯片5存在三个测试项对应的三个外设接口8，三个外设接口8的引脚数目分别为3、4、5，则N的数目可以为5(也可以大于5)。另外，仿真外设接口2的N个GPIO接口，可以引出多个接口，多个接口适配于被测芯片5的多个外设接口8，以使仿真外设接口2连接至被测芯片5的多个外设接口8，在进行多个测试项的测试时，仿真外设接口2引出多个接口轮流使用，然本实施例对此不作任何限制，可以根据具体的测试需求来设定。
本实施例中，调试器10还可以通过调试接口4从被测芯片5获取反馈数据，并将反馈数据上传到上位机7，以供上位机7对反馈数据进行分析得到测试结果。其中，反馈数据为被测芯片5在测试项的测试过程中产生的数据。
本实施例中，被测芯片5进行测试的测试项的类别可以根据具体测试需求来进行分类，本实施例将测试项分为两类，分别为算法测试以及外设控制器测试。其中，算法测试中例如为指纹算法测试、图像算法测试等；外设控制器 测试例如为SPI主设备控制器的验证，SPI主设备控制器的验证中包含以下测试项：测试时钟各种占空比、测试各种串行外设接口SPI的模式、测试标准(Standard)、2比特(Dual)或4比特(Quad)串行外设接口SPI等。下面用具体的例子来进行介绍：
1、测试项为指纹算法测试，具体的测试过程如下：微处理器1通过调试接口4对被测芯片5进行调试，在调试过程中，在被测芯片5进行指纹算法测试项的测试时，利用指纹算法测试对应的固件对仿真外设接口2进行配置，即将指纹算法测试对应的固件烧录到调试器10中，仿真外设接口2被配置为具有SPI从设备功能和GPIO功能，具体为4个GPIO接口被复用为SPI从设备接口(串行外设接口SPI功能)，1个GPIO接口用于模拟中断(通用输入/输出GPIO功能)，同时对被测芯片5的外设接口8进行配置，使其具有接收指纹测试数据的功能，上位机7将指纹测试数据通过SPI从设备接口传输到被测芯片5，指纹测试数据中至少包括一个测试例的指纹数据，当检测到GPIO接口的模拟中断信号时，将该测试例的指纹数据通过SPI从设备接口传输到被测芯片5，被测芯片5利用该测试例的指纹数据进行指纹算法验证，并将验证结果存储在被测芯片5上的存储器9中；若指纹测试数据中包括多个测试例的指纹数据，则重复上述过程。微处理器1通过调试接口4从被测芯片5获取指纹测试数据的验证结果(即反馈数据)，并通过通信接口3将反馈数据上传至上位机7，以便于上位机7对验证结果进行分析，得到指纹算法测试的测试结果。
2、测试项为被测芯片5的SPI主设备验证，具体的测试过程如下：微处理器1通过调试接口4对被测芯片5进行调试，在调试过程中，在被测芯片5进行SPI主设备的验证时，利用SPI主设备验证对应的固件对仿真外设接口2 进行配置，仿真外设接口2被配置为具有SPI从设备功能，同时上位机7对被测芯片5的外设接口8进行配置，使其具有SPI主设备功能，上位机7将SPI主设备验证对应的测试数据(SPI主设备验证对应的测试数据可以称为SPI从设备数据)通过仿真外设接口2传输到被测芯片5，被测芯片5接收并存储SPI从设备数据到被测芯片5的存储器9中，上位机7通过调试器10从被测芯片5的存储器9中读取被测芯片5存储的SPI从设备数据，并与本地的SPI从设备数据进行对比，以判断从仿真外设接口2传输SPI从设备数据到被测芯片5是否成功，当对比结果为相同时，判定从仿真外设接口2传输SPI从设备数据到被测芯片5成功；否则，则说明传输SPI从设备数据失败。
需要说明的是，上位机7中可以存储有多个测试项对应的测试数据以及固件，在对被测芯片5进行测试时，各个测试项按照预设顺序进行测试，仿真外设接口2按照该预设顺序安装或者烧录固件从而被配置具有不同的功能，多个测试项对应的测试数据按照该预设顺序依次被传输至被测芯片5。
本实施例相对于现有技术而言，在对芯片测试过程中，通过仿真外设接口模拟不同的外设向被测芯片传输测试数据，而无需测试人员手动操作，提升了测试效率；同时，由于无需购买外设便能完成与外设相关的测试，降低了测试成本。
本申请第二实施例涉及一种调试器，本实施例是对第一实施例的细化，主要细化之处在于：请参考图2，调试器10还包括存储器11。
本实施例中，微处理器1连接于存储器11，存储器11用于预先储存测试项对应的测试数据；例如，测试项为指纹算法测试，则存储器11中预先存储指纹算法测试对应的指纹测试数据。微处理器1在测试项的测试过程中，即， 被测芯片5进行测试项的测试时，微处理器1将存储器11中的测试项对应的测试数据通过仿真外设接口2传输至被测芯片5。
需要说明的是，当上位机7需要对被测芯片进行多个测试项的连续测试时，调试器10的存储器9中可以预先存储有多个测试项对应的测试数据。上位机7中设定了多个测试项的测试顺序，在对被测芯片5进行调试过程中，各个测试项按照预设顺序进行测试，仿真外设接口2被按照该预设顺序配置具有不同的功能，多个测试项对应的测试数据按照该预设顺序依次被传输至被测芯片5。
本实施例相对于第一实施例而言，提供了另一种测试数据的具体传输方式。
本申请第三实施例涉及一种芯片调试方法，应用于通过调试器10对被测芯片5进行调试的上位机7；其中，调试器10为第一实施例或第二实施例中的调试器10。
本实施例中的芯片调试方法的具体流程如图3所示。其中，请参考图1和图2，调试器10通过与微处理器1连接的通信接口3与上位机7连接，上位机7控制调试器10通过调试接口4对被测芯片5进行调试。其中，被测芯片5安装在电路板上，电路板上设有与被测芯片5连接多种接口。
本实施例可以应用于被测芯片5的单个测试项的测试。此时，在上位机7中存储有该测试项对应的测试数据，然不限于此，也可以在调试器10的存储器9中存储有该测试项对应的测试数据。
步骤101，将仿真外设接口配置为具有支持一测试项进行测试的功能。
具体而言，在被测芯片5进行测试项的测试时，上位机7可以根据具体 的测试需求将仿真外设接口2配置为具有支持一测试项进行测试的功能；同时，上位机7也会通过调试器10对被测芯片5的外设接口8进行配置，以使外设接口8具有相应的测试功能。具体来说，上位机7控制调试器10对被测芯片5进行调试，被测芯片5进行某一测试项(涉及外设的测试项)的测试时需要外接外设，此时，上位机7将仿真外设接口2配置为支持该测试项进行测试的功能。其中，仿真外设接口2的配置方式可以为：在上位机7中存储至少一测试项对应的固件，被测芯片5在进行该测试项的测试时，从上位机7烧录该固件，以对仿真外设接口2进行配置。
本实施例中，仿真外设接口2可以理解为包括由微处理器1上引出的N个通用输入/输出GPIO接口，根据被测芯片5进行测试的测试项，N个GPIO接口中的至少部分接口被配置为具有以下功能的其中之一或任意组合：串行外设接口SPI功能、串行通讯总线I2C功能、通用输入/输出GPIO功能、脉冲宽度调制PWM功能。其中，N的大小可以为被测芯片5的多个测试项所用的外设接口8的所需的最大引脚数目，例如，被测芯片5存在三个测试项对应的三个外设接口8，三个外设接口8的引脚数目分别为3、4、5，则N的数目可以为5(也可以大于5)。另外，仿真外设接口2的N个GPIO接口，可以引出多个接口，多个接口适配于被测芯片5的多个外设接口8，以使仿真外设接口2连接至被测芯片5的多个外设接口8，在进行多个测试项的测试时，仿真外设接口2引出多个接口轮流使用，然本实施例对此不作任何限制，可以根据具体的测试需求来设定。
以测试项为指纹算法测试为例，在调试过程中，在被测芯片5进行指纹算法测试项的测试时，利用指纹算法测试对应的固件对仿真外设接口2进行配 置，即将指纹算法测试对应的固件烧录到调试器10中，仿真外设接口2被配置为具有SPI从设备功能和GPIO功能，具体为4个GPIO接口被复用为SPI从设备接口(串行外设接口SPI功能)，1个GPIO接口用于模拟中断(通用输入/输出GPIO功能)；同时对被测芯片5的外设接口8进行配置，使其具有接收指纹测试数据的功能。
步骤102，在测试项的测试过程中，通过仿真外设接口将测试项对应的测试数据传输至被测芯片。
具体而言，在测试项的测试过程中，调试器10模拟所需外设通过配置后的仿真外设接口2向被测芯片5传输该测试项对应的测试数据。以测试项为指纹算法测试为例，仿真外设接口2被配置后，上位机7将指纹测试数据通过SPI从设备接口传输到被测芯片5，指纹测试数据中至少包括一个测试例的指纹数据，当检测到GPIO接口的模拟中断信号时，将该测试例的指纹数据通过SPI从设备接口传输到被测芯片5，被测芯片5利用该测试例的指纹数据进行指纹算法验证，并将验证结果存储在被测芯片5上的存储器9中；若指纹测试数据中包括多个测试例的指纹数据，则重复上述过程。
本实施例中，调试器10模拟所需外设通过仿真外设接口2向被测芯片5传输该测试项对应的测试数据，其中测试数据的两种传输方式如下：
第一种方式，请参考图1，测试项对应的测试数据存储在上位机7中，调试器10通过通讯接口3与上位机7通讯，微处理器1在测试项的测试过程中，即，被测芯片5进行测试项的测试时，微处理器1通过通讯接口7从上位机7中接收测试项对应的测试数据，并将该测试数据传输至被测芯片5。
第二种方式，请参考图2，存储器11用于预先储存测试项对应的测试数 据；例如，测试项为指纹算法测试，则存储器11中预存存储有指纹算法测试对应的指纹测试数据。微处理器1在测试项的测试过程中，即，被测芯片5进行测试项的测试时，微处理器1将存储器11中的测试项对应的测试数据通过仿真外设接口2传输至被测芯片5。
步骤103，接收调试器从被测芯片获取的反馈数据，并根据反馈数据得出测试项对应的测试结果。
具体而言，调试器10的调试接口4与被测芯片5上的调试接口6通信连接，以测试项为指纹算法测试为例，反馈数据为微处理器1通过调试接口4从被测芯片5获取指纹测试数据的验证结果，指纹测试数据的验证结果数据存储于被测芯片5的存储器9中，因此，调试器10的微处理器1通过调试接口4从存储器9中获取验证结果，微处理器1通过调试接口4从被测芯片5获取指纹测试数据的验证结果(即反馈数据)，并通过通信接口3将反馈数据上传至上位机7，上位机7对验证结果进行分析，得到指纹算法测试的测试结果。
需要说明的，本实施例以及之后的实施例中以测试项属于算法测试，且算法测试为指纹算法测试为例进行说明，然本实施例对测试项的具体类型不作任何限制。
本实施例相对于现有技术而言，在对芯片测试过程中，通过仿真外设接口模拟不同的外设向被测芯片传输测试数据，而无需测试人员手动操作，提升了测试效率；同时，由于无需购买外设便能完成与外设相关的测试，降低了测试成本。
本申请第四实施例涉及一种芯片调试方法，本实施例与第三实施例大致相同，主要不同之处在于：在第三实施例中，被测芯片5的一个测试项单独测 试；本实施例中，被测芯片5的多个测试项连续测试，需要对测试项是否开始测试进行检测，以识别出当前要进行测试的测试项。
即，本实施例应用于被测芯片5的多个测试项的连续测试，上位机7内储存的测试程序可以对该被测芯片5依次进行该多个测试项的测试，即实现多个测试项的自动测试。此时，在上位机7中存储有多个测试项对应的测试数据，然不限于此，也可以在被测芯片5的存储器9中存储有多个测试项对应的测试数据。
其中，步骤202至步骤204与步骤101至步骤103大致相同，在此不再赘述，主要不同之处在于，本实施例中，增加了步骤201，具体如下：
步骤201，检测测试项是否开始测试。
具体而言，上位机7可以检测被测芯片5正在测试的测试项，以确定该测试项对应的测试数据，继而进入步骤202(与第三实施例中步骤101相同)将仿真外设接口2配置为具有支持一测试项进行测试的功能，之后再进入步骤203(与第三实施例中步骤102相同)在测试项的测试过程中，通过仿真外设接口2将测试项对应的测试数据传输至被测芯片5，以完成该测试项的测试。
其中，在被测芯片5的多个测试项连续测试时，在一个测试项测试完成后，便回到步骤201重新检测下一个测试项是否开始测试，直至多个测试项均测试完毕。
本实施例相对于第三实施例而言，可以实现多个测试项的自动连续测试。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (14)

  1. 一种调试器，用于在上位机的控制下对被测芯片进行调试，其特征在于，所述调试器包括至少一仿真外设接口；
    所述仿真外设接口连接于所述调试器的微处理器，且用于与所述被测芯片的至少一外设接口连接，所述仿真外设接口被配置为具有支持一测试项进行测试的功能；
    所述微处理器在所述测试项的测试过程中，通过所述仿真外设接口将所述测试项对应的测试数据传输至所述被测芯片。
  2. 如权利要求1所述的调试器，其特征在于，所述调试器还包括连接于所述微处理器的存储器；
    所述存储器用于预先储存所述测试项对应的测试数据；
    所述微处理器在所述测试项的测试过程中，将所述存储器中的所述测试项对应的测试数据传输至所述被测芯片。
  3. 如权利要求1所述的调试器，其特征在于，所述微处理器在所述测试项的测试过程中，将从所述上位机接收的所述测试项对应的测试数据传输至所述被测芯片。
  4. 如权利要求1所述的调试器，其特征在于，所述仿真外设接口被配置为具有以下功能的其中之一或任意组合：串行外设接口SPI功能、串行通讯总线I2C功能、通用输入/输出GPIO功能、脉冲宽度调制PWM功能。
  5. 如权利要求1所述的调试器，其特征在于，所述测试项属于外设控制器测试或算法测试。
  6. 如权利要求5所述的调试器，其特征在于，所述测试项属于所述算法测试，且所述测试项为指纹算法测试，所述仿真外设接口被配置为具有SPI从设备功能和GPIO功能。
  7. 一种芯片调试方法，其特征在于，应用于通过调试器对被测芯片进行调试的上位机；所述调试器包括至少一仿真外设接口，所述仿真外设接口用于与所述被测芯片的至少一外设接口连接；所述方法包括：
    将所述仿真外设接口配置为具有支持一测试项进行测试的功能；
    在所述测试项的测试过程中，通过所述仿真外设接口将所述测试项对应的测试数据传输至所述被测芯片。
  8. 如权利要求7所述的芯片调试方法，其特征在于，所述通过所述仿真外设接口将所述测试项对应的测试数据传输至所述被测芯片，具体为：
    通过所述仿真外设接口将所述调试器内预存的所述测试项对应的测试数据传输至所述被测芯片。
  9. 如权利要求7所述的芯片调试方法，其特征在于，所述通过所述仿真外设接口将所述测试项对应的测试数据传输至所述被测芯片，具体为：
    将所述上位机内预存的所述测试项对应的测试数据发送至所述调试器，并通过所述仿真外设接口将所述测试项对应的测试数据传输至所述被测芯片。
  10. 如权利要求7所述的芯片调试方法，其特征在于，所述将所述仿真外设接口配置为具有支持一测试项进行测试的功能之前，还包括：
    检测所述测试项是否开始测试；
    若检测到所述测试项开始测试，进入将所述仿真外设接口配置为具有支持一测试项进行测试的功能的步骤。
  11. 如权利要求7所述的芯片调试方法，其特征在于，所述仿真外设接口能够被配置为具有以下功能的其中之一或任意组合：串行外设接口SPI功能、串行通讯总线I2C功能、通用输入/输出GPIO功能、脉冲宽度调制PWM功能。
  12. 如权利要求7所述的芯片调试方法，其特征在于，所述测试项属于外设控制器测试或属于算法测试。
  13. 如权利要求12所述的芯片调试方法，其特征在于，所述测试项属于所述算法测试，且所述测试项为指纹算法测试；
    所述将所述仿真外设接口配置为具有支持一测试项进行测试的功能，具体为：将所述仿真外设接口配置为具有SPI从设备功能和GPIO功能。
  14. 如权利要求7所述的芯片调试方法，其特征在于，在所述通过所述仿真外设接口将所述测试项对应的测试数据传输至所述被测芯片之后，所述方法还包括：
    接收所述调试器从所述被测芯片获取的反馈数据，并根据所述反馈数据得出所述测试项对应的测试结果；其中，所述反馈数据为所述被测芯片在所述测试项的测试过程中产生的数据。
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