WO2019104822A1 - 一种显示面板及其制造方法和控制方法 - Google Patents

一种显示面板及其制造方法和控制方法 Download PDF

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Publication number
WO2019104822A1
WO2019104822A1 PCT/CN2018/070019 CN2018070019W WO2019104822A1 WO 2019104822 A1 WO2019104822 A1 WO 2019104822A1 CN 2018070019 W CN2018070019 W CN 2018070019W WO 2019104822 A1 WO2019104822 A1 WO 2019104822A1
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Prior art keywords
thin film
film transistor
gate
display panel
pixel
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PCT/CN2018/070019
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English (en)
French (fr)
Inventor
洪光辉
龚强
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武汉华星光电技术有限公司
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Priority to US15/751,945 priority Critical patent/US10747076B2/en
Publication of WO2019104822A1 publication Critical patent/WO2019104822A1/zh

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3614Control of polarity reversal in general
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/13624Active matrix addressed cells having more than one switching element per pixel
    • G02F1/136245Active matrix addressed cells having more than one switching element per pixel having complementary transistors
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/165Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on translational movement of particles in a fluid under the influence of an applied field
    • G02F1/1675Constructional details
    • G02F2001/1678Constructional details characterised by the composition or particle type
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243Details of the generation of driving signals
    • G09G2310/0245Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/06Details of flat display driving waveforms
    • G09G2310/061Details of flat display driving waveforms for resetting or blanking
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0247Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present invention relates to the field of screen display technologies, and in particular, to a display panel, a manufacturing method thereof, and a control method.
  • the display area (Active Area) of the panel is an effective display area of the entire display panel, which generally includes a gate gate line to implement panel progressive scanning, a data data line to provide potential to the pixel, and a pixel electrode to realize liquid crystal rotation in the panel. And a control device N thin film transistor is included in each pixel.
  • the pixels of the display area are repeating units formed by the array, and finally the normal display of the panel is achieved.
  • the reverse type of the commonly used sub-pixels is Column inversion and dot inversion. Please refer to Figure 1 and Figure 2 respectively. It is the reverse type of two Sub Pixel displays commonly used in the panel, including column inversion and dot inversion.
  • Figure 1 is a schematic diagram of pixel column inversion, where "+ "This pixel is driven by a positive charge. "-" means that the pixel is driven by a negative charge. In column inversion mode, a column of pixels in a frame is driven by a positive charge, and adjacent pixels are driven by a negative charge.
  • FIG. 2 is a schematic diagram of pixel inversion.
  • one pixel in a frame is driven by a positive charge, and adjacent pixels are driven by a negative charge; likewise, one pixel is driven by a negative charge, Adjacent pixels are driven by a positive charge.
  • FIG. 3 shows the charge state in the pixel when the column is reversed and the power is off.
  • the schematic diagram because it is the column inversion driving mode, the residual charge in the pixels of two adjacent rows in the panel is different.
  • the dot inversion driving mode the electric charges remaining in the adjacent two pixels are different when the power is turned off. Since the residual charge in the pixel is inconsistent, when the panel is driven again, gray scale flicker may be caused due to the inconsistency of the residual charge in the pixel, thereby affecting the quality of the panel.
  • the technical problem to be solved by the present invention is to provide a display panel, a manufacturing method thereof and a control method thereof, which are capable of improving problems such as gray scale flicker caused by charge residual in a pixel due to sudden power failure, thereby improving the quality of the panel.
  • the present invention provides a display panel comprising:
  • the pixel electrodes being located in the pixel region;
  • a plurality of first thin film transistors are disposed in the pixel region, a gate of the first thin film transistor is connected to the gate line, and a source and a drain of the first thin film transistor are respectively connected to the data line
  • the pixel electrodes are connected;
  • the display panel further includes:
  • the second thin film transistor gate is connected to the global signal line, and the source and the drain of the second thin film transistor are respectively adjacent to two pixels
  • the electrodes are connected.
  • the potential of the global signal line applied to the gate of the second thin film transistor is a gate low potential; when the display panel is powered off, the global signal line is applied
  • the potential on the gate of the second thin film transistor is a high potential of the gate and is maintained for a period of time.
  • each pixel in the display panel is at a positive potential with a lower charge amount. Or at the same negative potential of the lower charge, or at the GND potential.
  • the second thin film transistor is an N-type thin film transistor.
  • the invention also provides a manufacturing method of a display panel, comprising:
  • a plurality of gate lines and a plurality of data lines are disposed on the substrate, and the plurality of gate lines and the plurality of data lines intersect to form a plurality of pixel regions;
  • a second thin film transistor is disposed between adjacent two pixel electrodes, and the second thin film transistor is in a non-conducting state when the display panel is normally operated, and is in an on state when the display panel is powered off.
  • the manufacturing method further comprises:
  • the present invention also provides a control method for a display panel, the display panel includes: a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines and the plurality of data lines intersect to form a plurality of pixel regions; a pixel electrode, the pixel electrode is located in the pixel region; a plurality of first thin film transistors are located in the pixel region, and a gate of the first thin film transistor is connected to the gate line, the first film a source and a drain of the transistor are respectively connected to the data line and the pixel electrode; a second thin film transistor connected between adjacent two pixel electrodes;
  • the control method includes: controlling the second thin film transistor to be in a non-conduction state when the display panel is in normal operation, and controlling the second thin film transistor to be in an on state when the display panel is powered off.
  • the display panel further includes a global signal line between adjacent two gate lines, a gate of the second thin film transistor is connected to the global signal line, and a source of the second thin film transistor is The drains are respectively connected to the adjacent two pixel electrodes, and the control method further includes:
  • the global signal line applies a gate low potential on the gate of the second thin film transistor; when the display panel is powered off, the global signal line is on the second film A gate high potential is applied to the gate of the transistor for a period of time.
  • each pixel in the display panel is at a positive potential with a lower charge amount. Or at the same negative potential of the lower charge, or at the GND potential.
  • the beneficial effects of the embodiments of the present invention are as follows: by adding a second thin film transistor between adjacent pixel electrodes in a row of pixels in the display area, the charges in the pixels are released from each other in the case of sudden power failure, and the improvement is caused by sudden power failure. Problems such as gray-scale flicker caused by residual charge in the pixel, thereby improving the quality of the panel.
  • FIG. 1 is a schematic diagram of column inversion of a commonly used pixel display in a panel.
  • FIG. 2 is a schematic diagram of dot inversion of a common pixel display in a panel.
  • FIG. 3 is a schematic diagram showing the state of residual charge in a pixel when a pixel column of a conventional panel is turned off in an inverted state.
  • FIG. 4 is a schematic structural view of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the charge state of each pixel of the display panel after power-off according to the first embodiment of the present invention.
  • a first embodiment of the present invention provides a display panel, including:
  • the pixel electrodes being located in the pixel region;
  • a plurality of first thin film transistors are disposed in the pixel region, a gate of the first thin film transistor is connected to the gate line, and a source and a drain of the first thin film transistor are respectively connected to the data line
  • the pixel electrodes are connected;
  • a second thin film transistor connected between adjacent two pixel electrodes.
  • the display panel of this embodiment further includes a global signal line between adjacent two gate lines, a gate of the second thin film transistor is connected to the global signal line, and a source and a drain are respectively Two adjacent pixel electrodes are connected.
  • the charges in the pixels are released from each other in the case of sudden power failure, and the improvement is due to sudden
  • the power-off causes problems such as gray-scale flicker caused by residual charge in the pixels, thereby improving the quality of the panel.
  • the commonly used panel pixel driving method is a column inversion and a dot inversion mode.
  • adjacent pixels in each row of pixels are driven by opposite charges, that is, one is positive.
  • the charge is driven and the other is driven by a negative charge (there are three cases: the amount of positive charge is greater than the amount of negative charge, the amount of positive charge is equal to the amount of negative charge, and the amount of positive charge is less than the amount of negative charge).
  • the specific working principle of the TFT display panel of this embodiment is that when the panel is working normally, the added GAS signal is VGL potential (Voltage Gate Low), and the added second thin film transistor is in a non-conducting state.
  • the potential between the adjacent two pixels does not affect each other, so the added second thin film transistor does not affect the normal display of the panel; when the panel is suddenly powered off, the VGH potential is maintained for a period of time by the GAS signal (Voltage Gate High, gate Very high potential), the second thin film transistor thus increased is in an on state, and since the adjacent two pixels are driven by opposite charges, a neutralization effect between positive and negative charges can be achieved, thereby ensuring a panel
  • the pixels in the same potential are at a lower potential, and there is no problem such as gray scale flicker caused by charge residue. According to the result of the neutralization effect, there are three cases: the pixel is at the same positive potential with a lower charge, the pixel is at the same negative potential with a lower charge, and the pixels are at the GND potential.
  • each pixel is in the same charge amount. Low positive potential.
  • the amount of positive charge in the pixel before the power-off is less than the amount of negative charge, after the control of the added second thin film transistor, after the neutralization effect between the positive and negative charges is achieved, each pixel is in the same negative amount of negative charge. Potential. If the amount of positive charge in the pixel before the power-off is equal to the amount of negative charge, after the control of the added second thin film transistor, after achieving the neutralization effect between the positive and negative charges, each pixel is at the same GND potential.
  • the first thin film transistor and the second thin film transistor are both N-type thin film transistors
  • the N-type thin film transistor includes: a gate, a source, and a drain, which work.
  • the principle is that when the gate is high, the source and drain are turned on; when Gate is at VGL, the source and drain are disconnected. Therefore, when the second N-type thin film transistor is added, the gate thereof is connected to the global signal line (GAS), and the source and the drain are respectively connected to the laterally adjacent two pixel electrodes, so that when the panel is working normally, the global The signal line is applied to the gate of the second N thin film transistor at a low potential.
  • GAS global signal line
  • the second N thin film transistor is in a non-conducting state, and the potential between adjacent pixels does not affect each other, so the added second N film The transistor does not affect the normal display of the panel; when the panel is suddenly powered off, the global signal line applies a high potential to the gate of the second N thin film transistor for a period of time, and the added second N thin film transistor is turned on. State, and because the adjacent two pixels are driven by opposite charges, the neutralization effect between positive and negative charges can be realized, thereby ensuring that the pixels in the panel are at the same potential of lower charge, and no charge is generated. Problems such as grayscale flicker caused by residue.
  • a second embodiment of the present invention provides a method for manufacturing a display panel, including:
  • a plurality of gate lines and a plurality of data lines are disposed on the substrate, and the plurality of gate lines and the plurality of data lines intersect to form a plurality of pixel regions;
  • a plurality of first thin film transistors and a plurality of pixel electrodes are disposed in the pixel region, and a gate of the first thin film transistor is connected to the gate line, and a source and a drain of the first thin film transistor are respectively respectively The data line is connected to the pixel electrode;
  • a second thin film transistor is disposed between adjacent two pixel electrodes, and the second thin film transistor is in a non-conducting state when the display panel is normally operated, and is in an on state when the display panel is powered off.
  • the manufacturing method further comprises:
  • the present invention also provides a control method for a display panel, the display panel includes: a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines and the plurality of data lines intersect to form a plurality of pixel regions; a pixel electrode, the pixel electrode is located in the pixel region; a plurality of first thin film transistors are located in the pixel region, and a gate of the first thin film transistor is connected to the gate line, the first film a source and a drain of the transistor are respectively connected to the data line and the pixel electrode; a second thin film transistor connected between adjacent two pixel electrodes;
  • the control method includes: controlling the second thin film transistor to be in a non-conduction state when the display panel is in normal operation, and controlling the second thin film transistor to be in an on state when the display panel is powered off.
  • the display panel further includes a global signal line between adjacent two gate lines, a gate of the second thin film transistor is connected to the global signal line, and a source of the second thin film transistor is The drains are respectively connected to the adjacent two pixel electrodes, and the control method further includes:
  • the global signal line applies a gate low potential on the gate of the second thin film transistor; when the display panel is powered off, the global signal line is on the second film A gate high potential is applied to the gate of the transistor for a period of time.
  • each pixel in the display panel is at a positive potential with a lower charge amount. Or at the same negative potential of the lower charge, or at the GND potential.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板及其制造方法和控制方法,其中,显示面板包括:多条栅极线和多条数据线,多条栅极线和多条数据线交叉形成多个像素区域;多个像素电极,像素电极位于像素区域内;多个第一薄膜晶体管,位于像素区域内,第一薄膜晶体管的栅极与栅极线连接,第一薄膜晶体管的源极和漏极分别与数据线和像素电极连接;连接在相邻两像素电极之间的第二薄膜晶体管,第二薄膜晶体管在显示面板正常工作时处于非导通状态,在显示面板断电时处于导通状态。通过在显示区一行像素中的相邻像素电极之间增加一个第二薄膜晶体管,改善由于突然断电造成像素中电荷残留而引起的灰阶闪烁等问题,进而改善面板的品质。

Description

一种显示面板及其制造方法和控制方法
本申请要求于2017年11月29日提交中国专利局、申请号为201711230619.1、发明名称为“一种显示面板及其制造方法和控制方法”的中国专利申请的优先权,上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及屏幕显示技术领域,尤其涉及一种显示面板及其制造方法和控制方法。
背景技术
面板的显示(Active Area)区是整个显示面板的有效显示区,其中通常包括栅极Gate线来实现面板逐行扫描,数据Data线来实现给像素提供电位,像素电极来实现面板中液晶的转动以及每个像素中包含控制器件N薄膜晶体管。显示区的像素是通过阵列形成的重复单元,最终实现面板的正常显示。
众所周知,面板中像素是通过反转类型的电荷来驱动液晶转动的,其目的主要是为了防止直流残留等对面板显示以及品质造成影响,常用的两种子像素(Sub Pixel)显示的反转类型是列反转和点反转。请分别参照图1、图2所示,是现在面板中常用的两种Sub Pixel显示的反转类型,其中包括列反转和点反转,图1是像素列反转的示意图,其中“+”表示这颗像素由正电荷来驱动,“–”表示这颗像素由负电荷来驱动,在列反转模式下,一帧中一列像素为正电荷驱动,其相邻的像素为负电荷驱动;同样地,一列像素为负电荷驱动,其相邻的像素为正电荷驱动。图2是像素点反转的示意图,在点反转模式下,一帧中一颗像素为正电荷驱动,其相邻的像素为负电荷驱动;同样地,一颗像素为负电荷驱动,其相邻的像素为正电荷驱动。
上述显示区像素的设计方案中,如果出现面板突然断电,像素中的电荷没有释放路径,就会出现像素中的电荷残留,图3所示为列反转下断电时的像素中电荷状况示意图,由于是列反转驱动模式,所以面板中相邻两行的像素中残留的电荷不同。如果是点反转驱动模式,则断电时相邻两个像素中残 留的电荷不同。由于像素中的残留电荷不一致,当面板再次驱动时会由于像素中残留的电荷不一致造成灰阶闪烁进而影响面板的品质。
发明内容
本发明所要解决的技术问题在于,提供一种显示面板及其制造方法和控制方法,以改善由于突然断电造成像素中电荷残留而引起的灰阶闪烁等问题,进而改善面板的品质。
为了解决上述技术问题,本发明提供一种显示面板,包括:
多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;
多个像素电极,所述像素电极位于所述像素区域内;
多个第一薄膜晶体管,位于所述像素区域内,所述第一薄膜晶体管的栅极与所述栅极线连接,所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;
连接在相邻两像素电极之间的第二薄膜晶体管,所述第二薄膜晶体管在所述显示面板正常工作时处于非导通状态,在所述显示面板断电时处于导通状态。
其中,所述显示面板还包括:
位于相邻两栅极线之间的全局信号线,所述第二薄膜晶体管器栅极连接在所述全局信号线上,所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连。
其中,在所述显示面板正常工作时,所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极低电位;在所述显示面板断电时,所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间。
其中,在所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间之后,所述显示面板中各像素处于同一个电荷量较低的正电位,或者处于同一个电荷量较低的负电位,或者都处于GND电位。
其中,所述第二薄膜晶体管为N型薄膜晶体管。
本发明还提供一种显示面板的制造方法,包括:
在基板上设置多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;
在所述像素区域内设置多个第一薄膜晶体管和多个像素电极,将所述第一薄膜晶体管的栅极与所述栅极线连接,将所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;
在相邻两像素电极之间的设置第二薄膜晶体管,所述第二薄膜晶体管在所述显示面板正常工作时处于非导通状态,在所述显示面板断电时处于导通状态。
其中,所述制造方法还包括:
在相邻两栅极线之间设置全局信号线,将所述第二薄膜晶体管的栅极连接在所述全局信号线上,将所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连。
本发明还提供一种显示面板的控制方法,所述显示面板包括:多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;多个像素电极,所述像素电极位于所述像素区域内;多个第一薄膜晶体管,位于所述像素区域内,所述第一薄膜晶体管的栅极与所述栅极线连接,所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;连接在相邻两像素电极之间的第二薄膜晶体管;
所述控制方法包括:在所述显示面板正常工作时,控制所述第二薄膜晶体管处于非导通状态,在所述显示面板断电时,控制所述第二薄膜晶体管处于导通状态。
其中,所述显示面板还包括位于相邻两栅极线之间的全局信号线,所述第二薄膜晶体管的栅极连接在所述全局信号线上,所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连,所述控制方法还包括:
在所述显示面板正常工作时,所述全局信号线在所述第二薄膜晶体管栅极上施加栅极低电位;在所述显示面板断电时,所述全局信号线在所述第二薄膜晶体管栅极上施加栅极高电位并维持一段时间。
其中,在所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间之后,所述显示面板中各像素处于同一个电荷量较 低的正电位,或者处于同一个电荷量较低的负电位,或者都处于GND电位。
本发明实施例的有益效果在于:通过在显示区一行像素中的相邻像素电极之间增加一个第二薄膜晶体管来实现面板在突然断电情况下像素中电荷相互释放,改善由于突然断电造成像素中电荷残留而引起的灰阶闪烁等问题,进而改善面板的品质。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是面板中常用像素显示的列反转示意图。
图2是面板中常用像素显示的点反转示意图。
图3是现有面板的像素列反转下断电时的像素中残留电荷状况示意图。
图4是本发明实施例一一种显示面板的结构示意图。
图5是本发明实施例一的显示面板在断电后各像素的电荷状况示意图。
具体实施方式
以下各实施例的说明是参考附图,用以示例本发明可以用以实施的特定实施例。
请参照图4所示,本发明实施例一提供一种显示面板,包括:
多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;
多个像素电极,所述像素电极位于所述像素区域内;
多个第一薄膜晶体管,位于所述像素区域内,所述第一薄膜晶体管的栅极与所述栅极线连接,所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;
连接在相邻两像素电极之间的第二薄膜晶体管。
进一步地,本实施例的显示面板还包括位于相邻两栅极线之间的全局信号线,所述第二薄膜晶体管的栅极连接在所述全局信号线上,源极和漏极分别与相邻两像素电极相连。
本发明实施例通过在显示区一行像素中的相邻像素电极之间增加一个由全局信号(GAS)控制的第二薄膜晶体管来实现面板在突然断电情况下像素中电荷相互释放,改善由于突然断电造成像素中电荷残留而引起的灰阶闪烁等问题,进而改善面板的品质。
具体地,常用的面板像素驱动方式是列反转和点反转两种模式,这两种驱动模式下,每一行像素中的相邻两个像素之间都是相反电荷驱动的,即一个是正电荷驱动,另一个是负电荷驱动(有三种情况:正电荷量大于负电荷量、正电荷量等于负电荷量、正电荷量小于负电荷量)。本实施例的TFT显示面板具体工作原理是,在面板正常工作时,增加的GAS信号为VGL电位(Voltage Gate Low,栅极低电位),增加的第二薄膜晶体管处于非导通的状态,相邻两像素之间的电位不会相互影响,因此增加的第二薄膜晶体管并不会影响面板的正常显示;当面板突然断电时,通过GAS信号维持一段时间的VGH电位(Voltage Gate High,栅极高电位),这样增加的第二薄膜晶体管处于导通的状态,而且由于相邻两个像素之间都是相反电荷驱动的,因此可以实现正负电荷之间的中和效应,从而保证面板中像素处于同一个电荷量较低的电位,不会出现因电荷残留导致的灰阶闪烁等问题。根据中和效应的结果存在三种情况:像素处于同一个电荷量较低的正电位、像素处于同一个电荷量较低的负电位、像素都处于GND电位。
如图5所示,由于断电前像素中正电荷量大于负电荷量,经过增加的第二薄膜晶体管的控制,在实现正负电荷之间的中和效应后,各像素处于同一个电荷量较低的正电位。相应地,如果断电前像素中正电荷量小于负电荷量,经过增加的第二薄膜晶体管的控制,在实现正负电荷之间的中和效应后,各像素处于同一个电荷量较低的负电位。如果断电前像素中正电荷量等于负电荷量,经过增加的第二薄膜晶体管的控制,在实现正负电荷之间的中和效应后,各像素处于同一个GND电位。
进一步地,本实施例中第一薄膜晶体管和第二薄膜晶体管均为N型薄膜晶体管,该N型薄膜晶体管包括:栅极(Gate)、源极(Source)以及漏极(Drain),其工作原理是当栅极为高电位时,源极和漏极两极是导通的;当Gate为VGL电位时,源极和漏极两极是断开的。由此,增设第二N型薄膜晶体管时,将 其栅极连接在全局信号线(GAS)上,源极和漏极分别与横向相邻两像素电极相连,这样,在面板正常工作时,全局信号线给第二N薄膜晶体管的栅极施加的为低电位,此时第二N薄膜晶体管处于非导通的状态,相邻像素之间的电位不会相互影响,因此增加的第二N薄膜晶体管并不会影响面板的正常显示;当面板突然断电时,全局信号线给第二N薄膜晶体管的栅极施加高电位并维持一段时间,此时增加的第二N薄膜晶体管处于导通的状态,而且由于相邻两个像素之间都是相反电荷驱动的,可以实现正负电荷之间的中和效应,从而保证面板中像素处于同一个电荷量较低的电位,不会出现因电荷残留导致的灰阶闪烁等问题。
相应于本发明实施例一,本发明实施例二提供一种显示面板的制造方法,包括:
在基板上设置多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;
在所述像素区域内设置多个第一薄膜晶体管和多个像素电极,将所述第一薄膜晶体管的栅极与所述栅极线连接,将第一薄膜晶体管的源极和漏极分别与所述数据线所述像素电极连接;
在相邻两像素电极之间的设置第二薄膜晶体管,所述第二薄膜晶体管在所述显示面板正常工作时处于非导通状态,在所述显示面板断电时处于导通状态。
其中,所述制造方法还包括:
在相邻两栅极线之间设置全局信号线,将所述第二薄膜晶体管的栅极连接在所述全局信号线上,将所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连。
本发明还提供一种显示面板的控制方法,所述显示面板包括:多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;多个像素电极,所述像素电极位于所述像素区域内;多个第一薄膜晶体管,位于所述像素区域内,所述第一薄膜晶体管的栅极与所述栅极线连接,所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;连接在相邻两像素电极之间的第二薄膜晶体管;
所述控制方法包括:在所述显示面板正常工作时,控制所述第二薄膜晶体管处于非导通状态,在所述显示面板断电时,控制所述第二薄膜晶体管处于导通状态。
其中,所述显示面板还包括位于相邻两栅极线之间的全局信号线,所述第二薄膜晶体管的栅极连接在所述全局信号线上,所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连,所述控制方法还包括:
在所述显示面板正常工作时,所述全局信号线在所述第二薄膜晶体管栅极上施加栅极低电位;在所述显示面板断电时,所述全局信号线在所述第二薄膜晶体管栅极上施加栅极高电位并维持一段时间。
其中,在所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间之后,所述显示面板中各像素处于同一个电荷量较低的正电位,或者处于同一个电荷量较低的负电位,或者都处于GND电位。
有关上述实施例二、三的工作原理及有益效果,请参照本发明实施例一的说明,此处不再赘述。
以上所揭露的仅为本发明较佳实施例而已,当然不能以此来限定本发明之权利范围,因此依本发明权利要求所作的等同变化,仍属本发明所涵盖的范围。

Claims (10)

  1. 一种显示面板,其中,包括:
    多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;
    多个像素电极,所述像素电极位于所述像素区域内;多个第一薄膜晶体管,位于所述像素区域内,所述第一薄膜晶体管的栅极与所述栅极线连接,所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;
    连接在相邻两像素电极之间的第二薄膜晶体管,所述第二薄膜晶体管在所述显示面板正常工作时处于非导通状态,在所述显示面板断电时处于导通状态。
  2. 根据权利要求1所述的显示面板,其中,还包括:位于相邻两栅极线之间的全局信号线,所述第二薄膜晶体管的栅极连接在所述全局信号线上,源极和漏极分别与相邻两像素电极相连。
  3. 根据权利要求2所述的显示面板,其中,在所述显示面板正常工作时,所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极低电位;在所述显示面板断电时,所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间。
  4. 根据权利要求3所述的显示面板,其中,在所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间之后,所述显示面板中各像素处于同一个电荷量较低的正电位,或者处于同一个电荷量较低的负电位,或者都处于GND电位。
  5. 根据权利要求1所述的显示面板,其中,所述第二薄膜晶体管为N型薄膜晶体管。
  6. 一种显示面板的制造方法,其中,包括:
    在基板上设置多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;
    在所述像素区域内设置多个第一薄膜晶体管和多个像素电极,将所述第一薄膜晶体管的栅极与所述栅极线连接,将所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接
    在相邻两像素电极之间设置第二薄膜晶体管,所述第二薄膜晶体管在所述显示面板正常工作时处于非导通状态,在所述显示面板断电时处于导通状态。
  7. 根据权利要求6所述的制造方法,其中,还包括:
    在相邻两栅极线之间设置全局信号线,将所述第二薄膜晶体管的栅极连接在所述全局信号线上,将所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连。
  8. 一种显示面板的控制方法,其中,所述显示面板包括:多条栅极线和多条数据线,所述多条栅极线和多条数据线交叉形成多个像素区域;多个像素电极,所述像素电极位于所述像素区域内;多个第一薄膜晶体管,位于所述像素区域内,所述第一薄膜晶体管的栅极与所述栅极线连接,所述第一薄膜晶体管的源极和漏极分别与所述数据线和所述像素电极连接;连接在相邻两像素电极之间的第二薄膜晶体管;
    所述控制方法包括:在所述显示面板正常工作时,控制所述第二薄膜晶体管处于非导通状态,在所述显示面板断电时,控制所述第二薄膜晶体管处于导通状态。
  9. 根据权利要求8所述的控制方法,其中,所述显示面板还包括位于相邻两栅极线之间的全局信号线,所述第二薄膜晶体管的栅极连接在所述全局信号线上,所述第二薄膜晶体管的源极和漏极分别与相邻两像素电极相连,所述控制方法还包括:
    在所述显示面板正常工作时,所述全局信号线在所述第二薄膜晶体管栅极上施加栅极低电位;在所述显示面板断电时,所述全局信号线在所述第二薄膜晶体管栅极上施加栅极高电位并维持一段时间。
  10. 根据权利要求9所述的控制方法,其中,在所述全局信号线施加在所述第二薄膜晶体管栅极上的电位为栅极高电位并维持一段时间之后,所述显示面板中各像素处于同一个电荷量较低的正电位,或者处于同一个电荷量较低的负电位,或者都处于GND电位。
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