WO2019100464A1 - 背沟道蚀刻型氧化物半导体tft基板的制作方法 - Google Patents

背沟道蚀刻型氧化物半导体tft基板的制作方法 Download PDF

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WO2019100464A1
WO2019100464A1 PCT/CN2017/116281 CN2017116281W WO2019100464A1 WO 2019100464 A1 WO2019100464 A1 WO 2019100464A1 CN 2017116281 W CN2017116281 W CN 2017116281W WO 2019100464 A1 WO2019100464 A1 WO 2019100464A1
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passivation layer
source
drain
oxide semiconductor
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姜春生
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a back channel etch type oxide semiconductor TFT substrate.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and is widely used, such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptops. Screen, etc.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • Thin Film Transistor is the main driving component in current liquid crystal display devices and active matrix OLED display devices, and is directly related to the development direction of high performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the thin film transistor for preparing the corresponding structure is also various, and an amorphous silicon (a-Si) material is a relatively common one.
  • a-Si amorphous silicon
  • the conventional a-Si has a mobility of only about 1 cm 2 /(Vs) which cannot meet the requirements, and is oxidized by indium gallium zinc.
  • the metal oxide material represented by Indium Gallium Zinc Oxide (IGZO) has a mobility of more than 10 cm 2 /(Vs) or more, and the preparation of the corresponding thin film transistor and the existing a-Si semiconductor driven thin film transistor production line The compatibility is good, and in recent years, it has quickly become the focus of research and development in the display field.
  • IGZO Indium Gallium Zinc Oxide
  • IGZO TFTs Compared to traditional a-Si TFTs, IGZO TFTs have the following advantages:
  • the resolution of the IGZO TFT display backplane can be more than twice that of the a-Si TFT, and the carrier in the IGZO material is thick. High degree and high mobility, which can reduce the size of TFT and ensure the resolution is improved;
  • IGZO TFT has a leakage current of less than 1pA; the driving frequency is reduced from the original 30-50Hz to 2-5Hz, and even 1Hz can be achieved through a special process.
  • the alignment of the liquid crystal molecules can be maintained without affecting the quality of the picture, thereby reducing the power consumption of the display backplane; in addition, the high mobility of the IGZO semiconductor material allows a smaller size TFT to provide sufficient The charging capacity and the higher capacitance value, and the aperture ratio of the liquid crystal panel is increased, the effective area of light penetration is increased, and the same brightness can be achieved with less backplane components or low power consumption, thereby reducing energy consumption;
  • IGZO as a semiconductor active layer TFT generally adopts an etch barrier (ESL) structure, and an etch barrier layer is used in the source/drain etching process due to the existence of an etch stop layer (Etch Stop Layer). It can effectively protect IGZO from being affected and ensure that the TFT has excellent semiconductor characteristics.
  • ESL etch barrier
  • Etch Stop Layer etch stop layer
  • the preparation process of the IGZO TFT of the ESL structure is complicated, and it is necessary to go through 6 times of yellow light process, which is disadvantageous for cost reduction. Therefore, the industry generally pursues the development of an IGZO TFT with a less back channel etching (BCE) structure with a yellow light process.
  • the BCE structure of the IGZO TFT is realized by using metal copper to make the source and drain while removing the Etch Stop Layer to reduce the yellow light process.
  • the existing copper etching solution is inevitable. A certain degree of damage is caused to the IGZO active layer, and the surface characteristics of the IGZO active layer are changed, thereby deteriorating the stability of the TFT substrate.
  • the commonly used copper etching solution is hydrogen peroxide (H 2 O 2 ) system, which has less damage to the IGZO active layer, especially the fluorine-free (F) element copper etching solution, but it is experimentally verified that there is no F element.
  • the copper etching solution still damages the IGZO active layer, especially the balance of the oxygen (O) element in the shallow surface layer of the back channel, which easily affects the leakage current (I off ) and the operational stability of the TFT device.
  • An object of the present invention is to provide a method for fabricating a back channel etch-type oxide semiconductor TFT substrate, which can ensure the balance of oxygen elements in the superficial layer of the channel region and ensure the operational stability of the TFT.
  • the present invention provides a method for fabricating a back channel etch-type oxide semiconductor TFT substrate, comprising:
  • a gate insulating layer covering the gate is formed on the substrate, and an active corresponding to the upper portion of the gate is formed on the gate insulating layer a layer, the active layer being a metal oxide semiconductor material;
  • the source and the drain Forming a source and a drain on the active layer and the gate insulating layer, the source and the drain defining a channel region between the source and the drain on the active layer, a source contact region on one side of the channel region and in contact with the source; and a drain contact region on the other side of the channel region and in contact with the drain;
  • the surface layer is supplemented with oxygen to ensure the balance of oxygen in the superficial layer
  • the material of the active layer includes indium gallium zinc oxide.
  • the source and drain materials include metallic copper.
  • the etching solution used in the photolithography process of the source and the drain is a fluorine-free hydrogen peroxide-based copper etching solution.
  • the oxygen element balance of the superficial layer refers to the content of the oxygen element in the superficial layer before it reaches the source and drain.
  • the material of the first passivation layer is silicon oxide, and the thickness of the first passivation layer is silicon oxide
  • the plasma of the oxygen-containing element is a nitrous oxide plasma.
  • the process of treating the surface of the first passivation layer by using an oxygen-containing plasma is performed by plasma enhanced chemical vapor deposition, and the power and pressure of the chemical vapor deposition are controlled by plasma to ensure only a trace amount of oxygen.
  • the element penetrates into the superficial layer of the channel region of the active layer via the first passivation layer to achieve oxygen balance of the superficial layer.
  • the material of the second passivation layer is silicon oxide, and the thickness of the second passivation layer is silicon oxide.
  • the material of the pixel electrode includes indium tin oxide.
  • the present invention also provides a method for fabricating a back channel etch-type oxide semiconductor TFT substrate, comprising:
  • a gate insulating layer covering the gate is formed on the substrate, and an active corresponding to the upper portion of the gate is formed on the gate insulating layer a layer, the active layer being a metal oxide semiconductor material;
  • the source and the drain Forming a source and a drain on the active layer and the gate insulating layer, the source and the drain defining a channel region between the source and the drain on the active layer, a source contact region on one side of the channel region and in contact with the source; and a drain contact region on the other side of the channel region and in contact with the drain;
  • the surface layer is supplemented with oxygen to ensure the balance of oxygen in the superficial layer
  • the material of the active layer comprises indium gallium zinc oxide
  • the material of the source and the drain comprises metallic copper
  • the etching solution used in the photolithography process of the source and the drain is a fluorine-free hydrogen peroxide copper etching solution
  • the material of the first passivation layer is silicon oxide, and the thickness of the first passivation layer is silicon oxide
  • the oxygen element balance of the superficial layer refers to the content of the oxygen element in the superficial layer before the source and the drain are etched.
  • the present invention provides a method of fabricating a back channel etch-type oxide semiconductor TFT substrate by first depositing a first passivation layer on a source, a drain, and an active layer, and then using an oxygen-containing element
  • the surface of the first passivation layer is treated such that a trace amount of oxygen element permeates through the first passivation layer to a superficial layer of a channel region of the active layer, to a superficial layer of the channel region
  • the oxygen element is supplemented to ensure the oxygen balance of the superficial layer, and during the plasma treatment, the first passivation layer functions as a barrier layer of the source and the drain, so that only a trace amount of oxygen can be reached.
  • the source and the drain are insufficient to cause oxidation of the source and the drain to ensure the operational stability of the TFT.
  • FIG. 1 is a flow chart showing a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step S2 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 4 is a schematic view showing a step S3 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 5 is a schematic view showing a step S4 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • FIG. 6 is a schematic view showing a step S5 of a method of fabricating a back channel etch type oxide semiconductor TFT substrate of the present invention
  • Fig. 7 is a schematic view showing a step S6 of the method of fabricating the back channel etching type oxide semiconductor TFT substrate of the present invention.
  • the present invention provides a method for fabricating a back channel etch type oxide semiconductor TFT substrate, comprising the following steps:
  • Step S1 as shown in FIG. 2, a base substrate 10 is provided, a gate electrode 20 is formed on the base substrate 10, and a gate insulating layer 30 covering the gate electrode 20 is formed on the base substrate 10, An active layer 40 corresponding to the upper portion of the gate electrode 20 is formed on the gate insulating layer 30, and the active layer 40 is a metal oxide semiconductor material.
  • the material of the active layer 40 includes indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • Step S2 as shown in FIG. 3, a source 51 and a drain 52 are formed on the active layer 40 and the gate insulating layer 30, and the source 51 and the drain 52 are defined on the active layer 40. a channel region 41 between the source 51 and the drain 52, a source contact region 42 on the side of the channel region 41 and in contact with the source 51, and a channel region located in the channel region A drain contact region 43 on the other side and in contact with the drain 52.
  • the material of the source 51 and the drain 52 includes metallic copper
  • the etching liquid used in the photolithography process of the source 51 and the drain 52 is a fluorine-free hydrogen peroxide-based copper etching solution.
  • the fluorine-based hydrogen peroxide copper etching solution is less harmful to the channel region 41, but still causes damage to the oxygen element balance in the superficial layer 415 of the channel region 41, causing oxygen in the superficial layer 415 of the channel region 41.
  • the element content is reduced and the IGZO surface produces more oxygen vacancies.
  • Step S3 as shown in FIG. 4, a first passivation layer 61 is deposited on the source 51, the drain 52, and the active layer 40.
  • the material of the first passivation layer 61 is silicon oxide (SiO x ), and the thickness of the first passivation layer 61 is silicon oxide (SiO x ), and the thickness of the first passivation layer 61 is silicon oxide (SiO x ), and the thickness of the first passivation layer 61 is silicon oxide (SiO x ), and the thickness of the first passivation layer 61 is silicon oxide (SiO x ), and the thickness of the first passivation layer 61 is
  • Step S4 as shown in FIG. 5, the surface of the first passivation layer 61 is treated with a plasma containing an oxygen element, and a trace amount of oxygen element is infiltrated into the active layer 40 via the first passivation layer 61.
  • the superficial layer 415 of the channel region 41 replenishes the superficial layer 415 of the channel region 41 with oxygen to ensure the oxygen element balance of the superficial layer 415.
  • the oxygen content of the IGZO can be improved, the oxygen vacancies on the surface of the IGZO can be reduced, and the IGZO of the channel region 41 when etching the source 51 and the drain 52 can be compensated. influences.
  • the oxygen element balance of the superficial layer 415 refers to the content of the oxygen element in the superficial layer 415 before the source and drain are etched.
  • the plasma of the oxygen-containing element is a nitrous oxide (N 2 O) plasma.
  • the first passivation layer 61 functions as a barrier layer of the source 51 and the drain 52, so that only a trace amount of oxygen can reach the source 51 and the drain 52, which is insufficient for the source.
  • the pole 51 and the drain 52 cause oxidation.
  • the oxygen-containing plasma oxidizes the metal copper of the source 51 and the drain 52, reducing the source 51 and the drain 52 and the blunt above it.
  • the bonding force between the layers causes the passivation layer above it to warp and bubble, and affects the subsequent fabrication of the pixel electrode 70 and the electrical contact between the source 51 and the drain 52.
  • Step S5 as shown in FIG. 6, a second passivation layer 62 is deposited on the first passivation layer 61.
  • Step S6 as shown in FIG. 7, a via hole 65 corresponding to the upper surface of the source 51 is formed on the first passivation layer 61 and the second passivation layer 62; on the second passivation layer 62 Forming a pixel electrode 70.
  • the pixel electrode 70 is in contact with the source 51 via the through hole 65.
  • the material of the pixel electrode 70 includes indium tin oxide (ITO).
  • the present invention provides a method for fabricating a back channel etch-type oxide semiconductor TFT substrate by depositing a first passivation layer on the source, drain, and active layers, and then using an oxygen-containing element. Treating the surface of the first passivation layer with a plasma, so that a trace amount of oxygen element penetrates into the superficial layer of the channel region of the active layer via the first passivation layer, and performs superficial layer on the channel region The supplement of oxygen ensures the balance of oxygen in the superficial layer, and during the plasma treatment, the first passivation layer acts as a barrier layer for the source and the drain, so that only a trace amount of oxygen can reach the source.
  • the pole and the drain are insufficient to cause oxidation of the source and the drain to ensure the operational stability of the TFT.

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  • Physics & Mathematics (AREA)
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Abstract

一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，通过先在源极（51）、漏极（52）及有源层（40）上沉积第一钝化层（61），然后采用含氧元素的等离子体对所述第一钝化层（61）表面进行处理，使微量的氧元素经由所述第一钝化层（61）渗透至所述有源层（40）的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡，并且在等离子处理过程中，所述第一钝化层（61）起到源极（51）和漏极（52）的阻挡层的作用，这样仅有微量的氧元素能够到达源极（51）和漏极（52），不足以对源极（51）和漏极（52）造成氧化，保证TFT的工作稳定性。

Description

背沟道蚀刻型氧化物半导体TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种背沟道蚀刻型氧化物半导体TFT基板的制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
有机发光二极管(Organic Light-Emitting Diode，OLED)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是目前液晶显示装置和有源矩阵型OLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的材料也具有多种，非晶硅(a-Si)材料是比较常见的一种。然而，随着液晶显示装置和OLED显示装置朝着大尺寸和高分辨率的方向发展，传统的a-Si仅有1cm2/(Vs)左右的迁移率已经无法满足要求，以铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)为代表的金属氧化物材料具备超过10cm2/(Vs)以上的迁移率，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的薄膜晶体管产线的兼容性好，近年来迅速成为显示领域研发的重点。
相对于传统的a-Si TFT，IGZO TFT具有以下优势：
1、提高显示背板的分辨率，在保证相同透过率的前提下，IGZO TFT显示背板的分辨率可以做到a-Si TFT的2倍以上，IGZO材料中的载流子浓 度高，迁移率大，可以缩小TFT的体积，保证分辨率的提升；
2、减少显示器件的能耗，IGZO TFT与a-Si TFT、LTPS TFT相比，漏电流小于1pA；驱动频率由原来的30-50Hz减少到2-5Hz，通过特殊工艺，甚至可以达到1Hz，虽然减少TFT的驱动次数，仍然可以维持液晶分子的配向，不影响画面的质量，从而减少显示背板的耗电量；另外，IGZO半导体材料的高迁移率使得较小尺寸的TFT即可提供足够的充电能力和较高的电容值，而且提高了液晶面板的开口率，光穿透的有效面积变大，可以用较少的背板组件或低功率消耗达到相同的亮度，减少能耗；
3、通过采用间歇式驱动等方式，能够降低液晶显示器驱动电路的噪点对触摸屏检测电路造成的影响，可以实现更高的灵敏度，甚至尖头的圆珠笔笔端也能够响应，而且由于画面无更新时可以切断电源，因此其在节能的效果上表现更为优秀。
目前，IGZO作为半导体有源层的TFT一般采用刻蚀阻挡(ESL)结构，由于有刻蚀阻挡层(Etch Stop Layer)存在，源漏极(Source/Drain)的蚀刻过程中，刻蚀阻挡层可以有效的保护IGZO不受到影响，保证TFT具有优异的半导体特性。但是ESL结构的IGZO TFT的制备过程较为复杂，需要经过6次黄光工艺，不利于降低成本，因此业界普遍追求黄光工艺更少的背沟道蚀刻(BCE)结构的IGZO TFT的开发。
BCE结构的IGZO TFT的实现是在采用金属铜制作源漏极的同时，去除刻蚀阻挡层(Etch Stop Layer)，达到减少一次黄光工艺的目的，然而现有的铜蚀刻液不可避免的会对IGZO有源层造成一定程度的损害，使IGZO有源层的表面特性发生改变，从而使TFT基板的稳定性变差。目前常用的铜刻蚀液为双氧水(H2O2)系，对IGZO有源层的蚀刻伤害较小，尤其是无氟(F)元素铜刻蚀液，但是通过实验验证，无F元素的铜刻蚀液仍然对IGZO有源层有伤害，尤其是对背沟道浅表层中的氧(O)元素平衡的破坏，容易影响TFT器件的漏电流(Ioff)和工作稳定性。
发明内容
本发明的目的在于提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，能够保证沟道区的浅表层的氧元素平衡，保证TFT的工作稳定性。
为实现上述目的，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层，在所述栅极绝缘层上形成对应于栅极上方的有源 层，所述有源层为金属氧化物半导体材料；
在所述有源层与栅极绝缘层上形成源极与漏极，所述源极与漏极在所述有源层上限定出位于所述源极与漏极之间的沟道区、位于所述沟道区一侧且与所述源极相接触的源极接触区以及位于所述沟道区另一侧且与所述漏极相接触的漏极接触区；
在所述源极、漏极及有源层上沉积第一钝化层；
采用含氧元素的等离子体对所述第一钝化层表面进行处理，氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡；
在所述第一钝化层上沉积第二钝化层；
在所述第一钝化层与第二钝化层上形成对应于所述源极上方的通孔；在所述第二钝化层上形成像素电极，所述像素电极经由所述通孔与所述源极相接触。
所述有源层的材料包括铟镓锌氧化物。
所述源极与漏极的材料包括金属铜。
所述源极与漏极的光刻制程中使用的蚀刻液为无氟元素的双氧水系铜蚀刻液。
所述浅表层的氧元素平衡指的是所述浅表层中的氧元素达到蚀刻源极和漏极之前的含量。
所述第一钝化层的材料为氧化硅，所述第一钝化层的厚度为
Figure PCTCN2017116281-appb-000001
所述含氧元素的等离子体为一氧化二氮等离子体。
采用含氧元素的等离子体对所述第一钝化层表面进行处理的制程按照等离子体增强化学气相沉积的方式进行，通过控制等离子体增强化学气相沉积的功率和压力，保证仅有微量的氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，实现浅表层的氧元素平衡即可。
所述第二钝化层的材料为氧化硅，所述第二钝化层的厚度为
Figure PCTCN2017116281-appb-000002
所述像素电极的材料包括氧化铟锡。
本发明还提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
提供衬底基板，在所述衬底基板上形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层，在所述栅极绝缘层上形成对应于栅极上方的有源层，所述有源层为金属氧化物半导体材料；
在所述有源层与栅极绝缘层上形成源极与漏极，所述源极与漏极在所述有源层上限定出位于所述源极与漏极之间的沟道区、位于所述沟道区一侧且与所述源极相接触的源极接触区以及位于所述沟道区另一侧且与所述漏极相接触的漏极接触区；
在所述源极、漏极及有源层上沉积第一钝化层；
采用含氧元素的等离子体对所述第一钝化层表面进行处理，氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡；
在所述第一钝化层上沉积第二钝化层；
在所述第一钝化层与第二钝化层上形成对应于所述源极上方的通孔；在所述第二钝化层上形成像素电极，所述像素电极经由所述通孔与所述源极相接触；
其中，所述有源层的材料包括铟镓锌氧化物；
其中，所述源极与漏极的材料包括金属铜；
其中，所述源极与漏极的光刻制程中使用的蚀刻液为无氟元素的双氧水系铜蚀刻液；
其中，所述第一钝化层的材料为氧化硅，所述第一钝化层的厚度为
Figure PCTCN2017116281-appb-000003
其中，所述浅表层的氧元素平衡指的是所述浅表层中的氧元素达到蚀刻源极和漏极之前的含量。
本发明的有益效果：本发明提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，通过先在源极、漏极及有源层上沉积第一钝化层，然后采用含氧元素的等离子体对所述第一钝化层表面进行处理，使微量的氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡，并且在等离子处理过程中，所述第一钝化层起到源极和漏极的阻挡层的作用，这样仅有微量的氧元素能够到达源极和漏极，不足以对源极和漏极造成氧化，保证TFT的工作稳定性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的流程图；
图2为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S1的示意图；
图3为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S2的示意图；
图4为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S3的示意图；
图5为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S4的示意图；
图6为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S5的示意图；
图7为本发明的背沟道蚀刻型氧化物半导体TFT基板的制作方法的步骤S6的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤S1、如图2所示，提供衬底基板10，在所述衬底基板10上形成栅极20，在所述衬底基板10上形成覆盖栅极20的栅极绝缘层30，在所述栅极绝缘层30上形成对应于栅极20上方的有源层40，所述有源层40为金属氧化物半导体材料。
具体的，所述有源层40的材料包括铟镓锌氧化物(IGZO)。
步骤S2、如图3所示，在所述有源层40与栅极绝缘层30上形成源极51与漏极52，所述源极51与漏极52在所述有源层40上限定出位于所述源极51与漏极52之间的沟道区41、位于所述沟道区41一侧且与所述源极51相接触的源极接触区42以及位于所述沟道区41另一侧且与所述漏极52相接触的漏极接触区43。
具体的，所述源极51与漏极52的材料包括金属铜，所述源极51与漏极52的光刻制程中使用的蚀刻液为无氟元素的双氧水系铜蚀刻液。虽然无 氟元素的双氧水系铜蚀刻液对沟道区41的伤害较小，但是仍然会对沟道区41的浅表层415中的氧元素平衡造成破坏，使沟道区41的浅表层415中的氧元素含量降低，IGZO表面产生较多氧空位。
步骤S3、如图4所示，在所述源极51、漏极52及有源层40上沉积第一钝化层61。
具体的，所述第一钝化层61的材料为氧化硅(SiOx)，所述第一钝化层61的厚度为
Figure PCTCN2017116281-appb-000004
步骤S4、如图5所示，采用含氧元素的等离子体对所述第一钝化层61表面进行处理，微量的氧元素经由所述第一钝化层61渗透至所述有源层40的沟道区41的浅表层415，对沟道区41的浅表层415进行氧元素的补充，保证浅表层415的氧元素平衡。
通过对沟道区41的浅表层415进行氧元素补充处理，可以改善IGZO的含氧量，减少IGZO表面的氧空位，补偿刻蚀源极51与漏极52时对沟道区41的IGZO的影响。
具体的，所述浅表层415的氧元素平衡指的是所述浅表层415中的氧元素达到蚀刻源极和漏极之前的含量。
具体的，所述含氧元素的等离子体为一氧化二氮(N2O)等离子体。
具体，采用含氧元素的等离子体对所述第一钝化层61表面进行处理的制程按照等离子体增强化学气相沉积(PECVD)的方式进行，通过控制等离子体增强化学气相沉积的功率和压力，保证仅有微量的氧元素经由所述第一钝化层61渗透至所述有源层40的沟道区41的浅表层415，实现浅表层415的氧元素平衡即可。
在等离子处理过程中，所述第一钝化层61起到源极51和漏极52的阻挡层的作用，这样仅有微量的氧元素能够到达源极51和漏极52，不足以对源极51和漏极52造成氧化。
在源极51和漏极52上方不设置阻挡层的情况下，含氧元素的等离子体会对源极51与漏极52的金属铜进行氧化，降低源极51与漏极52和其上方的钝化层之间的结合力，导致其上方的钝化层出现翘起和鼓泡，并且会影响后续制作的像素电极70和源极51与漏极52之间的电性接触。
步骤S5、如图6所示，在所述第一钝化层61上沉积第二钝化层62。
具体的，所述第二钝化层62的材料为氧化硅(SiOx)，所述第二钝化层62的厚度为
Figure PCTCN2017116281-appb-000005
步骤S6、如图7所示，在所述第一钝化层61与第二钝化层62上形成对应于所述源极51上方的通孔65；在所述第二钝化层62上形成像素电极 70，所述像素电极70经由所述通孔65与所述源极51相接触。
具体的，所述像素电极70的材料包括氧化铟锡(ITO)。
综上所述，本发明提供一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，通过先在源极、漏极及有源层上沉积第一钝化层，然后采用含氧元素的等离子体对所述第一钝化层表面进行处理，使微量的氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡，并且在等离子处理过程中，所述第一钝化层起到源极和漏极的阻挡层的作用，这样仅有微量的氧元素能够到达源极和漏极，不足以对源极和漏极造成氧化，保证TFT的工作稳定性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层，在所述栅极绝缘层上形成对应于栅极上方的有源层，所述有源层为金属氧化物半导体材料；
    在所述有源层与栅极绝缘层上形成源极与漏极，所述源极与漏极在所述有源层上限定出位于所述源极与漏极之间的沟道区、位于所述沟道区一侧且与所述源极相接触的源极接触区以及位于所述沟道区另一侧且与所述漏极相接触的漏极接触区；
    在所述源极、漏极及有源层上沉积第一钝化层；
    采用含氧元素的等离子体对所述第一钝化层表面进行处理，氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡；
    在所述第一钝化层上沉积第二钝化层；
    在所述第一钝化层与第二钝化层上形成对应于所述源极上方的通孔；在所述第二钝化层上形成像素电极，所述像素电极经由所述通孔与所述源极相接触。
  2. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述有源层的材料包括铟镓锌氧化物。
  3. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述源极与漏极的材料包括金属铜。
  4. 如权利要求3所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述源极与漏极的光刻制程中使用的蚀刻液为无氟元素的双氧水系铜蚀刻液。
  5. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述第一钝化层的材料为氧化硅，所述第一钝化层的厚度为
    Figure PCTCN2017116281-appb-100001
  6. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述含氧元素的等离子体为一氧化二氮等离子体。
  7. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，采用含氧元素的等离子体对所述第一钝化层表面进行处理的制程按照等离子体增强化学气相沉积的方式进行，通过控制等离子体增强化 学气相沉积的功率和压力，保证仅有微量的氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，实现浅表层的氧元素平衡即可。
  8. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述浅表层的氧元素平衡指的是所述浅表层中的氧元素达到蚀刻源极和漏极之前的含量。
  9. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述第二钝化层的材料为氧化硅，所述第二钝化层的厚度为
    Figure PCTCN2017116281-appb-100002
  10. 如权利要求1所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述像素电极的材料包括氧化铟锡。
  11. 一种背沟道蚀刻型氧化物半导体TFT基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上形成栅极，在所述衬底基板上形成覆盖栅极的栅极绝缘层，在所述栅极绝缘层上形成对应于栅极上方的有源层，所述有源层为金属氧化物半导体材料；
    在所述有源层与栅极绝缘层上形成源极与漏极，所述源极与漏极在所述有源层上限定出位于所述源极与漏极之间的沟道区、位于所述沟道区一侧且与所述源极相接触的源极接触区以及位于所述沟道区另一侧且与所述漏极相接触的漏极接触区；
    在所述源极、漏极及有源层上沉积第一钝化层；
    采用含氧元素的等离子体对所述第一钝化层表面进行处理，氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，对沟道区的浅表层进行氧元素的补充，保证浅表层的氧元素平衡；
    在所述第一钝化层上沉积第二钝化层；
    在所述第一钝化层与第二钝化层上形成对应于所述源极上方的通孔；在所述第二钝化层上形成像素电极，所述像素电极经由所述通孔与所述源极相接触；
    其中，所述有源层的材料包括铟镓锌氧化物；
    其中，所述源极与漏极的材料包括金属铜；
    其中，所述源极与漏极的光刻制程中使用的蚀刻液为无氟元素的双氧水系铜蚀刻液；
    其中，所述第一钝化层的材料为氧化硅，所述第一钝化层的厚度为
    Figure PCTCN2017116281-appb-100003
    其中，所述浅表层的氧元素平衡指的是所述浅表层中的氧元素达到蚀刻源极和漏极之前的含量。
  12. 如权利要求11所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述含氧元素的等离子体为一氧化二氮等离子体。
  13. 如权利要求11所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，采用含氧元素的等离子体对所述第一钝化层表面进行处理的制程按照等离子体增强化学气相沉积的方式进行，通过控制等离子体增强化学气相沉积的功率和压力，保证仅有微量的氧元素经由所述第一钝化层渗透至所述有源层的沟道区的浅表层，实现浅表层的氧元素平衡即可。
  14. 如权利要求11所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述第二钝化层的材料为氧化硅，所述第二钝化层的厚度为
    Figure PCTCN2017116281-appb-100004
  15. 如权利要求11所述的背沟道蚀刻型氧化物半导体TFT基板的制作方法，其中，所述像素电极的材料包括氧化铟锡。
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CN108598041A (zh) * 2018-05-09 2018-09-28 深圳市华星光电技术有限公司 Tft阵列基板的制作方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090142887A1 (en) * 2007-12-03 2009-06-04 Samsung Electronics Co., Ltd. Methods of manufacturing an oxide semiconductor thin film transistor
CN103620788A (zh) * 2011-06-30 2014-03-05 应用材料公司 用PECVD SiO2钝化保护(passivation)制造铟镓锌氧化物(IGZO)和氧化锌(ZNO)薄膜晶体管的方法
CN103887344A (zh) * 2014-02-28 2014-06-25 上海和辉光电有限公司 Igzo薄膜晶体管及改善igzo薄膜晶体管电学性能的方法
CN104637952A (zh) * 2013-11-07 2015-05-20 乐金显示有限公司 阵列基板及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101510212B1 (ko) * 2008-06-05 2015-04-10 삼성전자주식회사 산화물 반도체 박막 트랜지스터의 제조방법
JP6657770B2 (ja) * 2014-11-27 2020-03-04 三菱瓦斯化学株式会社 液体組成物およびこれを用いたエッチング方法
CN107406966B (zh) * 2015-03-03 2020-11-20 株式会社半导体能源研究所 氧化物半导体膜、包括该氧化物半导体膜的半导体装置以及包括该半导体装置的显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090142887A1 (en) * 2007-12-03 2009-06-04 Samsung Electronics Co., Ltd. Methods of manufacturing an oxide semiconductor thin film transistor
CN103620788A (zh) * 2011-06-30 2014-03-05 应用材料公司 用PECVD SiO2钝化保护(passivation)制造铟镓锌氧化物(IGZO)和氧化锌(ZNO)薄膜晶体管的方法
CN104637952A (zh) * 2013-11-07 2015-05-20 乐金显示有限公司 阵列基板及其制造方法
CN103887344A (zh) * 2014-02-28 2014-06-25 上海和辉光电有限公司 Igzo薄膜晶体管及改善igzo薄膜晶体管电学性能的方法

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