WO2019091348A1 - Fpga云主机开发方法和系统 - Google Patents

Fpga云主机开发方法和系统 Download PDF

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Publication number
WO2019091348A1
WO2019091348A1 PCT/CN2018/113901 CN2018113901W WO2019091348A1 WO 2019091348 A1 WO2019091348 A1 WO 2019091348A1 CN 2018113901 W CN2018113901 W CN 2018113901W WO 2019091348 A1 WO2019091348 A1 WO 2019091348A1
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Prior art keywords
development
file
fpga
management platform
programming
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English (en)
French (fr)
Chinese (zh)
Inventor
梁晨
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Alibaba Group Holding Ltd
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Alibaba Group Holding Ltd
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Priority to JP2020526207A priority Critical patent/JP2021502648A/ja
Priority to EP18875358.6A priority patent/EP3712764B1/en
Publication of WO2019091348A1 publication Critical patent/WO2019091348A1/zh
Priority to US15/930,113 priority patent/US11132436B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
    • G06F21/12—Protecting executable software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/03—Indexing scheme relating to G06F21/50, monitoring users, programs or devices to maintain the integrity of platforms
    • G06F2221/033—Test or assess software
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/10—Requirements analysis; Specification techniques

Definitions

  • the present invention relates to the field of Internet technologies, and in particular, to an FPGA cloud host development method and system.
  • the FPGA cloud host or FPGA cloud server is a Field Programmable Gate Array (FPGA)-based computing service.
  • FPGA Field Programmable Gate Array
  • An FPGA cloud host can be understood as a normal cloud host (virtual machine) with an FPGA device. After purchasing the FPGA cloud host, if you want to use the FPGA, you need to develop the FPGA, get a burning file, and then burn this file into the FPGA. The FPGA implements the user-developed function.
  • FPGA development environment and process are all developed and debugged by the user in the user's own environment, ie, the user side environment.
  • the FPGA hardware is owned by the developer.
  • FPGA development will face some new security challenges, both to ensure that users can develop FPGAs, and to ensure the security of cloud hosts and prevent malicious attacks.
  • the embodiments of the present invention provide an FPGA cloud host development method and system, which are used to implement user development of an FPGA and prevent malicious attacks on the FPGA hardware.
  • an embodiment of the present invention provides an FPGA cloud host development method, which is applied to a development management platform, and includes:
  • the programming file obtained by the integrated processing is programmed into the FPGA.
  • the method before the programming of the programming file obtained by the integrated processing into the FPGA, the method further includes:
  • the programming file obtained by the integrated processing is programmed into the FPGA, including:
  • the programming file corresponding to the programming indication is programmed into the FPGA in response to a programming indication triggered by the development device.
  • an embodiment of the present invention provides an FPGA cloud host development method, which is applied to a development device, and includes:
  • an embodiment of the present invention provides an FPGA cloud host development system, including:
  • the development device is configured to design a design file, and upload the obtained design file to the development management platform, where the design file includes an actual constraint file corresponding to the FPGA;
  • the development management platform is configured to perform legality detection on the actual constraint file. If the legality detection is passed, the design file is comprehensively processed, and the programming file obtained by the comprehensive processing is programmed into the FPGA. .
  • the foregoing development management platform includes a processor and a memory for storing a program supporting the development management platform to execute the FPGA cloud host development method in the above first aspect, the processor being configured It is used to execute a program stored in the memory.
  • the development management platform may also include a communication interface for the development management platform to communicate with other devices or communication networks.
  • the embodiment of the invention provides a computer storage medium for storing computer software instructions used in the development management platform, which comprises a program for executing the FPGA cloud host development method in the first aspect.
  • the foregoing development device includes a processor and a memory for storing a program supporting the development device to execute the FPGA cloud host development method in the second aspect, the processor configured to Used to execute programs stored in the memory.
  • the development device can also include a communication interface for the communication device to communicate with other devices or communication networks.
  • An embodiment of the present invention provides another computer storage medium for storing computer software instructions for developing a device, which includes a program for executing the FPGA cloud host development method in the second aspect.
  • the FPGA cloud host development method and system provided by the embodiments of the present invention can be developed and designed by the user in the user-side development device to obtain a design file including the actual constraint file designed by the user for the FPGA, and then developed.
  • the device uploads the design file to the development management platform.
  • the development management platform ensures the security of the FPGA hardware by detecting the legality of the actual constraint file to avoid malicious attacks on the FPGA by changing the constraint file.
  • Embodiment 1 is a schematic structural diagram of Embodiment 1 of an FPGA cloud host development system according to an embodiment of the present invention
  • Embodiment 2 is a schematic structural diagram of Embodiment 2 of an FPGA cloud host development system according to an embodiment of the present invention
  • FIG. 3 is a flowchart of Embodiment 1 of an FPGA cloud host development method according to an embodiment of the present disclosure
  • Embodiment 4 is a flowchart of Embodiment 2 of an FPGA cloud host development method according to an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of a development management platform according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a development device according to an embodiment of the present invention.
  • the words “if” and “if” as used herein may be interpreted to mean “when” or “when” or “in response to determining” or “in response to detecting.”
  • the phrase “if determined” or “if detected (conditions or events stated)” may be interpreted as “when determined” or “in response to determination” or “when detected (stated condition or event) “Time” or “in response to a test (condition or event stated)”.
  • FIG. 1 is a schematic structural diagram of Embodiment 1 of an FPGA cloud host development system according to an embodiment of the present invention. As shown in FIG. 1 , the system includes:
  • Development equipment development management platform for remote communication connection with development equipment, and FPGA in FPGA cloud host.
  • the development device is a user-side development device
  • the development management platform is a network side or a cloud management platform, such as a server
  • the development device and the development management platform can be understood as a relationship between the client and the server, that is, development.
  • a client that supports user development can be set in the device.
  • the development device is selected by the user and is a device for FPGA development. Alternatively, it may be a user offline device, such as a user's own computer or a virtual machine of the FPGA cloud host. In summary, the user can perform FPGA design and development related work in the device, including code writing, constraint design, and viewing comprehensive reports.
  • the development device is used for the user to design the design file, and uploads the obtained design file to the development management platform, and the design file includes the actual constraint file corresponding to the FPGA.
  • the development management platform is used for the legality detection of the actual constraint file. If the legality detection is passed, the design file is comprehensively processed, and the programming file obtained by the comprehensive processing is written into the FPGA.
  • the development device is further configured to: receive a comprehensive report obtained by the integrated processing of the development management platform feedback; and send a programming instruction triggered by the comprehensive report to the development management platform.
  • the development management platform is further configured to: feed back the comprehensive report obtained by the integrated processing to the development device; and program the above-mentioned programming file obtained by the integrated processing into the FPGA according to the above-mentioned programming instruction.
  • the user writes the development files required by the user in the development device, and can compile and debug the written code, and finally form a design file, which can include the code written by the user and the actual
  • the constraint file of the design is called the actual constraint file.
  • the development device is further configured to: in response to the user-initiated startup development operation, send a development request to the development management platform to request the template constraint file.
  • the development management platform is further configured to: send the template constraint file to the development device in response to the development request.
  • the development management platform can be regarded as a unified management platform, which can assist different users to develop their respective FPGA cloud hosts. Therefore, the FPGA of the user can be provided in the development device.
  • the setting item of the cloud host identification information when the user fills out the setting item and triggers a preset control or menu item, it is considered that the user triggers the startup development operation, and thus the development device can carry the development request sent to the development management platform.
  • the identification information of the FPGA cloud host is such that the development management platform acquires the template constraint file of the FPGA in the FPGA cloud host based on the identification information, and feeds the obtained template constraint file to the development device.
  • the identifier information of the FPGA cloud host may be used as a storage index, and the template constraint file corresponding to the FPGA of the plurality of FPGA cloud hosts is pre-stored.
  • the function of the constraint file mentioned in the embodiment of the present invention is to define a chip pin to which an FPGA input and output signal is bound, that is, which pin of a certain signal is input from a certain signal of the FPGA, which tube of a certain signal from the FPGA Foot output.
  • the constraint file defines various clock relationships, level standards, etc. in the FPGA, as well as some other constraints.
  • the development management platform provides the template constraint file of the FPGA that the user needs to develop to the user through the development device, the user may modify, delete, add, etc. the template constraint file in the actual development process to form the actual design.
  • the actual constraint file, and these operations will damage the FPGA itself and its surrounding hardware and software systems. Therefore, in order to ensure the security of the FPGA and prevent malicious attacks by users, the user submits the design file to the development management through the development device. After the platform, the development management platform needs to check the legality of the design file, specifically the legality detection of the actual constraint file in the design file.
  • the development management platform may compare the template constraint file corresponding to the FPGA and the actual constraint file stored locally, and if the comparison result indicates that the template constraint file is consistent with the actual constraint file, determining that the actual constraint file passes the legal Sex detection.
  • the template constraint file is consistent with the actual constraint file, that is, the various constraints included in the two files are the same, for example, the actual constraint file constrains a signal from a certain input of the FPGA, and if the template constraint file is also the same Constraining the signal from this pin input, then the two files have the same signal input constraints on the pin.
  • the development management platform When the development management platform detects that the actual constraint file fails the legality detection, it may send an error prompt message to the development device, so that the user redesigns the design file.
  • the design file uploaded by the development device can be comprehensively processed. In actual application, the integrated processing can be realized by using the existing comprehensive tool. Therefore, the development management platform is developed. A comprehensive tool is set in it.
  • the comprehensive process includes three steps of analysis, synthesis and optimization.
  • the design file can be described by the Hardware Description Language (HDL).
  • the analysis uses the standard HDL grammar rules to analyze the HDL design files and correct the syntax errors.
  • the synthesis is based on the selected FPGA structure and device.
  • HDL and FPGA netlist files are logically integrated, and the design files are compiled into logical connection netlists composed of basic logic units such as AND gates, OR gates, NOT gates, RAMs, flip-flops, etc., instead of real gate-level circuits; optimization is The logic and area are logically optimized according to the user's design constraints to produce an optimized FPGA netlist file for use by the FPGA layout and routing tools. After the completion, a number of comprehensive reports and programming files can be output.
  • the comprehensive report includes, for example, a time series report, a power report, a temperature report, etc., and the burn-in file can be analogized to the executable file compiled by the application.
  • the report documents list the comprehensive status and comprehensive results, such as resource usage and integrated level information.
  • IP cores that is, third-party intellectual property cores.
  • These IP cores can be used by the user after authorization (purchase or other means).
  • the IP core is a module that implements a certain function. Users can directly call an IP core in the application code to implement the corresponding function, which is equivalent to directly using an existing function module to avoid repeated development. .
  • the third-party IP core can improve user development efficiency and avoid duplication of development, it is technically necessary to prevent users from exporting these IP cores to their own devices, because once they are spread out, users can provide IP cores to other unauthorized devices.
  • the user uses or spreads to the Internet, etc., causing the problem of "one person to buy, all to use”. Therefore, in order to ensure the security of the use of the third-party IP core, it is not spread to the unauthorized user.
  • a solution for protecting the third-party IP core is also provided.
  • the development management platform may obtain a third-party IP core available for user authorization in advance, and store the third-party IP core locally, that is, the third-party IP core available to the user is stored in the development management platform.
  • the setting item of the identifier information of the FPGA cloud host mentioned in the foregoing, the setting item of the user identifier may also be set in the development device, so that the development request may further include the user identifier, so that the development management platform may be based on the The user ID obtains the corresponding third-party IP core by maintaining a server with a third-party IP core.
  • the third-party IP core is stored in the development management platform without being exposed to the user, that is, not provided to the user to develop the device.
  • a third-party IP core When a third-party IP core needs to be used in the user development process, it can be used by calling. For example, the function description and input parameters of the third-party IP core available to the user can be provided to the user, so that the user can select the call according to the actual demand. Which third party IP core. Therefore, during the development process, when a third-party IP core needs to be invoked, it is only necessary to write the calling code of the third-party IP core in the design file, which is equivalent to declaring which third-party IP core needs to be called.
  • the development management platform is also used to: if the third-party IP core is invoked in the design file, the third-party IP core and the design file to be called are comprehensively processed, and the comprehensive processing is obtained in advance.
  • the defined non-sensitive comprehensive report is fed back to the development device, where the information of the called third-party IP core is not included in the non-sensitive comprehensive report.
  • the input of the integrated processing includes the called third-party IP core in addition to the design file.
  • the development management platform can determine whether the third-party IP core is invoked and which third-party IP core is invoked by analyzing whether the design file contains the name of the third-party IP core.
  • the comprehensive report in the comprehensive result that can be reversed or extracted from the third-party IP core is not provided to the user. Therefore, after the development management platform comprehensively processes the called third-party IP core and the design file, only the pre-defined non-sensitive comprehensive report in the comprehensive processing result is fed back to the development device, wherein the non-sensitive comprehensive report does not include the called The information of the third-party IP core, that is, the comprehensive report of the third-party IP core will not be reversed or extracted.
  • the protection of third-party IP cores can be achieved by not feeding back the third-party IP core and the comprehensive results of the third-party IP core information to the user.
  • the user can analyze the comprehensive report received by the development device to determine if the design file for the FPGA needs to be modified. If it needs to be modified, redesign the design file, and then re-trigger the uploading, legality detection, and synthesis of the above design files. If no modification is required, the user can trigger a programming instruction for the current design file by the development device, which means that which programming file corresponding to the design file needs to be programmed into the FPGA.
  • the identifier of the design file such as the name of the design file and the check box and the programming control corresponding to the design file
  • the development management platform can learn which programming file corresponds to which programming file the user wants to burn according to the design file identifier carried in the programming instruction, so that the programming file obtained by the comprehensive processing of the design file is programmed into the FPGA.
  • design files may be developed during the user development process. Different design files will be synthesized by the development management platform, and the development management platform will save the synthesized programming files corresponding to different design files. As for which programming file should be programmed into the FPGA, it can be selected by the user.
  • the FPGA cloud host development system may further include a virtual machine manager (hypervisor) corresponding to the FPGA cloud host for managing the FPGA cloud host, so that the development management platform can pass the
  • the virtual machine manager implements programming of the programming file to the FPGA.
  • the virtual machine manager is configured to receive the programming file sent by the development management platform, and execute the preset programming program to program the programming file into the FPGA.
  • the FPGA cloud host development system further includes: a user virtual machine having a data access link with the FPGA, configured to deploy code in the design file and access the FPGA through the data access link.
  • a user virtual machine is a virtual machine that is delivered to a user. The user can see the FPGA device in the virtual machine, deploy its own design code, and access the FPGA device through the data link.
  • the virtual machine manager manages the user virtual machine and the FPGA cloud host, and the user cannot enter the virtual machine manager, but the virtual machine manager does not expose the download link of the FPGA to the user virtual machine, so that the user cannot directly in the user virtual machine.
  • the download operation is initiated on the FPGA, that is, the user cannot directly write the programming file to the FPGA. Since the download link of the FPGA is not exposed to the user, the user cannot perform the download type operation on the FPGA, and only the access operation can be performed, thereby preventing the user from burning the programming file containing the malicious attack component into the FPGA.
  • the programming file that is programmed into the FPGA through the virtual machine manager comes from the comprehensive result of the design file after the legality detection, thereby preventing malicious attacks on the FPGA.
  • the user can develop and design the FPGA in the development device on the user side to obtain a design file containing the actual constraint file actually designed by the user for the FPGA, and then upload the design file to the development management platform through the development device.
  • the development management platform checks the legality of the actual constraint file to avoid malicious attacks on the FPGA by the user by changing the constraint file. Further, the development management platform feeds back the comprehensive report of the comprehensive processing result to the development device for the user to view through the comprehensive processing of the design file, and responds to the user's programming instruction for a certain design file or for a comprehensive report.
  • the programming file included in the corresponding comprehensive processing result is programmed into the FPGA, thereby ensuring the security of the FPGA hardware while realizing the development of the FPGA.
  • the user obtains the FPGA basic project through the development device, including project files, top-level files, constraint files, and the like.
  • the user can trigger the sending of the development request to the development management platform by executing the operation of starting the development in the development interface of the development device.
  • the development management platform can feed back to the user development device that the constraint file is included.
  • the FPGA-based project of the aforementioned template constraint file is for user development and use.
  • the user develops the project in his development device, including code writing, simulation, etc. of the application to obtain the design file.
  • the development management platform checks the legality of the design file submitted by the user. If not, returns the error message to the user, and returns to step b; if passed, proceeds to the next step.
  • the development management platform determines whether a third-party IP core is invoked in the user design file. If so, the third-party IP core and design files to be called will need to be integrated, and if not, the design files will be processed directly.
  • the user analyzes the combined results and decides whether to program (download) the FPGA. If not, return to step b to modify the FPGA design file. If yes, go to the next step.
  • the development management platform sends the programming file to be written to the virtual machine manager, and the virtual machine manager then calls the relevant driver to program the FPGA.
  • the development management platform notifies the user that the FPGA is successfully programmed, and the user starts to access the FPGA through the user virtual machine.
  • Embodiment 1 of an FPGA cloud host development method is a flowchart of Embodiment 1 of an FPGA cloud host development method according to an embodiment of the present invention.
  • the FPGA cloud host development method provided in this embodiment is used to implement user development of an FPGA in an FPGA cloud host, and the method is developed by the foregoing.
  • the development management platform in the system is executed, and the development management platform can be a server. As shown in FIG. 3, the method includes the following steps:
  • step 301 is an optional step.
  • the user can obtain the template constraint file by other means.
  • the user obtains the template constraint file through the FPGA cloud host by logging in to the FPGA cloud host purchased by the user.
  • the development management platform can compare the template constraint file stored in the local with the actual constraint file in the design file. If the comparison result indicates that the template constraint file is consistent with the actual constraint file, it is determined that the actual constraint file passes the legality detection, otherwise Failure to pass legality test.
  • a third-party IP core may be scheduled in the user's design file. Therefore, if a third-party IP core is invoked in the design file, the third-party IP core and the design file stored locally are processed comprehensively. Conversely, if the third-party IP core is not called, the design file is processed comprehensively.
  • the programming file obtained by the integrated processing can be directly written into the FPGA. It can also be handled as follows:
  • the programming file corresponding to the programming instruction is programmed into the FPGA, and the programming file is obtained through comprehensive processing.
  • the user can trigger a burning instruction for a design file if it is determined that the design file need not be further modified.
  • the development management platform writes the programming file corresponding to the corresponding design file to the FPGA based on the programming instruction.
  • the development management platform may transmit the programming file to a virtual machine manager corresponding to the FPGA cloud host, to program the programming file into the FPGA through the virtual machine manager.
  • the network side development management platform is used to remotely assist the user to develop the FPGA in the FPGA cloud host.
  • the legality detection of the user-uploaded design file is used to avoid the user's malicious attack on the FPGA hardware.
  • the third-party IP core that needs to be protected is not exposed to the user, and the comprehensive process is completed on the development management platform side. The sensitive part of the comprehensive result is not provided to the user, thereby realizing the protection of the third-party IP core.
  • the FPGA is programmed by the development management platform, which also prevents malicious attacks caused by the user directly burning the FPGA.
  • Embodiment 1 of an FPGA cloud host development method is a flowchart of Embodiment 1 of an FPGA cloud host development method according to an embodiment of the present invention.
  • the FPGA cloud host development method provided in this embodiment is used to implement user development of an FPGA in an FPGA cloud host, and the method is developed by the foregoing.
  • the user side development device in the system is executed. As shown in FIG. 4, the method includes the following steps:
  • the above steps 401-402 are optional steps.
  • the template constraint file may also be obtained by other means.
  • the user obtains the template constraint file through the FPGA cloud host by logging in to the FPGA cloud host purchased by himself.
  • the user obtains the required template constraint file through the interaction between the user development device and the development management platform for designing the design file.
  • the user may change the template constraint file, resulting in damage to the FPGA hardware. Therefore, the user's design file needs to be submitted to the development management platform for legality detection.
  • the comprehensive report refers to a non-sensitive comprehensive report.
  • the user can determine whether to modify the design file by analyzing the comprehensive report. If no modification is needed, the programming instruction for the design file can be triggered to instruct the development management platform to design the design file. The corresponding programming file is programmed into the FPGA.
  • the user can remotely develop the FPGA in the FPGA cloud host, which is simple and convenient.
  • the foregoing development management platform may be implemented as a server.
  • the development management platform may include a processor 11 and a memory 12.
  • the memory 12 is configured to store a program that supports the development management platform to execute the FPGA cloud host development method provided in any of the above embodiments, and the processor 11 is configured to execute a program stored in the memory 12.
  • the program includes one or more computer instructions, wherein the one or more computer instructions are executed by the processor 11 to implement the following steps:
  • the programming file corresponding to the programming instruction is programmed into the FPGA, and the programming file is obtained by the comprehensive processing.
  • the processor 11 is further configured to perform all or part of the foregoing method steps.
  • the structure of the development management platform may further include a communication interface 13 for the development management platform to communicate with other devices or communication networks, such as communication with user development devices.
  • an embodiment of the present invention provides a computer storage medium for storing computer software instructions used in a development management platform, and includes a program involved in executing the FPGA cloud host development method in the foregoing method embodiments.
  • the above development device is, for example, a PC, as shown in FIG. 6, the development device may include: a processor 21 and a memory 22.
  • the memory 22 is configured to store a program supporting the development device to execute the FPGA cloud host development method provided in any of the above embodiments, and the processor 21 is configured to execute the program stored in the memory 22.
  • the program includes one or more computer instructions, wherein the one or more computer instructions are executed by the processor 21 to implement the following steps:
  • the programming indication is used to indicate that the programming file corresponding to the design file is programmed into the FPGA.
  • the processor 21 is further configured to perform all or part of the foregoing method steps.
  • the structure of the development device may further include a communication interface 23 for the development device to communicate with other devices or communication networks, such as communication with the development management platform.
  • an embodiment of the present invention provides a computer storage medium for storing computer software instructions for developing a device, which includes a program for executing the FPGA cloud host development method in the foregoing method embodiments.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
  • a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
  • processors CPUs
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • the memory may include non-persistent memory, random access memory (RAM), and/or non-volatile memory in a computer readable medium, such as read only memory (ROM) or flash memory.
  • RAM random access memory
  • ROM read only memory
  • Memory is an example of a computer readable medium.
  • Computer readable media includes both permanent and non-persistent, removable and non-removable media.
  • Information storage can be implemented by any method or technology.
  • the information can be computer readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory. (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, Magnetic tape cartridges, magnetic tape storage or other magnetic storage devices or any other non-transportable media can be used to store information that can be accessed by a computing device.
  • computer readable media does not include temporary storage of computer readable media, such as modulated data signals and carrier waves.

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