WO2019091267A1 - 像素电路、像素电路驱动的方法和显示装置 - Google Patents

像素电路、像素电路驱动的方法和显示装置 Download PDF

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Publication number
WO2019091267A1
WO2019091267A1 PCT/CN2018/110639 CN2018110639W WO2019091267A1 WO 2019091267 A1 WO2019091267 A1 WO 2019091267A1 CN 2018110639 W CN2018110639 W CN 2018110639W WO 2019091267 A1 WO2019091267 A1 WO 2019091267A1
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Prior art keywords
read
signal
read control
period
line
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PCT/CN2018/110639
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English (en)
French (fr)
Inventor
丁小梁
董学
王海生
刘英明
李昌峰
刘伟
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/338,762 priority Critical patent/US11380264B2/en
Publication of WO2019091267A1 publication Critical patent/WO2019091267A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G09G2360/147—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen the originated light output being determined for each pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method of a pixel circuit, and a display device.
  • a pixel compensation unit based on an OLED (Organic Light Emitting Diode) display generally includes: a light sensing module for converting an optical signal emitted by the pixel unit into a corresponding electrical signal; and a read control module for reading the control line on the corresponding row The control of the read control signal controls the electrical signal to be transmitted to the corresponding column read line during the read period; and the data voltage compensation module is configured to compare the data voltage of the corresponding column data line according to the electrical signal Make compensation.
  • the above pixel compensation unit cannot avoid the influence of the gate line and the data line timing on the light sensing module, and cannot dynamically adjust the integration time, so that the compensation result is inaccurate.
  • the present disclosure provides a pixel circuit including a plurality of rows of gate lines, a plurality of rows of read control lines, a plurality of rows and columns of pixel unit circuits, and a driving module; the pixel unit circuit includes a pixel compensation unit; and the pixel compensation unit and corresponding The row read control line connection; the driving module includes a gate driving circuit and a signal generating unit connected to the plurality of rows of gate lines.
  • the signal generating unit is connected to the gate driving circuit and the pixel compensation unit, and configured to generate a read control signal and a gate driving control signal, and transmit the read control signal to a corresponding row read control line. Transmitting the gate driving control signal to the gate driving circuit; the gate driving circuit is configured to generate a plurality of gate driving signals according to the gate driving control signal to control the reading period
  • the plurality of rows of gate lines are all closed.
  • the pixel compensation unit includes: a light sensing module, configured to convert an optical signal emitted by the pixel unit into a corresponding electrical signal; and the signal generating unit is configured to generate the reading according to the electrical signal. control signal.
  • the pixel compensation unit includes a read control module; the pixel circuit includes a plurality of columns of read lines; the read control module is coupled to a corresponding column read line; the electrical signal is a charge signal, and the signal is generated
  • the unit is specifically configured to determine a corresponding integration time according to the amount of charge indicated by the charge signal, and generate a corresponding read control signal according to the integration time; the integration time is controlled by the read control signal to control the read control module Transmitting the electrical signal to a time interval between a first time and a second time of the corresponding column read line; the second time is when the read control signal is adjacent to the end of the read time period
  • the timing at which the read control module begins to transmit the electrical signal to the corresponding column read line is controlled at a time.
  • the present disclosure also provides a driving method of the above pixel circuit, including:
  • the signal generating unit generates a read control signal and a gate drive control signal, and transmits the read control signal to a corresponding row read control line, and transmits the gate drive control signal to the gate drive circuit;
  • the gate driving circuit generates a plurality of gate driving signals according to the gate driving control signal to control that the plurality of gate lines are turned off during the reading period.
  • the step of generating the read control signal by the signal generating unit specifically includes: the signal generating unit generating the read control signal according to the electrical signal; the electrical signal is a light sensing module pair pixel included in the pixel compensation unit An electrical signal obtained by converting an optical signal emitted by a unit.
  • the pixel compensation unit includes a read control module; the pixel circuit includes a plurality of columns of read lines; the read control module is coupled to a corresponding column read line; the electrical signal is a charge signal, and the signal generation unit is The step of generating the read control signal by the electrical signal specifically includes: the signal generating unit determining a corresponding integration time according to the amount of charge indicated by the charge signal, and generating a corresponding read control signal according to the integration time; The integration time is a time during which the read control signal controls the interval between the first time and the second time at which the read control module starts transmitting the electrical signal to the corresponding column read line; the second time is The read control signal next controls the timing at which the read control module begins to transmit the electrical signal to the corresponding column read line next to the end of the read period.
  • the first charge amount indicated by the first charge signal is greater than the second charge amount indicated by the second charge signal
  • the first integration time determined by the signal generating unit according to the first charge amount is smaller than the signal generating unit according to the signal generating unit The second amount of time determined by the second amount of charge.
  • the pixel compensation unit includes a light sensing module; the pixel compensation unit includes a read control module; the pixel circuit includes a plurality of columns of read lines; the read control module is coupled to a corresponding column read line; The nth read period is set between a period in which the nth row gate line is open and a period in which the n+1th gate line is turned on; and an Nth read time is set in the adjacent two driving periods.
  • a segment is a number of rows of gate lines included in the pixel circuit; N is a positive integer;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes:
  • the signal generating unit controls to output a corresponding read control signal to the nth row read control line, so that all pixel compensation units included in the nth row included in the pixel circuit are included in the nth read period
  • the read control module is turned on to turn on the connection between the light sensing module included in the pixel compensation unit located in the nth row and the corresponding column read line;
  • the signal generating unit controls to output a corresponding read control signal to the Nth row read control line, so that all pixel compensation units included in the Nth row included in the pixel circuit are included in the Nth read period
  • the read control module is turned on to turn on the connection between the light sensing module included in the pixel compensation unit located in the Nth row and the corresponding column read line;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes: the gate driving circuit according to the gate Driving a control signal to generate a plurality of gate driving signals to control, in the nth read period and the Nth read period, all gate lines included in the pixel circuit are turned off; n is a positive integer, n +1 is less than or equal to N.
  • the pixel compensation unit includes a light sensing module; the pixel compensation unit includes a read control module; the pixel circuit includes a plurality of columns of read lines; the read control module is coupled to a corresponding column read line;
  • the nth read period is set between a period in which the gate line of the nth row is turned on and a period in which the gate line of the n+1th row is turned on, and the period in which the gate line is opened in the n+1th row and the nth
  • the n+1th read period is set between the periods in which the +2 row gate lines are open; the Nth read period is set in the adjacent two drive periods; N is the gate line included in the pixel circuit Number of rows; N is a positive integer;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line includes:
  • the signal generating unit outputs a corresponding read control signal to the nth row read control line such that the pixel circuit includes the nth read period and the (n+1)th read period
  • All the pixel compensation units located in the nth row include a read control module that is turned on to turn on a connection between the light sensing module included in the pixel compensation unit of the nth row and the corresponding column read line;
  • the signal generating unit outputs a corresponding read control signal to the Nth row read control line such that the pixel circuit includes the Nth row in the Nth read period and the first read period
  • All of the pixel compensation units include a read control module that is turned on to turn on a connection between the light sensing module included in the pixel compensation unit located in the Nth row and the corresponding column read line;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes: the gate driving circuit according to the gate Driving a control signal to generate a plurality of gate driving signals to control, in the nth read period and the Nth read period, all gate lines included in the pixel circuit are turned off;
  • n is a positive integer and n+1 is less than or equal to N.
  • the pixel compensation unit includes a light sensing module; the pixel compensation unit includes a read control module; the pixel circuit includes a plurality of columns of read lines; the read control module is coupled to a corresponding column read line; A blank phase is set between the display phases of the neighbors; the blank phase includes M read time segments set in sequence; M is the number of rows of read control lines included in the pixel circuit; M is a positive integer;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes:
  • the gate driving circuit generates a plurality of gate driving signals according to the gate driving control signal to control and control that all gate lines included in the pixel circuit are turned off during the blanking phase;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes: the signal generating unit outputs a corresponding read control signal to the a-th row read control line, so that a blank reading stage includes a reading period of the first reading period, wherein all of the pixel compensation units included in the pixel row include a read control module that is turned on to turn on the pixel compensation unit included in the a row a connection between the light sensing module and the corresponding column read line;
  • a is a positive integer less than or equal to M.
  • the pixel compensation unit includes a light sensing module; the pixel compensation unit includes a read control module; the pixel circuit includes a plurality of columns of read lines; the read control module is coupled to a corresponding column read line; A blank period is set between display periods;
  • the blank period includes M read time periods set in sequence; M is the number of rows of read control lines included in the pixel circuit; M is a positive integer;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes:
  • the gate driving circuit generates a plurality of gate driving signals according to the gate driving control signal to control and control that all gate lines included in the pixel circuit are turned off during the blank period;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes:
  • the signal generating unit outputs a corresponding read control signal to the b-th row read control line such that the pixel circuit includes all of the b-th row included in the b-th row read period included in the blank period
  • the pixel control unit includes a read control module that is turned on to turn on a connection between the light sensing module included in the pixel compensation unit of the bth row and the corresponding column read line;
  • b is a positive integer less than or equal to M.
  • the present disclosure also provides a display device including the above pixel circuit.
  • 1A is a circuit diagram of a pixel compensation unit
  • FIG. 1B is a structural diagram of a driving module of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 3 is a timing chart corresponding to a first embodiment of a driving method of a pixel circuit according to the present disclosure
  • FIG. 4 is a timing diagram corresponding to a second embodiment of a driving method of a pixel circuit according to the present disclosure
  • FIG. 5 is a timing chart corresponding to a third embodiment of a driving method of a pixel circuit according to the present disclosure
  • FIG. 6 is a timing chart corresponding to a fourth embodiment of a driving method of a pixel circuit according to the present disclosure.
  • FIG. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel compensation unit includes a read control transistor MS, a photodiode DS, a gate of the MS connected to a corresponding read control line Sense, a source of the MS connected to the read line RL, and an anode of the photodiode.
  • the low level input is VSS connected and the cathode of the photodiode is connected to the drain of the MS.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the pixel circuit of the embodiment of the present disclosure includes a multi-row gate line, a multi-row read control line, a multi-row multi-column pixel unit circuit, and a driving module; the pixel unit circuit includes a pixel compensation unit.
  • the driving module includes a gate driving circuit connected to the plurality of rows of gate lines.
  • the drive module further includes a signal generating unit. a signal generating unit is connected to the gate driving circuit and the pixel compensation unit for generating a read control signal and a gate driving control signal, and transmitting the read control signal to a corresponding row read control line, The gate drive control signal is transmitted to the gate drive circuit.
  • the gate driving circuit is configured to generate a plurality of gate driving signals according to the gate driving control signal to control that the plurality of rows of gate lines are turned off during the reading period.
  • the driving module of the pixel circuit includes a signal generating unit, and the read control signal and the gate driving control signal generated by the signal generating unit can make the display driving and the compensation based on the brightness of the pixel unit not simultaneously Therefore, the influence of the gate line and the data line timing on the photovoltaic module can be avoided.
  • the pixel circuit 100 may include a plurality of rows of gate lines 110, a plurality of columns of data lines 120, a plurality of rows of read control lines 130, a plurality of columns of read lines 140, and a plurality of rows and columns of pixels.
  • the pixel unit circuit 150 in the same row is connected to the same row gate line 110 and the same row read control line 130; the pixel unit circuits in the same column are connected to the same column data line and the same column read line;
  • the pixel unit circuit 150 includes a pixel compensation unit 13 and a pixel unit 154.
  • the pixel compensation unit 13 includes a light sensing module 132 for converting an optical signal emitted by the pixel unit 154 into a corresponding electrical signal, and a read control module 134 for reading the control line 130 on the corresponding row.
  • the control of the read control signal controls the electrical signal to be transmitted to the corresponding column read line 140 during the read period; and the data voltage compensation module 136.
  • the driving module 200 of the pixel circuit includes a gate driving circuit 11 connected to the plurality of rows of gate lines 110.
  • the drive module further includes a signal generating unit 12.
  • the signal generating unit 12 is connected to the gate driving circuit 11 and the pixel compensating unit 13.
  • the signal generating unit 12 is configured to generate a read control signal SW and a gate drive control signal SGC, and transmit the read control signal SW to the pixel compensation through a row read control line 130 corresponding to the pixel compensation unit 13
  • the unit 13 transmits the gate drive control signal SGC to the gate drive circuit 11.
  • the gate driving circuit 11 is configured to generate a plurality of gate driving signals according to the gate driving control signal to control that the plurality of rows of gate lines are turned off during the reading period.
  • One of the gate drive signals corresponds to one row of the gate lines.
  • the driving module of the pixel circuit can enable the display driving and the pixel-based light-emitting luminance by setting the signal generating unit 12 and using the read control signal and the gate driving control signal generated by the signal generating unit 12 The compensation is not performed at the same time, so that the influence of the gate line and the data line timing on the light sensing module can be avoided.
  • the signal generating unit 12 is specifically configured to generate the read control signal according to an electrical signal.
  • the electrical signal may be a charge signal
  • the signal generating unit is specifically configured to determine a corresponding integration time according to the amount of charge indicated by the charge signal, and generate a corresponding read control signal according to the integration time.
  • the integration time is a time during which the read control signal controls the interval between the first time and the second time at which the read control module 134 begins transmitting the electrical signal to the corresponding column read line 140.
  • the second time is a timing at which the read control signal 134 next time the read control signal 134 starts to transmit the electrical signal to the corresponding column read line after the end of the read time period.
  • the driving module of the pixel circuit can determine the integration time by the amount of charge.
  • the integration time is short.
  • the integration time is long, which can be dynamically adjusted according to the amount of charge. Integration time to accommodate light intensity detection in large dynamic range.
  • the light sensing module 132 senses the optical signal emitted by the corresponding pixel unit 154 and converts the optical signal into a current signal, and the amount of charge indicated by the charge signal is stored in a parasitic capacitance (eg, when pixel compensation When the unit 13 is configured as shown in FIG.
  • the light sensing module 132 may be a photodiode DS
  • the read control module 134 may be a read control transistor MS
  • the parasitic capacitance is a cathode of the photodiode DS and the photodiode
  • the charge stored in the parasitic capacitance is transferred to the read line.
  • the driving method of the pixel circuit uses the driving module of the pixel circuit to drive the pixel circuit. As shown in FIG. 2, the driving method of the pixel circuit includes:
  • the signal generating unit generates a read control signal and a gate drive control signal, and transmits the read control signal to a corresponding row read control line, and transmits the gate drive control signal to the gate drive circuit;
  • the gate driving circuit generates a plurality of gate driving signals according to the gate driving control signal to control that the plurality of gate lines are turned off during the reading period.
  • the driving method of the pixel circuit according to the embodiment of the present disclosure generates the read control signal and the gate drive control signal by the signal generating unit, so that the display driving and the compensation of the light-emitting luminance based on the pixel unit can be performed at different times, thereby avoiding the gate line.
  • the pixel circuit includes a plurality of rows of gate lines, a plurality of columns of data lines, a plurality of rows of read control lines, a plurality of columns of read lines, and a plurality of rows and columns of pixel unit circuits; and the pixel unit circuits of the same row are the same
  • the row gate line and the same row read control line are connected; the pixel unit circuits in the same column are connected to the same column data line and the same column read line;
  • the pixel unit circuit includes a pixel compensation unit and a pixel unit;
  • the pixel compensation unit includes: a light sensing module configured to convert an optical signal emitted by the pixel unit into a corresponding electrical signal; and a read control module connected to the corresponding row read control line and the corresponding column read line, Controlling the electrical signal to the corresponding column read line during the read time period under control of the read control signal on the corresponding row read control line; and, the data voltage compensation module.
  • the step of generating the read control signal by the signal generating unit specifically includes: the signal generating unit generating the read control signal according to the electrical signal.
  • the electrical signal may be a charge signal
  • the step of the signal generating unit generating the read control signal according to the electrical signal may specifically include: the amount of charge indicated by the signal generating unit according to the charge signal To determine a corresponding integration time, and generate a corresponding read control signal according to the integration time;
  • the integration time is a time during which the read control signal controls the interval between the first time and the second time when the read control module starts transmitting the electrical signal to the corresponding column read line;
  • the second time is a time when the read control signal next controls the read control module to start transmitting the electrical signal to the corresponding column read line next time after the end of the read period.
  • the first charge amount indicated by the first charge signal is greater than the second charge amount indicated by the second charge signal, and the first integration time determined by the signal generating unit according to the first charge amount is smaller than the signal Generating a second integration time determined by the second charge amount.
  • the driving method of the pixel circuit according to the embodiment of the present disclosure can determine the integration time by the amount of charge.
  • the integration time is short.
  • the integration time is long, so that the integral can be dynamically adjusted according to the amount of charge. Time to adapt to the large dynamic range of light intensity detection.
  • a period between a period in which the nth gate line is turned on and a period in which the n+1th gate line is turned on is set in one driving period.
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes:
  • the signal generating unit controls to output a corresponding read control signal to the nth row read control line, so that all pixel compensation units included in the nth row included in the pixel circuit are included in the nth read period
  • the read control module is turned on to turn on the connection between the light sensing module included in the pixel compensation unit located in the nth row and the corresponding column read line;
  • the signal generating unit controls to output a corresponding read control signal to the Nth row read control line, so that all pixel compensation units included in the Nth row included in the pixel circuit are included in the Nth read period
  • the read control module is turned on to turn on the connection between the light sensing module included in the pixel compensation unit located in the Nth row and the corresponding column read line;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes: the gate driving circuit according to the gate Driving a control signal to generate a plurality of gate driving signals to control, in the nth read period and the Nth read period, all gate lines included in the pixel circuit are turned off; n is a positive integer, n +1 is less than or equal to N.
  • the first embodiment of the driving method of the pixel circuit according to the present disclosure is a single row idle detecting mode; as shown in FIG. 3, in the first driving period T1 (when the gate driving circuit includes an N-stage shift register unit, When driving the N-row gate line, a driving period is the time for scanning the N-row gate line, and N is an integer greater than 3)
  • the first read period t11 in the first drive period T1 is set between the time period in which the potential of the gate drive signal of the gate 2 is high) (that is, the first line read control line Sense1 outputs a high level) period);
  • the second read period in the first drive period T1 is set between the time period in which the potential of the gate drive signal of the gate 3 is high (that is, the time at which the second line read control line Sense2 outputs the high level) segment);
  • the label of GateN is the Nth row gate line, and the waveform corresponding to GateN is the waveform of the gate driving signal for driving GateN;
  • the period in which the first row gate line Gate1 is turned on (that is, the period in which the potential for driving the gate driving signal of Gate1 is at the high level) and the second row gate line Gate2 are turned on.
  • the first reading period t21 in the second driving period T2 is set between the time period (that is, the period in which the potential for driving the gate driving signal of Gate 2 is high) (that is, the first line reading)
  • the control line Sense1 outputs a high level period);
  • the second read period in the second drive period T2 is set between the time period in which the potential of the gate drive signal of the gate 3 is high (that is, the time at which the second line read control line Sense2 outputs the high level) segment);
  • the integration time TI is the time interval between the time at which t11 ends and the time at which t21 starts, that is, equal to 1 frame time (also That is, the duration of a drive cycle).
  • charge reading is performed in a time gap of every two lines of gate line scanning, in order to accommodate detection of a large dynamic range (OLED light emission)
  • the grayscale voltage is between 0 and 255, it may vary greatly. It is necessary to dynamically adjust the exposure time according to the read value. If the amount of charge read is too small, the integration time is increased. If the amount of charge read is too large or even saturated, the integration time is reduced.
  • a period between a period in which the nth gate line is turned on and a period in which the n+1th gate line is turned on is set in one driving period.
  • the Nth read period is set in the driving cycle; N is the number of rows of the gate lines included in the pixel circuit; N is a positive integer;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes:
  • the signal generating unit outputs a corresponding read control signal to the nth row read control line such that the pixel circuit includes the nth read period and the (n+1)th read period
  • All the pixel compensation units located in the nth row include a read control module that is turned on to turn on a connection between the light sensing module included in the pixel compensation unit of the nth row and the corresponding column read line;
  • the signal generating unit outputs a corresponding read control signal to the Nth row read control line such that the pixel circuit includes the Nth row in the Nth read period and the first read period
  • All of the pixel compensation units include a read control module that is turned on to turn on a connection between the light sensing module included in the pixel compensation unit located in the Nth row and the corresponding column read line;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes: the gate driving circuit according to the gate Driving a control signal to generate a plurality of gate driving signals to control, in the nth read period and the Nth read period, all gate lines included in the pixel circuit are turned off;
  • n is a positive integer and n+1 is less than or equal to N.
  • a second embodiment of the driving method of the pixel circuit according to the present disclosure is another single-line idle detecting mode; as shown in FIG. 4, in the first driving period T1 (when the gate driving circuit includes an N-stage shift register unit) When driving the N-row gate line, a driving period is the time for scanning the N-row gate line, and N is an integer greater than 3)
  • a first reading period t1 in the first driving period T1 is set between a period in which the first row gate line Gate1 is open and a period in which the second row gate line Gate2 is on, and the second row gate line Gate2 is turned on.
  • a second reading period t12 in the first driving period T1 is disposed between the time period and the period in which the third row gate line Gate3 is open;
  • the first line of the read control line Sense1 outputs a high level
  • the integration time TI is a period from the end of t11 to the beginning of t12, that is, one line of time.
  • a blank phase is disposed between two adjacent display stages; the blank phase includes M read time periods sequentially set; a number of rows of read control lines included in the pixel circuit; M is a positive integer;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes:
  • the gate driving circuit generates a plurality of gate driving signals according to the gate driving control signal to control and control that all gate lines included in the pixel circuit are turned off during the blanking phase;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes: the signal generating unit outputs a corresponding read control signal to the a-th row read control line, so that The blank phase includes a ith read period, and all of the pixel compensation units included in the pixel circuit include a read control module that is turned on to turn on the pixel compensation unit included in the a row. a connection between the light sensing module and the corresponding column read line;
  • a is a positive integer less than or equal to M.
  • the gate driving circuit sequentially scans a plurality of rows of gate lines in one display phase.
  • a third embodiment of the driving method of the pixel circuit according to the present disclosure is a multi-line idle detection mode; as shown in FIG. 5,
  • a blank phase is disposed between two adjacent display phases; the blank phase includes M read time segments sequentially set; M is a number of rows of read control lines included in the pixel circuit;
  • the TB1 and M line read control lines are sequentially turned on (that is, each line of the read control lines sequentially outputs a high level to sequentially control the corresponding read control module to turn on the corresponding light sensing module and corresponding reading.
  • Sense1 is the first line read control line
  • Sense2 is the second line read control line
  • SenseM is the Mth line read control line
  • the m+1th row gate line Getem+1, the m+2th gate line Gatem+2, ..., the Nth row gate line GateN are sequentially driven (N is a strip of the gate line included in the pixel circuit And then sequentially driving the first row gate line Gate1, the second row gate line Gate2, ... the mth gate line tellem (m is an integer greater than 2);
  • the M line read control lines are sequentially turned on (that is, each line of the read control lines sequentially outputs a high level to sequentially control the corresponding read control module to turn on the corresponding light sensing module and the corresponding read line. the connection between).
  • the time period when Sense1 first outputs a high level is the first reading period t11
  • the time period when Sense1 outputs the high level for the second time is the second reading period t12
  • the integration time TI is equal to t11. The time between the end time and the time t12 starts.
  • a third embodiment of the driving method shown in FIG. 5 is a long H blank mode, that is, a read period for reading data is inserted after driving of a plurality of rows of gate lines.
  • a blank period is set between two adjacent display periods
  • the blank period includes M read time periods set in sequence; M is the number of rows of read control lines included in the pixel circuit; M is a positive integer;
  • the step of the gate driving circuit generating a plurality of gate driving signals according to the gate driving control signal to control the multi-row gate lines in the reading period includes:
  • the gate driving circuit generates a plurality of gate driving signals according to the gate driving control signal to control and control that all gate lines included in the pixel circuit are turned off during the blank period;
  • the step of the signal generating unit transmitting the read control signal to the corresponding row read control line specifically includes:
  • the signal generating unit outputs a corresponding read control signal to the b-th row read control line such that the pixel circuit includes all of the b-th row included in the b-th row read period included in the blank period
  • the pixel control unit includes a read control module that is turned on to turn on a connection between the light sensing module included in the pixel compensation unit of the bth row and the corresponding column read line;
  • b is a positive integer less than or equal to M.
  • a fourth embodiment of the driving method of the pixel circuit of the present disclosure is a multi-frame idle detection mode; as shown in FIG. 6, a blank period is set between two adjacent display periods;
  • the blank period includes M read time periods set in sequence; M is the number of rows of read control lines included in the pixel circuit; M is an integer;
  • all the row gate lines included in the pixel circuit are sequentially driven during a display period, and all rows included in the pixel circuit are included in the blank period.
  • the read control line sequentially outputs a high level;
  • the display period may also be a frame display time, and a blank period is set between two adjacent frame display times;
  • the first row gate line Gate1, the second row gate line Gate2, ..., the Nth row gate line GateN sequentially output a high level
  • the first row read control line Sense1, the second row read control line Sense2, ..., the Mth row read control line SenseM sequentially outputs a high level
  • the first row gate line Gate1, the second row gate line Gate2, ..., the Nth row gate line GateN sequentially output a high level
  • the first line read control Line Sense1, second line read control line Sense2, ..., Mth line read control line SenseM sequentially output high level
  • the time period during which the Sense1 outputs a high level is the first read time period t11
  • the time period during which the Sense1 outputs a high level is the second read time period t12
  • the integration time TI is the time interval between the time at which t11 ends and the time at which t12 starts.
  • the maximum integration time can be long, reaching one frame or even several frame times.
  • the display device includes a pixel circuit, and further includes a driving module of the pixel circuit described above.

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Abstract

本公开提供一种像素电路、像素电路的驱动方法和显示装置。所述像素电路的驱动模组包括：信号生成单元，将读取控制信号传送至相应行读取控制线，将栅极驱动控制信号传送至栅极驱动电路；所述栅极驱动电路用于根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭；一所述栅极驱动信号对应于一行所述栅线。

Description

像素电路、像素电路驱动的方法和显示装置
相关申请的交叉引用
本申请主张在2017年11月7日在中国提交的中国专利申请号No.201711083776.4的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路、像素电路的驱动方法和显示装置。
背景技术
基于OLED(有机发光二极管)显示的像素补偿单元一般包括：光感模块，用于将像素单元发出的光信号转换为相应的电信号；读取控制模块，用于在相应行读取控制线上的读取控制信号的控制下控制在读取时间段将所述电信号传送至相应列读取线；以及，数据电压补偿模块，用于根据所述电信号对相应列数据线上的数据电压进行补偿。然而，上述像素补偿单元不能避免栅线与数据线时序对光感模块的影响，并且不能动态调节积分时间，使得补偿结果不准确。
发明内容
本公开提供了一种像素电路包括多行栅线、多行读取控制线、多行多列像素单元电路和驱动模组；所述像素单元电路包括像素补偿单元；所述像素补偿单元与相应行读取控制线连接；所述驱动模组包括与所述多行栅线连接的栅极驱动电路以及信号生成单元。其中，信号生成单元与所述栅极驱动电路和所述像素补偿单元连接，用于生成读取控制信号和栅极驱动控制信号，将所述读取控制信号传送至相应行读取控制线，将所述栅极驱动控制信号传送至所述栅极驱动电路；所述栅极驱动电路用于根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述读取时间段所述多行栅线都关闭。
实施时，所述像素补偿单元包括：光感模块，用于将所述像素单元发出 的光信号转换为相应的电信号；所述信号生成单元具体用于根据所述电信号生成所述读取控制信号。
实施时，所述像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；所述电信号为电荷信号，所述信号生成单元具体用于根据所述电荷信号指示的电荷量来确定相应的积分时间，并根据该积分时间生成相应的读取控制信号；所述积分时间为所述读取控制信号控制读取控制模块开始将所述电信号传送至相应列读取线的第一时刻与第二时刻之间间隔的时间；所述第二时刻为在所述读取时间段结束后所述读取控制信号相邻下一次控制所述读取控制模块开始将所述电信号传送至相应列读取线的时刻。
本公开还提供了一种上述像素电路的驱动方法，包括：
信号生成单元生成读取控制信号和栅极驱动控制信号，将所述读取控制信号传送至相应行读取控制线，将所述栅极驱动控制信号传送至栅极驱动电路；
栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭。
实施时，所述信号生成单元生成读取控制信号步骤具体包括：所述信号生成单元根据所述电信号生成所述读取控制信号；所述电信号为像素补偿单元包括的光感模块对像素单元发出的光信号进行转换得到的电信号。
实施时，像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；所述电信号为电荷信号，所述信号生成单元根据所述电信号生成所述读取控制信号步骤具体包括：所述信号生成单元根据所述电荷信号指示的电荷量来确定相应的积分时间，并根据该积分时间生成相应的读取控制信号；所述积分时间为所述读取控制信号控制所述读取控制模块开始将所述电信号传送至相应列读取线的第一时刻与第二时刻之间间隔的时间；所述第二时刻为在所述读取时间段结束后所述读取控制信号相邻下一次控制所述读取控制模块开始将所述电信号传送至相应列读取线的时刻。
实施时，第一电荷信号指示的第一电荷量大于第二电荷信号指示的第二 电荷量，所述信号生成单元根据所述第一电荷量确定的第一积分时间小于所述信号生成单元根据所述第二电荷量确定的第二积分时间。
实施时，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在一驱动周期内，在第n行栅线打开的时间段和第n+1行栅线打开的时间段之间设置有第n读取时间段；在相邻的两驱动周期内设置有第N读取时间段；N为所述像素电路包括的栅线的行数；N为正整数；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
所述信号生成单元控制向第n行读取控制线输出相应的读取控制信号，以使得在所述第n读取时间段，所述像素电路包括的位于第n行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第n行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述信号生成单元控制向第N行读取控制线输出相应的读取控制信号，以使得在所述第N读取时间段，所述像素电路包括的位于第N行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第N行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述第n读取时间段和所述第N读取时间段，所述像素电路包括的所有栅线都关闭；n为正整数，n+1小于或等于N。
实施时，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在一驱动周期内，在第n行栅线打开的时间段和第n+1行栅线打开的时间段之间设置有第n读取时间段，在第n+1行栅线打开的时间段和第n+2行栅线打开的时间段之间设置有第n+1读取时间段；在相邻的两驱动周期内设置有第N读取时间段；N为所述像素电路包括的栅线的行数；N为正整数；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具 体包括：
所述信号生成单元向第n行读取控制线输出相应的读取控制信号，以使得在所述第n读取时间段和所述第n+1读取时间段，所述像素电路包括的位于第n行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第n行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述信号生成单元向第N行读取控制线输出相应的读取控制信号，以使得在所述第N读取时间段和第一读取时间段，所述像素电路包括的位于第N行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第N行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述第n读取时间段和所述第N读取时间段，所述像素电路包括的所有栅线都关闭；
n为正整数，n+1小于或等于N。
实施时，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在两个相邻的显示阶段之间设置有一空白阶段；所述空白阶段包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为正整数；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制控制在所述空白阶段内所述像素电路包括的所有栅线都关闭；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：所述信号生成单元向第a行读取控制线输出相应的读取控制信号，以使得在所述空白阶段包括的第a读取时间段，所述像素电路包括的位于第a行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第a行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
a为小于或等于M的正整数。
实施时，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在两相邻显示周期之间设置有一空白周期；
所述空白周期包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为正整数；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制控制在所述空白周期内所述像素电路包括的所有栅线都关闭；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
所述信号生成单元向第b行读取控制线输出相应的读取控制信号，以使得在所述空白周期包括的第b行读取时间段，所述像素电路包括的位于第b行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第b行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
b为小于或等于M的正整数。
本公开还提供了一种显示装置，包括上述像素电路。
附图说明
图1A是像素补偿单元的电路图；
图1B是本公开实施例所述的像素电路的驱动模组的结构图；
图2是本公开实施例所述的像素电路的驱动方法的流程图；
图3是本公开所述的像素电路的驱动方法的第一具体实施例对应的时序图；
图4是本公开所述的像素电路的驱动方法的第二具体实施例对应的时序图；
图5是本公开所述的像素电路的驱动方法的第三具体实施例对应的时序图；
图6是本公开所述的像素电路的驱动方法的第四具体实施例对应的时序 图；及
图7是本公开实施例所述的像素电路的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图1A所示，像素补偿单元包括读取控制晶体管MS、光敏二极管DS，MS的栅极与相应的读取控制线Sense连接，MS的源极与读取线RL连接，光敏二极管的阳极与低电平输入端VSS连接，光敏二极管的阴极与MS的漏极连接。然而，上述像素补偿单元不能避免栅线与数据线时序对光感模块的影响，并且不能动态调节积分时间，使得补偿结果不准确。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括多行栅线、多行读取控制线、多行多列像素单元电路和驱动模组；所述像素单元电路包括像素补偿单元。所述驱动模组包括与所述多行栅线连接的栅极驱动电路。所述驱动模组还包括信号生成单元。信号生成单元与所述栅极驱动电路和所述像素补偿单元连接，用于生成读取控制信号和栅极驱动控制信号，将所述读取控制信号传送至相应行读取控制线，将所述栅极驱动控制信号传送至所述栅极驱动电路。
所述栅极驱动电路用于根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述读取时间段所述多行栅线都关闭。
本公开实施例所述的像素电路的驱动模组包括信号生成单元，该信号生成单元生成的读取控制信号和栅极驱动控制信号能够使得显示驱动和基于像素单元的发光亮度的补偿不同时进行，从而能够避免栅线与数据线时序对光 电模块的影响。
在具体实施时，如图7所示，所述像素电路100可以包括多行栅线110、多列数据线120、多行读取控制线130、多列读取线140、多行多列像素单元电路150和驱动模组200。其中，位于同一行的像素单元电路150与同一行栅线110和同一行读取控制线130连接；位于同一列的像素单元电路与同一列数据线和同一列读取线连接；
所述像素单元电路150包括一像素补偿单元13和一像素单元154。
所述像素补偿单元13包括：光感模块132，用于将所述像素单元154发出的光信号转换为相应的电信号；读取控制模块134，用于在相应行读取控制线130上的读取控制信号的控制下控制在读取时间段将所述电信号传送至相应列读取线140；以及，数据电压补偿模块136。
如图1B所示，本公开实施例所述的像素电路的驱动模组200包括与所述多行栅线110连接的栅极驱动电路11。所述驱动模组还包括信号生成单元12。
信号生成单元12与所述栅极驱动电路11和像素补偿单元13连接。信号生成单元12用于生成读取控制信号SW和栅极驱动控制信号SGC，将所述读取控制信号SW通过与所述像素补偿单元13对应的行读取控制线130传送至所述像素补偿单元13，将所述栅极驱动控制信号SGC传送至所述栅极驱动电路11。
所述栅极驱动电路11用于根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述读取时间段所述多行栅线都关闭。一所述栅极驱动信号对应于一行所述栅线。
本公开实施例所述的像素电路的驱动模组通过设置信号生成单元12，并利用该信号生成单元12生成的读取控制信号和栅极驱动控制信号能够使得显示驱动和基于像素单元的发光亮度的补偿不同时进行，从而能够避免栅线与数据线时序对光感模块的影响。
在实际操作时，所述信号生成单元12具体用于根据电信号生成所述读取控制信号。
在具体实施时，所述电信号可以为电荷信号，所述信号生成单元具体用于根据所述电荷信号指示的电荷量来确定相应的积分时间，并根据该积分时 间生成相应的读取控制信号。
所述积分时间为所述读取控制信号控制所述读取控制模块134开始将所述电信号传送至相应列读取线140的第一时刻与第二时刻之间间隔的时间。
所述第二时刻为在所述读取时间段结束后所述读取控制信号相邻下一次控制所述读取控制模块134开始将所述电信号传送至相应列读取线的时刻。
本公开实施例所述的像素电路的驱动模组可以通过电荷量大小来确定积分时间，当所述电荷量大时积分时间短，当电荷量小时积分时间长，这样可以根据电荷量大小动态调节积分时间，以适应大动态范围的光强检测。
在实际操作时，光感模块132感应相应的像素单元154发出的光信号，并将该光信号转换为电流信号，所述电荷信号指示的电荷量即为存储于寄生电容(例如，当像素补偿单元13采用如图1A所示结构时，所述光感模块132可以为光敏二极管DS，读取控制模块134可以为读取控制晶体管MS；所述寄生电容为光敏二极管DS的阴极与该光敏二极管DS的阳极之间的寄生电容)中的电荷量，当读取控制线130上的读取控制信号控制读取控制模块即读取控制晶体管MS导通光感模块132即光敏二极管DS与读取线之间的连接时，存储于所述寄生电容中的电荷传送至所述读取线上。
本公开实施例所述的像素电路的驱动方法，采用上述的像素电路的驱动模组以驱动像素电路，如图2所示，所述像素电路的驱动方法包括：
S1:信号生成单元生成读取控制信号和栅极驱动控制信号，将所述读取控制信号传送至相应行读取控制线，将所述栅极驱动控制信号传送至栅极驱动电路；
S2:栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭。
本公开实施例所述的像素电路的驱动方法通过信号生成单元生成读取控制信号和栅极驱动控制信号，能够使得显示驱动和基于像素单元的发光亮度的补偿不同时进行，从而能够避免栅线与数据线时序对光感模块的影响。
在实际操作时，所述像素电路包括多行栅线、多列数据线、多行读取控制线、多列读取线和多行多列像素单元电路；位于同一行的像素单元电路与同一行栅线和同一行读取控制线连接；位于同一列的像素单元电路与同一列 数据线和同一列读取线连接；
所述像素单元电路包括一像素补偿单元和一像素单元；
所述像素补偿单元包括：光感模块，用于将所述像素单元发出的光信号转换为相应的电信号；读取控制模块，与相应行读取控制线和相应列读取线连接，用于在相应行读取控制线上的读取控制信号的控制下控制在读取时间段将所述电信号传送至相应列读取线；以及，数据电压补偿模块。
具体的，所述信号生成单元生成读取控制信号步骤具体包括：所述信号生成单元根据所述电信号生成所述读取控制信号。
在实际操作时，所述电信号可以为电荷信号，所述信号生成单元根据所述电信号生成所述读取控制信号步骤可以具体包括：所述信号生成单元根据所述电荷信号指示的电荷量来确定相应的积分时间，并根据该积分时间生成相应的读取控制信号；
所述积分时间为所述读取控制信号控制所述读取控制模块开始将所述电信号传送至相应列读取线的第一时刻与第二时刻之间间隔的时间；
所述第二时刻为在所述读取时间段结束后所述读取控制信号相邻下一次控制所述读取控制模块开始将所述电信号传送至相应列读取线的时刻。
在可选情况下，第一电荷信号指示的第一电荷量大于第二电荷信号指示的第二电荷量，所述信号生成单元根据所述第一电荷量确定的第一积分时间小于所述信号生成单元根据所述第二电荷量确定的第二积分时间。
本公开实施例所述的像素电路的驱动方法可以通过电荷量大小来确定积分时间，当所述电荷量大时积分时间短，当电荷量小时积分时间长，这样可以根据电荷量大小动态调节积分时间，以适应大动态范围的光强检测。
在本公开所述的像素电路的驱动方法的第一具体实施例中，在一驱动周期内，在第n行栅线打开的时间段和第n+1行栅线打开的时间段之间设置有第n读取时间段；在相邻的两驱动周期内设置有第N读取时间段；N为所述像素电路包括的栅线的行数；N为正整数；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
所述信号生成单元控制向第n行读取控制线输出相应的读取控制信号， 以使得在所述第n读取时间段，所述像素电路包括的位于第n行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第n行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述信号生成单元控制向第N行读取控制线输出相应的读取控制信号，以使得在所述第N读取时间段，所述像素电路包括的位于第N行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第N行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述第n读取时间段和所述第N读取时间段，所述像素电路包括的所有栅线都关闭；n为正整数，n+1小于或等于N。
本公开所述的像素电路的驱动方法的第一具体实施例即为单行空闲检测模式；如图3所示，在第一驱动周期T1(当栅极驱动电路包括N级移位寄存器单元，用于驱动N行栅线时，一驱动周期即为扫描完该N行栅线的时间，N为大于3的整数)内，
在第一行栅线Gate1打开的时间段(也即用于驱动Gate1的栅极驱动信号的电位为高电平的时间段)和第二行栅线Gate2打开的时间段(也即用于驱动Gate2的栅极驱动信号的电位为高电平的时间段)之间设置有第一驱动周期T1内的第一读取时间段t11(也即第一行读取控制线Sense1输出高电平的时间段)；
在第二行栅线Gate2打开的时间段(也即用于驱动Gate2的栅极驱动信号的电位为高电平的时间段)和第三行栅线Gate3打开的时间段(也即用于驱动Gate3的栅极驱动信号的电位为高电平的时间段)之间设置有第一驱动周期T1内的第二读取时间段(也即第二行读取控制线Sense2输出高电平的时间段)；
在图3中，标号为GateN的为第N行栅线，与GateN对应的波形为驱动GateN的栅极驱动信号的波形；
在第二驱动周期T2内，在第一行栅线Gate1打开的时间段(也即用于驱 动Gate1的栅极驱动信号的电位为高电平的时间段)和第二行栅线Gate2打开的时间段(也即用于驱动Gate2的栅极驱动信号的电位为高电平的时间段)之间设置有第二驱动周期T2内的第一读取时间段t21(也即第一行读取控制线Sense1输出高电平的时间段)；
在第二行栅线Gate2打开的时间段(也即用于驱动Gate2的栅极驱动信号的电位为高电平的时间段)和第三行栅线Gate3打开的时间段(也即用于驱动Gate3的栅极驱动信号的电位为高电平的时间段)之间设置有第二驱动周期T2内的第二读取时间段(也即第二行读取控制线Sense2输出高电平的时间段)；
在图3所示的本公开所述的像素电路的驱动方法的第一具体实施例中，积分时间TI为t11结束的时刻与t21开始的时刻时间的时间间隔，也即等于1帧时间(也即一个驱动周期持续的时间)。
在图3所示的本公开所述的像素电路的驱动方法的第一具体实施例中，在每两行栅线扫描的时间间隙来进行电荷读取，为了适应大动态范围的检测(OLED发光时的灰阶电压在0到255之间，可能变化巨大)，需要根据读取数值动态调节曝光时间。如果读取到的电荷量过小就要增加积分时间，如果读取到的电荷量过大乃至饱和，那么就要降低积分时间。
在本公开所述的像素电路的驱动方法的第二具体实施例中，在一驱动周期内，在第n行栅线打开的时间段和第n+1行栅线打开的时间段之间设置有第n读取时间段，在第n+1行栅线打开的时间段和第n+2行栅线打开的时间段之间设置有第n+1读取时间段；在相邻的两驱动周期内设置有第N读取时间段；N为所述像素电路包括的栅线的行数；N为正整数；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
所述信号生成单元向第n行读取控制线输出相应的读取控制信号，以使得在所述第n读取时间段和所述第n+1读取时间段，所述像素电路包括的位于第n行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第n行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述信号生成单元向第N行读取控制线输出相应的读取控制信号，以使 得在所述第N读取时间段和第一读取时间段，所述像素电路包括的位于第N行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第N行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述第n读取时间段和所述第N读取时间段，所述像素电路包括的所有栅线都关闭；
n为正整数，n+1小于或等于N。
本公开所述的像素电路的驱动方法的第二具体实施例为另一种单行空闲检测模式；如图4所示，在第一驱动周期T1(当栅极驱动电路包括N级移位寄存器单元，用于驱动N行栅线时，一驱动周期即为扫描完该N行栅线的时间，N为大于3的整数)内，
在第一行栅线Gate1打开的时间段和第二行栅线Gate2打开的时间段之间设置有第一驱动周期T1内的第一读取时间段t1，在第二行栅线Gate2打开的时间段和第三行栅线Gate3打开的时间段之间设置有第一驱动周期T1内的第二读取时间段t12；
在t11和t12内，第一行读取控制线Sense1输出高电平；
在图4所示的第二具体实施例中，积分时间TI为t11结束的时间段到t12开始的时间段，也即一行时间。
在本公开所述的像素电路的驱动方法的第三具体实施例中，在两个相邻的显示阶段之间设置有一空白阶段；所述空白阶段包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为正整数；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制控制在所述空白阶段内所述像素电路包括的所有栅线都关闭；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：所述信号生成单元向第a行读取控制线输出相应的读取控制信号，以使得在所述空白阶段包括的第a读取时间段，所述像素电路包括的位于第a 行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第a行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
a为小于或等于M的正整数。
在实际操作时，在一个显示阶段内，所述栅极驱动电路依次扫描多行栅线。
本公开所述的像素电路的驱动方法的第三具体实施例为多行空闲检测模式；如图5所示，
在两个相邻的显示阶段之间设置有一空白阶段；所述空白阶段包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；
在图5中仅示出的一驱动周期包括的两个显示阶段和两个空白阶段；
在第一显示阶段T11、依次驱动第一行栅线Gate1、第二行栅线Gate2、…第m行栅线Gatem(m为大于2的整数)；
在第一空白阶段TB1、M行读取控制线依次打开(也即各行读取控制线依次输出高电平，以依次控制相应的读取控制模块导通相应的光感模块与相应的读取线之间的连接)；在图5中，Sense1为第一行读取控制线，Sense2为第二行读取控制线，SenseM为第M行读取控制线；
在第二显示阶段T12，依次驱动第m+1行栅线Gatem+1、第m+2行栅线Gatem+2、…、第N行栅线GateN(N为像素电路包括的栅线的条数)，然后重新依次驱动第一行栅线Gate1、第二行栅线Gate2、…第m行栅线Gatem(m为大于2的整数)；
在第二空白阶段，M行读取控制线依次打开(也即各行读取控制线依次输出高电平，以依次控制相应的读取控制模块导通相应的光感模块与相应的读取线之间的连接)。
在图5中，Sense1第一次输出高电平的时间段为第一读取时间段t11，Sense1第二次输出高电平的时间段为第二读取时间段t12，积分时间TI等于t11结束的时刻与t12开始的时刻之间间隔的时间。
图5所示的驱动方法的第三具体实施例为long H blank(长H空白)方式，也即在多行栅线驱动后插入用于读取数据的读取时间段。
在本公开所述的像素电路的驱动方法的第四具体实施例中，在两相邻显 示周期之间设置有一空白周期；
所述空白周期包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为正整数；
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：
所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制控制在所述空白周期内所述像素电路包括的所有栅线都关闭；
所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
所述信号生成单元向第b行读取控制线输出相应的读取控制信号，以使得在所述空白周期包括的第b行读取时间段，所述像素电路包括的位于第b行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第b行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
b为小于或等于M的正整数。
本公开所述的像素电路的驱动方法的第四具体实施例为多帧空闲检测模式；如图6所示，在两相邻显示周期之间设置有一空白周期；
所述空白周期包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为整数；
在本公开所述的第四具体实施例中，在一所述显示周期内，依次驱动所述像素电路包括的所有行栅线，在一所述空白周期内，所述像素电路包括的所有行读取控制线依次输出高电平；一所述显示周期也可以为一帧显示时间，在两相邻帧显示时间之间设置一空白周期；
如图6所示，在第一显示周期T61内，第一行栅线Gate1、第二行栅线Gate2、…、第N行栅线GateN依次输出高电平，在第一空白周期TBC1内，第一行读取控制线Sense1、第二行读取控制线Sense2、…、第M行读取控制线SenseM依次输出高电平；
在第二显示周期T62内，第一行栅线Gate1、第二行栅线Gate2、…、第N行栅线GateN依次输出高电平，在第二空白周期TBC2内，第一行读取控制线Sense1、第二行读取控制线Sense2、…、第M行读取控制线SenseM依 次输出高电平；
在第一空白周期TBC1内，Sense1输出高电平的时间段为第一读取时间段t11，在第二空白周期TBC2内，Sense1输出高电平的时间段为第二读取时间段t12；积分时间TI为t11结束的时刻与t12开始的时刻之间间隔的时间。
在本公开实施例中，最多的积分时间可以很长，达到一帧甚至数帧时间。
本公开实施例所述的显示装置，包括像素电路，还包括上述的像素电路的驱动模组。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (12)

  1. 一种像素电路包括多行栅线、多行读取控制线、多行多列像素单元电路和驱动模组；
    其中，所述像素单元电路包括像素补偿单元；所述像素补偿单元与相应行读取控制线连接；所述驱动模组包括与所述多行栅线连接的栅极驱动电路以及信号生成单元；
    所述信号生成单元与所述栅极驱动电路和所述像素补偿单元连接，用于生成读取控制信号和栅极驱动控制信号，将所述读取控制信号传送至相应行读取控制线，将所述栅极驱动控制信号传送至所述栅极驱动电路；
    所述栅极驱动电路用于根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述读取时间段所述多行栅线都关闭。
  2. 如权利要求1所述的像素电路，其中，所述像素补偿单元包括：光感模块，用于将所述像素单元发出的光信号转换为相应的电信号；所述信号生成单元具体用于根据所述电信号生成所述读取控制信号。
  3. 如权利要求2所述的像素电路，其中，所述像素补偿单元包括读取控制模块；所述像素电路还包括多列读取线；该读取控制模块与相应列读取线连接；所述电信号为电荷信号，所述信号生成单元具体用于根据所述电荷信号指示的电荷量来确定相应的积分时间，并根据该积分时间生成相应的读取控制信号；
    所述积分时间为所述读取控制信号控制读取控制模块开始将所述电信号传送至相应列读取线的第一时刻与第二时刻之间间隔的时间；
    所述第二时刻为在所述读取时间段结束后所述读取控制信号相邻下一次控制所述读取控制模块开始将所述电信号传送至相应列读取线的时刻。
  4. 一种如权利要求1至3中任一权利要求所述的像素电路的驱动方法，包括：
    信号生成单元生成读取控制信号和栅极驱动控制信号，将所述读取控制信号传送至相应行读取控制线，将所述栅极驱动控制信号传送至栅极驱动电路；
    栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭。
  5. 如权利要求4所述的驱动方法，其中，所述信号生成单元生成读取控制信号步骤具体包括：所述信号生成单元根据所述电信号生成所述读取控制信号；所述电信号为像素补偿单元包括的光感模块对像素单元发出的光信号进行转换得到的电信号。
  6. 如权利要求5所述的驱动方法，其中，像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；所述电信号为电荷信号，所述信号生成单元根据所述电信号生成所述读取控制信号步骤具体包括：所述信号生成单元根据所述电荷信号指示的电荷量来确定相应的积分时间，并根据该积分时间生成相应的读取控制信号；
    所述积分时间为所述读取控制信号控制所述读取控制模块开始将所述电信号传送至相应列读取线的第一时刻与第二时刻之间间隔的时间；
    所述第二时刻为在所述读取时间段结束后所述读取控制信号相邻下一次控制所述读取控制模块开始将所述电信号传送至相应列读取线的时刻。
  7. 如权利要求6所述的驱动方法，其中，当电荷信号包括第一电荷信号和第二电荷信号，且第一电荷信号指示的第一电荷量大于第二电荷信号指示的第二电荷量，所述信号生成单元根据所述第一电荷量确定的第一积分时间小于所述信号生成单元根据所述第二电荷量确定的第二积分时间。
  8. 如权利要求4至7中任一权利要求所述的驱动方法，其中，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在一驱动周期内，在第n行栅线打开的时间段和第n+1行栅线打开的时间段之间设置有第n读取时间段；在相邻的两驱动周期内设置有第N读取时间段；N为所述像素电路包括的栅线的行数；N为正整数；
    所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
    所述信号生成单元控制向第n行读取控制线输出相应的读取控制信号，以使得在所述第n读取时间段，所述像素电路包括的位于第n行的所有像素 补偿单元包括的读取控制模块都打开，以导通位于第n行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
    所述信号生成单元控制向第N行读取控制线输出相应的读取控制信号，以使得在所述第N读取时间段，所述像素电路包括的位于第N行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第N行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
    所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述第n读取时间段和所述第N读取时间段，所述像素电路包括的所有栅线都关闭；n为正整数，n+1小于或等于N。
  9. 如权利要求4至7中任一权利要求所述的驱动方法，其中，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在一驱动周期内，在第n行栅线打开的时间段和第n+1行栅线打开的时间段之间设置有第n读取时间段，在第n+1行栅线打开的时间段和第n+2行栅线打开的时间段之间设置有第n+1读取时间段；在相邻的两驱动周期内设置有第N读取时间段；N为所述像素电路包括的栅线的行数；N为正整数；
    所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
    所述信号生成单元向第n行读取控制线输出相应的读取控制信号，以使得在所述第n读取时间段和所述第n+1读取时间段，所述像素电路包括的位于第n行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第n行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
    所述信号生成单元向第N行读取控制线输出相应的读取控制信号，以使得在所述第N读取时间段和第一读取时间段，所述像素电路包括的位于第N行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第N行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
    所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号， 以控制在读取时间段多行栅线都关闭步骤具体包括：所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在所述第n读取时间段和所述第N读取时间段，所述像素电路包括的所有栅线都关闭；
    n为正整数，n+1小于或等于N。
  10. 如权利要求4至7中任一权利要求所述的驱动方法，其中，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在两个相邻的显示阶段之间设置有一空白阶段；所述空白阶段包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为正整数；
    所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：
    所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制控制在所述空白阶段内所述像素电路包括的所有栅线都关闭；
    所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：所述信号生成单元向第a行读取控制线输出相应的读取控制信号，以使得在所述空白阶段包括的第a读取时间段，所述像素电路包括的位于第a行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第a行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
    a为小于或等于M的正整数。
  11. 如权利要求4至7中任一权利要求所述的驱动方法，其中，所述像素补偿单元包括光感模块；像素补偿单元包括读取控制模块；所述像素电路包括多列读取线；该读取控制模块与相应列读取线连接；在两相邻显示周期之间设置有一空白周期；
    所述空白周期包括依次设置的M个读取时间段；M为所述像素电路包括的读取控制线的行数；M为正整数；
    所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制在读取时间段多行栅线都关闭步骤具体包括：
    所述栅极驱动电路根据所述栅极驱动控制信号生成多个栅极驱动信号，以控制控制在所述空白周期内所述像素电路包括的所有栅线都关闭；
    所述信号生成单元将所述读取控制信号传送至相应行读取控制线步骤具体包括：
    所述信号生成单元向第b行读取控制线输出相应的读取控制信号，以使得在所述空白周期包括的第b行读取时间段，所述像素电路包括的位于第b行的所有像素补偿单元包括的读取控制模块都打开，以导通位于第b行的所述像素补偿单元包括的光感模块与相应列读取线之间的连接；
    b为小于或等于M的正整数。
  12. 一种显示装置，包括如权利要求1至3中任一权利要求所述的像素电路。
PCT/CN2018/110639 2017-11-07 2018-10-17 像素电路、像素电路驱动的方法和显示装置 WO2019091267A1 (zh)

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