WO2019084751A1

WO2019084751A1 - Display assembly, manufacturing method therefor, display, and terminal device

Info

Publication number: WO2019084751A1
Application number: PCT/CN2017/108506
Authority: WO
Inventors: 徐刚; 刘康仲; 境川亮
Original assignee: 华为技术有限公司
Priority date: 2017-10-31
Filing date: 2017-10-31
Publication date: 2019-05-09
Also published as: CN110114822A

Abstract

A display assembly (200), a manufacturing method therefor, a display, and a terminal device. The display assembly (200) comprises a thin-film transistor (TFT) substrate (203), and is characterized in that: a pixel switch array (204) and a driving microchip set are disposed on the upper surface of the TFT substrate (203), the driving microchip set is connected to the pixel switch array (204), any driving microchip (205, 206) in the driving microchip set is a monocrystalline silicon microchip, the width of any driving microchip (205, 206) in the driving microchip set is less than or equal to 500 μm, and the thickness of any driving microchip (205, 206) is less than or equal to 10 μm. Production costs of the display assembly (200) can be reduced, the performance of a driving chip in the display assembly (200) can be improved, and the width of the frame of the display assembly (200) can be reduced.

Description

Display component and its manufacturing method, display and terminal device

Technical field

The present application relates to the field of display technology, and more particularly to a display assembly and a method of manufacturing the same, a display, and a terminal device.

Background technique

A pixel switch array and row and column drive chips are generally disposed on the substrate of the display screen.

At present, regarding the manufacture of a pixel switch array and a row and column driver chip, a prior art is known, which is manufactured by the same process technology for the manufacture of a pixel switch array and a row and column driver chip. For example, it is manufactured by Indium Gallium Zinc Oxide (IGZO) process technology or low temperature poly-silicon (LTPS) process technology.

However, for the pixel switch array, the performance of the pixel switch array produced by the IGZO process technology is superior, and accordingly, the performance of the row and column drive chips produced by the LTPS process technology is superior. Therefore, for the production of the pixel switch array and the row and column driver chips, if the same process technology is used for manufacturing, the performance of the row and column driver chips or the performance of the pixel switch array is bound to be limited.

Another prior art is known which requires compatibility with both Indium Gallium Zinc Oxide (IGZO) and Low Temperature Poly-silicon (LTPS) process technologies, such as The pixel switch array is produced by the IGZO process, and the row and column drive chips are produced by the LTPS process.

However, the simultaneous compatibility of the above two process technologies on the production line will make the display manufacturing process more difficult, and will also increase the manufacturing cost (for example, increase the production cost of the production line).

Summary of the invention

The present application provides a display assembly, a manufacturing method thereof, a display, and a terminal device, which can reduce the cost of producing a display assembly, improve the performance of the driving chip in the display assembly, and can reduce the width of the frame of the display assembly (hereinafter referred to as the width of the side) ).

In a first aspect, a display device is provided, including a thin film transistor TFT substrate, wherein an upper surface of the TFT substrate is configured with a pixel switch array and a driving microchip group, and the driving microchip group and the pixel switch An array is connected, and any one of the driving microchip groups is a single crystal silicon microchip, and a width of any one of the driving microchip groups is less than or equal to 500 μm, and any one of the driving microchips is The thickness is less than or equal to 10 μm.

By generating a driving chip on a single crystal silicon wafer and cutting the generated driving chip into a large number of driving microchips (for example, driving a microchip group), a plurality of driving microchips in the driving microchip group formed by cutting are finally transplanted. The upper surface of the TFT substrate in the display assembly reduces the cost of producing the display assembly and improves the performance of the driver chip in the display assembly.

Moreover, a large number of driving microchips are obtained by cutting a wafer (for example, a single crystal silicon wafer on which a driving chip is grown) by a wet etching or a dry etching process, and the cutting process enables a channel between the diced wafers to be compared. Small, therefore, the width of the driven microchip after cutting is also small, which is beneficial to improve the utilization of the wafer, thereby contributing to cost reduction. Typically, the width of the driving microchip is less than or equal to 500 μm, and the thickness of any one of the driving microchips is less than or equal to 10 μm. Therefore, the side width of the display assembly can be reduced to some extent.

Optionally, any one of the driving microchip sets is driven on the upper surface of the TFT substrate by a massive transfer technique.

The massive transfer technology enables a large number of (for example, tens of thousands) of drive microchips to be transplanted at one time, and therefore, for a large number of drive microchips formed after dicing, the mass transfer technology A large number of driving microchips are transplanted on the upper surface of the TFT substrate, which can reduce the difficulty of transplantation of the large number of driving microchips and improve the transplantation efficiency. In conjunction with the first aspect, in some implementations of the first aspect, the driving microchip set includes at least two row driving microchips and/or at least two column driving microchips, the at least two row driving microchips Any one of the row driving microchips is connected to at least one row of pixel switches in the pixel switch array, and any one of the at least two column driving microchips is connected to at least one column of pixel switches.

By forming a row driver chip and/or a column driver chip on a single crystal silicon wafer, and cutting the generated row driver chip and/or column driver chip into a large number of row driving microchips and column driving microchips, the final shape will be formed by cutting. The row drive microchip and/or the column drive microchip are implanted on the upper surface of the TFT substrate in the display assembly by using a massive transfer technique to reduce the cost of producing the display assembly and improve the performance of the driver chip in the display assembly (for example, Control the pixel switch array to turn on/off faster.)

With reference to the first aspect, in some implementations of the first aspect, the display component further includes: a control chip, wherein the control chip drives the microchip with any one of the at least two row driving microchips, Any one of the at least two column driving microchips is connected to the microchip, the control chip is disposed on an upper surface of the TFT substrate, or the control chip is disposed on an upper surface of the flexible circuit board FPC, The FPC is in contact with an upper surface portion of the TFT substrate.

In conjunction with the first aspect, in some implementations of the first aspect, the control chip includes at least two control microchips, the control microchip is a single crystal silicon microchip, and any of the at least two control microchips The width of one of the control microchips is less than or equal to 500 μm, and the thickness of any one of the control microchips is less than or equal to 10 μm.

Optionally, the at least two column driving microchips are integrated with the control microchip on a same microchip, the microchip has the function of controlling the microchip, and has the at least two column driving micro The function of the chip.

By generating a control chip on the single crystal silicon wafer and cutting the generated control chip into a large number of control microchips, the control microchip formed by cutting is finally transplanted to the upper surface of the TFT substrate in the display assembly by using a massive transfer technique. (ie, connecting the control microchip to the corresponding circuit trace of the TFT substrate), achieving conduction between the chips on the TFT substrate in the display assembly, thereby reducing the production cost of the display assembly, and reducing the display assembly. The width of the bottom border.

In conjunction with the first aspect, in some implementations of the first aspect, the pixel switch array is an oxide semiconductor IGZO pixel switch array or a low temperature polysilicon LTPS pixel switch array or an amorphous silicon pixel switch array.

In conjunction with the first aspect, in some implementations of the first aspect, the display component is a liquid crystal display component, the liquid crystal display component further comprising: a first planar layer, a liquid crystal layer, and a liquid crystal layer upper panel, the first The flat layer is disposed on an upper surface of the pixel switch array, and the liquid crystal layer is disposed between the first flat layer and the upper panel of the liquid crystal layer.

The uniformity of the thickness of the liquid crystal layer is controlled by disposing a flat layer (for example, a first flat layer) on the upper surface of the pixel switch array and disposing the liquid crystal layer between the first flat layer and the upper panel of the liquid crystal layer.

In conjunction with the first aspect, in some implementations of the first aspect, the display component further includes: a second planar layer, the second planar layer is located on a lower surface of the upper panel of the liquid crystal layer, the liquid crystal layer configuration Between the first planar layer and the second planar layer.

By arranging a flat layer (for example, a first flat layer) on an upper surface of the pixel switch array, and arranging a second flat layer on a lower surface of the upper panel of the liquid crystal layer, the liquid crystal layer is disposed on the first flat layer and the second flat layer And can control the thickness of the liquid crystal layer and its uniformity.

In conjunction with the first aspect, in some implementations of the first aspect, the at least two row driving microchips and the at least two column driving microchips are disposed below or above the sealant layer of the liquid crystal display assembly Positioning, or the at least two row driving microchips, the at least two column driving microchips and the sealant layer of the liquid crystal display component are disposed on an upper surface of the TFT substrate, and the at least two rows Driving the microchip and the at least two column driving microchips disposed at an intermediate position between the sealant layer and the liquid crystal layer, or the at least two row driving microchips, the at least two column driving microchips and The sealant layer of the liquid crystal display assembly is disposed on an upper surface of the TFT substrate, and the at least two row drive microchips and the at least two column drive microchips are at least partially wrapped by the sealant layer.

By partially or completely wrapping the at least two row driving microchips 205 in the sealant layer 211, the total width occupied by the row driving microchip 205 and the sealant layer 211 on the TFT substrate 203 is reduced, thereby reducing The longitudinal side of the liquid crystal display assembly 200 is wide. In combination with the first aspect, in some implementations of the first aspect, the liquid crystal layer has a thickness ranging from 2 μm to 7 μm.

In a second aspect, a method of manufacturing a display assembly is provided, the method comprising: providing a pixel switch array and a driving microchip group on an upper surface of a thin film transistor TFT substrate, wherein the driving microchip group is connected to the pixel switch array The driving microchip of any one of the driving microchip sets is a single crystal silicon microchip, and the width of any one of the driving microchip sets is less than or equal to 500 μm, and the thickness of any one of the driving microchips is less than or Any one of the driving microchips equal to 10 μm is cut by a wet or dry engraving process on the wafer.

In conjunction with the second aspect, in some implementations of the second aspect, any one of the driving microchips in the driving microchip group is implanted on the upper surface of the TFT substrate by a massive transfer technique.

In conjunction with the second aspect, in some implementations of the second aspect, the driving microchip set includes at least two row driving microchips and/or at least two column driving microchips, the at least two row driving microchips Any one of the row driving microchips is connected to at least one row of pixel switches in the pixel switch array, and any one of the at least two column driving microchips is connected to at least one column of pixel switches.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: providing a control chip on an upper surface of the thin film transistor TFT substrate, wherein the control chip drives the microchip with the at least two rows respectively Any one of the row driving microchips, any one of the at least two column driving microchips is connected to the microchip.

With reference to the second aspect, in some implementations of the second aspect, the method further includes: providing a flexible circuit board FPC on an upper surface of the TFT substrate, and providing a control chip on an upper surface of the FPC, The control chip is respectively connected to any one of the at least two row driving microchips, and any one of the at least two column driving microchips, the FPC and the TFT substrate The upper surface is partially in contact.

With reference to the second aspect, in some implementations of the second aspect, the control chip includes at least two control microchips, the control microchip is a single crystal silicon microchip, and any of the at least two control microchips a control chip The width is less than or equal to 500 μm, and the thickness of any one of the control microchips is less than or equal to 10 μm, and any one of the control microchips is cut by a wet or dry engraving process on the wafer.

With reference to the second aspect, in some implementations of the second aspect, the method further includes integrating the column driving microchip and the control microchip on a same microchip, the microchip having the The function of the microchip is controlled and has the function of the column driving microchip.

In conjunction with the second aspect, in some implementations of the second aspect, the pixel switch array is an oxide semiconductor IGZO pixel switch array, a low temperature polysilicon LTPS pixel switch array, or an amorphous silicon pixel switch array.

With reference to the second aspect, in some implementations of the second aspect, in the case that the display component is a liquid crystal display component, the method further includes: providing a first planar layer on an upper surface of the pixel switch array; A liquid crystal layer upper panel is disposed above the first planar layer; and a liquid crystal layer is disposed between the first planar layer and the liquid crystal layer upper panel.

In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: providing a second planar layer on a lower surface of the upper panel of the liquid crystal layer; at the first planar layer and the second The liquid crystal layer is disposed between the flat layers.

In conjunction with the second aspect, in some implementations of the second aspect, the at least two row driving microchips and the at least two column driving micros are disposed below or above the sealant layer of the liquid crystal display assembly a chip; or the at least two row driving microchips and the at least two column driving microchips are disposed at an intermediate position between the sealant layer and the liquid crystal layer, and the at least two rows drive the microchips, The at least two column driving microchips and the sealant layer are disposed on an upper surface of the TFT substrate; or the at least two row driving microchips, the at least two columns are disposed on an upper surface of the TFT substrate Driving the microchip and the sealant layer of the liquid crystal display assembly, and the at least two row drive microchips and the at least two column drive microchips are at least partially wrapped by the sealant layer.

In combination with the second aspect, in some implementations of the second aspect, the liquid crystal layer has a thickness ranging from 2 μm to 7 μm.

In a third aspect, a display is provided, the display comprising a housing, a base, and the display assembly of any of the first aspect and the first aspect, wherein the display component is disposed on the housing internal.

In a fourth aspect, a terminal device is provided, characterized in that the terminal device comprises a housing and the display component in any one of the above first aspect and the first aspect, wherein the display component configuration Inside the outer casing.

DRAWINGS

Figure 1 is a schematic illustration of a prior art display assembly.

2 is a schematic diagram of a display assembly of an embodiment of the present application.

3 is another schematic diagram of a display assembly of an embodiment of the present application.

FIG. 4 is still another schematic diagram of the display assembly of the embodiment of the present application.

FIG. 5 is still another schematic diagram of the display assembly of the embodiment of the present application.

6 is a schematic view of a cross section of a liquid crystal display device of an embodiment of the present application.

7 is another schematic view of a cross section of a liquid crystal display device of an embodiment of the present application.

FIG. 8 is still another schematic diagram of a cross section of a liquid crystal display device of an embodiment of the present application.

Detailed ways

The technical solutions in the present application will be described below with reference to the accompanying drawings.

In order to better understand the display device of the embodiment of the present application, the existing display component is simplified in conjunction with FIG. 1 below. Single introduction.

An existing display module will be described by taking an existing liquid crystal display device as an example. 1 is a schematic structural view of a conventional liquid crystal display assembly. The liquid crystal display assembly 100 can be located in a terminal device (for example, a mobile phone, a tablet computer, and other electronic devices including a liquid crystal display). As shown in FIG. 1, the display assembly 100 includes a liquid crystal layer upper panel 101 [], a liquid crystal layer (covered by the liquid crystal layer upper panel 101, not shown in FIG. 1), a TFT substrate 102, and a pixel switch array (on the liquid crystal layer). The panel 101 is covered, not shown in FIG. 1), the row driving chip 103, the column driving chip 104, and the control chip 105.

The liquid crystal layer upper panel 101, the liquid crystal layer, the pixel switch array, and the TFT substrate 102 are sequentially disposed in the liquid crystal display device 100 from top to bottom, and a pixel switch array (on the liquid crystal layer) is disposed on the upper surface of the TFT substrate 102. The panel 101 is covered (not shown in FIG. 1), the row driving chip 103, the column driving chip 104, and the control chip 105, and the area on the liquid crystal layer upper panel 101 covering the pixel switch array constitutes a display area of the display assembly 100.

It should be noted that the control chip 105 can also be disposed on the upper surface of the Flexible Printed Circuits (FPC) 106 of the display assembly 100, and the FPC 106 is in contact with the upper surface portion of the TFT substrate 102.

The row driving chip 103 is connected to each row of pixel switches of the pixel switch array for controlling a row of pixel switches of the pixel switch array to be turned on or off at a certain time, and each column switch of the column driving chip 103 and the pixel switch array is Connected to charge a liquid crystal pixel corresponding to each pixel switch of the row of pixel switches after the pixel switch of the pixel switch array is turned on, and the control chip 105 is respectively connected to the row driving chip 103 and the column driving core 104 for The row driving chip 103 and the column driving chip 104 are controlled to cause the row driving chip 103 and the column driving chip 104 to perform corresponding operations on the pixel switch array, thereby achieving the purpose of performing progressive scanning on the pixel switch array.

For the liquid crystal display device 100 of FIG. 1, the pixel switch array, the row driver chip and the column driver chip in the display assembly can be manufactured by two techniques, which will be separately described below.

Technology 1

The pixel switch array, the row driver chip, and the column driver chip are all manufactured by the same process technology, for example, by being compatible with Indium Gallium Zinc Oxide (IGZO) process technology or low temperature poly-silicon (Low Temperature Poly-silicon, The LTPS) process technology is manufactured, and the pixel switch array, the row driver chip, and the column driver chip are all directly formed on the TFT substrate.

However, for the pixel switch array, the performance of the pixel switch array produced by the IGZO process technology is superior, and accordingly, the performance of the row and column drive chips produced by the LTPS process technology is superior. Therefore, for the production of the pixel switch array and the row driver chip and the column driver chip, if the manufacturing process is performed by one of the above-mentioned process technologies, the performance of the row driver chip, the column driver chip, or the performance of the pixel switch array is bound to be inevitable. Subject to certain restrictions.

Technology 2

The technology is compatible with both Indium Gallium Zinc Oxide (IGZO) and Low Temperature Poly-silicon (LTPS) processes on the production line. For example, the IGZO process produces pixel switch arrays through LTPS. Process production line, column driver chip.

However, the simultaneous compatibility of the above two process technologies on the production line will make the manufacturing of display components more difficult, and at the same time increase the manufacturing cost (for example, increase the investment cost of the production line).

In order to reduce the production cost of the display assembly and improve the performance of the above chip (for example, controlling the speed at which the pixel switch array is turned on/off), the present application proposes a display assembly by generating a driver chip on a single crystal silicon wafer, and The generated driver chip is cut into a large number of driving microchips (for example, driving a microchip group), and finally formed by cutting Driving a plurality of driving microchips in the microchip group to be transplanted on an upper surface of the TFT substrate in the display assembly (ie, connecting a plurality of driving microchips in the driving microchip group to corresponding circuit traces of the TFT substrate), Thereby, conduction between the respective chips on the TFT substrate in the display module is achieved.

It should be noted that, in the embodiment of the present application, the driving microchip is obtained by cutting on a wafer (for example, a single crystal silicon wafer on which a driving chip is grown) by a wet etching or a dry etching process, and the cutting is performed. The process enables the width of the driven microchip after cutting to be very small. Typically, the width of the driving microchip is less than or equal to 500 μm and the thickness of any one of the driving microchips is less than or equal to 10 μm.

Since the width of the driving microchip proposed in the embodiment of the present application is less than or equal to 500 μm, the side width of the display assembly can be reduced.

2 is a schematic diagram of a display assembly of an embodiment of the present application. The display assembly 200 includes:

a thin film transistor TFT substrate 203 having a pixel switch array 204 (covered by the upper panel 201 of the display unit 200, not shown in FIG. 2) and a driving microchip group, the driving microchip group and the upper surface of the TFT substrate 203 The pixel switch array 204 is connected, and any one of the driving microchip groups is a single crystal silicon microchip, and the width of any one of the driving microchip groups is less than or equal to 500 μm, and any one of the driving microchips The thickness is less than or equal to 10 μm.

The upper panel 201, the pixel switch array 204, and the TFT substrate 203 are sequentially disposed in the display module 200 from top to bottom.

Specifically, a driving chip is first formed on a single crystal silicon wafer, and a single crystal silicon wafer on which a driving chip is grown is cut into a large number of driving microchips (for example, a driving microchip group) by a wet etching or dry etching process, and The plurality of driving microchips are transplanted onto the upper surface of the TFT substrate 203, and any one of the driving microchips implanted on the upper surface of the TFT substrate 203 is connected to the pixel switch array 204 (ie, the driving one of the driving microchips is turned on) Circuitry between respective pixel switches in pixel switch array 204) such that the drive microchip performs specific operations on pixel switch array 204.

Optionally, any one of the driving microchips in the driving microchip group is implanted on the upper surface of the TFT substrate by a massive transfer technique.

The massive transfer technology enables a large number of (for example, tens of thousands) of drive microchips to be transplanted at one time, and therefore, for a large number of drive microchips formed after dicing, the mass transfer technology A large number of driving microchips are transplanted on the upper surface of the TFT substrate, which can reduce the difficulty of transplantation of the large number of driving microchips and improve the transplantation efficiency.

Optionally, the driving microchip group comprises at least two row driving microchips 205 and/or at least two column driving microchips 206, and any one of the at least two row driving microchips 205 drives the microchip 205 and the At least one row of pixel switches in the pixel switch array 204 are connected, and any one of the at least two column drive microchips 206 drives the microchip 206 to be connected to at least one column of pixel switches. Specifically, for the plurality of row driving microchips 205 and the column driving microchips 206 formed by the cutting, at least two of the plurality of row driving microchips 205 drive the microchip 205 and at least two columns of the plurality of row driving microchips. The driving microchip 206 is transplanted to the upper surface of the TFT substrate 203 by a massive transfer technique, and causes any one of the at least two row driving microchips 205 transplanted on the upper surface of the TFT substrate 203 to drive the microchip 205 and the pixel switch. At least one row of pixel switches of the array 204 are connected such that any one of the at least two column driving microchips 206 implanted on the upper surface of the TFT substrate 203 is connected to at least one column of the pixel switches of the pixel switch array 204. A row driving microchip 205 is used to control a row of pixel switches of the pixel switch array 204 to be turned on or off at a certain time, and the at least two column driving microchips 206 are used to open the pixels. After the pixel switch of the row 204 is turned on, the liquid crystal pixels corresponding to each pixel switch of the row of pixel switches are charged, and the control chip is respectively connected to the at least two row driving microchips 205 and at least two column driving microchips 206. The at least two row driving microchips 205 and the at least two column driving microchips 206 are controlled to enable the at least two row driving microchips 205 and the at least two column driving microchips 206 to the pixel switch array 204. Perform specific actions.

It should be noted that, in the embodiment of the present application, only a large number of row driving microchips 205 formed after cutting may be transplanted to the upper surface of the TFT substrate by a massive transfer technique, and the column driving chip adopts a conventional driving chip; Only a large number of the column driving microchips 206 formed after the dicing are transferred to the upper surface of the TFT substrate by the mass transfer technique, and the conventional driving chip is used for the row driving chip, which is not particularly limited in the embodiment of the present application.

It should be noted that, in the embodiment of the present application, the driving microchip may include other types of microchips in addition to the above-mentioned row driving microchip and column driving microchip, which is not specifically limited in the present application.

Optionally, in the embodiment of the present application, the pixel switch array 204 may be an oxide semiconductor IGZO pixel switch array or a low temperature polysilicon LTPS pixel switch array or an amorphous silicon pixel switch array. Therefore, in the embodiment of the present application, by generating a driving chip on a single crystal silicon wafer, and cutting the generated driving chip into a large number of driving microchips (for example, driving a microchip group), the driving microchip finally formed by cutting is formed. A plurality of driving microchips in the group are implanted on the upper surface of the TFT substrate in the display assembly, thereby reducing the cost of producing the display assembly and improving the performance of the driving chip in the display assembly.

Moreover, a large number of driving microchips are obtained by cutting a wafer (for example, a single crystal silicon wafer on which a driving chip is grown) by a wet etching or dry etching process, and the cutting process can make the width of the driven microchip after cutting very small. Generally, the width of the driving microchip is less than or equal to 500 μm. Therefore, the side width of the display assembly can be reduced to some extent. And at the same time reduce the edge width of the display component.

Optionally, as shown in FIG. 2, the control chip 207 of the display component 200 may be disposed on an upper surface of the TFT substrate, and respectively drive the microchip 205 with any one of the at least two row driving microchips 205. Any one of the at least two column driving microchips 206 is connected to the microchip 206, and the flexible circuit board FPC212 in the display component is in contact with the upper surface portion of the TFT substrate 203;

Alternatively, as shown in FIG. 3, the control chip 207 may be disposed on an upper surface of the flexible circuit board FPC212 in the display component 200, and respectively drive the microchip 205 with any one of the at least two row driving microchips 205. And any one of the at least two column driving microchips 206 is connected to the microchip 206, and the FPC 212 is in contact with the upper surface portion of the TFT substrate 203.

Optionally, the control chip includes at least two control microchips 207, wherein the control microchip 207 is a single crystal silicon microchip, and any one of the at least two control microchips controls the width of the microchip to be less than or equal to 500 μm, and the The thickness of any one of the control microchips is less than or equal to 10 μm.

Specifically, a control chip is formed on the single crystal silicon wafer, and the control chip generated on the silicon wafer is cut into a large number of control microchips 207, and any one of the large number of control microchips 207 is controlled by the microchip 207. The width is less than or equal to 500 μm, and the thickness of any one of the driving microchips is less than or equal to 10 μm. For a large number of control microchips 207 formed by cutting, at least two control microchips 207 of the plurality of control microchips 207 are transplanted onto the upper surface of the base station by a massive transfer technique, and are implanted on the upper surface of the TFT substrate 203. Any one of the at least two control microchips 207 is connected to the at least two row driving microchips 205, and is connected to at least one column driving microchip 206 of the at least two column driving microchips 206, as shown in the figure. As shown in FIG. 4, the at least two control microchips 207 are configured to perform the at least two row driving microchips 205 and the at least two column driving microchips 206. Controlling, so that the at least two row driving microchips 205 and the at least two column driving microchips 206 perform corresponding operations on the pixel switch array 204, thereby achieving the purpose of progressively scanning the pixel switch array 204.

For example, the pixel switch array 204 is a 1000*1000 size switch array, the at least two row drive microchips 205 include 10 row drive microchips 205, and the at least two column drive microchips 206 include 10 column drive microchips. 206, the at least two control microchips 207 comprise five control microchips 207, and any one of the 10 column drive microchips 206 drives the microchip 206 to be connected to 100 columns of pixel switches, the 10 row drive microchips Any one of the row driving microchips 205 is connected to the pixel switches of 100 rows, and any two adjacent control microchips 207 of the five control microchips 207 are connected, and the five control microchips 207 are connected. Any one of the control microchips 207 is connected to the two column drive microchips 206, and the control microchips 207 closest to the row drive microchips 205 of the five control microchips 207 are connected to the ten row drive microchips 205.

When the control microchip 207 needs to scan the 50th row pixel switch in the 1000 rows of pixel switch array 204, the 5 control microchips 207 need to drive the microchip 206 to the 10 columns and drive the 10 columns. The instructions sent by the chip 206 are synchronized, and then the control microchip 207 closest to the row driving microchip 205 among the five control microchips 207 sends an instruction to the ten row driving microchips 205 to the 10 rows. The driving microchip 205 instructs to turn on the 50th row of pixel switches, and turns off the other 999 rows of pixel switches. At the same time, the 5 control microchips 207 send instructions to the 10 column driving microchips 206, and the instructions are driven to the 10 columns. The microchip 206 indicates the voltage value that needs to be applied to the liquid crystal pixels of the 50th row.

After receiving the corresponding instructions sent by the five control microchips 207, the 10 column driving microchips 206 and the 10 column driving microchips 206 perform corresponding operations on the pixel switch array 204, so that the 50th row The liquid crystal pixels are lit.

It should be noted that the above various numerical examples are merely illustrative, and are not intended to limit the embodiments of the present application.

By generating a control chip on the single crystal silicon wafer, and cutting the generated control chip into a large number of control microchips 207, the control microchip 207 formed by cutting is finally transplanted into the TFT substrate in the display assembly 200 by using a massive transfer technique. The upper surface of the 203 (ie, the control microchip 207 is connected to the corresponding circuit trace of the TFT substrate 203) to achieve conduction between the chips on the TFT substrate 203 in the display assembly 200, thereby reducing the liquid crystal layer. The vertical distance between the lower edge of the panel 201 and the lower edge of the TFT substrate 203 (i.e., the width of the lower frame of the display assembly 200).

Optionally, in the embodiment of the present application, the column driving microchip 206 and the control microchip 207 may be the same microchip 207, as shown in FIG. 5, that is, the microchip 208 and the function of the control microchip 208. It also has the function of the above column driving microchip 208.

Optionally, the display component 200 proposed in the present application may be a liquid crystal display component 200, and FIG. 6 shows a cross-sectional view of the liquid crystal display component 200. The liquid crystal display component 200 includes a TFT substrate 203, a pixel switch array 204, The liquid crystal display assembly 200 further includes: a first flat layer 209, a liquid crystal layer 202, and a liquid crystal layer upper panel 201, where the at least two rows drive the microchip 205, the at least two column driving microchips 206, and the control chip 208. The liquid crystal layer 202 is disposed with a sealant layer 211 for preventing liquid crystal leakage of the liquid crystal layer 202, and the liquid crystal layer upper panel 201, the liquid crystal layer 202, the pixel switch array 204, and the TFT substrate 203 are The lower portion is sequentially disposed in the liquid crystal display unit 200. The first planar layer 209 is disposed on the upper surface of the pixel switch array 204. The liquid crystal layer 202 is disposed between the first planar layer 209 and the liquid crystal layer upper panel 201.

Specifically, the row driving microchip 205 and the column driving microchip 206 are implanted on the upper surface of the TFT substrate 203. Thereafter, it is possible that the height of the at least two row driving microchips 205 and the at least two column driving microchips 206 is higher than the liquid crystal and the thickness of the sealant, thereby affecting a certain thickness and necessary uniformity of the liquid crystal layer 202. control. Therefore, in order to control the thickness and uniformity of the liquid crystal layer 202, the first flat layer 209 is covered on the upper surface of the pixel switch array 204, so that the liquid crystal layer 202 is disposed on the upper surface of the first flat layer 209, That is, the liquid crystal layer 202 is disposed between the first flat layer 209 and the lower surface of the liquid crystal layer upper panel 201.

As can be seen from the cross-sectional view of the liquid crystal display device 200 shown in FIG. 6, the first planar layer 209 is disposed on the upper surface of the at least two row driving microchips 205, and the liquid crystal layer 202 is disposed on the first planar layer. 209 is between the lower surface of the liquid crystal layer upper panel 201.

By arranging a flat layer (for example, the first flat layer 209) on the upper surface of the pixel switch array 204, and arranging the liquid crystal layer between the first flat layer 209 and the liquid crystal layer upper panel 201, the thickness of the liquid crystal layer 202 is controlled and Evenness.

Optionally, FIG. 7 shows another cross-sectional view of the liquid crystal display assembly 200 including a TFT substrate 203, a pixel switch array 204, at least two row drive microchips 205, and at least two columns. The liquid crystal display device 200 further includes a first flat layer 209, a second flat layer 210, a liquid crystal layer 202, and a liquid crystal layer upper panel 201. The liquid crystal layer 202 is provided with a sealant. The layer 211 is used to prevent the liquid crystal layer 202 from leaking out of the liquid crystal layer 202. The second flat layer 210 is located on a lower surface of the liquid crystal layer upper panel 201 , and the liquid crystal layer 202 is disposed between the first flat layer 209 and the second flat layer 210 .

Specifically, the liquid crystal display assembly 200 may further include a second planar layer 210. As can be seen from the cross-sectional view of the liquid crystal display assembly 200 shown in FIG. 7, the second planar layer 210 is located on the upper panel 201 of the liquid crystal layer. The lower surface, the liquid crystal layer 202 is disposed between the first planar layer 209 and the second planar layer 210.

By arranging a flat layer (for example, the first flat layer 209) on the upper surface of the pixel switch array 204, and disposing the second flat layer 210 on the lower surface of the liquid crystal layer upper panel 201, the liquid crystal layer 202 is disposed on the first flat layer 209. The thickness and uniformity of the liquid crystal layer 202 can be controlled between the second flat layer 210 and the second flat layer 210.

The positional relationship between the at least two row driving microchips 205, the at least two column driving microchips 206, and the sealant layer 211 of the liquid crystal display device will be described below with reference to FIG.

Optionally, the at least two row driving microchips 205 and the at least two column driving microchips 206 are disposed under the glue layer 211 of the liquid crystal display component, or

The at least two row driving microchips 205, the at least two column driving microchips 206 and the glue layer 211 of the liquid crystal display component are disposed on the upper surface of the TFT substrate 203, and the at least two row driving microchips 205 and The at least two column driving microchips 206 are disposed at an intermediate position between the sealant layer 211 and the liquid crystal layer 202.

As shown in FIG. 8 , the at least two row driving microchips 205 , the at least two column driving microchips 206 and the glue layer 211 of the liquid crystal display component are disposed on an upper surface of the TFT substrate 203 , and the at least two The row drive microchip 205 and the at least two column drive microchips 206 are at least partially wrapped by the sealant layer 211.

By partially or completely wrapping the at least two row driving microchips 205 in the sealant layer 211, the total width occupied by the row driving microchip 205 and the sealant layer 211 on the TFT substrate 203 is reduced, thereby reducing The longitudinal side of the liquid crystal display assembly 200 is wide.

Alternatively, by way of example and not limitation, the thickness of the liquid crystal layer 202 ranges from 2 μm to 7 μm.

It should be noted that at least two row driving microchips 205 in the liquid crystal display device 200 may be located on both sides of the pixel switch array 204, and the row driving microchip 205 on the side of the pixel switch array 204 may be used to control odd row pixels. The switch is turned on or off, and the row driving microchip 205 on the other side of the pixel switch array 204 can be used for control. The even-numbered rows of the pixel switches are turned on or off. Alternatively, the at least two row-driven microchips 205 of the liquid crystal display device 200 may be located on the same side of the pixel switch array 204, which is not specifically limited in the embodiment of the present application.

It should be noted that the TFT substrate in the display module 200 proposed in the present application can be applied to an organic light emitting diode (OLED) display component or other types of display components in addition to the liquid crystal display component described above. This application does not specifically limit this.

The application also includes a method of making a display assembly that includes at least the following steps.

Providing a pixel switch array and a driving microchip group on the upper surface of the thin film transistor TFT substrate, the driving microchip group being connected to the pixel switch array, wherein any one of the driving microchip groups driving the microchip is a single crystal silicon microchip, the driving The width of any one of the driving microchips in the microchip group is less than or equal to 500 μm, and the thickness of any one of the driving microchips is less than or equal to 10 μm, and any one of the driving microchips is cut by wet etching or dry etching on the wafer. Made.

Optionally, any one of the driving microchips in the driving microchip group is transplanted to the upper surface of the TFT substrate by a massive transfer technique.

Optionally, the driving microchip group comprises at least two row driving microchips and/or at least two column driving microchips, and any one of the at least two row driving microchips drives the microchip and the pixel switching array At least one row of pixel switches is connected, and any one of the at least two column driving microchips drives the microchip to be connected to at least one column of pixel switches.

Optionally, the method further includes: providing a control chip on an upper surface of the TFT substrate of the thin film transistor, the control chip respectively driving a microchip with any one of the at least two row driving microchips, and the at least two column drivers Any one of the microchips drives the microchips to be connected; or a flexible circuit board FPC is disposed on the upper surface of the TFT substrate, and a control chip is disposed on the upper surface of the FPC, and the control chip respectively drives the microchip with the at least two rows Any one of the row driving microchips, any one of the at least two column driving microchips is connected to the microchip, and the FPC is in contact with an upper surface portion of the TFT substrate.

Optionally, the control chip includes at least two control microchips, wherein the control microchip is a single crystal silicon microchip, and any one of the at least two control microchips controls the width of the microchip to be less than or equal to 500 μm, and the arbitrary one The thickness of the control microchip is less than or equal to 10 μm, and any one of the driving microchips is cut by a wet or dry etching process on the wafer.

Optionally, the at least two column driving microchips are integrated on the same microchip with the control microchip, and the microchip has the function of the control microchip and has the function of the at least two column driving microchips.

Optionally, the pixel switch array is an oxide semiconductor IGZO pixel switch array or a low temperature polysilicon LTPS pixel switch array or an amorphous silicon pixel switch array.

Optionally, the method further includes: providing a first flat layer on an upper surface of the pixel switch array; providing a liquid crystal layer upper panel above the first flat layer; and forming a liquid crystal layer upper panel on the first flat layer and the liquid crystal layer The liquid crystal layer is disposed between.

Optionally, the method further includes: providing a second flat layer on a lower surface of the upper panel of the liquid crystal layer; and disposing the liquid crystal layer between the first flat layer and the second flat layer.

The control chip is respectively connected to any one of the at least two row driving microchips, and any one of the at least two column driving microchips; or

a flexible circuit board FPC is disposed on an upper surface of the TFT substrate, and a control chip is disposed on an upper surface of the FPC, and the control chip drives the microchip, the at least two, respectively, with any one of the at least two row driving microchips Column drive Any one of the columns in the microchip drives the microchips to be connected, and the FPC is in contact with the upper surface portion of the TFT substrate.

Optionally, the liquid crystal layer has a thickness ranging from 2 μm to 7 μm.

The application also includes a display that includes a housing and a base, wherein the display assembly 200 is located within the housing.

The application further includes a terminal device including the display assembly 200, the housing in any of the above embodiments, wherein the display assembly 200 is disposed inside the housing. The terminal device can be a smartphone, a tablet, a wearable device, a personal computer, and the like.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The functions may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a standalone product. Based on such understanding, the technical solution of the present application, which is essential or contributes to the prior art, or a part of the technical solution, may be embodied in the form of a software product, which is stored in a storage medium, including The instructions are used to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. .

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

A display device comprising a thin film transistor TFT substrate, wherein an upper surface of the TFT substrate is provided with a pixel switch array and a driving microchip group, and the driving microchip group is connected to the pixel switch array, the driving Any one of the driving microchips in the microchip group is a single crystal silicon microchip, and the width of any one of the driving microchip groups is less than or equal to 500 μm, and the thickness of any one of the driving microchips is less than or equal to 10 μm.
The display module according to claim 1, wherein any one of the driving microchip groups is implanted on the upper surface of the TFT substrate by a massive transfer technique.
The display module according to claim 1 or 2, wherein the driving microchip group comprises at least two row driving microchips and/or at least two column driving microchips, the at least two row driving microchips Any one of the row driving microchips is connected to at least one row of pixel switches in the pixel switch array, and any one of the at least two column driving microchips is connected to at least one column of pixel switches.
The display assembly of claim 3, wherein the display component further comprises:

a control chip, wherein the control chip is respectively connected to any one of the at least two row driving microchips, and any one of the at least two column driving microchips, the control chip The surface is disposed on an upper surface of the TFT substrate.
The display module according to claim 4, wherein the control chip is disposed on an upper surface of the flexible circuit board FPC, and the FPC is in contact with an upper surface portion of the TFT substrate.
The display module according to claim 4, wherein the control chip comprises at least two control microchips, the control microchip is a single crystal silicon microchip, and any one of the at least two control microchips controls The width of the microchip is less than or equal to 500 μm, and the thickness of any one of the control microchips is less than or equal to 10 μm.
The display assembly according to claim 6, wherein the column driving microchip is integrated with the control microchip on a same microchip, and the microchip has the function of controlling the microchip, and has the The function of driving the microchip is described.
The display module according to any one of claims 1 to 7, wherein the pixel switch array is an oxide semiconductor IGZO pixel switch array, a low temperature polysilicon LTPS pixel switch array or an amorphous silicon pixel switch array.
The display assembly according to any one of claims 1 to 8, wherein the display component is a liquid crystal display component, and the liquid crystal display component further comprises:

a first flat layer, a liquid crystal layer and a liquid crystal layer upper panel, wherein the first flat layer is disposed on an upper surface of the pixel switch array, and the liquid crystal layer is disposed on the first flat layer and the upper panel of the liquid crystal layer between.
The display assembly of claim 9, wherein the display component further comprises:

a second flat layer, the second flat layer is located on a lower surface of the upper panel of the liquid crystal layer, and the liquid crystal layer is disposed between the first flat layer and the second flat layer.
The display assembly according to claim 9 or 10, wherein the at least two row driving microchips and the at least two column driving microchips are disposed below or above the sealant layer of the liquid crystal display assembly Location, or

The at least two row driving microchips, the at least two column driving microchips, and the sealant of the liquid crystal display assembly The layer is disposed on an upper surface of the TFT substrate, and the at least two row driving microchips and the at least two column driving microchips are disposed at an intermediate position between the sealant layer and the liquid crystal layer, or

The at least two row driving microchips, the at least two column driving microchips and the sealant layer of the liquid crystal display component are disposed on an upper surface of the TFT substrate, and the at least two row driving microchips and The at least two column drive microchips are at least partially wrapped by the sealant layer.
The display module according to any one of claims 9 to 11, wherein the liquid crystal layer has a thickness ranging from 2 μm to 7 μm.
A method of manufacturing a display assembly, the method comprising:

Providing a pixel switch array and a driving microchip group on an upper surface of the thin film transistor TFT substrate, wherein the driving microchip group is connected to the pixel switch array, and any one of the driving microchip groups driving the microchip is a single crystal silicon microchip The width of any one of the driving microchip groups is less than or equal to 500 μm, and the thickness of any one of the driving microchips is less than or equal to 10 μm, and any one of the driving microchips is wet-etched or dried on the wafer. The engraved process is cut.
The method according to claim 13, wherein any one of the driving microchip groups is transplanted to the upper surface of the TFT substrate by a massive transfer technique.
The method according to claim 13 or 14, wherein the driving microchip group comprises at least two row driving microchips and/or at least two column driving microchips, and the at least two row driving microchips Any one of the row driving microchips is connected to at least one row of pixel switches in the pixel switch array, and any one of the at least two column driving microchips is connected to at least one column of pixel switches.
The method of claim 15 wherein the method further comprises:

Providing a control chip on an upper surface of the thin film transistor TFT substrate, wherein the control chip respectively drives any one of the at least two row driving microchips and the at least two column driving microchips A column drive microchip is connected.
The method of claim 15 wherein the method further comprises:

a flexible circuit board FPC is disposed on an upper surface of the TFT substrate, and a control chip is disposed on an upper surface of the FPC, and the control chip drives a microchip with any one of the at least two row driving microchips, Any one of the at least two column driving microchips is connected to the microchip, and the FPC is in contact with an upper surface portion of the TFT substrate.
The method according to claim 16, wherein the control chip comprises at least two control microchips, the control microchip is a single crystal silicon microchip, and any one of the at least two control microchips controls the micro The width of the chip is less than or equal to 500 μm, and the thickness of any one of the control microchips is less than or equal to 10 μm, and any one of the control microchips is cut by a wet or dry process on the wafer.
The method of claim 18, wherein the method further comprises:

The column driving microchip and the control microchip are integrated on a same microchip, the microchip has the function of controlling the microchip, and has the function of the column driving microchip.
The method according to any one of claims 13 to 19, wherein the pixel switch array is an oxide semiconductor IGZO pixel switch array, a low temperature polysilicon LTPS pixel switch array or an amorphous silicon pixel switch array.
Method according to any one of claims 13 to 20, wherein the display component is a liquid In the case of a crystal display assembly, the method further includes:

Providing a first flat layer on an upper surface of the pixel switch array;

Providing a liquid crystal layer upper panel above the first planar layer;

A liquid crystal layer is disposed between the first flat layer and the upper panel of the liquid crystal layer.
The method of claim 21, wherein the method further comprises:

Providing a second flat layer on a lower surface of the upper panel of the liquid crystal layer;

The liquid crystal layer is disposed between the first flat layer and the second flat layer.
A method according to claim 21 or 22, wherein

Locating the at least two row driving microchips and the at least two column driving microchips at a position below or above the sealant layer of the liquid crystal display assembly; or

Locating the at least two row driving microchips and the at least two column driving microchips at an intermediate position between the sealant layer and the liquid crystal layer, and the at least two rows driving the microchips, the at least two a column driving microchip and the sealant layer are disposed on an upper surface of the TFT substrate; or

Providing at least two row driving microchips, the at least two column driving microchips and a sealant layer of the liquid crystal display assembly on an upper surface of the TFT substrate, and the at least two row driving microchips The at least two column drive microchips are at least partially wrapped by the sealant layer.
The method according to any one of claims 21 to 23, wherein the liquid crystal layer has a thickness ranging from 2 μm to 7 μm.
A display, comprising: a housing, a base, and a display assembly according to any one of claims 1 to 12, wherein the display assembly is disposed inside the housing.
A terminal device, comprising: a housing and a display assembly according to any one of claims 1 to 12, wherein the display assembly is disposed inside the housing.