TWI521690B - Transfer-bonding method for light-emitting devices and light-emitting device array - Google Patents

Transfer-bonding method for light-emitting devices and light-emitting device array Download PDF

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TWI521690B
TWI521690B TW101118745A TW101118745A TWI521690B TW I521690 B TWI521690 B TW I521690B TW 101118745 A TW101118745 A TW 101118745A TW 101118745 A TW101118745 A TW 101118745A TW I521690 B TWI521690 B TW I521690B
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layer
light
emitting
substrate
transferring
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TW101118745A
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TW201306242A (en
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葉文勇
趙嘉信
吳明憲
戴光佑
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財團法人工業技術研究院
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Priority to CN201210258044.5A priority Critical patent/CN102903804B/en
Priority to US13/557,231 priority patent/US20130026511A1/en
Publication of TW201306242A publication Critical patent/TW201306242A/en
Priority to US14/583,594 priority patent/US9306117B2/en
Priority to US14/970,548 priority patent/US9825013B2/en
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發光元件的轉移方法以及發光元件陣列 Light-emitting element transfer method and light-emitting element array

本申請案是有關於一種發光元件陣列的製造方法,且特別是有關於一種發光元件的轉移方法。 The present application relates to a method of fabricating an array of light-emitting elements, and more particularly to a method of transferring a light-emitting element.

無機發光二極體顯示器具備主動發光、高亮度等特點,因此已經廣泛地被應用於照明、顯示器等技術領域中。但單片微顯示器(monolithic micro-displays)一直以來都面臨彩色化的技術瓶頸。目前,已有習知技術提出利用磊晶技術於單一發光二極體晶片中製作出多層能夠發出不同色光之發光層,以使單一發光二極體晶片即可提供不同色光。但由於能夠發出不同色光之發光層的晶格常數不同,因此不容易成長在同一個基板上。此外,其他習知技術提出了利用發光二極體晶片搭配不同色轉換材料之彩色化技術,但是此技術仍面臨色轉材料之轉換效率過低以及塗佈均勻性等問題。 The inorganic light-emitting diode display has the characteristics of active light emission and high brightness, and thus has been widely used in the technical fields of illumination, display, and the like. However, monolithic micro-displays have always faced the technical bottleneck of colorization. At present, it has been proposed in the prior art to use a epitaxial technique to fabricate a plurality of light-emitting layers capable of emitting different colors of light in a single light-emitting diode wafer, so that a single light-emitting diode wafer can provide different color lights. However, since the lattice constants of the light-emitting layers capable of emitting different color lights are different, it is not easy to grow on the same substrate. In addition, other conventional techniques have proposed a colorization technique using a light-emitting diode chip with different color conversion materials, but this technology still faces problems such as low conversion efficiency and uniformity of color conversion materials.

除了上述兩種彩色化技術,亦有習知技術提出了發光二極體之轉貼技術,由於能夠發出不同色光之發光二極體可分別在適當的基板上成長,故發光二極體能夠具備較佳的磊晶品質與發光效率。是以,發光二極體之轉貼技術較有機會使單片微顯示器的亮度以及顯示品質提升。然而,如何快速且有效率地將發光二極體轉貼至單片微顯示器的線路基板上,實為目前業界關注的議題之一。 In addition to the above two colorization techniques, there are also known techniques for the transfer of light-emitting diodes. Since the light-emitting diodes capable of emitting different color lights can be respectively grown on appropriate substrates, the light-emitting diodes can be compared. Good epitaxial quality and luminous efficiency. Therefore, the transposition technology of the light-emitting diode is more organic, which increases the brightness and display quality of the single-chip microdisplay. However, how to quickly and efficiently transfer the light-emitting diodes to the circuit substrate of the single-chip microdisplay is one of the current topics of concern in the industry.

本申請案之一實施例提供一種發光元件的轉移方法以及發光元件陣列。 An embodiment of the present application provides a method for transferring a light-emitting element and an array of light-emitting elements.

本申請案之一實施例提供一種發光元件的轉移方法,其包括下列步驟(a)~步驟(d)。步驟(a):於一第一基板上形成多個陣列排列之發光元件,各發光元件包括一元件層以及一犧牲圖案,且犧牲圖案位於元件層與第一基板之間。步驟(b):於第一基板上形成一保護層以選擇性地覆蓋部分的發光元件,其中部分的發光元件未被保護層所覆蓋。步驟(c):令未被保護層所覆蓋之元件層與一第二基板接合。步驟(d):移除未被保護層所覆蓋的犧牲圖案,以使部分的元件層與第一基板分離而轉移至第二基板上。 An embodiment of the present application provides a method for transferring a light-emitting element, which comprises the following steps (a) to (d). Step (a): forming a plurality of array-arranged light-emitting elements on a first substrate, each of the light-emitting elements including an element layer and a sacrificial pattern, and the sacrificial pattern is between the element layer and the first substrate. Step (b): forming a protective layer on the first substrate to selectively cover a portion of the light-emitting elements, wherein a portion of the light-emitting elements are not covered by the protective layer. Step (c): bonding the component layer not covered by the protective layer to a second substrate. Step (d): removing the sacrificial pattern covered by the unprotected layer to separate part of the element layer from the first substrate and transferring it onto the second substrate.

本申請案之一實施例提供一種發光元件陣列,其包括一線路基板以及多個能夠發出不同色光的元件層,其中線路基板具有多個接墊以及多個位於接墊上的導電凸塊,而多個能夠發出不同色光的元件層係透過導電凸塊以及接墊而與線路基板電性連接。能夠發出不同色光的元件層具有不同的厚度,而與能夠發出不同色光的元件層接合的導電凸塊具有不同的高度,以使能夠發出不同色光的元件層之頂表面位於同一水平高度上。 An embodiment of the present application provides an array of light-emitting elements, including a circuit substrate and a plurality of component layers capable of emitting different colors of light, wherein the circuit substrate has a plurality of pads and a plurality of conductive bumps on the pads, and more An element layer capable of emitting different color lights is electrically connected to the circuit substrate through the conductive bumps and the pads. The element layers capable of emitting different color lights have different thicknesses, and the conductive bumps joined to the element layers capable of emitting different color lights have different heights such that the top surfaces of the element layers capable of emitting different color lights are at the same level.

本申請案之另一實施例提供一種發光元件陣列,其包括一線路基板以及多個能夠發出不同色光的元件層,其中線路基板具有多個接墊以及多個位於接墊上的導電凸塊,而多個能夠發出不同色光的元件層係透過導電凸塊以及接墊而與線路基板電性連接。能夠發出不同色光的元件層具 有不同的厚度,而與能夠發出不同色光的元件層接合的導電凸塊具有不同的高度,以使能夠發出不同色光的元件層之頂表面位於不同的水平高度上。 Another embodiment of the present application provides an array of light emitting elements including a circuit substrate and a plurality of component layers capable of emitting different color lights, wherein the circuit substrate has a plurality of pads and a plurality of conductive bumps on the pads, and A plurality of component layers capable of emitting different color lights are electrically connected to the circuit substrate through the conductive bumps and the pads. Component layer capable of emitting different colored lights There are different thicknesses, and the conductive bumps that are bonded to the component layers capable of emitting different colored lights have different heights so that the top surfaces of the component layers capable of emitting different colored lights are at different levels.

本申請案之一實施例可以快速且有效率地將發光元件由一基板轉移至另一基板上,有助於發光元件在微顯示器領域中的應用。 One embodiment of the present application can quickly and efficiently transfer a light-emitting element from one substrate to another, contributing to the application of the light-emitting element in the field of microdisplays.

為讓本申請案之上述特徵能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 In order to make the above-described features of the present application more apparent, the following detailed description of the embodiments and the accompanying drawings are set forth below.

【第一實施例】 [First Embodiment]

圖1A至圖1K為本申請案一實施例之發光元件的轉移方法之流程示意圖。請參照圖1A,首先,於一第一基板SUB1上形成多個陣列排列之發光元件100,各個發光元件100包括元件層110以及犧牲圖案120,且犧牲圖案120位於元件層110與第一基板SUB1之間。在本實施例中,位於同一個第一基板SUB1上的元件層110適於發出相同顏色的光線。舉例而言,第一基板SUB1上的元件層110例如同為紅光發光二極體、綠光發光二極體或者藍光發光二極體。此外,每個元件層110皆已包含一電極(未繪示)。 1A to 1K are schematic flow charts showing a method of transferring a light-emitting element according to an embodiment of the present application. Referring to FIG. 1A, first, a plurality of arrayed light-emitting elements 100 are formed on a first substrate SUB1. Each of the light-emitting elements 100 includes an element layer 110 and a sacrificial pattern 120, and the sacrificial pattern 120 is located on the element layer 110 and the first substrate SUB1. between. In the present embodiment, the element layer 110 on the same first substrate SUB1 is adapted to emit light of the same color. For example, the element layer 110 on the first substrate SUB1 is, for example, a red light emitting diode, a green light emitting diode or a blue light emitting diode. In addition, each of the component layers 110 already includes an electrode (not shown).

接著請參照圖1B,於第一基板SUB1上形成保護層PV以選擇性地覆蓋部分的發光元件100,其中部分的發光元件100未被保護層PV所覆蓋。在本實施例中,保護層PV例如為一光阻材料或其他介電材料,以在後續之犧牲圖案120的移除過程中,確保被保護層PV所覆蓋的發光 元件100不會與第一基板SUB1分離。舉例而言,保護層PV之材質可以是聚乙醯胺(Polyimide)或其他高分子材質,保護層PV之材質亦可以是氧化矽(SiOx)、氮化矽(SiNx)或其他無機介電材質。 Next, referring to FIG. 1B, a protective layer PV is formed on the first substrate SUB1 to selectively cover a portion of the light emitting element 100, wherein a portion of the light emitting element 100 is not covered by the protective layer PV. In this embodiment, the protective layer PV is, for example, a photoresist material or other dielectric material to ensure the illumination covered by the protective layer PV during the subsequent removal of the sacrificial pattern 120. The element 100 is not separated from the first substrate SUB1. For example, the material of the protective layer PV may be polyimide or other polymer materials, and the material of the protective layer PV may also be yttrium oxide (SiOx), tantalum nitride (SiNx) or other inorganic dielectric materials. .

接著請參照圖1C與圖1D,令未被保護層PV所覆蓋之元件層110與一第二基板SUB2接合,並且移除未被保護層PV所覆蓋的犧牲圖案120(如圖1C所示),以使部分的元件層110與第一基板SUB1分離而轉移至第二基板SUB2上(如圖1D所示)。在本實施例中,第二基板SUB2例如為單片微顯示器(monolithic micro-displays)中的線路基板(如具有多個接墊PAD之互補金氧半導體晶片),而未被保護層PV所覆蓋之元件層110例如是透過導電凸塊B與第二基板SUB2上之接墊PAD接合。舉例而言,導電凸塊B例如是金凸塊(gold bump)或是其他合金凸塊,而導電凸塊B與第二基板SUB2上之接墊PAD的接合(電性連接)例如是透過回焊(reflow)或是其他焊接製程達成。 Referring to FIG. 1C and FIG. 1D, the device layer 110 not covered by the protective layer PV is bonded to a second substrate SUB2, and the sacrificial pattern 120 not covered by the protective layer PV is removed (as shown in FIG. 1C). The part of the element layer 110 is separated from the first substrate SUB1 and transferred to the second substrate SUB2 (as shown in FIG. 1D). In this embodiment, the second substrate SUB2 is, for example, a circuit substrate in monolithic micro-displays (such as a complementary gold-oxygen semiconductor wafer having a plurality of pads PAD), and is not covered by the protective layer PV. The element layer 110 is bonded to the pad PAD on the second substrate SUB2 through the conductive bumps B, for example. For example, the conductive bumps B are, for example, gold bumps or other alloy bumps, and the bonding (electrical connection) of the conductive bumps B to the pads PAD on the second substrate SUB2 is, for example, transmitted back. Reflow or other welding process is achieved.

如圖1C所示,在導電凸塊B與接墊PAD接合的過程中,保護層PV可以有效且直接地控制第一基板SUB1與第二基板SUB2之間的距離,避免過度壓合的現象產生。換言之,保護層PV提供了接合終止(bonding stop)的功能,使得製程控制更為容易。 As shown in FIG. 1C, during the bonding of the conductive bump B and the pad PAD, the protective layer PV can effectively and directly control the distance between the first substrate SUB1 and the second substrate SUB2 to avoid excessive pressing. . In other words, the protective layer PV provides a bonding stop function, making process control easier.

在本實施例中,移除犧牲圖案的方法例如為濕式蝕刻(wet etch)。值得注意的是,所選用的蝕刻劑(etchant)與保護層PV之材質相關,具體而言,所選用的蝕刻劑對犧牲圖案120的蝕刻速率需遠高對保護層PV的蝕刻速率,以 確保被保護層PV所覆蓋之元件層110以及犧牲圖案120不會受到蝕刻劑的損害。 In the present embodiment, the method of removing the sacrificial pattern is, for example, a wet etch. It is worth noting that the selected etchant is related to the material of the protective layer PV. Specifically, the etching rate of the selected etchant to the sacrificial pattern 120 needs to be much higher than the etching rate of the protective layer PV. It is ensured that the element layer 110 and the sacrificial pattern 120 covered by the protective layer PV are not damaged by the etchant.

圖1A至圖1D已經概略敘述了將發光元件100從第一基板SUB1轉移至第二基板SUB2上的方法,為了將適於發出不同色光的元件層轉移至同一第二基板SUB2上,本實施例可選擇性地進行圖1E至圖1K中所繪示的製程步驟。 1A to 1D have schematically described a method of transferring the light-emitting element 100 from the first substrate SUB1 to the second substrate SUB2, in order to transfer the element layers suitable for emitting different color lights onto the same second substrate SUB2, this embodiment The process steps illustrated in Figures 1E-1K can be selectively performed.

接著請參照圖1E,於另一第一基板SUB1’上形成多個陣列排列之發光元件100’,各個發光元件100’包括元件層110’以及犧牲圖案120’,且犧牲圖案120’位於元件層110’與第一基板SUB1’之間。在本實施例中,位於同一個第一基板SUB1’上的元件層110’適於發出相同顏色的光線。舉例而言,第一基板SUB1’上的元件層110’例如同為紅光發光二極體、綠光發光二極體或者藍光發光二極體。值得注意的是,元件層110’與元件層110適於分別發出不同顏色的光線。 1E, a plurality of arrayed light-emitting elements 100' are formed on another first substrate SUB1'. Each of the light-emitting elements 100' includes an element layer 110' and a sacrificial pattern 120', and the sacrificial pattern 120' is located at the element layer. 110' is between the first substrate SUB1'. In the present embodiment, the element layer 110' on the same first substrate SUB1' is adapted to emit light of the same color. For example, the element layer 110' on the first substrate SUB1' is, for example, a red light emitting diode, a green light emitting diode or a blue light emitting diode. It is to be noted that the element layer 110' and the element layer 110 are adapted to emit light of different colors, respectively.

如圖1E所示,第一基板SUB1’上形成有保護層PV’以選擇性地覆蓋部分的發光元件100’,其中部分的發光元件100’未被保護層PV’所覆蓋。圖1E中的保護層PV’與圖1B中的保護層PV具有相同的功能,故於此不再贅述。 As shown in Fig. 1E, a protective layer PV' is formed on the first substrate SUB1' to selectively cover a portion of the light-emitting element 100', wherein a portion of the light-emitting element 100' is not covered by the protective layer PV'. The protective layer PV' in Fig. 1E has the same function as the protective layer PV in Fig. 1B, and therefore will not be described again.

接著請參照圖1F與圖1G,令未被保護層PV’所覆蓋之元件層110’與一第二基板SUB2接合,並且移除未被保護層PV’所覆蓋的犧牲圖案120’(如圖1F所示),以使部分的元件層110’與第一基板SUB1’分離而轉移至第二基板SUB2上(如圖1G所示)。在本實施例中,未被保護層 PV’所覆蓋之元件層110’例如是透過導電凸塊B’與第二基板SUB2上之接墊PAD接合。舉例而言,導電凸塊B’例如是金凸塊(gold bump)或是其他合金凸塊,而導電凸塊B’與第二基板SUB2上之接墊PAD的接合(電性連接)例如是透過回焊(reflow)或是其他焊接製程達成。 1F and FIG. 1G, the device layer 110' not covered by the protective layer PV' is bonded to a second substrate SUB2, and the sacrificial pattern 120' not covered by the protective layer PV' is removed (as shown in FIG. 1F), so that part of the element layer 110' is separated from the first substrate SUB1' and transferred to the second substrate SUB2 (as shown in FIG. 1G). In this embodiment, the unprotected layer The element layer 110' covered by the PV' is bonded to the pad PAD on the second substrate SUB2 through the conductive bump B', for example. For example, the conductive bump B' is, for example, a gold bump or other alloy bump, and the bonding (electrical connection) of the conductive bump B' to the pad PAD on the second substrate SUB2 is, for example, Reached by reflow or other welding processes.

請參照圖1H,於另一第一基板SUB1”上形成多個陣列排列之發光元件100”,各個發光元件100”包括元件層110”以及犧牲圖案120”,且犧牲圖案120”位於元件層110”與第一基板SUB1”之間。在本實施例中,位於同一個第一基板SUB1”上的元件層110”適於發出相同顏色的光線。舉例而言,第一基板SUB1”上的元件層110”例如同為紅光發光二極體、綠光發光二極體或者藍光發光二極體。值得注意的是,元件層110”、元件層110’與元件層110適於分別發出不同顏色的光線。 Referring to FIG. 1H, a plurality of arrayed light-emitting elements 100" are formed on another first substrate SUB1". Each of the light-emitting elements 100" includes an element layer 110" and a sacrificial pattern 120", and the sacrificial pattern 120" is located at the element layer 110. Between "with the first substrate SUB1". In the present embodiment, the element layer 110" located on the same first substrate SUB1" is adapted to emit light of the same color. For example, the element layer 110 ′ on the first substrate SUB 1 ′′ is, for example, a red light emitting diode, a green light emitting diode or a blue light emitting diode. It is to be noted that the element layer 110", the element layer 110' and the element layer 110 are adapted to emit light of different colors, respectively.

如圖1H所示,第一基板SUB1”上形成有保護層PV”以選擇性地覆蓋部分的發光元件100”,其中部分的發光元件100”未被保護層PV”所覆蓋。圖1E中的保護層PV”與圖1B中的保護層PV具有相同的功能,故於此不再贅述。 As shown in FIG. 1H, a protective layer PV" is formed on the first substrate SUB1" to selectively cover a portion of the light-emitting element 100", wherein a portion of the light-emitting element 100" is not covered by the protective layer PV". The protective layer PV" has the same function as the protective layer PV in FIG. 1B, and thus will not be described again.

接著請參照圖1I,令未被保護層PV”所覆蓋之元件層110”與一第二基板SUB2接合,並且移除未被保護層PV”所覆蓋的犧牲圖案120”,以使部分的元件層110”與第一基板SUB1”分離而轉移至第二基板SUB2上(如圖1G所示)。在本實施例中,未被保護層PV”所覆蓋之元件層110”例如是透過導電凸塊B”與第二基板SUB2上之接墊PAD接合。舉例而言,導電凸塊B”例如是金凸塊(gold bump) 或是其他合金凸塊,而導電凸塊B”與第二基板SUB2上之接墊PAD的接合(電性連接)例如是透過回焊(reflow)或是其他焊接製程達成。 Referring to FIG. 1I, the device layer 110" covered by the unprotected layer PV" is bonded to a second substrate SUB2, and the sacrificial pattern 120" covered by the unprotected layer PV" is removed to make part of the components. The layer 110" is separated from the first substrate SUB1" and transferred onto the second substrate SUB2 (as shown in FIG. 1G). In this embodiment, the device layer 110" not covered by the protective layer PV" is bonded to the pad PAD on the second substrate SUB2, for example, through the conductive bump B". For example, the conductive bump B" is, for example, Gold bump Or other alloy bumps, and the bonding (electrical connection) of the conductive bumps B" to the pads PAD on the second substrate SUB2 is achieved, for example, by reflow or other soldering processes.

如圖1A至圖1I所示,本實施例會依序將元件層110、元件層110’以及元件層110”轉移至第二基板SUB2上。詳言之,本實施例令元件層110與導電凸塊B的總厚度小於元件層110’與導電凸塊B’的總厚度,並令元件層110’與導電凸塊B’的總厚度小於元件層110”與導電凸塊B”的總厚度。當元件層110與導電凸塊B的總厚度小於元件層110’與導電凸塊B’的總厚度時,元件層110”在轉移至第二基板SU2B的過程中便不會受到元件層110的干涉。同樣地,當元件層110’與導電凸塊B’的總厚度小於元件層110”與導電凸塊B”的總厚度時,元件層110'''在轉移至第二基板SU2B的過程中便不會受到元件層110’的干涉。 As shown in FIG. 1A to FIG. 1I, in this embodiment, the element layer 110, the element layer 110', and the element layer 110" are sequentially transferred onto the second substrate SUB2. In detail, the device layer 110 and the conductive bump are in this embodiment. The total thickness of the block B is smaller than the total thickness of the element layer 110' and the conductive bump B', and the total thickness of the element layer 110' and the conductive bump B' is smaller than the total thickness of the element layer 110" and the conductive bump B". When the total thickness of the element layer 110 and the conductive bump B is smaller than the total thickness of the element layer 110' and the conductive bump B', the element layer 110" is not subjected to the element layer 110 during the transfer to the second substrate SU2B. put one's oar in. Similarly, when the total thickness of the element layer 110' and the conductive bump B' is smaller than the total thickness of the element layer 110" and the conductive bump B", the element layer 110"" is transferred to the second substrate SU2B. It is not interfered by the element layer 110'.

接著請參照圖1J,為了確保元件層110、110’、100”之間的發生異常的短路現象,本實施例可先於第二基板SUB2上形成一絕緣層IN以填入元件層110、110’、100”之間,之後再於元件層110、110’、100”以及絕緣層IN上形成一共通電極COM。 Referring to FIG. 1J, in order to ensure an abnormal short circuit between the element layers 110, 110', 100", the present embodiment may form an insulating layer IN on the second substrate SUB2 to fill the element layers 110, 110. Between ', 100', a common electrode COM is formed on the element layers 110, 110', 100" and the insulating layer IN.

接著請參照圖1K,由於能夠發出不同色光的元件層110、110’、100”在厚度上不盡相同,而導電凸塊B、B’、B”具有不同的高度,因此能夠發出不同色光的元件層110、110’、100”之頂表面位於不同的水平高度上。承上述,本實施例可於共通電極COM上形成一平坦層PLN,而在完成平坦層PLN的製作之後,本實施例可以選擇性地 於平坦層PLN上形成黑矩陣BM及/或微透鏡陣列MLA。舉例而言,黑矩陣BM具有多個開口AP,且各開口AP分別位於元件層110、110’、100”至少其中一個上方。此外,微透鏡陣列MLA包括多個陣列排列之微透鏡ML,且各微透鏡ML分別位於元件層110、110’、100”至少其中一個上方。更具體而言,各微透鏡ML分別位於其各開口AP中,且對應於元件層110、110’、100”至少其中一個。 Referring to FIG. 1K, since the element layers 110, 110', 100" capable of emitting different color lights are different in thickness, and the conductive bumps B, B', B" have different heights, different color lights can be emitted. The top surface of the element layers 110, 110', 100" is located at different levels. In the above embodiment, a flat layer PLN may be formed on the common electrode COM, and after the fabrication of the flat layer PLN is completed, the embodiment Optionally A black matrix BM and/or a microlens array MLA is formed on the flat layer PLN. For example, the black matrix BM has a plurality of openings AP, and each of the openings AP is located at least one of the element layers 110, 110', 100". Further, the microlens array MLA includes a plurality of arrays of microlenses ML, and Each of the microlenses ML is located above at least one of the element layers 110, 110', 100". More specifically, each of the microlenses ML is located in each of its openings AP, and corresponds to at least one of the element layers 110, 110', 100".

由於本實施例採用了犧牲圖案120、120’、120”、保護層PV、PV’、PV”以及導電凸塊B、B’、B”之搭配,因此本實施例可以十分有效率地將不同的元件層110、110’、100”轉移至第二基板SUB2上。 Since the embodiment adopts the matching of the sacrificial patterns 120, 120', 120", the protective layer PV, the PV', the PV" and the conductive bumps B, B', B", the embodiment can be very efficiently different. The component layers 110, 110', 100" are transferred to the second substrate SUB2.

為了更為有效率地將能夠發出不同色光的發光元件轉移至同一個第二基板SUB2上,本實施例提出圖2、圖3以及圖4中的接合順序,透過圖2、圖3以及圖4中的接合順序可以讓所有的發光元件皆順利地轉移至第二基板SUB2上,不會有部分發光元件仍然遺留在第一基板SUB1(或第一基板SUB1’、SUB1”)上的問題。 In order to more efficiently transfer the light-emitting elements capable of emitting different color lights onto the same second substrate SUB2, the present embodiment proposes the bonding sequence in FIGS. 2, 3 and 4 through FIG. 2, FIG. 3 and FIG. The bonding order in the middle allows all of the light-emitting elements to be smoothly transferred onto the second substrate SUB2 without the problem that some of the light-emitting elements remain on the first substrate SUB1 (or the first substrate SUB1', SUB1").

如圖2至圖4所示,首先,提供3個第一基板SUB1(如圖3所示)或4個第一基板SUB1(如圖2或圖4所示),其中一個第一基板SUB上具有紅色發光元件110R,另外一個第一基板SUB1上具有藍色發光元件110B,而其餘第一基板SUB1上具有綠色發光元件110G。接著,第一基板SUB1上的紅色發光元件110R、綠色發光元件110G以及藍色發光元件110B轉移至第二基板SUB2的預定位置上(如依照虛線箭頭所示)。如此,即可快速且有效率 地將紅色發光元件110R、綠色發光元件110G以及藍色發光元件110B轉移至第二基板SUB2從第一基板SUB1轉移至第二基板SUB2上,不會有部分發光元件仍然遺留在第一基板SUB1上的問題。 As shown in FIG. 2 to FIG. 4, first, three first substrates SUB1 (as shown in FIG. 3) or four first substrates SUB1 (shown in FIG. 2 or FIG. 4) are provided, one of which is on the first substrate SUB. There is a red light-emitting element 110R, and the other first substrate SUB1 has a blue light-emitting element 110B, and the remaining first substrate SUB1 has a green light-emitting element 110G. Next, the red light-emitting element 110R, the green light-emitting element 110G, and the blue light-emitting element 110B on the first substrate SUB1 are transferred to predetermined positions of the second substrate SUB2 (as indicated by the dashed arrows). So you can be fast and efficient The red light emitting element 110R, the green light emitting element 110G, and the blue light emitting element 110B are transferred to the second substrate SUB2 and transferred from the first substrate SUB1 to the second substrate SUB2, and some of the light emitting elements are still left on the first substrate SUB1. The problem.

犧牲圖案的製造方法Sacrificial pattern manufacturing method

圖5A至圖5C為一種犧牲圖案的製造方法。首先請參照圖5A,於第一基板SUB1上依序形成犧牲層120a以及半導體磊晶層110a,其中第一基板SUB1例如為藍寶石(sapphire)基板,而犧牲層120a例如是藉由磊晶方式形成的氧化鋅(ZnO)磊晶層、AlGaN磊晶層、AlInN磊晶層等。 5A to 5C are views showing a method of manufacturing a sacrificial pattern. First, referring to FIG. 5A, a sacrificial layer 120a and a semiconductor epitaxial layer 110a are sequentially formed on the first substrate SUB1, wherein the first substrate SUB1 is, for example, a sapphire substrate, and the sacrificial layer 120a is formed by, for example, epitaxy. A zinc oxide (ZnO) epitaxial layer, an AlGaN epitaxial layer, an AlInN epitaxial layer, or the like.

接著請參照圖5B,圖案化半導體磊晶層110a以及犧牲層120a,以於第一基板SUB1上形成多個元件層110以及多個位於元件層110與第一基板SUB1之間的犧牲圖案120。在本實施例中。圖案化半導體磊晶層110a以及犧牲層120a的方法例如為微影蝕刻製程。 Next, referring to FIG. 5B, the semiconductor epitaxial layer 110a and the sacrificial layer 120a are patterned to form a plurality of element layers 110 and a plurality of sacrificial patterns 120 between the element layer 110 and the first substrate SUB1 on the first substrate SUB1. In this embodiment. The method of patterning the semiconductor epitaxial layer 110a and the sacrificial layer 120a is, for example, a photolithography etching process.

最後請參照圖5C,當部分的元件層110被保護層PV所覆蓋,未被保護層PV所覆蓋的犧牲圖案120可以透過蝕刻劑而被移除,使未被保護層PV所覆蓋的元件層110與第一基板SUB1分離。當犧牲圖案120之材質為氧化鋅時,所使用的蝕刻劑包括磷酸(H3PO4)、鹽酸(HCl)或其他酸性溶液。當犧牲圖案120b之材質為AlGaN或AlInN時,所使用的蝕刻劑包括氫氧化鉀(KOH)、硝酸(HNO3)或其他溶液。 Finally, referring to FIG. 5C, when a part of the element layer 110 is covered by the protective layer PV, the sacrificial pattern 120 not covered by the protective layer PV may be removed by an etchant, so that the element layer not covered by the protective layer PV The 110 is separated from the first substrate SUB1. When the material of the sacrificial pattern 120 is zinc oxide, the etchant used includes phosphoric acid (H 3 PO 4 ), hydrochloric acid (HCl) or other acidic solution. When the material of the sacrificial pattern 120b is AlGaN or AlInN, the etchant used includes potassium hydroxide (KOH), nitric acid (HNO 3 ) or other solutions.

圖6A至圖6C為另一種犧牲圖案的製造方法。請參照 圖6A,先於第一基板SUB1上形成柵狀犧牲層120b,在於柵狀犧牲層120b以及第一基板SUB1上形成半導體磊晶層110a,其中第一基板SUB1例如為藍寶石(sapphire)基板,而柵狀犧牲層120b例如是藉由磊晶方式形成的氧化鋅(ZnO)磊晶層、AlGaN磊晶層、AlInN磊晶層等。 6A to 6C illustrate another method of fabricating a sacrificial pattern. Please refer to 6A, a gate sacrificial layer 120b is formed on the first substrate SUB1, and a semiconductor epitaxial layer 110a is formed on the gate sacrificial layer 120b and the first substrate SUB1, wherein the first substrate SUB1 is, for example, a sapphire substrate, and The gate sacrificial layer 120b is, for example, a zinc oxide (ZnO) epitaxial layer, an AlGaN epitaxial layer, an AlInN epitaxial layer, or the like formed by epitaxy.

接著請參照圖6B,圖案化半導體磊晶層110a,以於第一基板SUB1上形成多個元件層110以及多個鑲嵌於元件層110與第一基板SUB1之間的柵狀犧牲圖案120b。在本實施例中。圖案化半導體磊晶層110a的方法例如為微影蝕刻製程。 Next, referring to FIG. 6B, the semiconductor epitaxial layer 110a is patterned to form a plurality of element layers 110 and a plurality of gate-shaped sacrificial patterns 120b embedded between the element layer 110 and the first substrate SUB1 on the first substrate SUB1. In this embodiment. The method of patterning the semiconductor epitaxial layer 110a is, for example, a photolithography etching process.

最後請參照圖6C,當部分的元件層110被保護層PV所覆蓋,未被保護層PV所覆蓋的犧牲圖案120b可以透過蝕刻劑而被移除,使未被保護層PV所覆蓋的元件層110能夠很容易地與第一基板SUB1分離。當犧牲圖案120b之材質為氧化鋅時,所使用的蝕刻劑包括磷酸(H3PO4)、鹽酸(HCl)或其他酸性溶液。當犧牲圖案120b之材質為AlGaN或AlInN時,所使用的蝕刻劑包括氫氧化鉀(KOH)、硝酸(HNO3)或其他溶液。 Finally, referring to FIG. 6C, when a part of the element layer 110 is covered by the protective layer PV, the sacrificial pattern 120b not covered by the protective layer PV may be removed by an etchant, so that the element layer not covered by the protective layer PV The 110 can be easily separated from the first substrate SUB1. When the material of the sacrificial pattern 120b is zinc oxide, the etchant used includes phosphoric acid (H 3 PO 4 ), hydrochloric acid (HCl) or other acidic solution. When the material of the sacrificial pattern 120b is AlGaN or AlInN, the etchant used includes potassium hydroxide (KOH), nitric acid (HNO 3 ) or other solutions.

【第二實施例】 [Second embodiment]

圖7A至圖7K為本申請案第二實施例之發光元件的轉移方法之流程示意圖。請參照圖7A,首先,於成長基板SUB上依序形成第一型摻雜半導體層210a、發光層210b以及第二型摻雜半導體層210c。在本實施例中,第一型摻雜半導體層210a例如是藉由磊晶方式所形成的N型摻雜 GaN磊晶層,發光層210b例如是藉由磊晶方式所形成的單一或多重量子井發光層,而第二型摻雜半導體層210c例如是藉由磊晶方式所形成的P型摻雜GaN磊晶層。此領域具有通常知識者可根據實際設計需求而在此階段進行光子晶體、共振腔、歐姆接觸層等元件的製作,本實施例不再詳加說明。 7A to 7K are schematic flow charts showing a method of transferring a light-emitting element according to a second embodiment of the present application. Referring to FIG. 7A, first, a first type doped semiconductor layer 210a, a light emitting layer 210b, and a second type doped semiconductor layer 210c are sequentially formed on the growth substrate SUB. In the present embodiment, the first type doped semiconductor layer 210a is, for example, an N-type doping formed by epitaxial means. The GaN epitaxial layer, the light-emitting layer 210b is, for example, a single or multiple quantum well light-emitting layer formed by epitaxial means, and the second-type doped semiconductor layer 210c is, for example, a P-type doped GaN formed by epitaxial means. Epitaxial layer. The general knowledge in this field can be used to fabricate components such as photonic crystals, resonant cavities, and ohmic contact layers at this stage according to actual design requirements, and this embodiment will not be described in detail.

請參照圖7B,於第一基板SUB1上形成一犧牲層120a,並令第二型摻雜半導體層210c與犧牲層120a暫時性接合。 Referring to FIG. 7B, a sacrificial layer 120a is formed on the first substrate SUB1, and the second type doped semiconductor layer 210c is temporarily bonded to the sacrificial layer 120a.

請參照圖7C,令第一型摻雜半導體層210a與成長基板SUB分離。在本實施例中,令第一型摻雜半導體層210a與成長基板SUB分離的方法包括雷射剝離技術(laser lift-off)。此外,此領域具有通常知識者可選擇性地在第一型摻雜半導體層210a與成長基板SUB分離之後,進行第一型摻雜半導體層210a的薄化製程(例如研磨或回蝕刻),或於第一型摻雜半導體層210a上進行光子晶體的製作。 Referring to FIG. 7C, the first type doped semiconductor layer 210a is separated from the growth substrate SUB. In the present embodiment, the method of separating the first type doped semiconductor layer 210a from the growth substrate SUB includes a laser lift-off technique. In addition, a person skilled in the art can selectively perform a thinning process (eg, grinding or etch back) of the first type doped semiconductor layer 210a after the first type doped semiconductor layer 210a is separated from the growth substrate SUB, or Fabrication of the photonic crystal is performed on the first type doped semiconductor layer 210a.

請參照圖7D,第一型摻雜半導體層210a與成長基板SUB分離之後,圖案化第一型半導體層210a、發光層210b、第二型半導體層210c以及犧牲層120a,以形成多個第一型半導體圖案210a’、多個發光圖案210b’、多個第二型半導體圖案210c’以及犧牲圖案120。 Referring to FIG. 7D, after the first type doped semiconductor layer 210a is separated from the growth substrate SUB, the first type semiconductor layer 210a, the light emitting layer 210b, the second type semiconductor layer 210c, and the sacrificial layer 120a are patterned to form a plurality of first The semiconductor pattern 210a', the plurality of light emitting patterns 210b', the plurality of second type semiconductor patterns 210c', and the sacrificial pattern 120.

請參照圖7E,於第一型半導體圖案210a’上形成多個電極210d,其中位於同一個犧牲圖案120上的第一型半導體圖案210a’、發光圖案210b’、第二型半導體圖案210c’ 以及電極210d構成一元件層210。 Referring to FIG. 7E, a plurality of electrodes 210d are formed on the first type semiconductor pattern 210a', wherein the first type semiconductor pattern 210a', the light emitting pattern 210b', and the second type semiconductor pattern 210c' are located on the same sacrificial pattern 120. And the electrode 210d constitutes an element layer 210.

請參照圖7F,於第一基板SUB1上形成保護層PV以選擇性地覆蓋部分的元件層210以及犧牲圖案120,其中部分的元件層210以及犧牲圖案120未被保護層PV所覆蓋。在本實施例中,保護層PV例如為一光阻材料或其他介電材料,以在後續之犧牲圖案120的移除過程中,確保被保護層PV所覆蓋的元件層210不會與第一基板SUB1分離。舉例而言,保護層PV之材質可以是聚乙醯胺(Polyimide)或其他高分子材質,保護層PV之材質亦可以是氧化矽(SiOx)、氮化矽(SiNx)或其他無機介電材質。 Referring to FIG. 7F, a protective layer PV is formed on the first substrate SUB1 to selectively cover a portion of the element layer 210 and the sacrificial pattern 120, wherein a portion of the element layer 210 and the sacrificial pattern 120 are not covered by the protective layer PV. In this embodiment, the protective layer PV is, for example, a photoresist material or other dielectric material to ensure that the component layer 210 covered by the protective layer PV does not overlap with the first during the subsequent removal of the sacrificial pattern 120. The substrate SUB1 is separated. For example, the material of the protective layer PV may be polyimide or other polymer materials, and the material of the protective layer PV may also be yttrium oxide (SiOx), tantalum nitride (SiNx) or other inorganic dielectric materials. .

接著請參照圖7G,提供一第二基板SUB2,此第二基板SUB2例如為單片微顯示器(monolithic micro-displays)中的線路基板(如具有多個接墊PAD之互補金氧半導體晶片)。接著,令未被保護層PV所覆蓋之元件層210與一第二基板SUB2接合,並且移除未被保護層PV所覆蓋的犧牲圖案120,以使部分的元件層110與第一基板SUB1分離而轉移至第二基板SUB2上。,而未被保護層PV所覆蓋之元件層210例如是透過導電凸塊B與第二基板SUB2上之接墊PAD接合。舉例而言,導電凸塊B例如是金凸塊(gold bump)或是其他合金凸塊,而導電凸塊B與第二基板SUB2上之接墊PAD的接合(電性連接)例如是透過回焊(reflow)或是其他焊接製程達成。 Next, referring to FIG. 7G, a second substrate SUB2 is provided. The second substrate SUB2 is, for example, a circuit substrate in monolithic micro-displays (such as a complementary gold-oxygen semiconductor wafer having a plurality of pads PAD). Next, the element layer 210 not covered by the protective layer PV is bonded to a second substrate SUB2, and the sacrificial pattern 120 not covered by the protective layer PV is removed to separate part of the element layer 110 from the first substrate SUB1. And transferred to the second substrate SUB2. The component layer 210 not covered by the protective layer PV is bonded to the pad PAD on the second substrate SUB2 through the conductive bump B, for example. For example, the conductive bumps B are, for example, gold bumps or other alloy bumps, and the bonding (electrical connection) of the conductive bumps B to the pads PAD on the second substrate SUB2 is, for example, transmitted back. Reflow or other welding process is achieved.

如圖7G所示,在導電凸塊B與接墊PAD接合的過程中,保護層PV可以有效且直接地控制第一基板SUB1與第二基板SUB2之間的距離,避免過度壓合的現象產生。換言之, 保護層PV提供了接合終止(bonding stop)的功能,使得製程控制更為容易。 As shown in FIG. 7G, during the bonding of the conductive bumps B and the pads PAD, the protective layer PV can effectively and directly control the distance between the first substrate SUB1 and the second substrate SUB2 to avoid excessive pressing. . In other words, The protective layer PV provides the function of a bonding stop, making process control easier.

請參照圖7H,在將元件層210轉移至第二基板SUB2之後,此領域具有通常知識者可以選擇性地重覆前述圖7A至圖7G中的步驟至少一次,以將元件層210’以及元件層210”轉移至第二基板SUB2上。由於元件層210、210’、210”能夠發出不同色光(例如是紅光、藍光、綠光之組合),因此第二基板SUB2上的元件層210、210’、210”能夠提供全彩顯示之功能。 Referring to FIG. 7H, after transferring the element layer 210 to the second substrate SUB2, those skilled in the art can selectively repeat the steps in the foregoing FIGS. 7A to 7G at least once to bring the element layer 210' and the element. The layer 210" is transferred onto the second substrate SUB2. Since the element layers 210, 210', 210" are capable of emitting different colors of light (for example, a combination of red, blue, and green light), the element layer 210 on the second substrate SUB2, 210', 210" can provide full color display.

如圖7H所示,由於能夠發出不同色光的元件層210、210’、210”具有不盡相同的厚度,且與元件層210、210’、210”接合的導電凸塊B、B’、B”亦具有不盡相同的高度,故元件層210、210’、210”之頂表面能夠位於相同的水平高度上。然而,本實施例並不限定元件層210、210’、210”之頂表面必須位於相同的水平高度上,經過導電凸塊B、B’、B”的高度調整,吾人亦可讓元件層210、210’、210”之頂表面分別位於不同水平高度上。 As shown in FIG. 7H, since the element layers 210, 210', 210" capable of emitting different color lights have different thicknesses, and the conductive bumps B, B', B bonded to the element layers 210, 210', 210" "There are also different heights, so the top surfaces of the component layers 210, 210', 210" can be located at the same level. However, the embodiment does not limit that the top surfaces of the component layers 210, 210', 210" must be at the same level. After the height adjustment of the conductive bumps B, B', B", the component layer 210 can also be used. The top surfaces of 210', 210" are located at different levels.

請參照圖7I與圖7J,在元件層210、210’、210”皆與第二基板SUB2接合之後,接著第二基板SUB2上之元件層210、210’、210”之間形成一絕緣平坦層PLN’(如圖7I所示),再於元件層210、210’、210”以及絕緣平坦層PLN’上形成一共通電極COM。之後,再於共通電極COM上形成一黑矩陣BM,此黑矩陣BM具有多個開口AP,且各個開口AP分別位於元件層210、210’或210”其中一個上方。在本實施例中,黑矩陣BM可選用導電性良好的遮光 材質,由於黑矩陣BM係直接設置於共通電極COM上,因此黑矩陣BM可以進一步降低共通電極COM的電阻值,以進一步提升元件層210、210’、210”的發光效率。 Referring to FIG. 7I and FIG. 7J, after the element layers 210, 210', 210" are bonded to the second substrate SUB2, an insulating flat layer is formed between the element layers 210, 210', 210" on the second substrate SUB2. PLN' (shown in FIG. 7I), a common electrode COM is formed on the element layers 210, 210', 210" and the insulating flat layer PLN'. Thereafter, a black matrix BM is formed on the common electrode COM, which is black. The matrix BM has a plurality of openings AP, and each of the openings AP is located above one of the element layers 210, 210' or 210". In this embodiment, the black matrix BM can be selected with good electrical conductivity. Since the black matrix BM is directly disposed on the common electrode COM, the black matrix BM can further reduce the resistance value of the common electrode COM to further improve the luminous efficiency of the element layers 210, 210', 210".

最後請參照圖7K,為了進一步優化元件層210、210’、210”的光學效能,本實施例可以選擇性地於元件層210、210’、210”上方形成一微透鏡陣列MLA,此微透鏡陣列MLA包括多個陣列排列之微透鏡ML,且各個微透鏡ML分別位於元件層210、210’或210”至少其中一個上方。 Finally, referring to FIG. 7K, in order to further optimize the optical performance of the element layers 210, 210', 210", the embodiment may selectively form a microlens array MLA above the element layers 210, 210', 210". The array MLA includes a plurality of array-arranged microlenses ML, and each microlens ML is located above at least one of the element layers 210, 210' or 210", respectively.

【第三實施例】 [Third embodiment]

圖8A至圖8K為本申請案第三實施例之發光元件的轉移方法之流程示意圖。本實施例之發光元件的轉移方法與第二實施例之發光元件的轉移方法類似,惟二者主要差異在於圖8B至圖8H所繪示的步驟。因此,以下將搭配圖8A至圖8K進行詳細之描述。 8A to 8K are schematic flow charts showing a method of transferring a light-emitting element according to a third embodiment of the present application. The transfer method of the light-emitting element of the present embodiment is similar to the transfer method of the light-emitting element of the second embodiment, but the main difference between the two is the steps illustrated in FIGS. 8B to 8H. Therefore, a detailed description will be made below with reference to FIGS. 8A to 8K.

請參照圖8A,首先,於成長基板SUB上依序形成第一型摻雜半導體層310a、發光層310b以及第二型摻雜半導體層310c。在本實施例中,第一型摻雜半導體層310a例如是藉由磊晶方式所形成的N型摻雜GaN磊晶層,發光層310b例如是藉由磊晶方式所形成的單一或多重量子井發光層,而第二型摻雜半導體層310c例如是藉由磊晶方式所形成的P型摻雜GaN磊晶層。此領域具有通常知識者可根據實際設計需求而在此階段進行光子晶體的製作,本實施例不再詳加說明。 Referring to FIG. 8A, first, a first type doped semiconductor layer 310a, a light emitting layer 310b, and a second type doped semiconductor layer 310c are sequentially formed on the growth substrate SUB. In this embodiment, the first type doped semiconductor layer 310a is, for example, an N-type doped GaN epitaxial layer formed by epitaxial method, and the luminescent layer 310b is, for example, a single or multiple quantum formed by epitaxial means. The well-emitting layer, and the second-type doped semiconductor layer 310c is, for example, a P-type doped GaN epitaxial layer formed by epitaxy. Photonic crystals can be produced at this stage according to actual design requirements by those skilled in the art, and will not be described in detail in this embodiment.

請參照圖8B,於第二型摻雜半導體層310c上形成多 個電極310d’,且電極310d與第二型摻雜半導體層310c之間具有良好的歐姆接觸。 Referring to FIG. 8B, a plurality of layers are formed on the second type doped semiconductor layer 310c. The electrodes 310d' have good ohmic contact between the electrodes 310d and the second type doped semiconductor layer 310c.

請參照圖8C,於第一基板SUB1上形成一犧牲層120a,並令第二型摻雜半導體層310c與犧牲層120a暫時性接合。 Referring to FIG. 8C, a sacrificial layer 120a is formed on the first substrate SUB1, and the second type doped semiconductor layer 310c is temporarily bonded to the sacrificial layer 120a.

請參照圖8D,令第一型摻雜半導體層310a與成長基板SUB分離。在本實施例中,令第一型摻雜半導體層310a與成長基板SUB分離的方法包括雷射剝離技術(laser lift-off)。此外,此領域具有通常知識者可選擇性地在第一型摻雜半導體層310a與成長基板SUB分離之後,進行第一型摻雜半導體層310a的薄化製程(例如研磨或回蝕刻),或於第一型摻雜半導體層310a上進行光子晶體的製作。 Referring to FIG. 8D, the first type doped semiconductor layer 310a is separated from the growth substrate SUB. In the present embodiment, the method of separating the first type doped semiconductor layer 310a from the growth substrate SUB includes a laser lift-off technique. In addition, a person skilled in the art can selectively perform a thinning process (eg, grinding or etch back) of the first type doped semiconductor layer 310a after the first type doped semiconductor layer 310a is separated from the growth substrate SUB, or Fabrication of the photonic crystal is performed on the first type doped semiconductor layer 310a.

請參照圖8E,第一型摻雜半導體層310a與成長基板SUB分離之後,圖案化第一型半導體層310a、發光層310b、第二型半導體層310c以及犧牲層120a,以形成多個第一型半導體圖案310a’、多個發光圖案310b’、多個第二型半導體圖案310c’以及犧牲圖案120。此處,位於同一個犧牲圖案120上的第一型半導體圖案310a’、發光圖案310b’、第二型半導體圖案310c’以及電極310d’構成一元件層310。 Referring to FIG. 8E, after the first type doped semiconductor layer 310a is separated from the growth substrate SUB, the first type semiconductor layer 310a, the light emitting layer 310b, the second type semiconductor layer 310c, and the sacrificial layer 120a are patterned to form a plurality of first The semiconductor pattern 310a', the plurality of light emitting patterns 310b', the plurality of second type semiconductor patterns 310c', and the sacrificial pattern 120. Here, the first type semiconductor pattern 310a', the light emitting pattern 310b', the second type semiconductor pattern 310c', and the electrode 310d' on the same sacrificial pattern 120 constitute an element layer 310.

請參照圖8F,於第一基板SUB1上形成保護層PV以選擇性地覆蓋部分的元件層310以及犧牲圖案120,其中部分的元件層310以及犧牲圖案120未被保護層PV所覆蓋。在本實施例中,保護層PV例如為一光阻材料或其他 介電材料,以在後續之犧牲圖案120的移除過程中,確保被保護層PV所覆蓋的元件層310不會與第一基板SUB1分離。舉例而言,保護層PV之材質可以是聚乙醯胺(Polyimide)或其他高分子材質,保護層PV之材質亦可以是氧化矽(SiOx)、氮化矽(SiNx)或其他無機介電材質。 Referring to FIG. 8F, a protective layer PV is formed on the first substrate SUB1 to selectively cover a portion of the element layer 310 and the sacrificial pattern 120, wherein a portion of the element layer 310 and the sacrificial pattern 120 are not covered by the protective layer PV. In this embodiment, the protective layer PV is, for example, a photoresist material or other The dielectric material is such that during the removal of the subsequent sacrificial pattern 120, it is ensured that the element layer 310 covered by the protective layer PV is not separated from the first substrate SUB1. For example, the material of the protective layer PV may be polyimide or other polymer materials, and the material of the protective layer PV may also be yttrium oxide (SiOx), tantalum nitride (SiNx) or other inorganic dielectric materials. .

接著請參照圖8G,提供一第二基板SUB2,此第二基板SUB2例如為一模版(stamp mold),而此模版具有多個突出P。接著,令此第二基板SUB2上的突出P與未被保護層PV所覆蓋之元件層310接合。之後,移除未被保護層PV所覆蓋的犧牲圖案120,以使部分的元件層310被轉移至模版(SUB2)上。 Next, referring to FIG. 8G, a second substrate SUB2 is provided. The second substrate SUB2 is, for example, a stamp mold, and the template has a plurality of protrusions P. Next, the protrusion P on the second substrate SUB2 is bonded to the element layer 310 not covered by the protective layer PV. Thereafter, the sacrificial pattern 120 not covered by the protective layer PV is removed, so that part of the element layer 310 is transferred onto the stencil (SUB2).

接著請參照圖8H,接著令轉移至模版(SUB2)上之元件層310與一線路基板SUB3接合,以將元件層310進一步轉移至此線路基板SUB3上,其中線路基板SUB3例如為單片微顯示器(monolithic micro-displays)中的線路基板(如具有多個接墊PAD之互補金氧半導體晶片)。在本實施例中,元件層310例如是透過導電凸塊B與第二基板SUB2上之接墊PAD接合。舉例而言,導電凸塊B例如是金凸塊(gold bump)或是其他合金凸塊,而導電凸塊B與第二基板SUB2上之接墊PAD的接合(電性連接)例如是透過回焊(reflow)或是其他焊接製程達成。 Next, referring to FIG. 8H, the component layer 310 transferred to the stencil (SUB2) is then bonded to a circuit substrate SUB3 to further transfer the component layer 310 onto the circuit substrate SUB3, wherein the circuit substrate SUB3 is, for example, a monolithic microdisplay ( A circuit substrate in a monolithic micro-displays (such as a complementary MOS wafer having a plurality of pads PAD). In the present embodiment, the element layer 310 is bonded to the pad PAD on the second substrate SUB2 through the conductive bump B, for example. For example, the conductive bumps B are, for example, gold bumps or other alloy bumps, and the bonding (electrical connection) of the conductive bumps B to the pads PAD on the second substrate SUB2 is, for example, transmitted back. Reflow or other welding process is achieved.

請參照圖8I,在將元件層310先轉移至第二基板SUB2再轉移至線路基板SUB3之後,此領域具有通常知識者可以選擇性地重覆前述圖8A至圖8H中的步驟至少一次,以將元件層310’以及元件層310”轉移至線路基板SUB3上。 Referring to FIG. 8I, after the component layer 310 is first transferred to the second substrate SUB2 and then transferred to the circuit substrate SUB3, those skilled in the art can selectively repeat the steps in the foregoing FIGS. 8A to 8H at least once. The element layer 310' and the element layer 310" are transferred onto the wiring substrate SUB3.

如圖8H所示,由於能夠發出不同色光的元件層310、310’、310”具有不盡相同的厚度,且與元件層310、310’、310”接合的導電凸塊B、B’、B”亦具有不盡相同的高度,故元件層310、310’、310”之頂表面能夠位於相同的水平高度上。然而,本實施例並不限定元件層310、310’、310”之頂表面必須位於相同的水平高度上,經過導電凸塊B、B’、B”的高度調整,吾人亦可讓元件層310、310’、310”之頂表面分別位於不同水平高度上。 As shown in FIG. 8H, since the element layers 310, 310', 310" capable of emitting different color lights have different thicknesses, and the conductive bumps B, B', B bonded to the element layers 310, 310', 310" "There are also different heights, so the top surfaces of the component layers 310, 310', 310" can be located at the same level. However, this embodiment does not limit that the top surfaces of the element layers 310, 310', 310" must be at the same level. After the height adjustment of the conductive bumps B, B', B", the component layer 310 can also be used. The top surfaces of 310', 310" are located at different levels.

由於圖8I至圖8K中所述之製程與圖7I至圖7K中所示之製程雷同,故本實施例於此不再重述。 Since the process described in FIG. 8I to FIG. 8K is the same as the process shown in FIG. 7I to FIG. 7K, the present embodiment will not be repeated here.

從上述之多個實施例可知,本申請案可以快速且有效率地將發光元件由一基板轉移至另一基板上,有助於發光元件在微顯示器領域中的應用。 It can be seen from the above various embodiments that the present application can quickly and efficiently transfer a light-emitting element from one substrate to another, which contributes to the application of the light-emitting element in the field of microdisplays.

雖然本申請案已以實施例揭露如上,然其並非用以限定本申請案,任何所屬技術領域中具有通常知識者,在不脫離本申請案之精神和範圍內,當可作些許之更動與潤飾,故本申請案之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present application has been disclosed in the above embodiments, it is not intended to limit the application, and any person having ordinary skill in the art can make some changes without departing from the spirit and scope of the present application. Retouching, the scope of protection of this application is subject to the definition of the scope of the patent application attached.

100、100’、100”‧‧‧發光元件 100, 100', 100" ‧ ‧ luminescent components

100R‧‧‧紅色發光元件 100R‧‧‧Red light-emitting elements

100G‧‧‧綠色發光元件 100G‧‧‧Green light-emitting elements

100B‧‧‧藍色發光元件 100B‧‧‧Blue light-emitting element

110、110’、110”‧‧‧元件層 110, 110', 110" ‧ ‧ component layers

110a‧‧‧半導體磊晶層 110a‧‧‧Semiconductor epitaxial layer

120、120’、120”、120b‧‧‧犧牲圖案 120, 120', 120", 120b‧‧‧ sacrificial patterns

120a‧‧‧犧牲層 120a‧‧‧sacrificial layer

210a、310a‧‧‧第一型摻雜半導體層 210a, 310a‧‧‧ first type doped semiconductor layer

210b、310b‧‧‧發光層 210b, 310b‧‧‧ luminescent layer

210c、310c‧‧‧第二型摻雜半導體層 210c, 310c‧‧‧Second type doped semiconductor layer

210、210’、210”、310、310’、310”‧‧‧元件層 210, 210', 210", 310, 310', 310" ‧ ‧ component layers

210a’、310a’‧‧‧第一型半導體圖案 210a', 310a'‧‧‧ first type semiconductor pattern

210b’、310b’‧‧‧發光圖案 210b’, 310b’‧‧‧ illuminating patterns

210c’、310c’‧‧‧第二型半導體圖案 210c', 310c'‧‧‧ second type semiconductor pattern

210d、310d‧‧‧電極 210d, 310d‧‧‧ electrodes

PV、PV’‧‧‧保護層 PV, PV'‧‧‧ protective layer

B、B’‧‧‧導電凸塊 B, B’‧‧‧ conductive bumps

IN‧‧‧絕緣層 IN‧‧‧Insulation

COM‧‧‧共通電極 COM‧‧‧ common electrode

PLN‧‧‧平坦層 PLN‧‧‧flat layer

PLN’‧‧‧絕緣平坦層 PLN’‧‧‧Insulated flat layer

BM‧‧‧黑矩陣 BM‧‧‧Black Matrix

AP‧‧‧開口 AP‧‧‧ openings

MLA‧‧‧微透鏡陣列 MLA‧‧‧Microlens Array

ML‧‧‧微透鏡 ML‧‧‧microlens

SUB‧‧‧成長基板 SUB‧‧‧ growth substrate

SUB1、SUB1’、SUB1”‧‧‧第一基板 SUB1, SUB1', SUB1"‧‧‧ first substrate

SUB2‧‧‧第二基板 SUB2‧‧‧second substrate

SUB3‧‧‧線路基板 SUB3‧‧‧ circuit substrate

PAD‧‧‧接墊 PAD‧‧‧ pads

圖1A至圖1K為本申請案第一實施例之發光元件的轉移方法之流程示意圖。 1A to 1K are schematic flow charts showing a method of transferring a light-emitting element according to a first embodiment of the present application.

圖2、圖3以及圖4為發光元件與第二基板之接合順序。 2, 3, and 4 show the bonding order of the light-emitting element and the second substrate.

圖5A至圖5C為一種犧牲圖案的製造方法。 5A to 5C are views showing a method of manufacturing a sacrificial pattern.

圖6A至圖6C為另一種犧牲圖案的製造方法。 6A to 6C illustrate another method of fabricating a sacrificial pattern.

圖7A至圖7K為本申請案第二實施例之發光元件的轉移方法之流程示意圖。 7A to 7K are schematic flow charts showing a method of transferring a light-emitting element according to a second embodiment of the present application.

圖8A至圖8K為本申請案第三實施例之發光元件的轉移方法之流程示意圖。 8A to 8K are schematic flow charts showing a method of transferring a light-emitting element according to a third embodiment of the present application.

100‧‧‧發光元件 100‧‧‧Lighting elements

110‧‧‧元件層 110‧‧‧Component layer

120‧‧‧犧牲圖案 120‧‧‧sacrificial pattern

PV‧‧‧保護層 PV‧‧‧ protective layer

B‧‧‧導電凸塊 B‧‧‧conductive bumps

SUB1‧‧‧第一基板 SUB1‧‧‧ first substrate

SUB2‧‧‧第二基板 SUB2‧‧‧second substrate

PAD‧‧‧接墊 PAD‧‧‧ pads

Claims (19)

一種發光元件的轉移方法,包括:(a)於一第一基板上形成多個陣列排列之發光元件,各發光元件包括一元件層以及一犧牲圖案,且該犧牲圖案位於該元件層與該第一基板之間;(b)於該第一基板上形成一保護層以選擇性地覆蓋部分的發光元件,其中部分的發光元件未被該保護層所覆蓋;(c)令未被該保護層所覆蓋之元件層與一第二基板接合;以及(d)將未被該保護層所覆蓋的犧牲圖案從該第一基板與該元件層上移除,以使部分的元件層與該第一基板分離而轉移至該第二基板上。 A method for transferring a light-emitting element, comprising: (a) forming a plurality of array-arranged light-emitting elements on a first substrate, each light-emitting element comprising an element layer and a sacrificial pattern, wherein the sacrificial pattern is located at the element layer and the (b) forming a protective layer on the first substrate to selectively cover a portion of the light-emitting elements, wherein a portion of the light-emitting elements are not covered by the protective layer; (c) is not protected by the protective layer The covered component layer is bonded to a second substrate; and (d) removing the sacrificial pattern not covered by the protective layer from the first substrate and the component layer such that a portion of the component layer and the first The substrate is separated and transferred onto the second substrate. 如申請專利範圍第1項所述之發光元件的轉移方法,其中於該第一基板上形成該些發光元件的方法包括:於一成長基板上依序形成一第一型摻雜半導體層、一發光層以及一第二型摻雜半導體層;於該第一基板上形成一犧牲層;令該第二型摻雜半導體層與該犧牲層接合;令該第一型摻雜半導體層與該成長基板分離;圖案化該第一型半導體層、該發光層、該第二型半導體層以及該犧牲層,以形成多個第一型半導體圖案、多個發光圖案、多個第二型半導體圖案以及該犧牲圖案;以及於該些第一型半導體圖案上形成多個電極。 The method for transferring a light-emitting element according to claim 1, wherein the method of forming the light-emitting elements on the first substrate comprises: sequentially forming a first-type doped semiconductor layer on a growth substrate, a light-emitting layer and a second-type doped semiconductor layer; forming a sacrificial layer on the first substrate; bonding the second-type doped semiconductor layer to the sacrificial layer; and the first-type doped semiconductor layer and the growth Separating the substrate; patterning the first type semiconductor layer, the light emitting layer, the second type semiconductor layer, and the sacrificial layer to form a plurality of first type semiconductor patterns, a plurality of light emitting patterns, a plurality of second type semiconductor patterns, and The sacrificial pattern; and forming a plurality of electrodes on the first type semiconductor patterns. 如申請專利範圍第2項所述之發光元件的轉移方法,其中該犧牲層包括一柵狀犧牲層。 The method of transferring a light-emitting element according to claim 2, wherein the sacrificial layer comprises a gate-like sacrificial layer. 如申請專利範圍第1項所述之發光元件的轉移方法,其中該第二基板包括一線路基板,該線路基板具有多個接墊以及多個位於該些接墊上的導電凸塊,而未被該保護層所覆蓋之元件層係透過部分的導電凸塊而與接墊接合,且當未被該保護層所覆蓋的犧牲圖案被移除時,部分的元件層被轉移至該線路基板上。 The method for transferring a light-emitting element according to claim 1, wherein the second substrate comprises a circuit substrate, the circuit substrate has a plurality of pads and a plurality of conductive bumps on the pads, and is not The component layer covered by the protective layer is bonded to the pad through a portion of the conductive bump, and when the sacrificial pattern not covered by the protective layer is removed, part of the component layer is transferred onto the circuit substrate. 如申請專利範圍第4項所述之發光元件的轉移方法,更包括重覆步驟(a)至步驟(d)至少一次,以將能夠發出不同色光的元件層轉移至該線路基板上。 The method for transferring a light-emitting element according to claim 4, further comprising repeating steps (a) to (d) at least once to transfer an element layer capable of emitting light of different colors onto the circuit substrate. 如申請專利範圍第5項所述之發光元件的轉移方法,其中能夠發出不同色光的元件層具有不同的厚度,而與能夠發出不同色光的元件層接合的導電凸塊具有不同的高度,以使能夠發出不同色光的元件層之頂表面位於同一的水平高度上。 The method for transferring a light-emitting element according to claim 5, wherein the element layers capable of emitting different color lights have different thicknesses, and the conductive bumps joined to the element layers capable of emitting different color lights have different heights, so that The top surfaces of the component layers capable of emitting different colored lights are at the same level. 如申請專利範圍第1項所述之發光元件的轉移方法,更包括:於該第二基板上之該些元件層上形成一共通電極。 The method for transferring a light-emitting element according to claim 1, further comprising: forming a common electrode on the element layers on the second substrate. 如申請專利範圍第7項所述之發光元件的轉移方法,更包括:於該共通電極上形成一黑矩陣,該黑矩陣具有多個開口,且各該開口分別位於至少其中一個元件層上方。 The method for transferring a light-emitting element according to claim 7, further comprising: forming a black matrix on the common electrode, the black matrix having a plurality of openings, and each of the openings is located above at least one of the element layers. 如申請專利範圍第1項所述之發光元件的轉移方法,更包括:形成一微透鏡陣列,該微透鏡陣列包括多個陣列排列之微透鏡,且各該微透鏡分別位於至少其中一個元件層上 方。 The method for transferring a light-emitting element according to claim 1, further comprising: forming a microlens array comprising a plurality of array-arranged microlenses, each of the microlenses being respectively located in at least one of the element layers on square. 如申請專利範圍第1項所述之發光元件的轉移方法,其中於該第一基板上形成該些發光元件的方法包括:於一成長基板上依序形成一第一型摻雜半導體層、一發光層以及一第二型摻雜半導體層;於該第二型摻雜半導體層上形成多個電極;於該第一基板上形成一犧牲層;令該犧牲層與該第二型摻雜半導體層以及該些電極接合;令該第一型摻雜半導體層與該成長基板分離;圖案化該第一型半導體層、該發光層、該第二型半導體層以及該犧牲層,以形成多個第一型半導體圖案、多個發光圖案、多個第二型半導體圖案以及該些犧牲圖案。 The method for transferring a light-emitting element according to claim 1, wherein the method of forming the light-emitting elements on the first substrate comprises: sequentially forming a first-type doped semiconductor layer on a growth substrate, a light emitting layer and a second type doped semiconductor layer; forming a plurality of electrodes on the second type doped semiconductor layer; forming a sacrificial layer on the first substrate; and the sacrificial layer and the second type doped semiconductor a layer and the electrodes are bonded; separating the first type doped semiconductor layer from the growth substrate; patterning the first type semiconductor layer, the light emitting layer, the second type semiconductor layer, and the sacrificial layer to form a plurality of a first type semiconductor pattern, a plurality of light emitting patterns, a plurality of second type semiconductor patterns, and the sacrificial patterns. 如申請專利範圍第10項所述之發光元件的轉移方法,其中該犧牲層包括一柵狀犧牲層。 The method of transferring a light-emitting element according to claim 10, wherein the sacrificial layer comprises a gate-like sacrificial layer. 如申請專利範圍第10項所述之發光元件的轉移方法,其中該第二基板包括一模版(stamp mold),該模版具有多個突出(protrusions),而未被該保護層所覆蓋之發光元件係與該些突出接合,且當未被該保護層所覆蓋的犧牲圖案被移除時,部分的元件層被轉移至該模版上。 The method for transferring a light-emitting element according to claim 10, wherein the second substrate comprises a stamp mold having a plurality of protrusions, and the light-emitting element not covered by the protective layer And engaging the protrusions, and when the sacrificial pattern not covered by the protective layer is removed, part of the element layer is transferred onto the stencil. 如申請專利範圍第12項所述之發光元件的轉移方法,更包括:(e)令轉移至該模版上之部分的元件層與一線路基板接合,以將元件層進一步轉移至一線路基板上,其中該線路基板具有多個接墊以及多個位於該些接墊上的導電凸塊,而該些電極係透過部分的導電凸塊而與接墊接合。 The method for transferring a light-emitting element according to claim 12, further comprising: (e) bonding the component layer transferred to the portion of the stencil to a circuit substrate to further transfer the component layer to a circuit substrate. The circuit substrate has a plurality of pads and a plurality of conductive bumps on the pads, and the electrodes are coupled to the pads through the conductive bumps of the portions. 如申請專利範圍第10項所述之發光元件的轉移方法,更包括重覆步驟(a)至步驟(e)至少一次,以將能夠發出不同色光的元件層轉移至該線路基板上。 The method for transferring a light-emitting element according to claim 10, further comprising repeating steps (a) to (e) at least once to transfer an element layer capable of emitting light of different colors onto the circuit substrate. 如申請專利範圍第14項所述之發光元件的轉移方法,其中能夠發出不同色光的元件層具有不同的厚度,而與能夠發出不同色光的元件層接合的導電凸塊具有不同的高度,以使能夠發出不同色光的元件層之頂表面位於不同的水平高度上。 The method for transferring a light-emitting element according to claim 14, wherein the element layers capable of emitting different color lights have different thicknesses, and the conductive bumps joined to the element layers capable of emitting different color lights have different heights, so that The top surfaces of the component layers capable of emitting different colored lights are at different levels. 一種發光元件陣列,包括:一線路基板,具有多個接墊以及多個位於該些接墊上的導電凸塊;以及多個能夠發出不同色光的元件層,透過該些導電凸塊以及該些接墊而與該線路基板電性連接,其中能夠發出不同色光的元件層具有不同的厚度,而與能夠發出不同色光的元件層接合的導電凸塊具有不同的高度,以使能夠發出不同色光的元件層之頂表面位於同一水平高度上。 An array of light-emitting elements includes: a circuit substrate having a plurality of pads and a plurality of conductive bumps on the pads; and a plurality of component layers capable of emitting different colors of light, through the conductive bumps and the connections The pad is electrically connected to the circuit substrate, wherein the component layers capable of emitting different color lights have different thicknesses, and the conductive bumps bonded to the component layers capable of emitting different color lights have different heights to enable components capable of emitting different color lights The top surfaces of the layers are at the same level. 如申請專利範圍第16項所述之發光元件陣列,更包括:一共通電極,位於該些元件層上。 The light-emitting device array of claim 16, further comprising: a common electrode disposed on the component layers. 如申請專利範圍第17項所述之發光元件陣列,更包括:一黑矩陣,位於該共通電極上,其中該黑矩陣具有多個開口,且各該開口分別位於其中一個元件層上方。 The light-emitting device array of claim 17, further comprising: a black matrix on the common electrode, wherein the black matrix has a plurality of openings, and each of the openings is located above one of the component layers. 如申請專利範圍第16項所述之發光元件陣列,更包括:一微透鏡陣列,包括多個陣列排列之微透鏡,且各該 微透鏡分別位於其中一個元件層上方。 The light-emitting element array of claim 16, further comprising: a microlens array comprising a plurality of array-arranged microlenses, and each of the The microlenses are respectively located above one of the component layers.
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