TWI708104B - Display array - Google Patents
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本發明是有關於一種半導體結構,且特別是有關於一種顯示陣列。The present invention relates to a semiconductor structure, and more particularly to a display array.
微型發光二極體(Micro Light Emitting Diode,Micro LED)具有諸如壽命長、體積小、高抗震性、低熱產生及低功率消耗等優點,在目前也已被應用於平板及小型尺寸的顯示器。近年來,微型發光二極體已朝多色彩及高亮度發展,因此,在未來的科技應用上,將會有更多的應用領域及層面,甚至能取代目前一般常見的發光二極體。Micro Light Emitting Diode (Micro LED) has advantages such as long life, small size, high shock resistance, low heat generation and low power consumption, and has also been applied to flat panel and small size displays. In recent years, miniature light-emitting diodes have developed toward multi-color and high-brightness. Therefore, in the future technology applications, there will be more application fields and levels, and can even replace the current common light-emitting diodes.
然而在目前的技術中,縮小晶粒尺寸將面臨兩個主要的困難點。其中一者為在發光的效率上,由於微型發光二極體的尺寸為微米級,故相較於一般尺寸的發光二極體而言,晶粒邊緣所帶來的發光效率衰退將佔整體發光效率的大半比例以上。此外,其中另一者為,在上述微型發光二極體陣列的製程中,除了需事先對晶粒切割或圖案化以定義出不同的發光平台之外,還需進行共電極、平坦化及巨量轉移等製程,使得製程不但複雜且成本居高不下。However, in the current technology, shrinking the grain size will face two main difficulties. One of them is the luminous efficiency. Since the size of the miniature light-emitting diode is in the micron range, compared with the general-sized light-emitting diode, the luminous efficiency degradation caused by the edge of the crystal grain will account for the overall luminescence. More than half of the efficiency. In addition, the other one is that in the above-mentioned micro light emitting diode array manufacturing process, in addition to cutting or patterning the dies in advance to define different light emitting platforms, common electrodes, planarization and macros are also required. Processes such as volume transfer make the process not only complicated but also costly.
本發明提供一種顯示陣列,可增加發光效率並降低製程難度。The invention provides a display array, which can increase the luminous efficiency and reduce the difficulty of the manufacturing process.
本發明提供一種顯示陣列,包括一半導體堆疊層、一絕緣層、多個電極墊以及一驅動背板。半導體堆疊層具有多個發光區域。絕緣層配置於半導體堆疊層的一外表面並與半導體堆疊層接觸。絕緣層具有多個開口。電極墊配置於絕緣層。驅動背板配置於半導體堆疊層,其中電極墊分別經過絕緣層的開口與部份的半導體堆疊層及驅動背板電性連接以驅動發光區域,電極墊位於絕緣層的開口中且被絕緣層隔開,且在半導體堆疊層中相鄰的發光區域間未經圖案化。The invention provides a display array including a semiconductor stack layer, an insulating layer, a plurality of electrode pads and a driving backplane. The semiconductor stacked layer has a plurality of light emitting regions. The insulating layer is disposed on an outer surface of the semiconductor stacked layer and is in contact with the semiconductor stacked layer. The insulating layer has a plurality of openings. The electrode pad is disposed on the insulating layer. The driving backplane is configured on the semiconductor stack, wherein the electrode pads are electrically connected to part of the semiconductor stack and the driving backplane through the openings of the insulating layer to drive the light-emitting area. The electrode pads are located in the openings of the insulating layer and are separated by the insulating layer. Open and unpatterned between adjacent light-emitting regions in the semiconductor stack.
基於上述,在本發明的顯示陣列中,絕緣層具有多個開口,以使電極墊位於絕緣層的開口中被絕緣層隔開,進而使電極墊分別經過絕緣層的開口與部份的半導體堆疊層電性連接以在半導體堆疊層形成彼此電性隔離的多個發光區域。因此,相較於傳統的作法,可簡化製程程序及製作難度,並解決傳統晶粒經蝕刻而產生邊界發光效率衰退的問題。Based on the above, in the display array of the present invention, the insulating layer has a plurality of openings, so that the electrode pads are located in the openings of the insulating layer and are separated by the insulating layer, so that the electrode pads respectively pass through the openings of the insulating layer and part of the semiconductor stack. The layers are electrically connected to form a plurality of light-emitting regions electrically isolated from each other in the semiconductor stack layer. Therefore, compared with the traditional method, the manufacturing process and manufacturing difficulty can be simplified, and the problem of the boundary luminous efficiency decline caused by the traditional die etching can be solved.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.
隨著科技的發展,顯示器的尺寸逐年縮小,故其內部元件及結構也需縮小。因此,本發明一實施例所提供的顯示陣列可提供作為微型發光二極體顯示器中的顯示陣列,並具有良好的發光效果。換句話說,即為由微型發光二極體所形成的微型顯示陣列。With the development of science and technology, the size of the display is shrinking year by year, so its internal components and structure also need to be reduced. Therefore, the display array provided by an embodiment of the present invention can be used as a display array in a miniature light emitting diode display, and has a good light emitting effect. In other words, it is a miniature display array formed by miniature light-emitting diodes.
圖1A至圖1G依序為本發明一實施例的顯示陣列的製造方法的剖面示意圖。請先參考圖1A及圖1B。在本實施例的晶體封裝製程中,首先,提供一基板10,且在基板10上形成一半導體堆疊層110。在本實施例中,基板10可以為砷化鎵(GaAs)基板、磷化鎵(GaP)基板、磷化銦(InP)基板、藍寶石(Sapphire)基板、碳化矽(SiC)基板、矽(Si)基板或氮化鎵(GaN)基板,以適於將多個半導體材料層、多個導電材料層及/或多個絕緣材料層鍍覆於其表面上。1A to 1G are schematic cross-sectional diagrams of a manufacturing method of a display array according to an embodiment of the present invention. Please refer to Figure 1A and Figure 1B first. In the crystal packaging process of this embodiment, first, a
在本實施例中,半導體堆疊層110包括第一半導體材料層112、發光材料層114以及第二半導體材料層116。第一半導體材料層112為P型(P-type)半導體層,且第二半導體材料層116為N型(N-type)半導體層,但本發明不限於此。在其他實施例中,第一半導體材料層112為N型半導體層,且第二半導體材料層116可以為P型半導體層。N型(N-type)半導體層的材料例如是具有IVA族元素摻雜的N型氮化鎵(n-GaN),P型半導體層的材料例如是具有IIA族元素摻雜的P型氮化鎵(p-GaN),發光材料層114例如具有多重量子井(Multiple Quantum Well;MQW)結構。多重量子井結構包括以重複的方式交替設置的多個量子井層(Well)和多個量子阻障層(Barrier)。In this embodiment, the semiconductor stacked
進一步來說,發光材料層114的材料例如是包括交替堆疊的多層氮化銦鎵(InGaN)以及多層氮化鎵(GaN),藉由設計發光材料層114中銦(In)或鎵(Ga)的比例,可使發光材料層114發出特定的顏色光線,在本實施例中,例如是藍光或紫外光。第一半導體材料層112、發光材料層114及第二半導體材料層116例如可以藉由有機金屬化學氣相沉積法(Metal-organic Chemical Vapor Deposition;MOCVD)形成。關於上述的第一半導體材料層112、發光材料層114或第二半導體材料層116的材料或形成方式僅為舉例,本發明並不以此為限。Further, the material of the
值得一提的是,半導體堆疊層110不具有圖案化或經切割的步驟。意即,半導體堆疊層110並未經過微影成像過程或進行蝕刻製程,或者半導體堆疊層110未經過切割製程而進一步分割區域。因此,半導體堆疊層110在平行基板10的延伸方向上為連續延伸的結構,故可降低顯示陣列的製程難度。It is worth mentioning that the semiconductor stacked
請參考圖1C至圖1E。在上述的步驟之後,形成一絕緣層120以及多個電極墊130於半導體堆疊層110上,其中絕緣層120具有多個開口O1,且這些電極墊130位於絕緣層120的開口O1中且被絕緣層120隔開,且絕緣層120直接連接於半導體堆疊層110的表面外,如圖1E所繪示。詳細而言,在本實施例中,絕緣層120包括一第一絕緣層122以及一第二絕緣層124。第一絕緣層122例如是由絕緣材料製成且具有陣列排列圖案化的介電保護層,形成於半導體堆疊層110上,且第一絕緣層122具有多個開口O11。所述絕緣材料可使用具吸光性質的絕緣材料或具反射性質的絕緣材料,其中具吸光性質的絕緣材料可以具吸光性質的材料直接製作而成,而具反射性質的絕緣材料可利用具有不同折射率的多層鍍膜所產生反射效果製作而成,但本發明並不限於此。電極墊130配置於第一絕緣層122的這些開口O11中。而第二絕緣層124例如是封裝絕緣膠體,填充於電極墊130之間的空間並固定電極墊130與第一絕緣層122。可使每個電極墊130位於第一絕緣層122的開口O11及第二絕緣層124的開口O12所共同形成的開口O1中,且第一絕緣層122位於第二絕緣層124與半導體堆疊層110之間。換句話說,在絕緣層120的這些開口O1中,這些電極墊130完全地接觸絕緣層。因此,這些電極墊130分別經過絕緣層120的這些開口O1與部份的半導體堆疊層110電性連接,進而在半導體堆疊層110中形成多個發光區域(見圖1G的發光區域A)。具體而言,在製造過程中,可規劃每個電極墊130與半導體堆疊層110接觸的面積及相鄰電極墊130的間距,而使這些發光區域彼此電性隔離,並且,相鄰電極墊130的週期相同於顯示面板相鄰子畫素的週期。更詳細而言,上述發光區域彼此電性隔離可以是指部份電性隔離的多個發光區域,或者是完全電性隔離的多個發光區域,本發明並不限於此。Please refer to Figure 1C to Figure 1E. After the above steps, an
圖2為圖1G的顯示陣列的俯視示意圖。請參考圖1F、圖1G及圖2。在上述的步驟之後,將半導體堆疊層110、絕緣層120及電極墊130由基板10轉移配置在一驅動背板140上,以形成顯示陣列100。驅動背板140的材質可為玻璃、石英、有機聚合物、矽質晶圓或是其他適宜的材料,適用於與半導體堆疊層110或電極墊130電性連接,但本發明並不限於此。在本實施例中,先將半導體堆疊層110背向基板10的一側與驅動背板140進行接合製程。在進行上述接合製程之後,移除基板10。詳細而言,可以將結構上下翻轉(如圖1F所繪示)之後,藉由雷射剝離(laser lift-off;LLO)或其他適宜的方法將基板10自半導體堆疊層110分離。FIG. 2 is a schematic top view of the display array of FIG. 1G. Please refer to Figure 1F, Figure 1G and Figure 2. After the above steps, the semiconductor stacked
此外,在一些實施例中,將半導體堆疊層110、絕緣層120及電極墊130由基板10轉移配置在驅動背板140上的方式亦可採用先移除後接合或先轉移至暫時基板後進行移除及接合製程,以使電極墊130位於半導體堆疊層110與驅動背板140之間,本發明並不限於此。而又在類似上述的其他實施例中,可在移除基板10之後先將半導體堆疊層110、絕緣層120及電極墊130配置在一黏著層,例如是黏著膠,再將黏著層配置於驅動背板140上,使黏著層位於電極墊130與驅動背板140之間以完成顯示陣列,但本發明亦不限於此。In addition, in some embodiments, the method of transferring the
因此,在完成上述的步驟之後可形成上述彼此電性隔絕的多個發光區域A,並可以驅動背板140驅動電極墊130以驅動發光區域A,且藉由將電極墊130配置於絕緣層120的開口(見如圖1E的開口O1)中的配置方式而達到各別驅動。故可透過對出光面與配置電極墊130的一端之間施加電壓,而讓這些發光區域A通有電流I以各自發光而不與鄰近的發光區域A的出光相干涉,如圖2所繪示。在本實施例中,兩相鄰發光區域A的週期小於或等於20微米,也就是說,兩相鄰發光區域A的兩發光中心點間隔小於或等於20微米。在另一實施例中,兩相鄰發光區域A的週期小於或等於10微米。詳細而言,在光學行為上,其中一個發光區域A所發出的光若傳遞至鄰近的發光區域A,也會因為與出光面所夾的角度過小而造成全反射現象,進而不使光線從鄰近的發光區域A發出。本實施例顯示陣列100的出光面側可額外配置導電層,其詳細配置方式將由後續說明,本發明亦不限於此。如此一來,相較於傳統的作法,可簡化製程程序及製作難度,並解決傳統晶粒經蝕刻而產生邊界發光效率衰退的問題。Therefore, after the above steps are completed, a plurality of light-emitting regions A electrically isolated from each other can be formed, and the
圖3為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖3。本實施例的顯示陣列100A類似於圖1G的顯示陣列100,唯兩者不同之處在於,在本實施例中,顯示陣列100A還包括多個色彩轉換件150,配置於半導體堆疊層110的出光側上。舉例而言,在本實施例中,半導體堆疊層110例如是發出藍光,故可在發光區域所形成陣列中,有規劃的配置紅光轉換件152及綠光轉換件154,例如是量子點薄膜(Quantum Dot Film)。因此,將可使顯示陣列100A所發出的光具有紅、綠、藍三色,以應用於不同種類的顯示器中。3 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 3. The
圖4為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖4。本實施例的顯示陣列100B類似於圖1G的顯示陣列100,唯兩者不同之處在於,在本實施例中,顯示陣列100B還包括一電極層160以及一吸光層170。電極層160配置於半導體堆疊層110,吸光層170配置於電極層160,且電極層160位於吸光層170與半導體堆疊層110間。詳細而言,在上述圖1G的步驟之後,還可繼續進行形成電極層160於半導體堆疊層110上以及形成吸光層170於電極層160上的步驟。4 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 4. The
詳細而言,在本實施例中,電極層160為透明導電材料,例如是氧化銦錫(indium tin oxide,ITO)膜。吸光層170例如是黑色吸光材料,且具有多個開口O2。發光區域A位於吸光層170的開口O2與電極墊130之間。因此,半導體堆疊層110的發光區域A可藉由電極墊130與電極層160之間的施加電壓而發光,並且所發出的光藉由通過吸光層170的開口O2而達到提高對比度的效果。從上視的視角觀察下,顯示陣列100B的顯示面積可定義為吸光層170的開口O2的佔有面積,而此佔有面積可小於或等於發光區域A的發光面積以提高對比度。詳細而言,發光區域A的發光面積大於或等於吸光層170的開口O2的佔有面積。而吸光層170的開口O2的佔有面積大於第一絕緣層122的開口O11的佔有面積。意即,吸光層170的覆蓋面積小於第一絕緣層122的覆蓋面積。因此,發光區域A可藉由第一絕緣層122的開口O11尺寸而與相鄰的發光區域A電性隔離,且發光區域A所發出的光可藉由吸光層170的開口O2限制出光面積。並且,相鄰第一絕緣層122的開口O11週期相同於顯示面板相鄰子畫素的週期。如此一來,可藉由調配顯示陣列100B的顯示面積並提升顯示陣列100B的發光品質。In detail, in this embodiment, the
圖5為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖5。本實施例的顯示陣列100C類似於圖4的顯示陣列100B,唯兩者不同之處在於,在本實施例中,顯示陣列100C的電極層160A具有多個開口O3,且電極層160A的開口O3位於吸光層170的開口O2與發光區域A之間。在本實施例中,電極層160A例如是柵狀金屬電極。詳細而言,在本實施例中,電極層160A是使用非透光導電材料製成。因此,本實施例的發光區域A所發出的光可藉由電極層160A的開口O3及吸光層170的開口O2限制出光面積。在本實施例中,電極層160A的開口O3的尺寸與吸光層170的開口O2的尺寸可為相同或不同,本發明並不限於此。此外,值得一提的是,圖4中顯示陣列100B及圖5中顯示陣列100C中的第一絕緣層122的材料可選用如同圖4的吸光層170的材料,以吸附半導體堆疊層110背向出光面的一側的光線。5 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 5. The
圖6為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖6。本實施例的顯示陣列100D類似於圖1G的顯示陣列100,唯兩者不同之處在於,在本實施例中,顯示陣列100D的絕緣層120A僅由封裝絕緣膠體所形成。具體而言,在本實施例中,可選用與半導體堆疊層110接觸面積較小的電極墊130A,以使所產生的發光區域A彼此可以電性隔離。6 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 6. The
圖7A至圖7F依序為本發明另一實施例的顯示陣列的製造方法的剖面示意圖。請參考圖1B及圖7A至圖7F,在本實施例中,在完成上述於基板10上形成半導體堆疊層110的步驟之後,可先以離子佈植(ion implantation)的方式在半導體堆疊層110中形成至少一電性隔離部B以電性分隔發光區域A而形成半導體堆疊層110A。換句話說,在此步驟中,僅以離子佈植的方式進一步提升相鄰發光區域A之間的絕緣特性而不需額外以前述的圖案化製程圖案化半導體堆疊層110。電性隔離部B的形狀為柵狀,且其阻抗值大於發光區域A的阻抗值的100倍。在本實施例中,電性隔離部B的深度分佈可達半導體堆疊層110A的相對兩面,即半導體堆疊層110A的厚度。然而在一些實施例中,電性隔離部B的深度分佈可以小於半導體堆疊層110A的厚度,例如是分佈於第二半導體材料層116或分佈於第二半導體材料層116及發光材料層114中而未貫穿整個半導體堆疊層110A,本發明並不限於此。7A to 7F are schematic cross-sectional diagrams of a manufacturing method of a display array according to another embodiment of the invention in sequence. Please refer to FIG. 1B and FIGS. 7A to 7F. In this embodiment, after the steps of forming the semiconductor stacked
因此,在對發光區域A施加電壓時,可更加確保相鄰發光區域A之間達到電性隔絕。如此一來,可加強相鄰的發光區域A的電性隔絕效果,並且進一步提升發光效率。圖7B至圖7F的製造方法為依序形成第一絕緣層122、多個電極墊130、第二絕緣層124以及將半導體堆疊層110A、絕緣層120及電極墊130由基板10轉移配置在驅動背板140上。其詳細的製作過程之步驟可由上述的圖1C至圖1G的說明內容獲取足夠啟示而進行製造,故不再贅述。Therefore, when a voltage is applied to the light-emitting area A, electrical isolation between adjacent light-emitting areas A can be more ensured. In this way, the electrical isolation effect of the adjacent light-emitting area A can be enhanced, and the light-emitting efficiency can be further improved. The manufacturing method of FIGS. 7B to 7F is to sequentially form a first insulating
圖8為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖8。本實施例的顯示陣列100F類似於圖7F的顯示陣列100E,唯兩者不同之處在於,在本實施例中,顯示陣列100F還包括類似於圖4所繪示的電極層160及吸光層170。因此可使半導體堆疊層110A的發光區域A藉由電極墊130與電極層160之間的施加電壓而發光,並且所發出的光藉由通過吸光層170的開口而達到提高對比度的效果。其詳細的製作過程之步驟可由上述圖4的說明內容獲取足夠啟示而進行製造,故不再贅述。FIG. 8 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 8. The
圖9為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖9。本實施例的顯示陣列100G類似於圖8的顯示陣列100F,唯兩者不同之處在於,在本實施例中,顯示陣列100G的電極層160A選用類似於圖5所繪示的電極層160A,具有多個開口,且電極層160A的開口位於吸光層170的開口與發光區域A之間。其詳細的製作過程之步驟可由上述圖5的說明內容獲取足夠啟示而進行製造,故不再贅述。9 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 9. The
圖10為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖10。本實施例的顯示陣列100H類似於圖7F的顯示陣列100E,唯兩者不同之處在於,在本實施例中,顯示陣列100H的絕緣層120A選用類似於圖6所繪示的絕緣層120A,僅由封裝絕緣膠體所形成。然在本實施例中,由於半導體堆疊層110A中具有電性隔離部B,故電極墊130B可不需選用與半導體堆疊層110A接觸面積較小者即可達到良好的相鄰發光區域A彼此電性隔絕的效果。其詳細的製作過程之步驟可由上述的圖6的說明內容獲取足夠啟示而進行製造,故不再贅述。10 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 10. The
圖11A至圖11C依序為本發明另一實施例的顯示陣列的製造方法的剖面示意圖。請先參考圖1C及圖11A,在本實施例中,在完成上述於半導體堆疊層110形成第一絕緣層122(即絕緣層120B)的步驟之後,在第一絕緣層122上配置電極墊130C以及主動元件180。在本實施例中,電極墊130C例如是氧化銦錫膜,而主動元件180例如是薄膜電晶體(Thin Film Transistor,TFT)。主動元件180與電極墊130C電性連接,因此,半導體堆疊層110可藉由主動元件180開啟並且所發出的光線可穿透電極墊130C。11A to 11C are schematic cross-sectional views of a manufacturing method of a display array according to another embodiment of the present invention in sequence. Please refer to FIGS. 1C and 11A first. In this embodiment, after the steps of forming the first insulating layer 122 (ie, insulating
請參考圖11B及圖11C。在完成上述步驟後,將半導體堆疊層110、絕緣層120B、電極墊130C及主動元件180由基板10轉移配置在驅動背板140上,以形成顯示陣列100I。在本實施例中,採用上述說明中所提及先移除後接合或先轉移至暫時基板後進行移除及接合製程,以使半導體堆疊層110位於電極墊130C與驅動背板140之間。詳細而言,在完成上述步驟後,移除基板10,如圖11B所繪示。接著,將半導體堆疊層110原先配置在基板10的一側配置於驅動背板140,以使半導體堆疊層110與驅動背板140電性連接。因此,半導體堆疊層110可藉由主動元件180開啟或關閉電流導通,當主動元件180開啟時,半導體堆疊層110可經由電極墊130C與驅動背板140之間的施加電壓而發光,並且所發出的光藉由透光的電極墊130C發出。如此一來,可簡化製程程序及製作難度,並解決傳統晶粒經蝕刻而產生邊界發光效率衰退的問題。Please refer to Figure 11B and Figure 11C. After completing the above steps, the
圖12為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖12。本實施例的顯示陣列100J類似於圖11C的顯示陣列100I,唯兩者不同之處在於,在本實施例中,顯示陣列100J的半導體堆疊層110A選用類似於圖7F所繪示的半導體堆疊層110A,具有至少一電性隔離部B以分隔發光區域A。此外,相較於圖11C的顯示陣列100I,本實施例由於半導體堆疊層110A具有電性隔離部B,故可省略圖11C顯示陣列100I所配置的絕緣層120B,但本發明並不限於此。12 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to Figure 12. The
圖13A至圖13D依序為本發明另一實施例的顯示陣列的製造方法的剖面示意圖。請參考圖11C、圖13A至圖13C,在本實施例中,圖13A的結構類似於圖11C的結構,唯兩者不同之處在於,在本實施例中,電極墊130選用非透光導電材料製成,且在形成第一絕緣層122、電極墊130、第二絕緣層124以及主動元件180的步驟之後,將半導體堆疊層110、絕緣層120、電極墊130及主動元件180由基板10轉移配置在一驅動背板140上,如圖13C所繪示。其詳細的製作過程之步驟可由上述的圖1E至圖1G的說明內容獲取足夠啟示而進行製造,故不再贅述。13A to 13D are schematic cross-sectional diagrams of a manufacturing method of a display array according to another embodiment of the invention in sequence. Please refer to FIGS. 11C and 13A to 13C. In this embodiment, the structure of FIG. 13A is similar to the structure of FIG. 11C, except that the difference between the two is that, in this embodiment, the
請參考圖13D。在完成上述步驟之後,形成電極層160於半導體堆疊層110,使半導體堆疊層110位於電極層160與主動元件180之間以完成顯示陣列100K。在本實施例中,電極層160為透明導電材料,例如是氧化銦錫(Indium Tin Oxide,ITO)膜。因此,半導體堆疊層110可經由電極墊130與電極層160之間的施加電壓而發光,並且所發出的光藉由透光的電極層160發出。其詳細的製作過程之步驟可由上述的圖4的說明內容獲取足夠啟示而進行製造,故不再贅述。Please refer to Figure 13D. After the above steps are completed, the
圖14為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖14,本實施例的顯示陣列100L類似於圖13D的顯示陣列100K,唯兩者不同之處在於,在本實施例中,顯示陣列100L還包括黏著層190,黏著層190位於電極墊130與驅動背板140之間,黏著層190例如是具有絕緣性質的黏著層或異方性導電膠。詳細而言,可在上述圖13A的過程中,在移除基板10之後先將半導體堆疊層110、絕緣層120B及電極墊130配置在黏著層190,再將黏著層190配置於驅動背板140上,使黏著層190位於電極墊130與驅動背板140之間以完成顯示陣列100L。14 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Referring to FIG. 14, the
圖15為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖15,本實施例的顯示陣列100M類似於圖13D的顯示陣列100K,唯兩者不同之處在於,在本實施例中,顯示陣列100M的半導體堆疊層110A選用類似於圖7F所繪示的半導體堆疊層110A,具有至少一電性隔離部B以分隔發光區域A。此外,由於半導體堆疊層110A具有電性隔離部B,故可省略圖13D顯示陣列100K所配置的絕緣層120,進而選用由封裝絕緣膠體所形成的絕緣層120A,但本發明並不限於此。15 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to FIG. 15, the
圖16為本發明另一實施例的顯示陣列的剖面示意圖。請參考圖16,本實施例的顯示陣列100N類似於圖15的顯示陣列100M,唯兩者不同之處在於,在本實施例中,顯示陣列100N還包括黏著層190,黏著層190位於電極墊130與驅動背板140之間,黏著層190例如是具有絕緣性質的黏著層或異方性導電膠。其詳細的製作過程之步驟可由上述的圖14的說明內容獲取足夠啟示而進行製造,故不再贅述。16 is a schematic cross-sectional view of a display array according to another embodiment of the invention. Please refer to FIG. 16, the
圖17為本發明一實施例的顯示陣列的製造方法的步驟流程圖。請參考圖1A至圖1G以及圖17。本實施例所教示的顯示陣列的製造方法至少可應用於上述的所有實施例中。為方便說明,下述說明將以圖1A至圖1G的實施例為例,但本發明並不限於此。在本實施例顯示陣列的製造方法中,首先執行步驟S200,提供一基板10,且在基板10上形成一半導體堆疊層110,如圖1B所繪示。接著,執行步驟S210,形成一絕緣層120以及多個電極墊130於半導體堆疊層110上,其中絕緣層120具有多個開口O1,且這些電極墊130位於絕緣層120的這些開口O1中且被絕緣層120隔開,如圖1E所繪示。最後,執行步驟S220,將半導體堆疊層110、絕緣層120及這些電極墊130由基板10轉移配置在一驅動背板140上,其中這些電極墊130分別經過絕緣層120的這些開口O1與部份的半導體堆疊層110及驅動背板140電性連接以在半導體堆疊層110形成彼此電性隔離的多個發光區域A,如圖1G所繪示。如此一來,相較於傳統的作法,可簡化製程程序及製作難度,並解決傳統晶粒經蝕刻而產生邊界發光效率衰退的問題。FIG. 17 is a flowchart of steps of a method of manufacturing a display array according to an embodiment of the invention. Please refer to Figure 1A to Figure 1G and Figure 17. The manufacturing method of the display array taught in this embodiment can at least be applied to all the above embodiments. For the convenience of description, the following description will take the embodiment of FIGS. 1A to 1G as an example, but the present invention is not limited thereto. In the manufacturing method of the display array of this embodiment, step S200 is first performed to provide a
綜上所述,在本發明的顯示陣列中,絕緣層具有多個開口,以使電極墊位於絕緣層的開口中被絕緣層隔開,進而使電極墊分別經過絕緣層的開口與部份的半導體堆疊層電性連接以在半導體堆疊層形成彼此電性隔離的多個發光區域。因此,相較於傳統的作法,可簡化製程程序及製作難度,並解決傳統晶粒經蝕刻而產生邊界發光效率衰退的問題。In summary, in the display array of the present invention, the insulating layer has a plurality of openings, so that the electrode pads are located in the openings of the insulating layer and are separated by the insulating layer, so that the electrode pads pass through the openings and part of the insulating layer respectively. The stacked semiconductor layers are electrically connected to form a plurality of light emitting regions electrically isolated from each other on the stacked semiconductor layers. Therefore, compared with the traditional method, the manufacturing process and manufacturing difficulty can be simplified, and the problem of the boundary luminous efficiency decline caused by the traditional die etching can be solved.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.
10‧‧‧基板100、100A、100B、100C、100D、100E、100F、100G、100H、100I、100J、100K、100L、100M、100N‧‧‧顯示陣列110、110A‧‧‧半導體堆疊層112‧‧‧第一半導體材料層114‧‧‧發光材料層116‧‧‧第二半導體材料層120、120A、120B‧‧‧絕緣層122‧‧‧第一絕緣層124‧‧‧第二絕緣層130、130A、130B、130C‧‧‧電極墊140‧‧‧驅動背板150‧‧‧色彩轉換件152‧‧‧紅光轉換件154‧‧‧綠光轉換件160、160A‧‧‧電極層170‧‧‧吸光層180‧‧‧主動元件190‧‧‧黏著層A‧‧‧發光區域B‧‧‧電性隔離部I‧‧‧電流O1、O11、O12、O2、O3‧‧‧開口S200、S210、S220‧‧‧步驟10‧‧‧
圖1A至圖1G依序為本發明一實施例的顯示陣列的製造方法的剖面示意圖。 圖2為圖1G的顯示陣列的俯視示意圖。 圖3為本發明另一實施例的顯示陣列的剖面示意圖。 圖4為本發明另一實施例的顯示陣列的剖面示意圖。 圖5為本發明另一實施例的顯示陣列的剖面示意圖。 圖6為本發明另一實施例的顯示陣列的剖面示意圖。 圖7A至圖7F依序為本發明另一實施例的顯示陣列的製造方法的剖面示意圖。 圖8為本發明另一實施例的顯示陣列的剖面示意圖。 圖9為本發明另一實施例的顯示陣列的剖面示意圖。 圖10為本發明另一實施例的顯示陣列的剖面示意圖。 圖11A至圖11C依序為本發明另一實施例的顯示陣列的製造方法的剖面示意圖。 圖12為本發明另一實施例的顯示陣列的剖面示意圖。 圖13A至圖13D依序為本發明另一實施例的顯示陣列的製造方法的剖面示意圖。 圖14為本發明另一實施例的顯示陣列的剖面示意圖。 圖15為本發明另一實施例的顯示陣列的剖面示意圖。 圖16為本發明另一實施例的顯示陣列的剖面示意圖。 圖17為本發明一實施例的顯示陣列的製造方法的步驟流程圖。1A to 1G are schematic cross-sectional diagrams of a manufacturing method of a display array according to an embodiment of the present invention. FIG. 2 is a schematic top view of the display array of FIG. 1G. 3 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 4 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 5 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 6 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 7A to 7F are schematic cross-sectional diagrams of a manufacturing method of a display array according to another embodiment of the invention in sequence. FIG. 8 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 9 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 10 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 11A to 11C are schematic cross-sectional views of a manufacturing method of a display array according to another embodiment of the present invention in sequence. 12 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 13A to 13D are schematic cross-sectional diagrams of a manufacturing method of a display array according to another embodiment of the invention in sequence. 14 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 15 is a schematic cross-sectional view of a display array according to another embodiment of the invention. 16 is a schematic cross-sectional view of a display array according to another embodiment of the invention. FIG. 17 is a flowchart of steps of a method of manufacturing a display array according to an embodiment of the invention.
100‧‧‧顯示陣列 100‧‧‧Display array
110‧‧‧半導體堆疊層 110‧‧‧Semiconductor stack
120‧‧‧絕緣層 120‧‧‧Insulation layer
130‧‧‧電極墊 130‧‧‧electrode pad
140‧‧‧驅動背板 140‧‧‧Drive Backplane
A‧‧‧發光區域 A‧‧‧Light-emitting area
I‧‧‧電流 I‧‧‧Current
Claims (14)
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US16/232,069 US20190355785A1 (en) | 2018-05-16 | 2018-12-26 | Display array |
CN201811600357.8A CN110504280A (en) | 2018-05-16 | 2018-12-26 | Array of display |
US17/385,954 US11837628B2 (en) | 2018-05-16 | 2021-07-27 | Display array |
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US201862672061P | 2018-05-16 | 2018-05-16 | |
US62/672,061 | 2018-05-16 |
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TWI699598B (en) | 2020-07-21 |
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