CN117255580A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
- Publication number
- CN117255580A CN117255580A CN202210648068.5A CN202210648068A CN117255580A CN 117255580 A CN117255580 A CN 117255580A CN 202210648068 A CN202210648068 A CN 202210648068A CN 117255580 A CN117255580 A CN 117255580A
- Authority
- CN
- China
- Prior art keywords
- electrode
- array substrate
- insulating layer
- substrate
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 88
- 239000003990 capacitor Substances 0.000 claims abstract description 89
- 238000003860 storage Methods 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims description 94
- 239000011229 interlayer Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 8
- 238000003475 lamination Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention discloses an array substrate, a display panel and a display device, wherein the array substrate comprises: a first electrode arranged on the same layer as the grid electrode, a second electrode arranged between the first electrode and the source-drain electrode, and a third electrode arranged between the second electrode and the source-drain electrode; since the storage capacitor comprises a first capacitor and a second capacitor which are connected in parallel; the first capacitor comprises a first electrode and a second electrode, the second capacitor comprises a second electrode and a third electrode, and the third electrode is electrically connected with the first electrode. Compared with the prior art, the invention can increase the capacitance value of the storage capacitor under the condition that the occupied area of the pixels is the same, so that the storage capacitor is more fully charged; or, under the condition of ensuring that the capacitance values of the storage capacitors are the same, the pixel occupation area can be reduced, so that the pixel resolution of the display panel can be improved under the same pixel circuit architecture, and high PPI display is realized.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
Organic light emitting diodes (Organic Light Emitting Diode, OLEDs) are one of the hot spots in the current display research field due to their low energy consumption, low production cost, self-luminescence, wide viewing angle, and fast response speed.
In an OLED display panel, a plurality of light emitting pixels are included, each pixel including a pixel circuit and a light emitting device, the pixel circuit is used for driving the light emitting device to emit light, the pixel circuit includes a storage capacitor and a plurality of transistors, and a 7T1C pixel circuit structure (7 transistors and one storage capacitor) is currently used. With the increasing requirement on the resolution (PPI) of the display product, if the PPI is to be further improved, the occupied area of each pixel needs to be reduced on the premise that the pixel circuit structure is not changed, but after the occupied area is reduced, the storage capacitor is correspondingly reduced, so that the voltage stabilizing capability of the storage capacitor is insufficient.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a display panel and a display device, which are used for improving the capacitance value of a storage capacitor in an OLED display panel.
The array substrate provided by the embodiment of the invention comprises a substrate and a pixel circuit positioned on the substrate, wherein the pixel circuit comprises a driving transistor, a storage capacitor and a power supply voltage line, one end of the storage capacitor is electrically connected with a gate electrode of the driving transistor, and the other end of the storage capacitor is electrically connected with the power supply voltage line;
the driving transistor comprises an active layer, the grid electrode and a source-drain electrode which are arranged on the substrate in a stacked mode, and the storage capacitor comprises a first capacitor and a second capacitor which are connected in parallel;
the array substrate further includes: a first electrode arranged on the same layer as the gate electrode, a second electrode arranged between the first electrode and the source-drain electrode, and a third electrode arranged between the second electrode and the source-drain electrode;
the first capacitor comprises the first electrode and the second electrode, the second capacitor comprises the second electrode and the third electrode, and the third electrode is electrically connected with the first electrode.
Optionally, in the above array substrate provided by the embodiment of the present invention, the power supply voltage line and the source-drain electrode are disposed in the same layer, the second electrode is electrically connected to the power supply voltage line, and the first electrode is electrically connected to the gate of the driving transistor.
Optionally, in the above array substrate provided by the embodiment of the present invention, the orthographic projection of the second electrode on the substrate covers the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second electrode on the substrate covers the orthographic projection of the third electrode on the substrate.
Optionally, in the above array substrate provided by the embodiment of the present invention, the method further includes: a first insulating layer between the first electrode and the second electrode, and a second insulating layer between the second electrode and the third electrode; the third electrode is electrically connected with the first electrode through a first via hole penetrating through the second insulating layer, the second electrode and the first insulating layer in sequence.
Optionally, in the above array substrate provided by the embodiment of the present invention, the method further includes: and an interlayer insulating layer between the third electrode and the source-drain electrode, the second electrode and the power supply voltage line being electrically connected through a second via hole penetrating the interlayer insulating layer and the second insulating layer.
Optionally, in the above array substrate provided by the embodiment of the present invention, the second electrode has a third via hole corresponding to the gate electrode of the driving transistor, and the orthographic projection of the third electrode on the substrate does not overlap with the orthographic projection of the second via hole and the third via hole on the substrate.
Optionally, in the above array substrate provided by the embodiment of the present invention, the method further includes: a data signal line arranged on the same layer as the source electrode and the drain electrode, a reset signal line arranged on the same layer as the grid electrode, a light-emitting control line and an initialization signal line arranged on the same layer as the second electrode.
Optionally, in the above array substrate provided by the embodiment of the present invention, a material of the second electrode and a material of the third electrode are the same as a material of the gate.
Correspondingly, the embodiment of the invention also provides a display panel which comprises the array substrate provided by the embodiment of the invention.
Correspondingly, the embodiment of the invention also provides a display device which comprises the display panel provided by the embodiment of the invention.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises: a first electrode arranged on the same layer as the grid electrode, a second electrode arranged between the first electrode and the source-drain electrode, and a third electrode arranged between the second electrode and the source-drain electrode; since the storage capacitor comprises a first capacitor and a second capacitor which are connected in parallel; the first capacitor comprises a first electrode and a second electrode, the second capacitor comprises a second electrode and a third electrode, and the third electrode is electrically connected with the first electrode. Compared with the prior art, the invention can increase the capacitance value of the storage capacitor under the condition that the occupied area of the pixels is the same, so that the storage capacitor is more fully charged; or, under the condition of ensuring that the capacitance values of the storage capacitors are the same, the pixel occupation area can be reduced, so that the pixel resolution of the display panel can be improved under the same pixel circuit architecture, and high PPI display is realized.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit provided in the related art;
fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of the drive transistor and storage capacitor of FIG. 2;
FIG. 4 is an equivalent circuit schematic diagram of a storage capacitor;
fig. 5A to 5G are schematic top view structures corresponding to each step of manufacturing an array substrate according to an embodiment of the present invention;
fig. 6A to 6F are schematic top view structures of stacked film layers between steps in manufacturing an array substrate according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution and advantages of the present invention more clear, specific embodiments of the array substrate, the display panel and the display device provided by the embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the following description of the preferred embodiments is provided for the purpose of illustrating and explaining the invention, and is not intended to limit the invention. And embodiments and features of embodiments in this application may be combined with each other without conflict.
The thickness, size and shape of each layer of film in the drawing do not reflect the actual proportion of the array substrate, and the purpose is only to illustrate the invention.
In an OLED display panel, as shown in fig. 1, a plurality of light emitting pixels are included, each pixel includes a pixel circuit and a light emitting device L, the pixel circuit is used for driving the light emitting device L to emit light, and currently, the pixel circuit is in a 7T1C structure, that is, the pixel circuit includes a storage capacitor Cst and seven transistors (T1 to T7). However, with the increasing requirement for the resolution (PPI) of the display product, if the PPI is to be further improved, the occupied area of each pixel needs to be reduced, but after the occupied area is reduced, the storage capacitor will be correspondingly reduced, so that the voltage stabilizing capability of the storage capacitor is insufficient. The current method for solving the problem is to reduce the thickness of the insulating layer in the storage capacitor, but reducing the thickness of the insulating layer in the storage capacitor can cause shortages of the upper polar plate and the lower polar plate of the storage capacitor.
In view of the above, an embodiment of the present invention provides an array substrate, as shown in fig. 2 and 3, fig. 2 is a schematic structural diagram of a pixel circuit in the array substrate provided by the embodiment of the present invention, fig. 3 is a schematic sectional diagram of a driving transistor and a storage capacitor in fig. 2, the array substrate includes a substrate 1 and a pixel circuit located on the substrate 1, the pixel circuit includes a driving transistor T3, a storage capacitor Cst and a power voltage line VDD, one end of the storage capacitor Cst is electrically connected with a gate electrode of the driving transistor T3, and the other end of the storage capacitor Cst is electrically connected with the power voltage line VDD;
the driving transistor T3 includes an active layer 2, a gate electrode 3, and a source-drain electrode 4 stacked on the substrate 1, and the storage capacitor Cst includes a first capacitor C1 and a second capacitor C2 connected in parallel;
the array substrate further includes: a first electrode 5 arranged in the same layer as the gate electrode 3, a second electrode 6 between the first electrode 5 and the source-drain electrode 4, and a third electrode 7 between the second electrode 6 and the source-drain electrode 4;
the first capacitor C1 includes a first electrode 5 and a second electrode 6, the second capacitor C2 includes a second electrode 6 and a third electrode 7, and the third electrode 7 is electrically connected to the first electrode 5.
The array substrate provided by the embodiment of the invention comprises the following components: a first electrode 5 arranged in the same layer as the gate electrode 3, a second electrode 6 between the first electrode 5 and the source-drain electrode 4, and a third electrode 7 between the second electrode 6 and the source-drain electrode 4; since the storage capacitor Cst includes the first capacitor C1 and the second capacitor C2 connected in parallel; the first capacitor C1 includes a first electrode 5 and a second electrode 6, the second capacitor C2 includes a second electrode 6 and a third electrode 7, and the third electrode 7 is electrically connected to the first electrode 5. Compared with the prior art, the invention can increase the capacitance value of the storage capacitor under the condition that the occupied area of the pixels is the same, so that the storage capacitor is more fully charged; or, under the condition of ensuring that the capacitance values of the storage capacitors are the same, the pixel occupation area can be reduced, so that the pixel resolution of the display panel can be improved under the same pixel circuit architecture, and high PPI display is realized.
In the embodiment, as shown in fig. 3, the gate electrode 3 of the driving transistor and the first electrode 5 of the storage capacitor are integrally formed.
It should be noted that the pixel circuit shown in fig. 2 further includes other transistors (T1, T2, T4 to T7), and in general, the layers having the same function in all the transistors are disposed in the same layer, for example, the active layers of all the transistors are disposed in the same layer, the gates of all the transistors are disposed in the same layer, and the source and drain electrodes of all the transistors are disposed in the same layer.
In a specific implementation, in the array substrate provided by the embodiment of the invention, as shown in fig. 3, the power supply voltage line VDD and the source drain electrode 4 are arranged in the same layer, so that the original pattern is only required to be changed when the source drain electrode 4 is formed, the patterns of the power supply voltage line VDD and the source drain electrode 4 can be formed through one-time patterning process, and the process of independently preparing the power supply voltage line VDD is not required to be increased, so that the preparation process flow can be simplified, the production cost is saved, and the production efficiency is improved. The second electrode 6 is electrically connected with the power supply voltage line VDD, the first electrode 5 is electrically connected with the gate of the driving transistor T3, so that one end of the storage capacitor Cst is electrically connected with the gate of the driving transistor T3, the other end of the storage capacitor Cst is electrically connected with the power supply voltage line VDD, the first capacitor C1 and the second capacitor C2 are arranged in parallel, and the capacitance value of the storage capacitor is increased.
In a specific implementation, in order to make the capacitance value of the first capacitor formed by the first electrode and the second electrode as large as possible and the capacitance value of the second capacitor formed by the second electrode and the third electrode as large as possible, in the array substrate provided by the embodiment of the present invention, as shown in fig. 3, the front projection of the second electrode 6 on the substrate 1 covers the front projection of the first electrode 5 on the substrate, and the front projection of the second electrode 6 on the substrate 1 covers the front projection of the third electrode 7 on the substrate 1.
In a specific implementation, in the above array substrate provided by the embodiment of the present invention, as shown in fig. 3, the method further includes: a first insulating layer 8 between the first electrode 5 and the second electrode 6, and a second insulating layer 9 between the second electrode 6 and the third electrode 7; the third electrode 7 and the first electrode 5 are electrically connected through a first via hole V1 penetrating the second insulating layer 9, the second electrode 6, and the first insulating layer 8 in this order.
In a specific implementation, in the above array substrate provided by the embodiment of the present invention, as shown in fig. 3, the method further includes: an interlayer insulating layer 10 between the third electrode 7 and the source-drain electrode 4, and the second electrode 6 and the power supply voltage line VDD are electrically connected through a second via hole V2 penetrating the interlayer insulating layer 10 and the second insulating layer 9.
In a specific implementation, in the above array substrate provided by the embodiment of the present invention, as shown in fig. 3, the method further includes: a buffer layer 11 between the substrate 1 and the active layer 2, and a gate insulating layer 12 between the active layer 2 and the gate electrode 3.
In a specific implementation, the array substrate provided in the embodiment of the present invention further includes: the data signal line is arranged on the same layer as the source and drain electrodes, so that the patterns of the data signal line and the source and drain electrodes can be formed through a one-time patterning process only by changing the original patterning patterns when the source and drain electrodes are formed, the process of independently preparing the data signal line is not needed to be added, the preparation process flow can be simplified, the production cost is saved, and the production efficiency is improved; further comprises: the reset signal line and the light-emitting control line are arranged on the same layer as the grid electrode, so that the patterns of the reset signal line, the light-emitting control line and the grid electrode can be formed through a one-time composition process only by changing the original composition patterns when the grid electrode is formed, the process of independently preparing the reset signal line and the light-emitting control line is not needed to be added, the preparation process flow can be simplified, the production cost is saved, and the production efficiency is improved; further comprises: the initialization signal line is arranged on the same layer as the second electrode, so that the patterns of the initialization signal line and the second electrode can be formed through one-time patterning process only by changing the original patterning pattern when the second electrode is formed, the process of independently preparing the initialization signal line is not needed to be increased, the preparation process flow can be simplified, the production cost is saved, and the production efficiency is improved.
In a specific implementation, in the array substrate provided in the embodiment of the present invention, as shown in fig. 3, the material of the second electrode 6 and the material of the third electrode 7 may be the same as the material of the gate electrode 3. Specifically, as shown in fig. 4, fig. 4 is an equivalent circuit schematic diagram of the storage capacitor, for example, the first electrode 5 is a Gate1 layer, the second electrode 6 is a Gate2 layer, and the third electrode 7 is a Gate3 layer.
The following describes a method for manufacturing the array substrate according to the embodiment of the present invention, taking the structure of the pixel circuit shown in fig. 2 and the storage capacitor shown in fig. 3 as an example, and specifically includes the following steps:
(1) As shown in fig. 5A, a buffer layer is formed on a substrate, a pattern of an active layer 2 is formed on the buffer layer, and fig. 5A only illustrates the pattern of the active layer 2, the active layer 2 serving as a channel and inter-transistor wiring of the transistors T1 to T7 in fig. 2.
(2) A gate insulating layer is deposited on the active layer 2, and the material of the gate insulating layer may be silicon oxide or silicon nitride, etc.
(3) As shown in fig. 5B, a pattern of the gate electrode 3 of the driving transistor and the first electrode 5 of the storage capacitor Cst is formed on the gate insulating layer; wherein, the grid electrode 3 of the driving transistor and the first electrode 5 of the storage capacitor Cst may be an integrated structure; in addition, the Gate electrode of the other transistor may be integrated with the Gate line Gate, the Reset signal line Reset, and the emission control line EM, in addition to the Gate electrode 3 of the driving transistor.
(4) A first insulating layer is deposited on the gate electrode 3 of the driving transistor and the first electrode 5 of the storage capacitor Cst, wherein the material of the first insulating layer may be silicon oxide or silicon nitride, etc.
(5) As shown in fig. 5C, a pattern of the second electrode 6 of the storage capacitor Cst and the initialization signal line Vinit, etc. is formed on the first insulating layer, the second electrode 6 having the third via hole V3 corresponding to the gate electrode 3 of the driving transistor T3, wherein the orthographic projection of the second electrode 6 on the substrate may cover the orthographic projection of the first electrode 5 on the substrate.
(6) As shown in fig. 5D, a second insulating layer is deposited, and a first via hole V1 penetrating the second insulating layer, the second electrode 6, and the first insulating layer is formed for electrically connecting the first electrode 5 and the third electrode 7 of the storage capacitor; the material of the second insulating layer may be silicon oxide or silicon nitride, etc.
(7) As shown in fig. 5E, the third electrode 7 of the storage capacitor Cst is formed on the second insulating layer, wherein the orthographic projection of the second electrode 6 on the substrate may cover the orthographic projection of the third electrode 7 on the substrate.
(8) As shown in fig. 5F, an interlayer insulating layer 10 is deposited on the third electrode 7, wherein the material of the interlayer insulating layer 10 may be silicon oxide or silicon nitride or the like; and forming a via hole penetrating the interlayer insulating layer 10, the second insulating layer, the first insulating layer and the gate insulating layer for electrically connecting the source and drain electrodes 4 formed later and the active layer 2; a second via hole V2 penetrating the interlayer insulating layer 10 and the second insulating layer 9 is formed for the second electrode 6 to be formed later to be electrically connected to the power supply voltage line VDD. The orthographic projection of the third electrode 7 on the substrate 1 and the orthographic projections of the second via hole V2 and the third via hole V3 on the substrate are not overlapped, so that the pattern of the third electrode 7 does not affect the electrical connection between the film layers when the film layers such as the source electrode and the drain electrode 4 are deposited later.
(9) As shown in fig. 5G, a pattern of the source/drain electrode 4, the Data signal line Data, and the power supply voltage line VDD is formed on the interlayer insulating layer 10.
Therefore, the array substrate provided by the embodiment of the invention can be formed through the steps (1) to (9).
The active layer 2, the first electrode 5, the second electrode 6, the second insulating layer 9, the third electrode 7, the interlayer insulating layer 10, and the source/drain electrode 4 are illustrated in fig. 5A to 5G, respectively, as illustrated in fig. 6A to 6F, fig. 6A is a schematic diagram of film lamination of fig. 5A to 5B, fig. 6B is a schematic diagram of film lamination of fig. 5A to 5C, fig. 6C is a schematic diagram of film lamination of fig. 5A to 5D, fig. 6D is a schematic layout of film lamination of fig. 5A to 5E, and fig. 6E is a schematic diagram of film lamination of fig. 5A to 5G.
As shown in fig. 6E, the second electrode 6 has a third via hole V3 corresponding to the gate electrode 3 of the driving transistor T3, has a second via hole V2 penetrating the interlayer insulating layer 10 and the second insulating layer 9, and the orthographic projection of the third electrode 7 on the substrate does not overlap with the orthographic projections of the second via hole V2 and the third via hole V3 on the substrate, so that the pattern of the third electrode 7 does not affect the electrical connection between the source-drain electrode 4, VDD, data, and the like and the underlying mask layer when the source-drain electrode 4, VDD, data, and the like shown in fig. 6F are formed.
In fig. 6F, the third electrode 7 covers only a portion of the second electrode 6, but the third electrode 7 may cover the entire second electrode 6, and the third electrode 7 corresponding to the positions of the second via hole V2 and the third via hole V3 may be removed to expose the second via hole V2 and the third via hole V3.
In summary, compared with the prior art, the array substrate provided by the embodiment of the invention can increase the capacitance value of the storage capacitor under the condition that the occupied area of the pixels is the same, so that the storage capacitor is more fully charged; or, under the condition of ensuring that the capacitance values of the storage capacitors are the same, the pixel occupation area can be reduced, so that the pixel resolution of the display panel can be improved under the same pixel circuit architecture, and high PPI display is realized.
Based on the same inventive concept, the embodiment of the invention also provides a display panel, which comprises any one of the array substrates provided by the embodiment of the invention. Since the principle of the display panel for solving the problem is similar to that of the aforementioned array substrate, the implementation of the display panel can refer to the embodiment of the aforementioned array substrate, and the repetition is omitted.
Specifically, the display panel provided by the embodiment of the invention is an OLED display panel.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises any display panel provided by the embodiment of the invention. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. The implementation of the display device can be referred to the embodiment of the array substrate, and the repetition is not repeated.
The embodiment of the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises: a first electrode arranged on the same layer as the grid electrode, a second electrode arranged between the first electrode and the source-drain electrode, and a third electrode arranged between the second electrode and the source-drain electrode; since the storage capacitor comprises a first capacitor and a second capacitor which are connected in parallel; the first capacitor comprises a first electrode and a second electrode, the second capacitor comprises a second electrode and a third electrode, and the third electrode is electrically connected with the first electrode. Compared with the prior art, the invention can increase the capacitance value of the storage capacitor under the condition that the occupied area of the pixels is the same, so that the storage capacitor is more fully charged; or, under the condition of ensuring that the capacitance values of the storage capacitors are the same, the pixel occupation area can be reduced, so that the pixel resolution of the display panel can be improved under the same pixel circuit architecture, and high PPI display is realized.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. An array substrate is characterized by comprising a substrate and a pixel circuit positioned on the substrate, wherein the pixel circuit comprises a driving transistor, a storage capacitor and a power supply voltage line, one end of the storage capacitor is electrically connected with a gate electrode of the driving transistor, and the other end of the storage capacitor is electrically connected with the power supply voltage line;
the driving transistor comprises an active layer, the grid electrode and a source-drain electrode which are arranged on the substrate in a stacked mode, and the storage capacitor comprises a first capacitor and a second capacitor which are connected in parallel;
the array substrate further includes: a first electrode arranged on the same layer as the gate electrode, a second electrode arranged between the first electrode and the source-drain electrode, and a third electrode arranged between the second electrode and the source-drain electrode;
the first capacitor comprises the first electrode and the second electrode, the second capacitor comprises the second electrode and the third electrode, and the third electrode is electrically connected with the first electrode.
2. The array substrate according to claim 1, wherein the power supply voltage line is provided in the same layer as the source-drain electrode, the second electrode is electrically connected to the power supply voltage line, and the first electrode is electrically connected to the gate electrode of the driving transistor.
3. The array substrate of claim 2, wherein the orthographic projection of the second electrode on the substrate covers the orthographic projection of the first electrode on the substrate, and wherein the orthographic projection of the second electrode on the substrate covers the orthographic projection of the third electrode on the substrate.
4. The array substrate of claim 3, further comprising: a first insulating layer between the first electrode and the second electrode, and a second insulating layer between the second electrode and the third electrode; the third electrode is electrically connected with the first electrode through a first via hole penetrating through the second insulating layer, the second electrode and the first insulating layer in sequence.
5. The array substrate of claim 4, further comprising: and an interlayer insulating layer between the third electrode and the source-drain electrode, the second electrode and the power supply voltage line being electrically connected through a second via hole penetrating the interlayer insulating layer and the second insulating layer.
6. The array substrate according to claim 5, wherein the second electrode has a third via corresponding to the gate electrode of the driving transistor, and the orthographic projection of the third electrode on the substrate is not overlapped with the orthographic projections of the second via and the third via on the substrate.
7. The array substrate of any one of claims 1-6, further comprising: a data signal line arranged on the same layer as the source electrode and the drain electrode, a reset signal line arranged on the same layer as the grid electrode, a light-emitting control line and an initialization signal line arranged on the same layer as the second electrode.
8. The array substrate according to any one of claims 1 to 6, wherein a material of the second electrode and a material of the third electrode are the same as a material of the gate electrode.
9. A display panel comprising an array substrate according to any one of claims 1-8.
10. A display device comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210648068.5A CN117255580A (en) | 2022-06-08 | 2022-06-08 | Array substrate, display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210648068.5A CN117255580A (en) | 2022-06-08 | 2022-06-08 | Array substrate, display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117255580A true CN117255580A (en) | 2023-12-19 |
Family
ID=89133675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210648068.5A Pending CN117255580A (en) | 2022-06-08 | 2022-06-08 | Array substrate, display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117255580A (en) |
-
2022
- 2022-06-08 CN CN202210648068.5A patent/CN117255580A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112071882B (en) | Display substrate, preparation method thereof and display device | |
| US20200075703A1 (en) | Array substrate structure and display device | |
| WO2020198975A1 (en) | Display substrate and preparation method therefor, and display panel | |
| CN113261106B (en) | Display substrate and display device | |
| CN113196374B (en) | Display substrate and display device | |
| WO2021254319A1 (en) | Display substrate and display device | |
| WO2021082648A1 (en) | Display substrate and manufacturing method therefor, and display device | |
| CN114651332B (en) | Display substrate and display device | |
| CN115280511A (en) | Display substrate and display device | |
| CN113196495A (en) | Display substrate and display device | |
| EP3992705A1 (en) | Display substrate and display device | |
| US20220199734A1 (en) | Display panel and display device | |
| US11974473B2 (en) | Display substrate, manufacturing method thereof and display device | |
| CN111834292B (en) | Display substrate, manufacturing method thereof, display panel and display device | |
| JP2019526162A (en) | AMOLED display substrate, manufacturing method thereof, and display device | |
| WO2021083226A1 (en) | Display substrate and manufacturing method therefor, and display device | |
| US20220208923A1 (en) | Display device and method of providing the same | |
| KR20210021218A (en) | Display device | |
| CN215771149U (en) | Display substrate and display panel | |
| WO2022088071A1 (en) | Display substrate and display device | |
| US12004376B2 (en) | Display motherboard, preparation method thereof, display substrate and display device | |
| CN117255580A (en) | Array substrate, display panel and display device | |
| US20220376022A1 (en) | Display Substrate, Manufacturing Method Thereof, and Display Device | |
| CN114497159A (en) | Display panel and display device | |
| CN115701310A (en) | Pixel driving circuit, driving method thereof and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication |