WO2019080291A1 - 显示面板及其应用的显示装置 - Google Patents

显示面板及其应用的显示装置

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Publication number
WO2019080291A1
WO2019080291A1 PCT/CN2017/115850 CN2017115850W WO2019080291A1 WO 2019080291 A1 WO2019080291 A1 WO 2019080291A1 CN 2017115850 W CN2017115850 W CN 2017115850W WO 2019080291 A1 WO2019080291 A1 WO 2019080291A1
Authority
WO
WIPO (PCT)
Prior art keywords
line segment
driving line
driving
substrate
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/115850
Other languages
English (en)
French (fr)
Inventor
黄北洲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to US16/758,167 priority Critical patent/US11532644B2/en
Publication of WO2019080291A1 publication Critical patent/WO2019080291A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates

Definitions

  • the present application relates to a circuit structure in a display, and more particularly to an array circuit of a display panel and a display device thereof.
  • LCDs Liquid crystal displays
  • driving technology With the improvement of driving technology, they have the advantages of low power consumption, light weight, low voltage driving, etc., and have been widely used in video recording and playback.
  • the gate driver circuit When the panel of the active switch-liquid crystal display (TFT-LCD) is normally displayed, the gate driver circuit (Gate driver) is required to be combined with the gate line (gate line), the source driver line (Source Driver) and the data line (data line).
  • a common electrode color film common electrode, CF Com
  • the pixel electrode signal is supplied by the data line after being turned on by the active switch (TFT).
  • the storage electrode signal is supplied from an array sharing line (AA Com) at the periphery of the effective display area to form a storage capacitor (Cst) with the pixel electrode.
  • the color film common electrode signal is supplied to the color filter substrate by a common voltage line of an array substrate (Wire On Array, WOA), and a liquid crystal capacitor (Clc) is formed between the color film common electrode and the pixel electrode.
  • the gate drive circuit, the gate line and the data line are often fabricated on the same display substrate, and the display substrate and the flip chip for transmitting the gate drive signal are used by the array line (Chip On Film, COF) connection.
  • the array lines include: Class A traces that provide a common voltage to the color filter substrate; Class B traces that provide power drive signals to the chip; and Class C traces that provide a working signal to the chip.
  • the signal of the gate line is transmitted to the chips (Chip) and integrated circuit (IC) of each level step by step through the array line, so the power driving signal supplied to the chip/integrated circuit through the class B trace cannot be distorted.
  • the resistance of Class B traces of these chips/ICs needs to be reduced.
  • the space of the array line becomes smaller and smaller, which also causes the wiring space of the driving traces of the chips/integrated circuits to become smaller and smaller, and the wiring is thinner. Not only is it getting thinner and longer, but the corresponding impedance value is greater. Not only cause serious drive signals Distortion, which in turn affects the display panel uniformity.
  • the purpose of the present application is to provide a circuit array circuit structure, which can reduce the resistance of a type B trace of an array line (WOA) in a narrow bezel, thereby improving product quality. And improve the reliability and service life of the product.
  • WOA array line
  • a display panel includes: a first substrate having a display area and a wiring area, wherein a plurality of active switches and a plurality of pixel units are disposed in a display area of the first substrate, and the plurality of pixel units are respectively coupled Connecting to the plurality of active switches; the second substrate is disposed opposite to the first substrate; the first driving line segment is disposed on the wiring area of the first substrate, and the first driving line segment includes a plurality of first circuits a second driving line segment disposed on the wiring area of the first substrate, the second driving line segment includes a plurality of second circuit pins, and a first guiding unit configured to respectively connect the plurality of first lines a circuit pin; and a dummy bit connection unit for respectively connecting the plurality of second circuit pins; wherein the first driving line segment is disposed at a periphery of the second driving line segment, the first receiving The unit is connected to the dummy bit
  • the first guiding unit is disposed in a single layer metal wiring manner or a double layer metal wiring manner.
  • the virtual bit connection unit is disposed in a single layer metal wiring manner or a double layer metal wiring manner.
  • the third driving line segment is electrically coupled to the plurality of dummy bit guiding units and the first guiding unit.
  • the third driving line segment is disposed in a single layer metal wiring manner or a double layer metal wiring manner.
  • the plurality of first circuit pins are connected to a driving chip.
  • the driving chip is a source driving chip.
  • the driving chip is a gate driving chip.
  • the display panel further includes: a fourth driving line segment disposed on the wiring area of the first substrate; and a flexible circuit board having a first line, the first line is electrically The first driving line segment and the fourth driving line segment are coupled.
  • the flexible circuit board further includes a second line, and the second line is connected to the first line to form a parallel line.
  • the flexible circuit board is a flexible printed circuit film or a flexible printed circuit board.
  • the display panel further includes: a fourth driving line segment disposed in the wiring area of the first substrate, the first guiding unit 151 connecting the first driving line segment and the a third driving line segment; and a flexible circuit board having a first line and a second line, the second line connecting the first line to form a parallel line, the first driving line segment and the fourth driving line segment Electrical coupling is formed by the first line.
  • the display panel further includes: a fourth driving line segment disposed on the wiring area of the first substrate; and a flexible circuit board having a first line and a second line, wherein the The two lines are connected to the first line to form a parallel line, and the first guiding unit electrically couples the first driving line segment and the fourth driving line segment to the plurality of virtual bit connecting units, The second driving line segments are electrically coupled to the plurality of dummy bit guiding units, respectively, to form a parallel circuit with the first driving line segment and the fourth driving segment line, respectively.
  • the display panel further includes: a fourth driving line segment disposed on the wiring area of the first substrate; and a flexible circuit board having a first line and a second line, wherein the The two lines are connected to the first line to form a parallel line, and the first line is respectively connected to the first driving line segment and the fourth driving line segment, and the first driving line segment and the fourth driving line segment pass through
  • the first driving unit is electrically coupled to the third driving line segment and the plurality of virtual bit guiding units, respectively
  • the second driving line segment is electrically coupled to the plurality of virtual bit guiding units And forming a parallel circuit with the first driving line segment and the fourth driving segment line, respectively, the third driving line segment being disposed between the plurality of virtual lead receiving units.
  • the edge of the second driving line segment has an active switch array.
  • a display panel comprising: a first substrate having a display area and a wiring area, wherein a plurality of active switches and a plurality of pixel units are disposed in a display area of the first substrate, the plurality of pixel units
  • the second driving substrate is disposed opposite to the first substrate; the first driving line segment is disposed on the wiring area of the first substrate, and the first driving line segment includes multiple a circuit pin; a second driving line segment disposed on the wiring area of the first substrate, the The second driving line segment includes a plurality of second circuit pins; the first guiding unit is configured to respectively connect the plurality of first circuit pins; and the dummy bit guiding unit is configured to respectively connect the plurality of second circuits a pin; wherein the first driving line segment is disposed at a periphery of the second driving line segment; the plurality of first circuit pins and the plurality of circuit pins are oriented in the same direction toward the first substrate a direction extending of the edge; the first guiding unit is electrical
  • the materials of the first and second alignment marks are selected from the group consisting of aluminum, molybdenum, chromium, and alloys thereof.
  • the materials of the first and second dummy units are selected from the group consisting of aluminum, molybdenum, chromium, and alloys thereof.
  • Still another object of the present application is a display device comprising: a control unit and a display panel, the display panel comprising: a first substrate having a display area and a wiring area, and a plurality of active switches and a plurality of display areas in the display area of the first substrate Each of the plurality of pixel units is coupled to the plurality of active switches; the second substrate is disposed opposite to the first substrate; the first driving line segment is disposed in the wiring area of the first substrate, The first driving line segment includes a plurality of first circuit pins; the second driving line segment is disposed on the wiring area of the first substrate, the second driving line segment includes a plurality of second circuit pins; the first connection a unit for respectively connecting the plurality of first circuit pins; and a dummy bit connection unit for respectively connecting the plurality of second circuit pins; wherein the first driving line segment is disposed on the The first driving unit is connected to the dummy bit guiding unit, and the second driving line segment is electrically coupled to the first driving line segment to form a
  • the application can reduce the resistance of the B-type traces of the Wire On Array (WOA) in the narrow frame, thereby improving the product quality and improving the reliability and service life of the product.
  • WOA Wire On Array
  • FIG. 1a is a schematic diagram of the architecture of an exemplary display device.
  • Figure 1b is a schematic diagram of traces of an exemplary line array.
  • Figure 1c is a schematic diagram of a Class B trace in an exemplary line array.
  • FIG. 2 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 3b is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a design of a B-type trace with a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a design of a class B trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1a is a schematic diagram of the architecture of an exemplary display device.
  • a display device 200 includes a control board 100 including a Timing Controller (TCON) 101, a printed circuit board 103, and a flexible flat cable passing through the control board 100 (
  • the flexible flat cable (FFC) 102 is connected to each other; the source driving unit 104 and the gate driving unit 105 are disposed in the wiring region 109, and are respectively connected to the data line 104a and the gate line 105a in the display region 106.
  • gate drive unit 105 and source drive unit 104 include, but are not limited to, a form of a flip chip.
  • the driving manner of the display device 200 includes: the system mainboard provides color (for example, R/G/B) compression signals, control signals, and power transmission to the control board 100.
  • the Timing Controller (TCON) 101 on the control board 100 after processing the signals, is transmitted to the printed circuit board through a flexible flat cable (FFC) 102 together with the power source processed by the driving circuit.
  • the gate driving unit 105 and the source driving unit 104 of the 103, the gate driving unit 105 and the source driving unit 104 transmit necessary data and power to the display area 106, thereby causing the display device 200 to obtain a power supply for presenting a picture, signal.
  • FIG. 1b is a schematic diagram of a trace of a line array of an exemplary display panel.
  • circuits such as the driving unit (104, 105), the gate line 105a, and the data line 104a are fabricated on the same display substrate, and the display substrate is used to transmit the driving signal by using the array line 120.
  • the drive units (104, 105) are connected.
  • array line 120 includes a class A trace 120a that transmits a common voltage, a class B trace 120b that provides a power drive signal to the chip, and a class C trace 120c that provides a working signal to the chip.
  • FIG. 1c is a schematic diagram of a Class B trace of an exemplary display panel. Please refer to FIG. 1c, which shows an example.
  • the array structure of the display panel (B-type trace 120b) has a plurality of drive line segments (B-type traces 120b), and each drive line segment includes a plurality of circuit pins and a lead-out unit.
  • the signal of the gate line 105a is transferred to the chip and the integrated circuit (IC) of the gate driving unit 105 of each level step by step via the array line 120, and thus is supplied to the chip through the class B trace 120b.
  • the power drive signal of the integrated circuit cannot be severely distorted.
  • the array line 120 between the gate driving units 105 for example, Gate to Gate, GG
  • FIG. 2 is a schematic diagram of a design of a B-type trace matching soft circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel 12 includes: a first substrate (not shown) having a display area and a wiring area, and a plurality of active switches and a display area in the display area of the first substrate a plurality of pixel units respectively coupled to the plurality of active switches; a second substrate (not shown) disposed opposite to the first substrate; a first driving line segment 121 disposed on the a wiring area of the first substrate, the first driving line segment 121 has a plurality of first circuit pins (121a, 121b); a second driving line segment 122, disposed in a wiring area of the first substrate, the second driving The line segment 122 has a plurality of second circuit pins (122a, 122b); the first connection unit 151 is respectively connected to the first circuit pins (121a, 121b); the dummy bit connection
  • the first driving line segment 121 further includes a first alignment mark (not shown) for connecting the first circuit pins (121a, 121b).
  • the second driving line segment 122 further includes a second alignment mark (not shown) for connecting the second circuit pins (122a, 122b).
  • the material of the first para-marker is selected from the group consisting of aluminum, molybdenum, chromium, and alloys thereof.
  • the material of the second alignment mark is selected from the group consisting of aluminum, molybdenum, chromium, and alloys thereof.
  • edges of the second circuit pins (122a, 122b) have an active switch array.
  • the first circuit pins (121a, 121b) are coupled to a driver chip (160, FIG. 5).
  • the driving chip 160 is a source driving chip.
  • the driving chip 160 is a gate driving chip.
  • the first guiding unit 151 is disposed in a single layer metal wiring manner or a double layer metal wiring manner.
  • the dummy bit connection unit 153 is disposed in a single layer metal wiring manner or a double layer metal wiring manner.
  • a third driving line segment (123, FIG. 3a) is further included, and the third driving line segment 123 is electrically coupled to the plurality of dummy bit guiding units and the first guiding unit, respectively.
  • the third driving line segment 123 is disposed in a single layer metal wiring manner or a double layer metal wiring manner.
  • the single-layer metal wiring method can minimize the influence of the outer frame or the air when a display panel is normally displayed.
  • Double-layer metal routing minimizes the resistance of the line array.
  • a display panel includes: a first substrate (not shown), an active switch and a pixel unit disposed on the first substrate; a second substrate (not shown), and The first substrate is oppositely disposed; a first driving line segment 121 has a plurality of first circuit pins 121a, 121b; and a second driving line segment 122 has a plurality of second circuit pins 122a, 122b;
  • the lead-in unit 151 is configured to respectively connect the first circuit pins 121a and 121b and the second circuit pins 122a and 122b, and a dummy bit connection unit 153 for respectively connecting the second circuit pins.
  • the first driving line segment 121 and the second driving line segment 153 are disposed in a wiring area of the first substrate, and the first guiding unit 151 is electrically
  • the dummy bit routing unit 153 is coupled to form a parallel circuit between the first driving line segment 121 and the second driving line segment 122; the second substrate edge is located at the first driving line segment 121 and the first connection Between the lead units 151 and the second drive line segment 122 and the dummy bit Between the 153; the first driving line segment 121 further includes a first alignment mark, the first alignment mark is used to connect the first circuit pins 121a, 121b; the second driving line segment 122 further includes a second alignment mark, the second alignment mark is used to connect the second circuit pins 122a, 122b; an edge of the second driving line segment 122 has an active switch array; the first receiving unit 151 and the virtual bit
  • the driving line segment 153 is electrically coupled to the first driving line segment 121 by a single layer
  • FIG. 3 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate, a wiring area including a display area and a periphery thereof, and a plurality of active switches and a plurality of pixel units are disposed in the display area of the first substrate, The plurality of pixel units are respectively coupled to the plurality of active switches; a second substrate (not shown) is disposed opposite to the first substrate; the first driving line segment 121 and the third driving line segment 123 are disposed in the wiring area The third driving line segment 123 and the circuit pins of the first driving line segment 121 are disposed in opposite directions; the third driving line segment 123 is respectively connected to the first guiding unit 151 to electrically couple the first driving Line segment 121.
  • FIG. 3b is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate (not shown), an active switch and a pixel unit are disposed on the first substrate; a second substrate (not shown), and the a substrate is oppositely disposed; the first driving line segment 121 and the third driving line segment 123 are disposed in the wiring area; the circuit pins of the third driving line segment 123 and the first driving line segment 121 are disposed in opposite directions; the first connection The unit 151 is connected to the first driving line segment 121; the dummy bit guiding unit 153 is connected to the third driving line segment 123; wherein the first guiding unit 151 is connected to the dummy bit guiding unit 153 to make the third driving line segment 123 is electrically coupled to the first driving line segment 121.
  • FIG. 4 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate, a wiring area including a display area and a periphery thereof, and a plurality of active switches and a plurality of pixel units are disposed in the display area of the first substrate, The plurality of pixel units are respectively coupled to the plurality of active switches; the first driving line segment 121 and the second driving line segment 122 are disposed in the wiring area; the third driving line segments 123 are electrically coupled to the plurality of virtual bit connections respectively The first driving line segment 121 is electrically coupled to the first guiding unit 151, and the second driving line segment 122 is electrically coupled to the plurality of virtual
  • the bit connection unit 153 forms a parallel circuit with the first driving line segment 121.
  • the third driving line segment 123, the first guiding unit 151 and the dummy bit guiding unit 153 are disposed in a single layer metal wiring manner or a double layer metal wiring.
  • FIG. 5 is a schematic diagram of a design of a B-type trace with a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate, a wiring area including a display area and a periphery thereof, and a plurality of active switches and a plurality of display areas in the display area of the first substrate Each of the plurality of pixel units is coupled to the plurality of active switches; the second substrate is disposed opposite to the first substrate; the first driving line segment 121 and the fourth driving line segment 124 are disposed on the a wiring area of the first substrate; the flexible circuit board 140 has a first line 141, the first line 141 is electrically coupled to the first driving line segment 121 and the fourth driving line segment 124; wherein the soft The circuit board 140 includes a second line 142 that is connected in parallel with the first line 141 to form a parallel line. In this way, the parallel line serves as an extension line of the first driving line segment 121 and the
  • the flexible circuit board 140 refers to a flexible printed circuit film or a flexible printed circuit board.
  • the second line 142 is electrically coupled to the plurality of dummy bit guiding units 153 and the first receiving unit 151, respectively.
  • FIG. 6 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate, a wiring area including a display area and a periphery thereof, and a plurality of active switches and a plurality of pixel units are disposed in the display area of the first substrate, The plurality of pixel units are respectively coupled to the plurality of active switches; the second substrate is disposed opposite to the first substrate; the first driving line segment 121, the third driving line segment 123 and the fourth driving line segment 124 are disposed on the a wiring area of the first substrate; a first guiding unit 151 for connecting the first driving line segment 121 and the third driving line segment 123; the flexible circuit board 140 having a first line 141 and a second line 142; The first driving line segment 121 and the fourth driving line segment 124 are electrically coupled through the first line 141; the second line 142 is connected to the first
  • FIG. 7 is a schematic diagram of a design of a B-type trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate, a wiring area including a display area and a periphery thereof, and a plurality of active switches and a plurality of pixel units are disposed in the display area of the first substrate, The plurality of pixel units are respectively coupled to the plurality of active switches; the first driving line segment 121, the second driving line segment 122 and the fourth driving line segment 124 are disposed on the wiring area of the first substrate; the flexible circuit board 140, Having a first line 141 and a second line 142, the second line 142 is connected to the first line 141 to form a parallel line; a first guiding unit 151, the first driving line segment 121 and the fourth driving line segment 124 electrically coupled to the plurality of virtual bit connection units 153; wherein, the second The driving line segments 122 are electrically coupled
  • FIG. 8 is a schematic diagram of a design of a class B trace and a flexible circuit board trace of a display panel according to an embodiment of the present application.
  • a display panel includes: a first substrate, a wiring area including a display area and a periphery thereof, and a plurality of active switches and a plurality of pixel units are disposed in the display area of the first substrate, The plurality of pixel units are respectively coupled to the plurality of active switches; the first driving line segment 121 and the fourth driving line segment 124 are disposed in the wiring area; and the flexible circuit board 140 has the first line 141 and the second line 142.
  • the second line 142 is connected to the first line 141 to form a parallel line; the first line 141 is respectively connected to the first driving line segment 121 and the fourth driving line segment 124; wherein, the first line The driving line segment 121 and the fourth driving line segment 124 are respectively electrically coupled to the third driving line segment 123 and the dummy bit guiding unit 153 through the first guiding unit 151, and the second driving line segment 122 is electrically coupled to the second driving line segment 122, respectively.
  • the plurality of dummy bit guiding units 153 are formed to form a parallel circuit with the first driving line segment 121 and the fourth driving segment line 124 respectively; the third driving line segment 123 is disposed between the dummy lead receiving units 153.
  • a display device includes: a control component, and further includes a display panel described in each embodiment.
  • FIG. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • a display device 200 of the present application includes: a control unit 190 for transmitting a common voltage, a driving power source and an operation signal through a transmission line, and the control unit 190 includes but is not limited to The timing module, the source driving unit 104 and the gate driving unit 105, and the display panel 201 include any one of the foregoing embodiments.
  • the display panel of the present application may be, for example, a liquid crystal display panel.
  • the display panel may be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, or a curved surface. Display panel or other type of display panel.
  • the application can reduce the resistance of the B-type traces of the Wire On Array (WOA) in the narrow frame, thereby improving the product quality and improving the reliability and service life of the product.
  • WOA Wire On Array

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Abstract

一种显示面板（12）及其应用的显示装置（200），显示面板（12）包括：第一基板，具有显示区和布线区，显示区设置多个主动开关和多个像素单元，多个像素单元分别耦接于多个主动开关；第二基板，与第一基板相对配置；第一驱动线段（121），设置于第一基板的布线区，第一驱动线段（121）包括多个第一电路引脚（121a、121b）；第二驱动线段（122），设置于第一基板的布线区，第二驱动线段（122）包括多个第二电路引脚（122a、122b）；第一接引单元（151），用以分别连接多个第一电路引脚（121a、121b）；以及虚位接引单元（153），用以分别连接多个第二电路引脚（122a、122b）；第一驱动线段（121）环设于第二驱动线段（122）外围，第一接引单元（151）连接虚位接引单元（153），使第二驱动线段（122）电性耦接至第一驱动线段（121）以形成并联电路。

Description

显示面板及其应用的显示装置 技术领域
本申请涉及一种显示器中的电路结构，特别是涉及一种显示面板的阵列线路及其应用的显示装置。
背景技术
液晶显示器(Liquid Crystal Display,LCD)近来已被广泛的运用，随着驱动技术的改良，使其具有低的消耗电功率、薄型量轻、低电压驱动等优点，目前已经广泛的应用在摄录放影机、笔记本电脑、桌上型显示器及各种投影设备上。
主动开关-液晶显示器(TFT-LCD)的面板正常显示时，需要栅级驱动线路(Gate Driver)结合栅极线(Gate line)、源极驱动线路(Source Driver)结合数据线(Data line)配合彩色滤光片基板的共同电极(彩膜共同电极，CF Com)和存储电极。其中像素(pixel)电极信号由数据线通过主动开关(TFT)打开后供给。存储电极信号由有效显示区外围的阵列共享线(AA Com)供给，以与像素电极之间形成存储电容(Cst)。彩膜共同电极信号由阵列基板的阵列线路(Wire On Array，WOA)的共同电压线路供给彩色滤光片基板，彩膜共同电极与像素电极之间形成液晶电容(Clc)。
为了节省成本，经常将栅极驱动电路、栅极线和数据线等电路制作在同一块显示基板上，再利用阵列线路将该显示基板与用于传输栅极驱动信号的覆晶薄膜(Chip On Film，COF)连接。一般而言，阵列线路包括：给彩色滤光片基板共同电压的A类走线；给芯片提供电源驱动信号的B类走线；给芯片提供工作信号的C类走线。然而，栅极线的信号是经由阵列线路，逐层逐级传递至各层级的芯片(Chip)与集成电路(IC)，因此通过B类走线提供给芯片/集成电路的电源驱动信号不能失真严重，在设计上，需将此等芯片/集成电路的B类走线的阻值降低。
但是，随着显示面板的窄边框越来越窄的要求，阵列线路的空间也就越来越小，此也造成此等芯片/集成电路的驱动走线的布线空间越来越小，走线不但越来越细，也越来越长，相应的阻抗值就越大。不但造成驱动信号严重 失真，进而影响到显示面板显示均齐性。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种线路阵列电路结构，能降低在窄边框中的阵列线路(Wire On Array，WOA)的B类走线的阻值，进而提升产品质量，并提高产品的信赖性和使用寿命。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种显示面板包括：第一基板，具有显示区和布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板，与所述第一基板相对配置；第一驱动线段，设置于所述第一基板的布线区，所述第一驱动线段包括多个第一电路引脚；第二驱动线段，设置于所述第一基板的布线区，所述第二驱动线段包括多个第二电路引脚；第一接引单元，用以分别连接所述多个第一电路引脚；以及虚位接引单元，用以分别连接所述多个第二电路引脚；其中，所述第一驱动线段环设于所述第二驱动线段外围，所述第一接引单元连接所述虚位接引单元，使所述第二驱动线段电性耦接至所述第一驱动线段以形成并联电路。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述第一接引单元是以单层金属布线方式或双层金属布线方式设置。
在本申请的一实施例中，所述虚位接引单元是以单层金属布线方式或双层金属布线方式设置。
在本申请的一实施例中，还包括第三驱动线段，所述第三驱动线段分别电性耦接多个虚位接引单元与所述第一接引单元。
在本申请的一实施例中，所述第三驱动线段是以单层金属布线方式或双层金属布线方式设置。
在本申请的一实施例中，所述多个第一电路引脚连接至一驱动芯片。
在本申请的一实施例中，所述驱动芯片为源极驱动芯片。
在本申请的一实施例中，所述驱动芯片为栅极驱动芯片。
在本申请的一实施例中，所述显示面板还包括：第四驱动线段，设置于所述第一基板的布线区；以及软性电路板，具有第一线路，所述第一线路电 性耦接所述第一驱动线段及所述第四驱动线段。
在本申请的一实施例中，所述软性电路板还包括第二线路，所述第二线路并接所述第一线路以形成并联线路。
在本申请的一实施例中，所述软性电路板为可挠性印刷电路薄膜或柔性印刷电路板。
在本申请的一实施例中，所述显示面板还包括：第四驱动线段，设置于所述第一基板的布线区，所述第一接引单元151连接所述第一驱动线段与所述第三驱动线段；以及软性电路板，具有第一线路和第二线路，所述第二线路并接所述第一线路以形成并联线路，所述第一驱动线段与所述第四驱动线段通过所述第一线路形成电性耦接。
在本申请的一实施例中，所述显示面板还包括：第四驱动线段，设置于所述第一基板的布线区；以及软性电路板，具有第一线路和第二线路，所述第二线路并接所述第一线路以形成并联线路，所述第一接引单元将所述第一驱动线段与第四驱动线段电性耦接至所述多个虚位接引单元，所述第二驱动线段分别电性耦接至所述多个虚位接引单元，以分别与所述第一驱动线段及第四驱动段线形成并联电路。
在本申请的一实施例中，所述显示面板还包括：第四驱动线段，设置于所述第一基板的布线区；以及软性电路板，具有第一线路和第二线路，所述第二线路并接所述第一线路以形成并联线路，所述第一线路分别连接所述第一驱动线段及所述第四驱动线段，所述第一驱动线段与所述第四驱动线段通过所述第一接引单元分别电性耦接至所述第三驱动线段与所述多个虚位接引单元，所述第二驱动线段分别电性耦接至所述多个虚位接引单元，以分别与所述第一驱动线段及第四驱动段线形成并联电路，所述第三驱动线段设置于所述多个虚引接引单元之间。
在本申请的一实施例中，所述第二驱动线段的边缘具有一主动开关阵列。
本申请的另一目的一种显示面板，包括：第一基板，具有显示区和布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板，与所述第一基板相对配置；第一驱动线段，设置于所述第一基板的布线区，所述第一驱动线段包括多个第一电路引脚；第二驱动线段，设置于所述第一基板的布线区，所述第 二驱动线段包括多个第二电路引脚；第一接引单元，用以分别连接所述多个第一电路引脚；以及虚位接引单元，用以分别连接所述多个第二电路引脚；其中，所述第一驱动线段环设于所述第二驱动线段外围；所述多个第一电路引脚与所述多个电路引脚以同向方式，朝向所述第一基板边缘的方向延伸配置；所述第一接引单元电性耦接所述虚位接引单元，以使所述第一驱动线段与所述第二驱动线段形成并联电路；所述第二基板边缘位于所述第一驱动线段及第一接引单元之间和位于所述第二驱动线段及虚位接引单元之间；所述第一驱动线段还包括一第一对位标记，所述第一对位标记用以连接所述第一电路引脚；所述第二驱动线段还包括一第二对位标记，所述第二对位标记用以连接所述第二电路引脚；所述第二驱动线段的边缘具有一主动开关阵列；所述第一接引单元与所述虚位驱动线段采用单层或双层金属布线方式电性耦接所述第一驱动线段。
在本申请的一实施例中，所述第一对位标记和第二对位标记的材料选自铝、钼、铬及其合金所组成的群组。
在本申请的一实施例中，所述第一接引单元和所述虚位接引单元的材料选自铝、钼、铬及其合金所组成的群组。
本申请的又一目的一种显示装置，包括：控制部件以及显示面板，显示面板包括：第一基板，具有显示区和布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板，与所述第一基板相对配置；第一驱动线段，设置于所述第一基板的布线区，所述第一驱动线段包括多个第一电路引脚；第二驱动线段，设置于所述第一基板的布线区，所述第二驱动线段包括多个第二电路引脚；第一接引单元，用以分别连接所述多个第一电路引脚；及虚位接引单元，用以分别连接所述多个第二电路引脚；其中，所述第一驱动线段环设于所述第二驱动线段外围，所述第一接引单元连接所述虚位接引单元，使所述第二驱动线段电性耦接至所述第一驱动线段以形成并联电路。
本申请能降低在窄边框中的阵列线路(Wire On Array，WOA)的B类走线的阻值，进而提升产品质量，并提高产品的信赖性和使用寿命。
附图说明
图1a为范例性的显示装置的架构示意图。
图1b是范例性的线路阵列的走线示意图。
图1c是范例性的线路阵列中的B类走线示意图。
图2为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图3a为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图3b为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图4为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图5为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图6为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图7为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图8为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。
图9为依据本申请一实施例的显示装置的架构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附 图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及实施例，对依据本申请提出的一种显示面板及其应用的显示装置，其具体实施方式、结构、特征及其功效，详细说明如后。
图1a为范例性的显示装置的架构示意图。请参照图1a，一种显示装置200包括：控制板100，所述控制板100包括时序模块(Timing Controller，TCON)101；印刷电路板103，与所述控制板100之间通过柔性扁平电缆(Flexible Flat Cable，FFC)102相连接；源极驱动单元104与栅极驱动单元105配置于布线区109，分别与显示区106内的数据线104a及栅极线105a连接。在一些实施例中，栅极驱动单元105及源极驱动单元104包括但不限制为覆晶薄膜形式。
显示装置200的驱动方式包括：系统主板提供颜色(例如：R/G/B)压缩信号、控制信号及电源传输至控制板100。控制板100上的时序控制器(Timing Controller，TCON)101于处理此等信号后，连同被驱动电路处理的电源，通过柔性扁平电缆(Flexible Flat Cable，FFC)102，一并传输至印刷电路板103的栅极驱动单元105及源极驱动单元104，栅极驱动单元105及源极驱动单元104将必要性的数据与电源传输于显示区106，从而使得显示装置200获得呈现画面需求的电源、信号。
图1b为范例性的显示面板的线路阵列的走线示意图。请配合参阅图1a以利于理解。在某些实施例中，将驱动单元(104，105)、栅极线105a和数据线104a等电路会制作在同一块显示基板上，再利用阵列线路120将显示基板与用于传输驱动信号的驱动单元(104，105)连接。一般而言，阵列线路120包括：传输共同电压的A类走线120a；给芯片提供电源驱动信号的B类走线120b；给芯片提供工作信号的C类走线120c。
图1c为范例性的显示面板的B类走线示意图。请参照图1c，其绘示范例 性的显示面板的阵列线路结构(B类走线120b)，其具有多个驱动线段(B类走线120b)，每一驱动线段包括多个电路引脚及接引单元。
然而，栅极线105a的信号是经由阵列线路120，逐层逐级传递至各层级的栅极驱动单元105的芯片(Chip)与集成电路(IC)，因此通过B类走线120b提供给芯片/集成电路的电源驱动信号不能失真严重。但实际使用上，由于栅极驱动单元105之间(例如Gate to Gate，G-G)的阵列线路120存在阻抗，故阵列线路120越长，相应的阻抗值就越大，这会让显示信号爬升和幅值。故在设计上，需将此等芯片/集成电路的B类走线120b的阻值降低。
图2为本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。请参照图2，本申请一实施例中，一种显示面板12包括：第一基板(图未示)，具有显示区和布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板(图未示)，与所述第一基板相对设置；第一驱动线段121，设置于所述第一基板的布线区，所述第一驱动线段121具有多个第一电路引脚(121a、121b)；第二驱动线段122，设置于所述第一基板的布线区，所述第二驱动线段122具有多个第二电路引脚(122a、122b)；第一接引单元151，分别连接该些第一电路引脚(121a、121b)；虚位接引单元153，分别连接该些第二电路引脚(122a、122b)；其中，所述第一驱动线段121环设于所述第二驱动线段122外围，所述第一接引单元151连接所述虚位接引单元153，使所述第二驱动线段122电性耦接至所述第一驱动线段121以形成并联电路。
在一实施例中，所述第一驱动线段121还包括一第一对位标记(图未示)，所述第一对位标记用以连接所述第一电路引脚(121a、121b)。
在一实施例中，所述第二驱动线段122还包括一第二对位标记(图未示)，所述第二对位标记用以连接所述第二电路引脚(122a、122b)。
在一实施例中，所述第一对位标记的材料选自铝、钼、铬及其合金所组成的群组。
在一实施例中，所述第二对位标记的材料选自铝、钼、铬及其合金所组成的群组。
在一实施例中，该些第二电路引脚(122a、122b)的边缘具有一主动开关阵列。
在一实施例中，该些第一电路引脚(121a、121b)连接至一驱动芯片(160，图5)。
在一实施例中，所述驱动芯片160为源极驱动芯片。
在一实施例中，所述驱动芯片160为栅极驱动芯片。
在一实施例中，所述第一接引单元151是以单层金属布线方式或双层金属布线方式设置。
在一实施例中，所述虚位接引单元153是以单层金属布线方式或双层金属布线方式设置。
在一实施例中，还包括第三驱动线段(123，图3a)，所述第三驱动线段123分别电性耦接多个虚位接引单元与所述第一接引单元。
在一实施例中，所述第三驱动线段123是以单层金属布线方式或双层金属布线方式设置。
其中，单层金属布线方式可使一显示面板在正常显示时会最大程度的避免外框或空气的影响。双层金属布线方式可造成最大限度的减小线路阵列的阻值。
在本申请的一实施例中，一种显示面板包括：一第一基板(图未示)，在所述第一基板上设置主动开关和像素单元；一第二基板(图未示)，与所述第一基板相对设置；一第一驱动线段121，具有多个第一电路引脚121a、121b；一第二驱动线段122，具有多个第二电路引脚122a、122b；一第一接引单元151，用以分别连接该些第一电路引脚121a、121b及该些第二电路引脚122a、122b；以及一虚位接引单元153，用以分别连接该些第二电路引脚122a、122b及所述第二驱动线段122；其中，所述第一驱动线段121和所述第二驱动线段153设置于所述第一基板的布线区，所述第一接引单元151电性耦接所述虚位接引单元153，以使所述第一驱动线段121与所述第二驱动线段122形成并联电路；所述第二基板边缘位于所述第一驱动线段121及第一接引单元151之间和位于所述第二驱动线段122及虚位接引单元153之间；所述第一驱动线段121还包括一第一对位标记，所述第一对位标记用以连接所述第一电路引脚121a、121b；所述第二驱动线段122还包括一第二对位标记，所述第二对位标记用以连接所述第二电路引脚122a、122b；所述第二驱动线段122的边缘具有一主动开关阵列；所述第一接引单元151与所述虚位 驱动线段153采用单层或双层金属布线方式电性耦接所述第一驱动线段121。
图3a为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请一实施例中，一种显示面板包括：第一基板，包括显示区及其外围的布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板(图未示)，与所述第一基板相对设置；第一驱动线段121与第三驱动线段123设置于所述布线区；第三驱动线段123与所述第一驱动线段121的电路引脚是以相对方向配置；第三驱动线段123分别连接所述第一接引单元151，以电性耦接所述第一驱动线段121。
图3b为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请的一实施例中，一种显示面板包括：第一基板(图未示)，在所述第一基板设置主动开关和像素单元；第二基板(图未示)，与所述第一基板相对设置；第一驱动线段121与第三驱动线段123设置于所述布线区；第三驱动线段123与所述第一驱动线段121的电路引脚是以相对方向配置；第一接引单元151连接第一驱动线段121；虚位接引单元153，连接第三驱动线段123；其中，所述第一接引单元151连接所述虚位接引单元153，使所述第三驱动线段123电性耦接至所述第一驱动线段121。
图4为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请一实施例中，一种显示面板包括：第一基板，包括显示区及其外围的布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第一驱动线段121与第二驱动线段122设置于所述布线区；所述第三驱动线段123分别电性耦接多个虚位接引单元153与所述第一接引单元151，所述第一驱动线段121分别电性耦接所述第一接引单元151；第二驱动线段122分别电性耦接至所述多个虚位接引单元153，以与所述第一驱动线段121形成并联电路。
在一些实施例中，所述第三驱动线段123、所述第一接引单元151与所述虚位接引单元153是以单层金属布线方式或双层金属布线设置。
图5为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请一实施例中，一种显示面板包括：第一基板，包括显示区及其外围的布线区，在所述第一基板的显示区设置多个主动开关和多 个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板，与所述第一基板相对配置；第一驱动线段121与第四驱动线段124，设置于所述第一基板的布线区；软性电路板140，具有第一线路141，所述第一线路141电性耦接所述第一驱动线段121及所述第四驱动线段124；其中，所述软性电路板140包括第二线路142，所述第二线路142并接所述第一线路141以形成并联线路。如此，所述并联线路作为所述第一驱动线段121及第四驱动线段124的延伸线路，扩张三者彼此的线宽及面积，而且通过并联线路的并联阻抗原理，相对较能辅助降低驱动线段的阻值。
在一些实施例中，所述软性电路板140是指可挠性印刷电路薄膜或柔性印刷电路板。
在一些实施例中，所述第二线路142分别电性耦接多个虚位接引单元153与所述第一接引单元151。
图6为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请一实施例中，一种显示面板包括：第一基板，包括显示区及其外围的布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第二基板，与所述第一基板相对配置；第一驱动线段121、第三驱动线段123与第四驱动线段124，设置于所述第一基板的布线区；第一接引单元151，用以连接所述第一驱动线段121与所述第三驱动线段123；软性电路板140，具有第一线路141与第二线路142；其中，所述第一驱动线段121与所述第四驱动线段124通过所述第一线路141形成电性耦接；所述第二线路142并接所述第一线路141以形成并联线路。
图7为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请一实施例中，一种显示面板包括：第一基板，包括显示区及其外围的布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第一驱动线段121、第二驱动线段122与第四驱动线段124，设置于所述第一基板的布线区；软性电路板140，具有第一线路141与第二线路142，所述第二线路142并接所述第一线路141以形成并联线路；第一接引单元151，将所述第一驱动线段121与第四驱动线段124电性耦接至多个虚位接引单元153；其中，第二 驱动线段122分别电性耦接至所述多个虚位接引单元153，以分别与所述第一驱动线段121及第四驱动段线124形成并联电路。
图8为依据本申请一实施例的显示面板的B类走线配合软性电路板走线的设计示意图。在本申请一实施例中，一种显示面板包括：第一基板，包括显示区及其外围的布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；第一驱动线段121与第四驱动线段124，设置于所述布线区；软性电路板140，具有第一线路141与第二线路142，所述第二线路142并接所述第一线路141以形成并联线路；所述第一线路141分别连接所述第一驱动线段121及所述第四驱动线段124；其中，所述第一驱动线段121与所述第四驱动线段124，通过第一接引单元151分别电性耦接至第三驱动线段123与虚位接引单元153，第二驱动线段122分别电性耦接至所述多个虚位接引单元153，以分别与所述第一驱动线段121及第四驱动段线124形成并联电路；所述第三驱动线段123设置于虚引接引单元153之间。
请同时参考图2至图8，在一实施例中，一种显示装置包括：控制部件、还包括各实施例中所述的显示面板。
图9为依据本申请一实施例的显示装置的架构示意图。请同时参考图2至图8，在一实施例中，本申请的一种显示装置200包括：控制部件190，通过传输线路以传输共同电压、驱动电源与工作信号，控制部件190包括但不限于先前所述时序模块、源极驱动单元104与栅极驱动单元105；显示面板201，其包括前述各实施例中的任一种显示面板。
在某些实施例中，本申请所述显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板、W-OLED显示面板、QLED显示面板、等离子体显示面板、曲面型显示面板或其他类型显示面板。
本申请能降低在窄边框中的阵列线路(Wire On Array，WOA)的B类走线的阻值，进而提升产品质量，并提高产品的信赖性和使用寿命。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上 的限制，虽然本申请已以实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许还动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (19)

  1. 一种显示面板，包括：
    第一基板，具有显示区和布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；
    第二基板，与所述第一基板相对配置；
    第一驱动线段，设置于所述第一基板的布线区，所述第一驱动线段包括多个第一电路引脚；
    第二驱动线段，设置于所述第一基板的布线区，所述第二驱动线段包括多个第二电路引脚；
    第一接引单元，用以分别连接所述多个第一电路引脚；以及
    虚位接引单元，用以分别连接所述多个第二电路引脚；
    其中，所述第一驱动线段环设于所述第二驱动线段外围，所述第一接引单元连接所述虚位接引单元，使所述第二驱动线段电性耦接至所述第一驱动线段以形成并联电路。
  2. 如权利要求1所述的显示面板，其中所述第一接引单元是以单层金属布线方式或双层金属布线方式设置。
  3. 如权利要求1所述的显示面板，其中所述虚位接引单元是以单层金属布线方式或双层金属布线方式设置。
  4. 如权利要求1所述的显示面板，其中还包括第三驱动线段，所述第三驱动线段分别电性耦接多个虚位接引单元与所述第一接引单元。
  5. 如权利要求4所述的显示面板，其中所述第三驱动线段是以单层金属布线方式或双层金属布线方式设置。
  6. 如权利要求1所述的显示面板，其中所述多个第一电路引脚连接至一驱动芯片。
  7. 如权利要求6所述的显示面板，其中所述驱动芯片为源极驱动芯片。
  8. 如权利要求6所述的显示面板，其中所述驱动芯片为栅极驱动芯片。
  9. 如权利要求1所述的显示面板，还包括：
    第四驱动线段，设置于所述第一基板的布线区；以及
    软性电路板，具有第一线路，所述第一线路电性耦接所述第一驱动线段及所述第四驱动线段。
  10. 如权利要求9所述的显示面板，其中所述软性电路板还包括第二线路，所述第二线路并接所述第一线路以形成并联线路。
  11. 如权利要求9所述的显示面板，其中所述软性电路板为可挠性印刷电路薄膜或柔性印刷电路板。
  12. 如权利要求4所述的显示面板，还包括：
    第四驱动线段，设置于所述第一基板的布线区，所述第一接引单元151连接所述第一驱动线段与所述第三驱动线段；以及
    软性电路板，具有第一线路和第二线路，所述第二线路并接所述第一线路以形成并联线路，所述第一驱动线段与所述第四驱动线段通过所述第一线路形成电性耦接。
  13. 如权利要求1所述的显示面板，还包括：
    第四驱动线段，设置于所述第一基板的布线区；以及
    软性电路板，具有第一线路和第二线路，所述第二线路并接所述第一线路以形成并联线路，所述第一接引单元将所述第一驱动线段与第四驱动线段电性耦接至所述多个虚位接引单元，所述第二驱动线段分别电性耦接至所述多个虚位接引单元，以分别与所述第一驱动线段及第四驱动段线形成并联电路。
  14. 如权利要求4所述的显示面板，还包括：
    第四驱动线段，设置于所述第一基板的布线区；以及
    软性电路板，具有第一线路和第二线路，所述第二线路并接所述第一线路以形成并联线路，所述第一线路分别连接所述第一驱动线段及所述第四驱动线段，所述第一驱动线段与所述第四驱动线段通过所述第一接引单元分别电性耦接至所述第三驱动线段与所述多个虚位接引单元，所述第二驱动线段分别电性耦接至所述多个虚位接引单元，以分别与所述第一驱动线段及第四驱动段线形成并联电路，所述第三驱动线段设置于所述多个虚引接引单元之间。
  15. 如权利要求1所述的显示面板，其中所述第二驱动线段的边缘具有一主动开关阵列。
  16. 一种显示面板，包括：
    第一基板，具有显示区和布线区，在所述第一基板的显示区设置多个主 动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；
    第二基板，与所述第一基板相对配置；
    第一驱动线段，设置于所述第一基板的布线区，所述第一驱动线段包括多个第一电路引脚；
    第二驱动线段，设置于所述第一基板的布线区，所述第二驱动线段包括多个第二电路引脚；
    第一接引单元，用以分别连接所述多个第一电路引脚；以及
    虚位接引单元，用以分别连接所述多个第二电路引脚；
    其中，所述第一驱动线段环设于所述第二驱动线段外围；所述多个第一电路引脚与所述多个电路引脚以同向方式，朝向所述第一基板边缘的方向延伸配置；所述第一接引单元电性耦接所述虚位接引单元，以使所述第一驱动线段与所述第二驱动线段形成并联电路；
    其中，所述第二基板边缘位于所述第一驱动线段及第一接引单元之间和位于所述第二驱动线段及虚位接引单元之间；
    其中，所述第一驱动线段还包括一第一对位标记，所述第一对位标记用以连接所述第一电路引脚；
    其中，所述第二驱动线段还包括一第二对位标记，所述第二对位标记用以连接所述第二电路引脚；
    其中，所述第二驱动线段的边缘具有一主动开关阵列；
    其中，所述第一接引单元与所述虚位驱动线段采用单层或双层金属布线方式电性耦接所述第一驱动线段。
  17. 如权利要求16所述的显示面板，其中所述第一对位标记和第二对位标记的材料选自铝、钼、铬及其合金所组成的群组。
  18. 如权利要求16所述的显示面板，其中所述第一接引单元和所述虚位接引单元的材料选自铝、钼、铬及其合金所组成的群组。
  19. 一种显示装置，包括：
    控制部件；以及
    显示面板，包括：
    第一基板，具有显示区和布线区，在所述第一基板的显示区设置多个主动开关和多个像素单元，所述多个像素单元分别耦接于所述多个主动开关；
    第二基板，与所述第一基板相对配置；
    第一驱动线段，设置于所述第一基板的布线区，所述第一驱动线段包括多个第一电路引脚；
    第二驱动线段，设置于所述第一基板的布线区，所述第二驱动线段包括多个第二电路引脚；
    第一接引单元，用以分别连接所述多个第一电路引脚；及
    虚位接引单元，用以分别连接所述多个第二电路引脚；
    其中，所述第一驱动线段环设于所述第二驱动线段外围，所述第一接引单元连接所述虚位接引单元，使所述第二驱动线段电性耦接至所述第一驱动线段以形成并联电路。
PCT/CN2017/115850 2017-10-26 2017-12-13 显示面板及其应用的显示装置 Ceased WO2019080291A1 (zh)

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