WO2019075950A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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WO2019075950A1
WO2019075950A1 PCT/CN2018/073972 CN2018073972W WO2019075950A1 WO 2019075950 A1 WO2019075950 A1 WO 2019075950A1 CN 2018073972 W CN2018073972 W CN 2018073972W WO 2019075950 A1 WO2019075950 A1 WO 2019075950A1
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layer
gate
insulating layer
active layer
oxide semiconductor
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French (fr)
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平山秀雄
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to the technical field of fabrication of array substrates in displays.
  • Display screens have been used more and more widely in electronic devices in various fields of production and life, such as consumer electronics such as mobile phones, tablet computers or desktop computers, home appliances such as televisions, and public devices such as outdoor advertising.
  • the display screen is mainly a liquid crystal display (LCD) or an organic light emitting diode (OLED).
  • LCD liquid crystal display
  • OLED organic light emitting diode
  • the narrow bezel display device can Effectively reduce the area of the non-display area in the splicing screen, effectively increase the screen ratio, and significantly improve the overall display effect. Therefore, the narrow frame has become an urgent problem to be solved in the field of display.
  • the present invention provides an array substrate having a smaller size.
  • a first thin film transistor and a second thin film transistor are disposed on the substrate at a predetermined distance and juxtaposed.
  • the first thin film transistor includes a first active layer, a first gate insulating layer, a first gate, an interlayer insulating layer, and a first source/drain, which are sequentially stacked on the substrate, the first A source/drain is electrically connected to the first active layer.
  • the second thin film transistor sequentially stacks a second gate, a second gate insulating layer, a second active layer, an etch barrier layer, and a second source/drain disposed on the substrate.
  • the first active layer and the second gate are both polysilicon materials, and the first gate and the second active layer comprise an oxide semiconductor material.
  • the oxide semiconductor material layer corresponding to the first gate insulating layer is correspondingly covered
  • the layer constitutes a first gate
  • the oxide semiconductor material layer corresponding to the second gate insulating layer constitutes a second active layer
  • the insulating layer constitutes the etch stop layer
  • a metal layer on the interlayer insulating layer and the etch barrier layer wherein a first source/drain is formed corresponding to the first gate position, and the first source/drain
  • the pole is electrically connected to the first active layer, the first active layer, the first gate insulating layer, the first gate, the interlayer insulating layer, and the first source And a drain constitutes a first thin film transistor;
  • a second source/drain is formed corresponding to the second gate position, and the second source/drain is electrically connected to the second active layer,
  • the second gate, the second gate insulating layer, the second active layer, the etch barrier layer, and the second source/drain constitute a second thin film transistor.
  • the first thin film transistor and the second thin film transistor are simultaneously fabricated. Therefore, it is not necessary to separately manufacture the second thin film transistor in the driving circuit, thereby improving the manufacturing efficiency.
  • the channel size of the second thin film transistor constituting the active layer by using the oxide semiconductor is small, so that the space occupied by the thin film transistor in each pixel unit is reduced, which in turn effectively increases the size of the display area in the display panel and improves the size.
  • An aperture ratio, and a first thin film transistor that passes through the polysilicon in the non-display area serves as a thin film transistor of the switch in the driving ground circuit, thereby making the scan driving circuit or the data driving circuit small in size and fast in response, thereby further reducing the size of the non-display area Reduce, so as to achieve the purpose of increasing the screen ratio to achieve a narrow border.
  • FIG. 1 is a schematic perspective view of a display device according to an embodiment of the invention.
  • FIG. 2 is a schematic plan view showing the planar structure of the array substrate in the display panel shown in FIG. 1.
  • FIG. 3 is a schematic side view showing the structure of the array substrate shown in FIGS.
  • FIG. 4 is a schematic side view showing the corresponding steps in the manufacturing process of the array substrate shown in FIG. 3.
  • FIG. 4 is a schematic side view showing the corresponding steps in the manufacturing process of the array substrate shown in FIG. 3.
  • FIG. 5 is a flow chart showing the fabrication of the array substrate shown in FIG.
  • FIG. 1 is a schematic perspective structural view of a display device according to an embodiment of the present invention.
  • the display device 100 includes a display panel 10 and other auxiliary structures (not shown), wherein the auxiliary structure shown includes a housing and a support structure.
  • the display panel 10 includes an image display area 10a and a non-display area 10b.
  • the display area 10a is used as an image display
  • the non-display area 10b is disposed around the display area 10a as a non-light-emitting area and is not used as an image display.
  • the display panel 10 further includes an array substrate 10c and an opposite substrate 10d, and a display medium layer 10e interposed between the array substrate 10c and the opposite substrate 10d.
  • the display medium is an Organic Electroluminescence Diode (OLED).
  • OLED Organic Electroluminescence Diode
  • the display panel 10 in the display device 100 can use a liquid crystal material as a display medium, and is not limited thereto.
  • a three-dimensional Cartesian coordinate system composed of a first direction X, a second direction Y, and a third direction Z that are perpendicular to each other is first defined.
  • the display device 100 has a thickness direction along the third direction Z.
  • FIG. 2 is a schematic plan view of the array substrate 10 c of the display panel 10 shown in FIG. 1 .
  • the first area (not labeled) of the corresponding image display area 10a of the array substrate 10c includes a plurality of m*n pixel units (Pixel) 110 and m (Data Line) data lines arranged in a matrix (Scan). Line) 120 and n scan lines 130, m, n are natural numbers greater than one.
  • the plurality of data lines 120 are insulated from each other and arranged in parallel along the first direction Y by a first predetermined distance.
  • the plurality of scan lines 130 are also insulated and parallel to each other along the second direction X by a second predetermined distance.
  • the plurality of scan lines 130 are insulated from the plurality of data lines 120, and the first direction X and the second direction Y are perpendicular to each other.
  • the m data lines 120 are respectively defined as D1, D2, ..., Dm-1, Dm;
  • the n scan lines 130 are respectively defined as G1, G2, .... ., Gn-1, Gn.
  • a plurality of the pixel units 110 are respectively located in a matrix formed by the plurality of data lines 120 and the scan lines 130, and are electrically connected to the corresponding data lines 120 and the scan lines 130.
  • the display device 100 (FIG. 1) further includes a control circuit 101 for displaying image display for driving the pixel units 110 of the plurality of matrix arrays in the non-display area 10b, and a data driving circuit (Data The driver 102 and the scan driver 103 are disposed in a second region (not shown) of the array substrate 11c.
  • the data driving circuit 102 is electrically connected to the plurality of data lines 120 for transmitting image data for display to the plurality of pixel units 110 in the form of data voltages through the plurality of data lines 120.
  • the scan driving circuit 103 is configured to be electrically connected to the plurality of scan lines 130 for outputting scan signals through the plurality of scan lines 130 for controlling when the pixel unit 110 receives image data for image display.
  • the control circuit 101 is electrically connected to the data driving circuit 102 and the scan driving circuit 103 for controlling the working timing of the data driving circuit 102 and the scan driving circuit 103, that is, outputting the corresponding timing control signal to the data driving circuit 102 and scanning. Drive circuit 103.
  • the scan driving circuit 103 is directly disposed on the non-display area 10b of the display panel 10.
  • the control circuit 101 and the data driving circuit 102 are disposed on the other carrier circuit board independently of the array substrate 10c.
  • the circuit elements in the scan driving circuit 103 are fabricated in the display panel 10 in the same process as the pixel unit 110 in the display panel 10, that is, the GOA (Gate on Array) technology.
  • FIG. 3 is a schematic side view of the array substrate shown in FIGS. 1 and 2 .
  • the array substrate 10c includes a substrate 11 made of a transparent material such as glass or plastic.
  • the substrate 11 includes opposing first and second surfaces 111, 112.
  • the first surface 111 is provided with a first thin film transistor T1 and a second thin film transistor T2 which are spaced apart by a predetermined distance along the first direction X and arranged in parallel.
  • the first direction X and the second direction Y are both parallel to the plane of the substrate 11.
  • the first thin film transistor T1 is a low temperature poly-silicon (LTPS) fabricated by a low temperature process
  • the second thin film transistor T2 is an oxide semiconductor thin film transistor, such as an indium.
  • Gallium zinc oxide is used as an active layer thin film transistor (Indium Gallium Zinc Oxide, IGZO).
  • the first thin film transistor T1 is located in the scan driving circuit 103 or the data driving circuit 102 for scanning or providing a data signal for each pixel unit 110 in the display area 10a.
  • the second thin film transistor T2 is located in each of the pixel units 110 and electrically connected to the pixel electrode Px and drives the pixel electrode Px for image display.
  • the buffer layer 12 is disposed on the substrate 11 , and the buffer layer 12 includes a first sub-buffer layer 121 and a second sub-buffer layer 122 respectively stacked in the third direction Z, that is, the first buffer layer 121 is disposed on the substrate 11 .
  • the first surface 111 and the second sub-buffer layer 122 are disposed on the surface of the first sub-buffer layer 121 away from the first surface 111.
  • the first sub-buffer layer 121 is a silicon oxide (SiOx) film layer
  • the second sub-buffer layer is a silicon nitride (SiNx) film layer.
  • the silicon nitride and silicon oxide laminates have a thickness of 50 to 100 nm.
  • the thickness ratio of the silicon nitride layer to the silicon oxide layer is from 1 to 1.5:0.8 to 1.6; for example, the thickness ratio of the silicon nitride layer to the silicon oxide layer is 1:1.
  • the thickness of the silicon oxide layer is 20 to 60 nm.
  • the reaction gas forming the SiNx film layer is a mixed gas of SiH4, NH3, and N2, or a mixed gas of SiH2C12, NH3, and N2; the reaction gas forming the SiOx film layer is a mixed gas of SiH4 and N2O, or SiH4 or silicon.
  • the first thin film transistor T1 is disposed in the third direction Z from the surface of the buffer layer 12, and the first active layer 131, the first gate insulating layer 132, the first gate electrode 133, the interlayer insulating layer 134, and the first source are sequentially stacked. / drain 135, wherein the first source/drain 135 is electrically connected to the first active layer 131 through the first via H1, respectively. Specifically, the first source 1351 and the first drain 1352 of the first source/drain 135 are respectively located on the two sides of the first gate 133 along the first direction X, and pass through the two first through holes H1. Electrically connected to opposite sides of the first active layer 131 along the first direction X, respectively.
  • the second thin film transistor T2 includes a second gate electrode 151, a second gate insulating layer 152, a second active layer 153, an etch barrier layer 154, and a second source layer which are sequentially stacked from the surface of the buffer layer 12 in the third direction Z. / drain 155.
  • the etch barrier layer 154 covers the second active layer 153 and is disposed on the opposite sides of the second active layer 153 along opposite sides of the first direction X.
  • the second source/drain 155 includes a second source 1551 and a second drain 1552 which are disposed at a predetermined distance along the first direction X, and are electrically connected to the second through the two second vias H2, respectively. Active layer 153.
  • the first active layer 131 and the second gate 151 are in the same layer structure and are fabricated in the same process, and the materials are all polycrystalline silicon (p-Si) fabricated by a low temperature process.
  • the polysilicon material of the first active layer 131 includes a channel dopant, so that the first thin film transistor T1 has a faster turn-off effect; the polysilicon material of the second gate 151 includes a conductive doping The foreign matter is made such that the conductive characteristics of the second thin film transistor T2 are better.
  • the first gate electrode 133 and the second active layer 153 each include a first oxide semiconductor layer I1 and a second oxide semiconductor layer I2 disposed adjacent to each other, wherein the first oxide semiconductor layer I1 is The second oxide semiconductor layer I2 is adjacent to the direction of the substrate 11.
  • the material of the first oxide semiconductor layer I1 is indium gallium zinc oxide (IGZO)
  • the material of the second oxide semiconductor layer I2 is indium tin oxide (ITO).
  • the second active layer 153 is made of an oxide semiconductor material, so that the second thin film transistor T2 is an IGZO/ITO thin film transistor, which is used as a thin film transistor for driving in the pixel unit 110 (FIG. 2), and a thin film transistor of IGZO.
  • the threshold voltage Vth having a small size and a high stability is obtained, so that the stability of the second thin film transistor T2 is better.
  • the interlayer insulating layer 134 and the etch barrier layer 154 are in the same layer structure and are fabricated in the same process, and are both silicon oxide (SiOx) material or silicon nitride (SiNx).
  • the first source/drain 135 and the second source/drain 155 are made of aluminum or titanium.
  • the first source/drain 135 and the second source/drain 155 are patterned by forming an aluminum or titanium metal layer formed on the surface of the interlayer insulating layer 134 and the etching barrier layer 154.
  • the first active layer 131 is made of a phosphorus (P) doped polysilicon material, such that the first thin film transistor T1 is configured as a top gate P-type thin film transistor.
  • the second active layer 154 is a nitrogen (N) doped oxide semiconductor such that the second transistor T2 constitutes a bottom gate N-type thin film transistor.
  • the first thin film transistor T1 used as the driving in the pixel unit 110 is fabricated in synchronization with the second thin film transistor T2 provided in the driving circuit in the non-display area 10b, and therefore, it is not necessary to separately target the driving circuit.
  • the second thin film transistor T2 is separately fabricated to improve the production efficiency.
  • the channel size of the second thin film transistor T2 constituting the active layer by using the oxide semiconductor is small, so that the space occupied by the thin film transistor in each pixel unit is reduced, which in turn effectively increases the size of the display region 10a in the display panel 10.
  • the first thin film transistor T1 passing through the polysilicon in the non-display region 10b serves as a thin film transistor of the switch in the driving ground circuit, thereby making the scan driving circuit or the data driving circuit small in size and fast in response, thereby making The size of the non-display area 10b is further reduced, thereby achieving the purpose of increasing the screen ratio to achieve a narrow border.
  • FIG. 4 is a schematic diagram of a side structure corresponding to each step in the manufacturing process of the array substrate 10 c shown in FIG. 3
  • FIG. 5 is a flow chart of the fabrication of the array substrate shown in FIG. 3 .
  • the fabrication steps of the array substrate 10c will be specifically described below with reference to FIGS.
  • Step 401 as shown by 4a in FIG. 4, provides the substrate 11, and the buffer layer 12 is formed on the first surface 111 on the side of the substrate 11.
  • a first sub-buffer layer 121 and a second sub-buffer layer 122 of a certain thickness are deposited on the first surface of the substrate 11 by plasma chemical vapor deposition (PECVD), for example, the certain thickness is 50. ⁇ 100nm.
  • the deposition material for the first sub-buffer layer 121 may be a silicon oxide (SiOx) film layer
  • the deposition material for the second sub-buffer layer 122 may be a silicon nitride (SiNx) film layer.
  • Step 402 as shown in FIG. 4b, forming a polysilicon layer on the surface of the second sub-buffer layer 122 and patterning, forming a first active layer 131 and a second gate spaced apart by a predetermined distance along the first direction X. 151.
  • an amorphous silicon layer is deposited on the surface of the buffer layer 12 away from the substrate by a plasma enhanced chemical vapor deposition (PECVD) process, followed by laser irradiation, An Exiler Laser Annel (ELA) and a photolithography process cause the amorphous silicon layer to be converted into a polysilicon layer.
  • PECVD plasma enhanced chemical vapor deposition
  • ELA Exiler Laser Annel
  • the deposition temperature is generally controlled below 500 ° C, and the thickness of the amorphous silicon layer is 40 nm to 50 nm. Of course, the appropriate thickness can also be selected according to the specific process needs.
  • the polysilicon layer is then doped and patterned.
  • the patterning can be completed by a dry etching and a strip process.
  • the polysilicon layer is doped by a boron ion implantation (CD implantation) at a position corresponding to a CD ion implantation doping (CD IMP), that is, doping boron ions having semiconductor characteristics.
  • CD implantation boron ion implantation
  • CD IMP CD ion implantation doping
  • the doped polysilicon layer is processed by NP lithography and an annealing process to form the first active layer 131.
  • the polysilicon material of the first active layer 131 contains a channel dopant, so that the first thin film transistor T1 has a faster turn-off effect.
  • Conductive doping is performed at a position corresponding to NP ion implantation doping (NP IMP) in the polysilicon layer, that is, a material having a conductor property is doped into the polysilicon layer.
  • NP IMP NP ion implantation doping
  • the polysilicon material of the second gate electrode 151 contains a conductive dopant, so that the conductive property of the second thin film transistor T2 is better.
  • the patterning is to partially etch the polysilicon layer by a patterning process to form a patterned first active layer 131 and a second gate 151 on the polysilicon layer.
  • an ashing and stripping process is performed thereon.
  • the etching of the polysilicon layer can be implemented by a prior art wet etching process or a dry etching process.
  • Step 403 as shown in 4c of FIG. 4, forming an insulating layer along the third direction Z on the surfaces of the first active layer 131 and the second gate 151, the insulating layers respectively forming the first gate insulating layer 132 and The second gate insulating layer 152. That is, the insulating layer corresponding to the position of the first active layer 131 constitutes the first gate insulating layer 132, and the insulating layer corresponding to the position of the second gate 152 constitutes the second gate insulating layer 152.
  • a certain thickness of silicon nitride (SiNx) and/or a silicon oxide film layer (SiOx) is deposited by a CVD process corresponding to the surfaces of the first active layer 131 and the second gate 151.
  • the first active layer 131 and the second gate 151 are formed with an insulating layer, the first active layer 131 and the second gate 151 are formed to perform DHF cleaning, and the first active layer 131 is formed.
  • An insulating layer is formed on the surface of the second gate electrode 151, followed by ashing and cleaning.
  • Step 404 as shown in 4d of FIG. 4, an oxide semiconductor material layer is disposed on the first gate insulating layer 132 and the second gate insulating layer 152 and patterned.
  • the oxide semiconductor material layer corresponding to the first gate insulating layer 132 constitutes a first gate 133; and the oxide semiconductor material layer corresponding to the second gate insulating layer 152 constitutes a first layer Two active layers 153.
  • the first gate 133 and the second active layer 153 each include a first oxide semiconductor layer I1 and a second oxide semiconductor layer I2 disposed adjacent to each other, wherein the first oxidation The material semiconductor layer I1 is closer to the substrate 11 than the second oxide semiconductor layer I2.
  • the material of the first oxide semiconductor layer I1 is indium gallium zinc oxide (IGZO)
  • the material of the second oxide semiconductor layer I2 is indium tin oxide (ITO).
  • an IGZO film layer is formed on the surface of the first gate insulating layer 132 and the second gate insulating layer 152 by sputtering, and then an ITO material is deposited on the surface of the IGZO film layer to form ITO.
  • the film layer is patterned by the patterning process for the IGZO film layer and the ITO film layer to form the first oxide semiconductor layer I1 and the second oxide semiconductor layer I2.
  • the first gate 133 including the first oxide semiconductor layer I1 and the second oxide semiconductor layer I2 of the first active layer 131 serves as a conductive electrode; and the first oxide semiconductor layer corresponding to the second gate 151
  • the second active layer 153 of I1 and the second oxide semiconductor layer I2 serves as a conductive channel.
  • source and drain regions are respectively formed on the opposite sides of the first active layer 131 along the first direction X corresponding to the first gate electrode 133 by ion implantation.
  • the patterning can be completed by a dry etching and a lift-off process, and after forming the first gate 133 and the second active layer 153, an activation annealing process is required. And cleaning process.
  • Step 405 forming an insulating layer on the first gate 133 and the second active layer 153, as shown by 4e in FIG. 4, wherein the insulating layer corresponding to the first gate 133 is formed.
  • the interlayer insulating layer 134 forms the etching stopper layer 154 corresponding to the insulating layer of the second active layer 153.
  • a certain thickness of silicon oxide is deposited on the surface of the first gate insulating layer 132, the first gate electrode 133, the second gate insulating layer 152, and the second active layer 153 away from the substrate 11 by a CVD process.
  • a silicon nitride (SiNx) film layer as the insulating layer.
  • the insulating layer corresponding to the first gate 133 constitutes an interlayer insulating layer 134
  • the insulating layer corresponding to the second active layer 153 constitutes the etching stopper layer 154.
  • the source and drain regions are respectively formed on the opposite sides of the second active layer 154 along the first direction X corresponding to the second gate 151 by ion implantation. .
  • the positions corresponding to the source and drain regions corresponding to the opposite sides of the first active layer 131 corresponding to the first gate 133 in the first direction X are respectively dried or wet.
  • the first via hole H1 is formed in an inscribed manner, and the through hole penetrates the interlayer insulating layer 134 and the first gate insulating layer 132 such that a portion of the first active layer 131 is exposed from the first via hole H1.
  • the second via holes H2 are formed respectively corresponding to the positions of the second active layer 153 corresponding to the source and drain regions on opposite sides of the first direction X, and the through holes penetrate the etch barrier layer 154, thereby A portion of the second active layer 153 is exposed from the second via hole H2.
  • a hydrogenation annealing process is performed after the interlayer insulating layer 134 and the etching stopper layer 154 are formed to repair defects and solidification in the polysilicon material in the first active layer 131 and the second gate electrode 151. Grain boundaries.
  • Step 406 as shown by 4f in FIG. 4, an aluminum or titanium metal layer is formed on the interlayer insulating layer 134 and the etching stopper layer 155 and patterned by dry etching or etching.
  • the first source/drain 135 is formed corresponding to the first gate along a position on both sides of the first direction X, and the first source/drain 135 and the first active layer 131 pass The first through holes H1 are electrically connected.
  • the first active layer 131, the first gate insulating layer 132, the first gate 133, the interlayer insulating layer 134, and the first source/drain 135 constitute a first A thin film transistor T1.
  • the second gate 151 Corresponding to the second gate 151 forming a second source/drain 155 along a position on both sides of the first direction X, and the second source/drain 155 and the second active layer 153 pass the first The two through holes H2 are electrically connected.
  • the second gate electrode 151, the second gate insulating layer 152, the second active layer 153, the etch barrier layer 154, and the second source/drain 155 constitute a second thin film transistor T2. It is understood that a pixel electrode (not shown) is further formed on the second source/drain 135, wherein the second source 1351 or the second drain 1352 is electrically connected to the pixel electrode (not shown).

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板及其制作方法。阵列基板（10c）包括在基底（11）上设置有间隔预定距离且并列设置的第一薄膜晶体管（T1）与第二薄膜晶体管（T2）。第一薄膜晶体管（T1）包括依次层叠设置在基底（11）上的第一有源层（131）、第一栅极绝缘层（132）、第一栅极（133）、层间绝缘层（134）以及第一源极（1351）/漏极（1352），第一源极（1351）/漏极（1352）与第一有源层（131）电性连接。第二薄膜晶体管（T2）包括依次层叠设置在基底（11）上的第二栅极（151）、第二栅极绝缘层（152）、第二有源层（153）、蚀刻阻挡层（154）以及第二源极/漏极（155）。第一有源层（131）与第二栅极（151）均为多晶硅材料，第一栅极（133）与第二有源层（153）包含氧化物半导体材料。

Description

阵列基板及其制作方法
本发明要求2017年10月20日递交的发明名称为“阵列基板及其制作方法”的申请号201710986111.8的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示技术领域，尤其涉及显示器中阵列基板的制作技术领域。
背景技术
显示屏已经越来越广泛地应用于人们的生产与生活的各个领域的电子装置内，例如手机、平板电脑或者台式电脑等消费性电子领域，电视等家电领域或者户外广告等公共设备领域。
目前显示屏主要为液晶显示屏(Liquid Crystal Display，LCD)或者有机发光显示屏(Organic Light Emitting Diode，OLED)。为了提高显示器的显示效果，无论是应用于户外的大型显示屏幕或者应用于消费性电子的小型显示屏幕，越来越多的人开始将注意力投向显示装置的窄边框设计，窄边框显示装置可以有效降低拼接屏中非显示区域的面积，有效提高屏占比，显著提高整体的显示效果。由此，窄边框成为目前显示器领域中亟待解决的问题。
发明内容
为解决窄边框的问题，本发明提供一种具有较小尺寸的阵列基板。
进一步，提供前述阵列基板的制作方法。
本发一实施例提供的阵列基板，在基底上设置有间隔预定距离且并列设置的第一薄膜晶体管与第二薄膜晶体管。所述第一薄膜晶体管包括依次叠设置在所述基底上的第一有源层、第一栅极绝缘层、第一栅极、层间绝缘层以及第一源极/漏极，所述第一源极/漏极与所述第一有源层电性连接。所述第二薄膜晶体管依次层叠设置在所述基底上的第二栅极、第二栅极绝缘层、第二有源层、蚀刻阻挡层以及第二源极/漏极。其中，所述第一有源层与所述第二栅极均为多晶硅材料，所述第一栅极与所述第二有源层包含氧化物半导体材料。
本发一实施例提供的阵列基板制作方法，包括步骤：
提供基板，并且在基板一侧形成缓冲层；
在所述缓冲层表面形成多晶硅层并进行图案化，形成间隔预定距离的第一有源层与第二栅极；
在所述第一有源层与所述第二栅极上形成覆盖所述第一有源层和第二栅极的绝缘层，所述绝缘层分别构成第一栅极绝缘层与第二栅极绝缘层；
在所述第一栅极绝缘层与所述第二栅极绝缘层上设置氧化物半导体材料层并且进行图案化，其中，对应覆盖所述第一栅极绝缘层的所述氧化物半导体材料层层构成第一栅极；对应覆盖所述第二栅极绝缘层的所述氧化物半导体材料层构成第二有源层；
在所述第一栅极与所述第二有源层上形成绝缘层，其中，对应所述第一栅极的所述绝缘层构成层间绝缘层，对应所述第二有源层的所述绝缘层构成所述蚀刻阻挡层；
在所述层间绝缘层与所述蚀刻阻挡层上形成金属层并且进行图案化，其中，对应所述第一栅极位置形成第一源极/漏极，且所述第一源极/漏极与所述第一有源层电性连接，所述第一有源层、所述第一栅极绝缘层、所述第一栅极、所述层间绝缘层以及所述第一源极/漏极构成第一薄膜晶体管；对应所述第二栅极位置形成第二源极/漏极，且所述第二源极/漏极与所述第二有源层电性连接，所述第二栅极、所述第二栅极绝缘层、所述第二有源层，蚀刻阻挡层以及所述第二源极/漏极构成第二薄膜晶体管。
相较于现有技术，第一薄膜晶体管与第二薄膜晶体管同步进行制作，因此，无需单独针对驱动电路中的第二薄膜晶体管单独进行制作，提高了制作效率。
进一步，利用氧化物半导体构成有源层的第二薄膜晶体管的通道尺寸较小，从而使得每个像素单元中薄膜晶体管占用的空间减小，继而有效增加了显示面板中显示区的尺寸以及提高了开口率，并且在非显示区通过多晶硅的第一薄膜晶体管作为驱动地电路中作为开关的薄膜晶体管，从而使得扫描驱动电路 或者数据驱动电路尺寸较小且响应速度快，继而使得非显示区尺寸进一步减小，从而达到提高屏占比实现窄边框的目的。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一实施例中显示装置立体结构示意图。
图2为图1所示显示面板中阵列基板的平面结构示意图。
图3为如图1、2所示阵列基板的侧面结构示意图。
图4为如图3所示阵列基板的制作过程中各步骤对应的侧面结构示意图。
图5为如图3所示阵列基板的制作流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
下面结合附图，具体说明本发明阵列基板的具体实施方式。
请参阅图1，图1为本发明一实施例中显示装置立体结构示意图。如图1所示，显示装置100包括显示面板10与其他辅助结构(图未示)，其中，所示辅助结构包括壳体与支撑结构。
显示面板10包括图像用显示区10a与非显示区10b。显示区10a用作图像显示，非显示区10b环绕设置于显示区10a周围并作为非出光区域，并不用作图像显示。其中，显示面板10还包括有阵列基板10c与对向基板10d，以及夹设于阵列基板10c与对向基板10d的显示介质层10e。本实施例中，显示介质为有机发光半导体材料(Organic Electroluminescence Diode，OLED)。当然，在本发明其他变更实施例中，显示装置100中的显示面板10可以以液晶 材料作为显示介质，并不以此为限。为了便于说明，先定义由相互垂直的第一方向X、第二方向Y以及第三方向Z构成的三维直角坐标系。其中，显示装置100沿着第三方向Z为其厚度方向。
请参阅图2，其为图1所示显示面板10中阵列基板10c的平面结构示意图。如图2所示，阵列基板10c中对应图像显示区10a的第一区域(未标示)包括多个呈矩阵排列的m*n像素单元(Pixel)110、m条(Data Line)数据线(Scan Line)120以及n条扫描线130，m、n为大于1的自然数。
其中，该多条数据线120沿第一方向Y间隔第一预定距离相互绝缘且平行排列，该多条扫描线130沿第二方向X亦间隔第二预定距离相互绝缘且平行排列，并且所该多条扫描线130与该多条数据线120相互绝缘，所述第一方向X与第二方向Y相互垂直。为便于说明，所述m条数据线120分别定义为D1、D2、......，Dm-1、Dm；所述n条扫描线130分别定义为G1、G2、......，Gn-1、Gn。多个所述像素单元110分别位于该多条数据线120、扫描线130构成的矩阵中，并且与对应的其中数据线120以及扫描线130电性连接。
对应显示面板10的非显示区10b，显示装置100(图1)进一步包括设置于非显示区10b的用于驱动多个矩阵排列的像素单元110进行图像显示的控制电路101、数据驱动电路(Data Driver)102以及扫描驱动电路(Scan Driver)103，设置于阵列基板11c的第二区域(未标示)。其中，数据驱动电路102与该多条数据线120电性连接，用于将待显示用的图像数据通过该多条数据线120以数据电压的形式传输至该多个像素单元110。扫描驱动电路103用于与该多条扫描线130电性连接，用于通过该多条扫描线130输出扫描信号用于控制像素单元110何时接收图像数据进行图像显示。控制电路101分别与数据驱动电路102和扫描驱动电路103电性连接，用于控制数据驱动电路102与扫描驱动电路103的工作时序，也即是输出对应的时序控制信号至数据驱动电路102以及扫描驱动电路103。
本实施例中，扫描驱动电路103直接设置于显示面板10的非显示区10b，控制电路101与数据驱动电路102则独立于阵列基板10c设置于其他的承载电路板板上。本实施例中，扫描驱动电路103中的电路元件与显示面板10中的像素单元110同一制程制作于显示面板10中，也即是GOA(Gate on Array)技术。
请参阅图3，其为如图1、2所示阵列基板的侧面结构示意图。
如图3所示，阵列基板10c包括基底11，所述基底11由透明材质的玻璃、塑胶等材质构成。基底11包括相对的第一表面111与第二表面112。所述第一表面111上设置有沿着第一方向X间隔预定距离且并列设置的第一薄膜晶体管T1与第二薄膜晶体管T2。其中，第一方向X与第二方向Y均平行基底11所在平面。
需要说明的是，本实施例中，第一薄膜晶体管T1为低温制程制作的多晶硅有源层薄膜晶体管(Low Temperature Poly-silicon，LTPS)，第二薄膜晶体管T2为氧化物半导体薄膜晶体管，例如铟镓锌氧化物作为有源层的薄膜晶体管(Indium Gallium Zinc Oxide，IGZO)。第一薄膜晶体管T1位于扫描驱动电路103或者数据驱动电路102中，用于针对显示区10a中的各个像素单元110进行扫描或者提供数据信号。第二薄膜晶体管T2为位于每一个像素单元110中并与像素电极Px电性连接并驱动像素电极Px进行图像显示。
基底11上设置有缓冲层12，缓冲层12分别包括沿着第三方向Z依次层叠设置的第一子缓冲层121与第二子缓冲层122，也即是第一缓冲层121设置于基底11的第一表面111，第二子缓冲层122则设置于第一子缓冲层121远离第一表面111的表面。其中，第一子缓冲层121为氧化硅(SiOx)膜层，第二子缓冲层为氮化硅(SiNx)膜层。
具体的，所述氮化硅及氧化硅叠层的厚度为50～100nm。又如，氮化硅层与氧化硅层的厚度比例为1～1.5∶0.8～1.6；例如，氮化硅层与氧化硅层的厚度比例为1∶1。例如，氧化硅层的厚度为20～60nm。其中，形成SiNx膜层的反应气体为SiH4、NH3、N2的混合气体，或者为SiH2C12、NH3、N2的混合气体；形成SiOx膜层的反应气体为SiH4、N2O的混合气体，或者为SiH4、硅酸乙酯(TEOS)的混合气体。
第一薄膜晶体管T1自缓冲层12表面沿第三方向Z依次叠设置的第一有源层131、第一栅极绝缘层132、第一栅极133、层间绝缘层134以及第一源极/漏极135，其中，第一源极/漏极135分别通过第一通孔H1与第一有源层电131电性连接。具体地，第一源极/漏极135中的第一源极1351与第一漏极1352分别位于第一栅极133沿着第一方向X的两侧，且通过两个第一通孔H1分别电性连接至第一有源层131沿着第一方向X的相对两侧。第二薄膜晶体管T2 包括自缓冲层12表面沿第三方向Z依次叠设置的第二栅极151、第二栅极绝缘层152、第二有源层153、蚀刻阻挡层154以及第二源极/漏极155。具体的，蚀刻阻挡层154覆盖于第二有源层153，并且在对应第二有源层153沿着第一方向X的相对两侧设置的第二通孔H2。对应地，第二源极/漏极155包括沿着第一方向X间隔预定距离设置的第二源极1551与第二漏极1552，通过两个第二通孔H2分别电性连接至第二有源层153。
较佳地，第一有源层131与第二栅极151位于同一层结构且在同一制程中制作完成，且材质均为采用低温制程制作的多晶硅(p-Si)。较佳地，第一有源层131的多晶硅材料中包含有沟道掺杂物，从而使得第一薄膜晶体管T1具有较快速的关断特效；第二栅极151的多晶硅材料中包含有导电掺杂物，从而使得第二薄膜晶体管T2的导电特性较好。
较佳地，第一栅极133与第二有源层153均包含相邻设置的第一氧化物半导体层I1与第二氧化物半导体层I2，其中，所述第一氧化物半导体层I1较所述第二氧化物半导体层I2邻近基底11的方向。本实施例中，第一氧化物半导体层I1的材质为铟镓锌氧化物(IGZO)，第二氧化物半导体层I2的材质为氧化铟锡(ITO)。
第二有源层153由于采用氧化物半导体材料构成，从而构成第二薄膜晶体管T2则为IGZO/ITO薄膜晶体管，其用作像素单元110(图2)中驱动用薄膜晶体管，由于IGZO的薄膜晶体管具有尺寸体积较小且具有稳定性较高的阈值电压Vth，进而使得第二薄膜晶体管T2稳定性较佳。层间绝缘层134与蚀刻阻挡层154位于同一层结构且在同一制程中制作完成，且均为氧化硅(SiOx)材料或者氮化硅(SiNx)。
第一源极/漏极135与第二源极/漏极155均为铝或者钛金属材质。其中，第一源极/漏极135与第二源极/漏极155为经过针对形成于所述层层间绝缘层134、蚀刻阻挡层154表面的铝或者钛金属层进行图案化形成。
较佳地，第一有源层131为磷(P)掺杂的多晶硅材质，使得第一薄膜晶体管T1构成为顶栅极(Top Gate)P型薄膜晶体管。第二有源层154为氮(N)掺杂的氧化物半导体，使得第二晶体管T2构成底栅极(Bottom Gate)N型薄膜晶体管。
相较于现有技术，像素单元110中用作驱动的第一薄膜晶体管T1与设置 在非显示区10b中的驱动电路中的第二薄膜晶体管T2同步进行制作，因此，无需单独针对驱动电路中的第二薄膜晶体管T2单独进行制作，提高了制作效率。
同时，利用氧化物半导体构成有源层的第二薄膜晶体管T2的通道尺寸较小，从而使得每个像素单元中薄膜晶体管占用的空间减小，继而有效增加了显示面板10中显示区10a的尺寸以及提高了开口率，并且在非显示区10b通过多晶硅的第一薄膜晶体管T1作为驱动地电路中作为开关的薄膜晶体管，从而使得扫描驱动电路或者数据驱动电路尺寸较小且响应速度快，继而使得非显示区10b尺寸进一步减小，从而达到提高屏占比实现窄边框的目的。
请参阅图4，其为如图3所示阵列基板10c的制作过程中各步骤对应的侧面结构示意图，图5为如图3所示阵列基板的制作流程图。下面结合图3-5具体说明阵列基板10c的制作步骤。
步骤401，如图4中的4a所示，提供基板11，并且在基板11一侧的第一表面111形成缓冲层12。
较佳地，在基底11的第一表面上利用等离子体化学气相沉积法(PECVD)沉积一层一定厚度的第一子缓冲层121与第二子缓冲层122，例如，所述一定厚度为50～100nm。其中，针对第一子缓冲层121的沉积材料可以为氧化硅(SiOx)膜层，针对第二子缓冲层122的沉积材料可以为氮化硅(SiNx)膜层。步骤402，如图4中的4b所示，在第二子缓冲层122表面形成多晶硅层并进行图案化，沿着第一方向X形成间隔预定距离的第一有源层131与第二栅极151。
具体地，在针对沉积有缓冲层12的基板11通过DGH清洗之后，采用等离子体增强化学气相沉积(PECVD)工艺在缓冲层12远离基板的表面上沉积非晶硅层，接着利用激光照射、准分子激光退火(Excimer Laser Annel，ELA)以及光刻制程使得所述非晶硅层使其转变为多晶硅层。其中，沉积温度一般控制在500℃以下，非晶硅层的厚度为40nm～50nm。当然，也可根据具体的工艺需要选择合适的厚度。
然后针对所述多晶硅层进行掺杂并且图案化。其中，所述图案化可以采用干刻(dry etching)以及剥离(Strip)制程完成。
然后，在多晶硅层通过硼离子注入(B implantation)采用离子注入掺杂的方式(CD ion implantation doping，CD IMP)对应的位置进行沟道掺杂，也即 是将具有半导体特性的硼离子掺杂入多晶硅层中，利用NP光刻以及退火制程针对掺杂后的多晶硅层进行处理，从而形成第一有源层131。由此，第一有源层131的多晶硅材料中包含有沟道掺杂物，从而使得第一薄膜晶体管T1具有较快速的关断特效。
在多晶硅层通过硼离子注入(B implantation)采用离子注入掺杂的方式(NP ion implantation doping，NP IMP)对应的位置进行导电物掺杂，也即是将具有导体特性的材质掺杂入多晶硅层中，从而形成第二栅极151。由此，第二栅极151的多晶硅材料中包含有导电掺杂物，从而使得第二薄膜晶体管T2的导电特性较好。所述图案化为通过构图工艺，对多晶硅层进行部分刻蚀，以使多晶硅层上形成图形化的第一有源层131及第二栅极151。较佳地，在完成第一有源层131与第二栅极151后，对其执行灰化(ashing)以及剥离制程。本实施例中，对多晶硅层的刻蚀可以采用现有技术的湿法刻蚀工艺或者干法刻蚀工艺实现。
步骤403，如图4中的4c所示，在第一有源层131与第二栅极151表面沿着第三方向Z形成绝缘层，所述绝缘层分别构成第一栅极绝缘层132与第二栅极绝缘层152。也即是对应所述第一有源层131位置的绝缘层构成第一栅极绝缘层132，对应第二栅极152位置的绝缘层构成第二栅极绝缘层152。
具体地，对应第一有源层131与第二栅极151的表面采用CVD工艺沉积一定厚度的氮化硅(SiNx)和/或氧化硅膜层(SiOx)。较佳地，在第一有源层131与第二栅极151表面形成绝缘层之前，对应形成有第一有源层131与第二栅极151进行DHF清洗，并且在第一有源层131与第二栅极151表面形成绝缘层之后进行灰化、清洗处理。
步骤404，如图4中的4d所示，在所述第一栅极绝缘层132与所述第二栅极绝缘层152上设置氧化物半导体材料层并且进行图案化。其中，对应覆盖所述第一栅极绝缘层132的所述氧化物半导体材料层层构成第一栅极133；对应覆盖所述第二栅极绝缘层152的所述氧化物半导体材料层构成第二有源层153。
本实施例中，较佳地，第一栅极133与第二有源层153均包含相邻设置的第一氧化物半导体层I1与第二氧化物半导体层I2，其中，所述第一氧化物半导体层I1较所述第二氧化物半导体层I2邻近基底11的方向。本实施例中， 第一氧化物半导体层I1的材质为铟镓锌氧化物(IGZO)，第二氧化物半导体层I2的材质为氧化铟锡(ITO)
具体地，将IGZO材料采用喷溅(sputter)方式在第一栅极绝缘层132以及第二栅极绝缘层152表面形成IGZO膜层，然后再将ITO材料沉积在所述IGZO膜层表面形成ITO膜层，再通过构图工艺针对IGZO膜层与ITO膜层进行图案化，从而形成第一氧化物半导体层I1与第二氧化物半导体层I2。其中，对应第一有源层131的包含第一氧化物半导体层I1与第二氧化物半导体层I2的第一栅极133作为导电电极；对应第二栅极151的包含第一氧化物半导体层I1与第二氧化物半导体层I2的第二有源层153作为导电沟道。
较佳地，形成第一栅极133以后，通过离子注入在第一有源层131沿着第一方向X对应第一栅极133的相对两侧分别形成源漏区。
较佳地，所述图案化可以通过干刻(dry etching)以及剥离制程来完成，并且在形成所述第一栅极133以及第二有源层153之后，需要进行主动退火制程(Activation Anneal)以及清洗制程。步骤405，如图4中的4e所示，在所述第一栅极133与所述第二有源层153上形成绝缘层，其中，对应所述第一栅极133的所述绝缘层构成层间绝缘层134，对应所述第二有源层153的所述绝缘层构成所述蚀刻阻挡层154。
具体地，采用CVD工艺在第一栅极绝缘层132、第一栅极133、第二栅极绝缘层152以及第二有源层153远离基板11的表面上沉积一定厚度的氧化硅(SiOx)或者氮化硅(SiNx)膜层，以作为所述绝缘层。当然，对应所述第一栅极133的所述绝缘层构成层间绝缘层134，对应所述第二有源层153的所述绝缘层构成所述蚀刻阻挡层154。
较佳地，在第二有源层153上形成蚀刻阻挡层154以后，通过离子注入在第二有源层154沿着第一方向X对应第二栅极151的相对两侧分别形成源漏区。
同时，需要说明的是，形成层间绝缘层134后，继续对应第一有源层131沿第一方向X对应第一栅极133的相对两侧对应源漏区的位置分别通过干刻或者湿刻方式形成第一通孔H1，所述通孔贯穿层间绝缘层134与第一栅极绝缘层132，从而使得部分第一有源层131自第一通孔H1显露出来。形成蚀刻阻挡层154后，继续对应第二有源层153沿第一方向X的相对两侧对应源漏 区的位置分别形成第二通孔H2，所述通孔贯穿蚀刻阻挡层154，从而使得部分第二有源层153自第二通孔H2显露出来。
较佳地，在形成所述层间绝缘层134与蚀刻阻挡层154以后执行氢化退火制程(Hydrogenation Anneal)，以修复第一有源层131与第二栅极151中多晶硅材料中的缺陷以及固化晶界。
步骤406，如图4中的4f所示，在所述层间绝缘层134与所述蚀刻阻挡层155上形成铝或者钛金属层并且进行干刻或者蚀刻方式图案化。其中，对应所述第一栅极沿着第一方向X两侧的位置形成第一源极/漏极135，且所述第一源极/漏极135与所述第一有源层131通过第一通孔H1电性连接。由此，所述第一有源层131、所述第一栅极绝缘层132、所述第一栅极133、所述层间绝缘层134以及所述第一源极/漏极135构成第一薄膜晶体管T1。
对应所述第二栅极151沿着第一方向X两侧的位置形成第二源极/漏极155，且所述第二源极/漏极155与所述第二有源层153通过第二通孔H2电性连接。所述第二栅极151、所述第二栅极绝缘层152、所述第二有源层153，蚀刻阻挡层154以及所述第二源极/漏极155构成第二薄膜晶体管T2。可以理解，后续在第二源极/漏极135上还形成有像素电极(图未示)，其中，第二源极1351或者第二漏极1352与像素电极(图未示)电性连接。
以上所述的实施方式，并不构成对该技术方案保护范围的限定。任何在上述实施方式的精神和原则之内所作的修改、等同替换和改进等，均应包含在该技术方案的保护范围之内。

Claims (10)

  1. 一种阵列基板，在基底上设置有间隔预定距离且并列设置的第一薄膜晶体管与第二薄膜晶体管，其中：
    所述第一薄膜晶体管包括依次叠设在所述基底上的第一有源层、第一栅极绝缘层、第一栅极、层间绝缘层以及第一源极/漏极，所述第一源极/漏极与所述第一有源层电性连接；
    所述第二薄膜晶体管包括依次层叠设置在所述基底上的第二栅极、第二栅极绝缘层、第二有源层、蚀刻阻挡层以及第二源极/漏极；
    所述第一有源层与所述第二栅极均为多晶硅材料，所述第一栅极与所述第二有源层包含氧化物半导体材料。
  2. 根据权利要求1所述的阵列基板，其中，所述第一栅极与所述第二有源层均包含相邻设置的第一氧化物半导体层与第二氧化物半导体层，所述第一氧化物半导体层相比所述第二氧化物半导体层靠近所述基底，所述第一氧化物半导体层的材质为铟镓锌氧化物，所述第二氧化物半导体层的材质为氧化铟锡。
  3. 根据权利要求1所述的阵列基板，其中，所述基底表面还设置有缓冲层，所述第一有源层与所述第二栅极均设置于所述缓冲层远离所述基底的表面。
  4. 根据权利要求1所述的阵列基板，其中，所述第一有源层与所述第二栅极位于同一层结构且在同一制程中制作完成，所述第一有源层的多晶硅材料中包含有沟道掺杂物，所述第二栅极的多晶硅材料中包含有导电掺杂物。
  5. 根据权利要求4所述的阵列基板，其中，所述层间绝缘层与所述第二栅极绝缘层均为氧化硅材料，且所述层间绝缘层与所述第二栅极绝缘层位于同一层结构且在同一制程中制作完成。
  6. 根据权利要求5所述的阵列基板，其中，所述第一栅极绝缘层与第二栅极绝缘层同层设置并相互连接从而构成一层覆盖所述第一有源层和第二栅极的绝缘层。
  7. 根据权利要求1所述的阵列基板，其中，所述第一薄膜晶体管为P型薄膜晶体管，所述第二薄膜晶体管为N型薄膜晶体管，所第二薄膜晶体管与进行图像显示的像素电极直接连接，用于驱动像素电极进行图像显示。
  8. 一种阵列基板制作方法，其中，包括步骤：
    提供基板，并且在基板一侧形成缓冲层；
    在所述缓冲层表面形成多晶硅层并进行图案化形成间隔预定距离的第一有源层与第二栅极；
    在所述第一有源层与所述第二栅极上形成覆盖所述第一有源层和第二栅极的绝缘层，所述绝缘层包括第一栅极绝缘层与第二栅极绝缘层；
    在所述第一栅极绝缘层与所述第二栅极绝缘层上设置氧化物半导体材料层并且进行图案化，其中，对应覆盖所述第一栅极绝缘层的所述氧化物半导体材料层层构成第一栅极；对应覆盖所述第二栅极绝缘层的所述氧化物半导体材料层构成第二有源层；
    在所述第一栅极与所述第二有源层上形成绝缘层，其中，对应所述第一栅极的所述绝缘层构成层间绝缘层，对应所述第二有源层的所述绝缘层构成所述蚀刻阻挡层；以及
    在所述层间绝缘层与所述蚀刻阻挡层上形成金属层并且进行图案化，其中，对应所述第一栅极位置形成第一源极/漏极，且所述第一源极/漏极与所述第一有源层电性连接，所述第一有源层、所述第一栅极绝缘层、所述第一栅极、所述层间绝缘层以及所述第一源极/漏极构成第一薄膜晶体管；对应所述第二栅极的位置形成第二源极/漏极，且所述第二源极/漏极与所述第二有源层电性连接，所述第二栅极、所述第二栅极绝缘层、所述第二有源层，蚀刻阻挡层以及所述第二源极/漏极构成第二薄膜晶体管。
  9. 根据权利要求8所述的阵列基板的制作方法，其中，所述第一栅极与所述第二有源层均包含相邻设置的第一氧化物半导体层与第二氧化物半导体层，所述第一氧化物半导体层相比所述第二氧化物半导体层靠近所述基底，所述第一氧化物半导体层的材质为铟镓锌氧化物，所述第二氧化物半导体层的材质为氧化铟锡。
  10. 根据权利要求8所述的阵列基板的制作方法，其中，所述第一有源层与所述第二栅极位于同一层结构且在同一制程中制作完成，所述第一有源层的多晶硅材料中包含有沟道掺杂物，所述第二栅极的多晶硅材料中包含有导电掺杂物，所述第一有源层与所述第二栅极均为多晶硅材料，所述层间绝缘层与所述蚀刻阻挡层均为氧化硅或者氮化硅材料。
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