WO2019061751A1 - Tft基板的制作方法及其结构 - Google Patents

Tft基板的制作方法及其结构 Download PDF

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Publication number
WO2019061751A1
WO2019061751A1 PCT/CN2017/111963 CN2017111963W WO2019061751A1 WO 2019061751 A1 WO2019061751 A1 WO 2019061751A1 CN 2017111963 W CN2017111963 W CN 2017111963W WO 2019061751 A1 WO2019061751 A1 WO 2019061751A1
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Prior art keywords
color
passivation layer
block
resist
spacer
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PCT/CN2017/111963
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English (en)
French (fr)
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叶岩溪
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深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to KR1020207011836A priority Critical patent/KR102299630B1/ko
Priority to EP17927583.9A priority patent/EP3690927B1/en
Priority to JP2020511795A priority patent/JP2020533626A/ja
Priority to US15/578,339 priority patent/US10503034B2/en
Priority to PL17927583.9T priority patent/PL3690927T3/pl
Publication of WO2019061751A1 publication Critical patent/WO2019061751A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13396—Spacers having different sizes
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/1343—Electrodes
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a structure thereof.
  • Liquid crystal display referred to as liquid crystal panel
  • LCD has many advantages such as thin body, power saving, no radiation, etc., and has been widely used, such as: LCD TV, smart phone, digital camera, tablet computer, computer Screens, or laptop screens, etc., dominate the field of flat panel display.
  • the structure of the liquid crystal panel is generally composed of a color filter (CF) substrate, a thin film transistor array substrate (TFT Array Substrate, TFT substrate), and a liquid crystal layer disposed between the two substrates.
  • CF color filter
  • TFT Array Substrate TFT substrate
  • liquid crystal layer disposed between the two substrates.
  • Liquid Crystal Layer is constructed by applying a driving voltage on two glass substrates to control the rotation of liquid crystal molecules of the liquid crystal layer, and refracting the light of the backlight module to generate a picture.
  • a color resistance of a plurality of colors for filtering and a black matrix (Black Matrix) for shielding light are generally provided on one side of the CF substrate, and a special one is disposed between the TFT substrate and the CF substrate.
  • Photo Space to support the cell thickness of the liquid crystal layer.
  • BPS 1 tone technology is one of the most cost effective BPS technologies.
  • BPS 1 tone technology means that the mask used in the BPS process has only one transmittance, and the corresponding BPS material only perceives one intensity of light, but the common BPS 1 tone technology requires the use of organic flattening (PFA).
  • PFA organic flattening
  • Layer this is because the common BPS 1 tone technology uses an island structure, which uses two color block blocks to act as a main photoresist spacer (Main PS) and a color block to serve as a sub-resistance interval.
  • Main PS main photoresist spacer
  • Sub (Sub PS) Because the height difference between the two color block and one color block is too large, the difference between the main photoresist spacer and the sub-resistor spacer is too large, and the organic flat layer is required. The height of the two-layer color block stack is flattened.
  • the BPS type TFT substrate from which the organic flattening layer is omitted uses a single-layer first island-shaped color resisting block 402 to pad the main photoresist spacer 701, and also uses a single-layer second island shape.
  • the color resist block 403 pads the secondary photoresist spacer 702, but only the second island shape of the sub-photoresist spacer 702
  • the color block 403 is formed by a slit diffraction type (SLT) mask for gray scale exposure, so that the second island-shaped color block 403 is semi-transparent; the corresponding main photoresist spacer 701 and the secondary photoresist
  • SLT slit diffraction type
  • the first island-shaped color resisting block 402 and the second island-shaped color resisting block 403 may be free from an organic flattening layer, and a second passivation layer combining silicon nitride (SiNx) and silicon oxide (SiOx) may be used.
  • the PV2 covers the color resist layer 401, the first island-shaped color resist block 402, the second island-shaped color resist block 403, and the existing first passivation layer PV1.
  • the TFT T and the first passivation layer PV1 covering the TFT T are formed on the base substrate 10; then the color resist is deposited and patterned to form the color resist layer 401 and the first island.
  • a color blocking block 402 and a second island-shaped color blocking block 403 depositing a second passivation layer PV2 and performing a patterning process; then depositing a conductive film and performing an etching process to form a pixel electrode 601 and a common electrode 602;
  • An integrated main photoresist spacer 701, a sub-resist spacer 702, and a black matrix 703 are formed on the second passivation layer PV2, the pixel electrode 601, and the common electrode 602.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can avoid the problem of residual conductive film due to the steep slope of the color resist edge and prevent the pixel electrode from being short-circuited with the common electrode.
  • the present invention first provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step S1 providing a substrate, forming TFTs arranged in an array on the substrate, and then depositing a first passivation layer covering all the TFTs;
  • Step S2 depositing a color color resist on the first passivation layer and performing a patterning process to form a color resist layer, a first color resist block and a second color block, and the height of the first color block is greater than the second The height of the color block;
  • Step S3 depositing a second passivation layer on the first passivation layer, the color resist layer, the first color block and the second color block;
  • Step S4 depositing a black photoresist on the second passivation layer and performing a patterning process.
  • Step S5 depositing a transparent conductive film on the integrated main photoresist spacer, the sub-resist spacer and the black matrix, and performing patterning processing to form a pixel electrode and a common electrode, wherein the pixel electrode passes through the The hole connects the drain of the TFT.
  • the step S2 performs patterning processing on the color color resistance using a slit diffraction type mask.
  • the color color resistance deposited in the step S2 includes a red color resistance, a green color resistance and a blue color resistance.
  • the material of the transparent conductive film is indium tin oxide.
  • the materials of the first passivation layer and the second passivation layer are both silicon nitride, silicon oxide or a combination of the two.
  • the first color block and the second color block are both island-shaped.
  • the invention also provides a TFT substrate structure, comprising:
  • a color resist layer a first color block and a second color block disposed on the first passivation layer, wherein a height of the first color block is greater than a height of the second color block;
  • a second passivation layer covering the first passivation layer, the color resist layer, the first color block and the second color block;
  • a pixel electrode and a common electrode disposed on the black matrix the pixel electrode connecting a drain of the TFT via a via hole penetrating the black matrix, the second passivation layer and the first passivation layer;
  • the via is completely blocked by the drain of the TFT.
  • the color resist layer includes a red color resist, a green color resist and a blue color resist; the first color resist block and the second color resist block are island-shaped.
  • the material of the pixel electrode 71 and the common electrode 72 is indium tin oxide.
  • the materials of the first passivation layer and the second passivation layer are both silicon nitride, silicon oxide or a combination of the two.
  • the invention also provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step S1 providing a substrate, and forming TFTs arranged in an array on the substrate; And depositing a first passivation layer covering all of the TFTs;
  • Step S2 depositing a color color resist on the first passivation layer and performing a patterning process to form a color resist layer, a first color resist block and a second color block, and the height of the first color block is greater than the second The height of the color block;
  • Step S3 depositing a second passivation layer on the first passivation layer, the color resist layer, the first color block and the second color block;
  • Step S4 depositing a black photoresist on the second passivation layer and performing a patterning process to form an integrated main photoresist spacer, a sub-resist spacer and a black matrix, and a black matrix, a via hole of the second passivation layer and the first passivation layer; wherein the main photoresist spacer is located above the first color resist block, and the sub-photo resist spacer is located above the second color resist block; The via hole is completely blocked by the drain of the TFT;
  • Step S5 depositing a transparent conductive film on the integrated main photoresist spacer, the sub-resist spacer and the black matrix, and performing patterning processing to form a pixel electrode and a common electrode, wherein the pixel electrode passes through the The hole is connected to the drain of the TFT;
  • the step S2 uses a slit diffraction type reticle to pattern the color color resistance
  • the color color resistance deposited in the step S2 includes a red color resistance, a green color resistance and a blue color resistance;
  • the material of the transparent conductive film is indium tin oxide
  • the materials of the first passivation layer and the second passivation layer are silicon nitride, silicon oxide or a combination of the two;
  • the first color block and the second color block are island-shaped.
  • the present invention provides a method for fabricating a TFT substrate by depositing a black photoresist on a second passivation layer and performing patterning treatment to form an integrated main photoresist spacer, a sub-resist spacer and After the black matrix, a transparent conductive film is deposited on the integrated main photoresist spacer, the sub-resist spacer and the black matrix, and patterned to form a pixel electrode and a common electrode, because of the integrated main light.
  • the spacer spacer, the sub-resistor spacer and the black matrix are filled, and the space in which the color resistance in the region where the black matrix is located is covered, so that the pixel electrode and the common electrode are formed on a relatively flat black matrix, and color resistance can be avoided.
  • the problem of residual etching of the conductive film caused by the steep edge slope prevents the pixel electrode from being short-circuited with the common electrode.
  • an integrated main photoresist spacer, a sub-resist spacer and a black matrix are disposed on the second passivation layer, and a pixel electrode and a common electrode are disposed on the black matrix
  • the integrated main photoresist spacer, the sub-resist spacer and the black matrix fill, cover the space where the color resistance in the region where the black matrix is located, and the pixel electrode and the common electrode are located on a relatively flat black matrix, which can be avoided.
  • Conductive film due to the steep slope of the color resist edge during the process The problem of etching residue prevents the pixel electrode from being short-circuited with the common electrode.
  • FIG. 1 is a schematic plan view of a conventional BPS type TFT substrate in which an organic flattening layer is omitted;
  • Figure 2 is a schematic cross-sectional view corresponding to A-A in Figure 1;
  • FIG. 3 is a top plan view showing a short circuit between a pixel electrode and a common electrode in a conventional BPS type TFT substrate in which an organic flattening layer is omitted;
  • FIG. 4 is a schematic cross-sectional view showing that a conventional BPS-type TFT substrate in which an organic flattening layer is omitted is likely to cause etching residue of a conductive film;
  • FIG. 5 is a flow chart showing a method of fabricating a TFT substrate of the present invention.
  • FIG. 6 is a top plan view showing a color resist layer, a first color resist block, and a second color block in the TFT substrate of the present invention
  • FIG. 7 is a cross-sectional view showing the TFT substrate of the invention at B-B shown in Figure 6;
  • Fig. 8 is a schematic cross-sectional view showing the TFT substrate of the present invention capable of avoiding etching residue of a conductive film.
  • the present invention first provides a method for fabricating a TFT substrate, including the following steps:
  • Step S1 a substrate 1 is provided, TFTs T arranged in an array are fabricated on the substrate 1, and then a first passivation layer PV1 covering all the TFTs T is deposited.
  • the base substrate 1 is preferably a glass substrate.
  • the TFT T in an array arrangement can be fabricated on the base substrate 1 by using a conventional conventional process, which will not be described here.
  • the TFT T includes a gate electrode, a gate insulating layer, a semiconductor active layer, an interlayer insulating layer, a source and a drain D, and the like, which is the same as the prior art, and will not be described here.
  • the material of the first passivation layer PV1 is silicon nitride (SiNx), silicon oxide (SiOx) or both The combination.
  • Step S2 depositing a color color resist on the first passivation layer PV1 and performing a patterning process to form a color resist layer 41, an island-shaped first color resist block 42 and an island-shaped second color resist block 43, and The height h1 of the first color block 42 is greater than the height h2 of the second color block 43.
  • the color color resist deposited in the step S2 includes a red color resist R, a green color resist G, and a blue color resist B.
  • step S2 the color resist is patterned using a slit diffraction type mask.
  • the slit diffraction type reticle can perform gray scale exposure, so that the light irradiated at the second color resist block 43 is semi-transparent, and the intensity of the light irradiated by the first color resist block 42 is greater than that of the second color resist block 43.
  • the intensity of the light that is illuminated so that the height h1 of the first color block 42 is greater than the height h2 of the second color block 43, but the difference between the two is not large.
  • Step S3 depositing a second passivation layer PV2 on the first passivation layer PV1, the color resist layer 41, the first color resist block 42 and the second color resist block 43.
  • the material of the second passivation layer PV2 is also SiNx, SiOx or a combination of the two.
  • Step S4 applying a BPS technique, depositing a black photoresist on the second passivation layer PV2 and performing a patterning process to form an integrated main photoresist spacer 61, a sub-photoresist spacer 62, and a black matrix 63. And a via hole V penetrating the black matrix 63, the second passivation layer PV2 and the first passivation layer PV1; wherein the main photoresist spacer 61 is correspondingly located above the first color resist block 42, the second time The photoresist spacer 62 is correspondingly located above the second color block 43.
  • the main photoresist spacer 61 is padded by the first color block 42, and the second color block 43 is used.
  • the secondary photoresist spacer 62 is padded, so there is a corresponding difference between the primary photoresist spacer 61 and the secondary photoresist spacer 62, which is the height h1 of the first color resist block 42 and the second color resist block. The difference between the height h2 of 43.
  • the via V is located above the drain D of the TFT T and is completely blocked by the drain D of the TFT T.
  • the purpose of the design is to compensate for the metal shading performance of the drain D of the TFT T.
  • the black matrix 63 has a risk of light leakage due to the opening of the via hole V.
  • Step S5 depositing a transparent conductive film on the integrated main photoresist spacer 61, the sub-resist spacer 62 and the black matrix 63 and performing patterning processing to form the pixel electrode 71 and the common electrode 72, the pixel The electrode 71 is connected to the drain D of the TFT T via the via hole V.
  • the material of the transparent conductive film is preferably Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • a black photoresist is deposited on the second passivation layer PV2 and After performing the patterning process to form the integrated main photoresist spacer 61, the sub-resist spacer 62 and the black matrix 63, the integrated main photoresist spacer 61, the sub-resist spacer 62, and A transparent conductive film is deposited on the black matrix 63 and patterned to form the pixel electrode 71 and the common electrode 72.
  • the integrated main photoresist spacer 61, the sub-resist spacer 62 and the black matrix 63 are filled and covered with black.
  • the space in which the color resistance in the region where the matrix 63 is located is excavated, so that the pixel electrode 71 and the common electrode 72 are formed on the relatively flat black matrix 63, and the conduction due to the steep slope of the color resist edge can be avoided as shown in FIG.
  • the problem of residual film etching prevents the pixel electrode 71 from being short-circuited with the common electrode 72.
  • the via hole V is formed over the drain D of the TFT T, and the risk of light leakage of the black matrix 63 due to the opening of the via hole V can be compensated for by the metal light shielding performance of the drain D of the TFT T.
  • the present invention further provides a TFT substrate structure, including:
  • a color resist layer 41 disposed on the first passivation layer PV1, an island-shaped first color resist block 42 and an island-shaped second color resist block 43, wherein the height h1 of the first color resist block 42 is greater than The height h2 of the dichroic block 43;
  • a second passivation layer PV2 covering the first passivation layer PV1, the color resist layer 41, the first color block 42 and the second color block 43;
  • a pixel electrode 71 disposed on the black matrix 63 and the common electrode 72.
  • the pixel electrode 71 is connected to the TFT via a via V extending through the black matrix 63 and the second passivation layer PV2 and the first passivation layer PV1.
  • the drain D of T is the drain of T.
  • the base substrate 1 is preferably a glass substrate
  • the materials of the first passivation layer PV1 and the second passivation layer PV2 are both SiNx, SiOx or a combination of the two;
  • the color resist layer 41 includes a red color resist R, a green color resist G and a blue color resist B;
  • the material of the pixel electrode 71 and the common electrode 72 is indium tin oxide.
  • the TFT substrate structure of the present invention is provided with an integrated main photoresist spacer 61, a sub-resist spacer 62 and a black matrix 63 on the second passivation layer PV2, a pixel electrode 71 is disposed on the black matrix 63.
  • the common electrode 72 due to the integrated main photoresist spacer 61, the secondary photoresist The spacer 62 and the black matrix 63 are filled to cover the space in which the color resistance in the region where the black matrix 63 is located is excavated, and the pixel electrode 71 and the common electrode 72 are located on the relatively flat black matrix 63, thereby avoiding color due to the process during the process.
  • the problem of residual etching of the conductive film caused by the steep edge of the edge is prevented, and the pixel electrode 71 and the common electrode 72 are prevented from being short-circuited.
  • the via V is disposed above the drain D of the TFT T and is completely blocked by the drain D of the TFT T, and the black matrix 63 can be compensated by the metal shading performance of the drain D of the TFT T. The risk of light leakage due to the opening of the via V.
  • a black photoresist is deposited on the second passivation layer and patterned to form an integrated main photoresist spacer, a sub-resist spacer and a black matrix. Then, a transparent conductive film is deposited on the integrated main photoresist spacer, the sub-resist spacer and the black matrix, and patterned to form a pixel electrode and a common electrode, because of the integrated main photoresist interval.
  • the material, the secondary photoresist spacer and the black matrix are filled, covering the space where the color resistance in the region where the black matrix is located is excavated, so that the pixel electrode and the common electrode are formed on a relatively flat black matrix, which can avoid the slope due to the color resistance edge
  • the problem of residual etching of the conductive film caused by excessive steepness prevents the pixel electrode from being short-circuited with the common electrode.
  • an integrated main photoresist spacer, a sub-resist spacer and a black matrix are disposed on the second passivation layer, and a pixel electrode and a common electrode are disposed on the black matrix
  • the main photoresist spacer, the sub-resistor spacer and the black matrix fill, cover the space where the color resistance in the region where the black matrix is located is excavated, and the pixel electrode and the common electrode are located on a relatively flat black matrix, which can be avoided.
  • the conductive film is left to be etched due to the steep slope of the color resist edge, preventing the pixel electrode from being short-circuited with the common electrode.

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Abstract

一种TFT基板的制作方法及其结构。该TFT基板的制作方法在第二钝化层(PV2)上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物(61)、次光阻间隔物(62)与黑色矩阵(63)之后，再沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极(71)与公共电极(72)，由于一体式的主光阻间隔物(61)、次光阻间隔物(62)与黑色矩阵(63)填充、覆盖了黑色矩阵(63)所在区域内的色阻被挖开的空间，使得像素电极(71)与公共电极(72)形成在较平坦的黑色矩阵(63)上，能够避免由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题，防止像素电极(71)与公共电极(72)短路。

Description

TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及其结构。
背景技术
液晶显示面板(Liquid Crystal Display，LCD)，简称液晶面板，具有机身薄、省电、无辐射等众多优点，得到了广泛地应用，如：液晶电视、智能手机、数字相机、平板电脑、计算机屏幕、或笔记本电脑屏幕等，在平板显示领域中占主导地位。
液晶面板的结构通常是由一彩色滤光片(Color Filter，CF)基板、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate简称TFT基板)、以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
对于传统的液晶面板，在CF基板一侧一般设置有用于滤光的多种颜色的色阻及用于遮光的黑色矩阵(Black Matrix，BM)，在TFT基板与CF基板之间设置有专门的光阻间隔物(Photo Space，PS)以支撑液晶层的盒厚。随着显示技术的发展，出现了一种把BM和PS合二为一的技术(Black Photo Spacer，BPS)。
BPS 1 tone技术是一种最节约成本的BPS技术。BPS 1 tone技术指的是BPS制程使用的光罩只有一种透过率，对应的BPS材料也只感受到一种强度的光，但普通的BPS 1 tone技术需要使用到有机物平坦化(PFA)层，这是因为普通的BPS 1 tone技术使用的是岛状(Island)结构，使用两个色阻块叠起来充当主光阻间隔物(Main PS)、一个色阻块来充当次光阻间隔物(Sub PS)由于两个色阻块和一个色阻块的高度差太大，做出来的主光阻间隔物和次光阻间隔物的断差就会过大，需要有机物平坦化层对两层色块阻堆叠的高度进行一个平坦化作用。
为了节约材料成本，省去有机物平坦化层的BPS型TFT基板被开发出来。请同时参阅图1与图2，省去有机物平坦化层的BPS型TFT基板使用单层的第一岛状色阻块402垫起主光阻间隔物701，亦使用单层的第二岛状色阻块403垫起次光阻间隔物702，只是垫起次光阻间隔物702的第二岛状 色阻块403是用狭缝衍射型(SLT)光罩做灰阶曝光，使得第二岛状色阻块403处照到的是半透光；相应的主光阻间隔物701和次光阻间隔物702的断差即为第一岛状色阻块402的高度h1与第二岛状色阻块403的高度h2之间的差值，而且断差不会很大，所以在色阻层401、第一岛状色阻块402与第二岛状色阻块403上面就可以不用有机物平坦化层，而是使用氮化硅(SiNx)与氧化硅(SiOx)组合的第二钝化层PV2覆盖在色阻层401、第一岛状色阻块402、第二岛状色阻块403及已有的第一钝化层PV1上。制作该BPS型TFT基板时，先在衬底基板10上制作出TFT T及覆盖TFT T的第一钝化层PV1；然后沉积色阻并做图案化处理，形成色阻层401、第一岛状色阻块402与第二岛状色阻块403；接着沉积第二钝化层PV2并做图案化处理；之后沉积导电薄膜并做刻蚀处理，形成像素电极601与公共电极602；最后在第二钝化层PV2、像素电极601与公共电极602上制作出一体式的主光阻间隔物701、次光阻间隔物702及黑色矩阵703。
结合图3与图4，这种新架构的BPS型TFT基板存在一个问题：由于黑色矩阵703所在区域内的色阻都被挖开，色阻边缘会形成一个斜坡，若斜坡的陡度太大，那么在做完第二钝化层PV2，再做导电薄膜时，斜坡的存在会导致导电薄膜刻蚀不干净产生残留，而残留的导电薄膜会造成像素电极601与公共电极602短路。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能够避免由于色阻边缘斜坡过陡导致的导电薄膜残留的问题，防止像素电极与公共电极短路。
本发明的目的还在于提供一种TFT基板结构，能够防止像素电极与公共电极短路。
为实现上述目的，本发明首先提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供衬底基板，在所述衬底基板上制作出呈阵列式排布的TFT，然后沉积一层覆盖所有TFT的第一钝化层；
步骤S2、在所述第一钝化层上沉积彩色色阻并进行图案化处理，形成色阻层、第一色阻块与第二色阻块，且第一色阻块的高度大于第二色阻块的高度；
步骤S3、在所述第一钝化层、色阻层、第一色阻块与第二色阻块上沉积覆盖第二钝化层；
步骤S4、在所述第二钝化层上沉积覆盖黑色光阻并进行图案化处理， 形成一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，以及一贯穿所述黑色矩阵、第二钝化层与第一钝化层的过孔；其中，所述主光阻间隔物对应位于第一色阻块上方，所述次光阻间隔物对应位于第二色阻块上方；所述过孔被TFT的漏极完全遮挡；
步骤S5、在所述一体式的主光阻间隔物、次光阻间隔物及黑色矩阵上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极与公共电极，所述像素电极经由所述过孔连接TFT的漏极。
所述步骤S2使用狭缝衍射型光罩对彩色色阻进行图案化处理。
所述步骤S2沉积的彩色色阻包括红色色阻、绿色色阻与蓝色色阻。
所述透明导电薄膜的材料为氧化铟锡。
所述第一钝化层与第二钝化层的材料均为氮化硅、氧化硅或二者的组合。
所述第一色阻块与第二色阻块均呈岛状。
本发明还提供一种TFT基板结构，包括：
衬底基板；
设在所述衬底基板上呈阵列式排布的TFT；
覆盖所有TFT的第一钝化层；
设在所述第一钝化层上的色阻层、第一色阻块与第二色阻块，其中，第一色阻块的高度大于第二色阻块的高度；
覆盖所述第一钝化层、色阻层、第一色阻块与第二色阻块的第二钝化层；
设在所述第二钝化层上的一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，其中，所述主光阻间隔物对应位于第一色阻块上方，所述次光阻间隔物对应位于第二色阻块上方；
以及设在所述黑色矩阵上的像素电极与公共电极，所述像素电极经由贯穿所述黑色矩阵、第二钝化层与第一钝化层的过孔连接TFT的漏极；
所述过孔被TFT的漏极完全遮挡。
所述色阻层包括红色色阻、绿色色阻与蓝色色阻；所述第一色阻块与第二色阻块均呈岛状。
所述像素电极71与公共电极72的材料为氧化铟锡。
所述第一钝化层与第二钝化层的材料均为氮化硅、氧化硅或二者的组合。
本发明还提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供衬底基板，在所述衬底基板上制作出呈阵列式排布的TFT， 然后沉积一层覆盖所有TFT的第一钝化层；
步骤S2、在所述第一钝化层上沉积彩色色阻并进行图案化处理，形成色阻层、第一色阻块与第二色阻块，且第一色阻块的高度大于第二色阻块的高度；
步骤S3、在所述第一钝化层、色阻层、第一色阻块与第二色阻块上沉积覆盖第二钝化层；
步骤S4、在所述第二钝化层上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，以及一贯穿所述黑色矩阵、第二钝化层与第一钝化层的过孔；其中，所述主光阻间隔物对应位于第一色阻块上方，所述次光阻间隔物对应位于第二色阻块上方；所述过孔被TFT的漏极完全遮挡；
步骤S5、在所述一体式的主光阻间隔物、次光阻间隔物及黑色矩阵上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极与公共电极，所述像素电极经由所述过孔连接TFT的漏极；
其中，所述步骤S2使用狭缝衍射型光罩对彩色色阻进行图案化处理；
其中，所述步骤S2沉积的彩色色阻包括红色色阻、绿色色阻与蓝色色阻；
其中，所述透明导电薄膜的材料为氧化铟锡；
其中，所述第一钝化层与第二钝化层的材料均为氮化硅、氧化硅或二者的组合；
其中，所述第一色阻块与第二色阻块均呈岛状。
本发明的有益效果：本发明提供的TFT基板的制作方法，在第二钝化层上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物、次光阻间隔物与黑色矩阵之后，再在所述一体式的主光阻间隔物、次光阻间隔物及黑色矩阵上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极与公共电极，由于一体式的主光阻间隔物、次光阻间隔物与黑色矩阵填充、覆盖了黑色矩阵所在区域内的色阻被挖开的空间，使得像素电极与公共电极形成在较平坦的黑色矩阵上，能够避免由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题，防止像素电极与公共电极短路。本发明提供的TFT基板结构，在所述第二钝化层上设置一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，在所述黑色矩阵上设置像素电极与公共电极，由于一体式的主光阻间隔物、次光阻间隔物与黑色矩阵填充、覆盖了黑色矩阵所在区域内的色阻被挖开的空间，像素电极与公共电极位于较平坦的黑色矩阵上，能够避免在制程过程中由于色阻边缘斜坡过陡导致的导电薄膜 蚀刻残留的问题，防止像素电极与公共电极短路。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的省去有机物平坦化层的BPS型TFT基板的俯视示意图；
图2为对应于图1中A-A处的剖面示意图；
图3为显示现有的省去有机物平坦化层的BPS型TFT基板会出现像素电极与公共电极短路的俯视示意图；
图4为显示现有的省去有机物平坦化层的BPS型TFT基板容易产生导电薄膜蚀刻残留的剖面示意图；
图5为本发明的TFT基板的制作方法的流程图；
图6为显示本发明的TFT基板中色阻层、第一色阻块与第二色阻块的俯视示意图；
图7为发明的TFT基板在图6所示B-B处的剖面示意图；
图8为显示本发明的TFT基板能够避免产生导电薄膜蚀刻残留的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图5，结合图6与图7，本发明首先提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供衬底基板1，在所述衬底基板1上制作出呈阵列式排布的TFT T，然后沉积一层覆盖所有TFT T的第一钝化层PV1。
具体地：
所述衬底基板1优选玻璃基板。
采用现有的常规制程即可在所述衬底基板1上制作出呈阵列式排布的TFT T，此处不做展开描述。所述TFT T包括有栅极、栅极绝缘层、半导体有源层、层间绝缘层、源极与漏极D等，这与现有技术无异，此处不做展开叙述。
所述第一钝化层PV1的材料为氮化硅(SiNx)、氧化硅(SiOx)或二者 的组合。
步骤S2、在所述第一钝化层PV1上沉积彩色色阻并进行图案化处理，形成色阻层41、岛状的第一色阻块42与岛状的第二色阻块43，且第一色阻块42的高度h1大于第二色阻块43的高度h2。
具体地：
该步骤S2中所沉积的彩色色阻包括红色色阻R、绿色色阻G与蓝色色阻B。
该步骤S2使用狭缝衍射型光罩对彩色色阻进行图案化处理。狭缝衍射型光罩能够进行灰阶曝光，使得第二色阻块43处照到的光是半透光，第一色阻块42处照到的光的强度大于第二色阻块43处照到的光的强度，从而第一色阻块42的高度h1大于第二色阻块43的高度h2，但二者之间的差值不会很大。
步骤S3、在所述第一钝化层PV1、色阻层41、第一色阻块42与第二色阻块43上沉积覆盖第二钝化层PV2。
具体地：所述第二钝化层PV2的材料亦为SiNx、SiOx或二者的组合。
步骤S4、应用BPS技术，在所述第二钝化层PV2上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物61、次光阻间隔物62与黑色矩阵63，以及一贯穿所述黑色矩阵63、第二钝化层PV2与第一钝化层PV1的过孔V；其中，所述主光阻间隔物61对应位于第一色阻块42上方，所述次光阻间隔物62对应位于第二色阻块43上方。
因为前述步骤S2中形成的第一色阻块42的高度h1大于第二色阻块43的高度h2，由第一色阻块42垫起主光阻间隔物61，由第二色阻块43垫起次光阻间隔物62，所以主光阻间隔物61和次光阻间隔物62之间相应存在断差，该断差即为第一色阻块42的高度h1与第二色阻块43的高度h2之间的差值。
值得一提的是，所述过孔V位于TFT T的漏极D上方而被TFT T的漏极D完全遮挡，这样设计的目的是利用TFT T的漏极D的金属遮光性能来弥补所述黑色矩阵63由于开设过孔V而存在的漏光风险。
步骤S5、在所述一体式的主光阻间隔物61、次光阻间隔物62及黑色矩阵63上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极71与公共电极72，所述像素电极71经由所述过孔V连接TFT T的漏极D。
具体地，所述透明导电薄膜的材料优选氧化铟锡(Indium Tin Oxide，ITO)。
上述TFT基板的制作方法，在第二钝化层PV2上沉积覆盖黑色光阻并 进行图案化处理，形成一体式的主光阻间隔物61、次光阻间隔物62与黑色矩阵63之后，再在所述一体式的主光阻间隔物61、次光阻间隔物62、及黑色矩阵63上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极71与公共电极72，由于一体式的主光阻间隔物61、次光阻间隔物62与黑色矩阵63填充、覆盖了黑色矩阵63所在区域内的色阻被挖开的空间，使得像素电极71与公共电极72形成在较平坦的黑色矩阵63上，能够如图8所示那样避免由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题，防止像素电极71与公共电极72短路。此外，将所述过孔V制作于TFT T的漏极D上方，能够利用TFT T的漏极D的金属遮光性能来弥补所述黑色矩阵63由于开设过孔V而存在的漏光风险。
请同时参阅图6至图8，本发明还提供一种TFT基板结构，包括：
衬底基板1；
设在所述衬底基板1上呈阵列式排布的TFT T；
覆盖所有TFT T的第一钝化层PV1；
设在所述第一钝化层PV1上的色阻层41、岛状的第一色阻块42与岛状的第二色阻块43，其中，第一色阻块42的高度h1大于第二色阻块43的高度h2；
覆盖所述第一钝化层PV1、色阻层41、第一色阻块42与第二色阻块43的第二钝化层PV2；
设在所述第二钝化层PV2上的一体式的主光阻间隔物61、次光阻间隔物62与黑色矩阵63，其中，所述主光阻间隔物61对应位于第一色阻块42上方，所述次光阻间隔物62对应位于第二色阻块43上方；
以及设在所述黑色矩阵63上的像素电极71与公共电极72，所述像素电极71经由贯穿所述黑色矩阵63、第二钝化层PV2与第一钝化层PV1的过孔V连接TFT T的漏极D。
具体地：
所述衬底基板1优选玻璃基板；
所述第一钝化层PV1与第二钝化层PV2的材料均为SiNx、SiOx或二者的组合；
所述色阻层41包括红色色阻R、绿色色阻G与蓝色色阻B；
所述像素电极71与公共电极72的材料为氧化铟锡。
由于本发明的TFT基板结构在所述第二钝化层PV2上设置一体式的主光阻间隔物61、次光阻间隔物62与黑色矩阵63，在所述黑色矩阵63上设置像素电极71与公共电极72，由于一体式的主光阻间隔物61、次光阻间 隔物62与黑色矩阵63填充、覆盖了黑色矩阵63所在区域内的色阻被挖开的空间，像素电极71与公共电极72位于较平坦的黑色矩阵63上，能够避免在制程过程中由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题，防止像素电极71与公共电极72短路。
值得一提的是：所述过孔V设于TFT T的漏极D上方并被TFT T的漏极D完全遮挡，能够利用TFT T的漏极D的金属遮光性能来弥补所述黑色矩阵63由于开设过孔V而存在的漏光风险。
综上所述，本发明的TFT基板的制作方法，在第二钝化层上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物、次光阻间隔物与黑色矩阵之后，再在所述一体式的主光阻间隔物、次光阻间隔物及黑色矩阵上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极与公共电极，由于一体式的主光阻间隔物、次光阻间隔物与黑色矩阵填充、覆盖了黑色矩阵所在区域内的色阻被挖开的空间，使得像素电极与公共电极形成在较平坦的黑色矩阵上，能够避免由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题，防止像素电极与公共电极短路。本发明的TFT基板结构，在所述第二钝化层上设置一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，在所述黑色矩阵上设置像素电极与公共电极，由于一体式的主光阻间隔物、次光阻间隔物与黑色矩阵填充、覆盖了黑色矩阵所在区域内的色阻被挖开的空间，像素电极与公共电极位于较平坦的黑色矩阵上，能够避免在制程过程中由于色阻边缘斜坡过陡导致的导电薄膜蚀刻残留的问题，防止像素电极与公共电极短路。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (11)

  1. 一种TFT基板的制作方法，包括以下步骤：
    步骤S1、提供衬底基板，在所述衬底基板上制作出呈阵列式排布的TFT，然后沉积一层覆盖所有TFT的第一钝化层；
    步骤S2、在所述第一钝化层上沉积彩色色阻并进行图案化处理，形成色阻层、第一色阻块与第二色阻块，且第一色阻块的高度大于第二色阻块的高度；
    步骤S3、在所述第一钝化层、色阻层、第一色阻块与第二色阻块上沉积覆盖第二钝化层；
    步骤S4、在所述第二钝化层上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，以及一贯穿所述黑色矩阵、第二钝化层与第一钝化层的过孔；其中，所述主光阻间隔物对应位于第一色阻块上方，所述次光阻间隔物对应位于第二色阻块上方；所述过孔被TFT的漏极完全遮挡；
    步骤S5、在所述一体式的主光阻间隔物、次光阻间隔物及黑色矩阵上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极与公共电极，所述像素电极经由所述过孔连接TFT的漏极。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S2使用狭缝衍射型光罩对彩色色阻进行图案化处理。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S2沉积的彩色色阻包括红色色阻、绿色色阻与蓝色色阻。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述透明导电薄膜的材料为氧化铟锡。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述第一钝化层与第二钝化层的材料均为氮化硅、氧化硅或二者的组合。
  6. 如权利要求1所述的TFT基板的制作方法，其中，所述第一色阻块与第二色阻块均呈岛状。
  7. 一种TFT基板结构，包括：
    衬底基板；
    设在所述衬底基板上呈阵列式排布的TFT；
    覆盖所有TFT的第一钝化层；
    设在所述第一钝化层上的色阻层、第一色阻块与第二色阻块，其中， 第一色阻块的高度大于第二色阻块的高度；
    覆盖所述第一钝化层、色阻层、第一色阻块与第二色阻块的第二钝化层；
    设在所述第二钝化层上的一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，其中，所述主光阻间隔物对应位于第一色阻块上方，所述次光阻间隔物对应位于第二色阻块上方；
    以及设在所述黑色矩阵上的像素电极与公共电极，所述像素电极经由贯穿所述黑色矩阵、第二钝化层与第一钝化层的过孔连接TFT的漏极；
    所述过孔被TFT的漏极完全遮挡。
  8. 如权利要求7所述的TFT基板结构，其中，所述色阻层包括红色色阻、绿色色阻与蓝色色阻；所述第一色阻块与第二色阻块均呈岛状。
  9. 如权利要求7所述的TFT基板结构，其中，所述像素电极与公共电极的材料为氧化铟锡。
  10. 如权利要求7所述的TFT基板结构，其中，所述第一钝化层与第二钝化层的材料均为氮化硅、氧化硅或二者的组合。
  11. 一种TFT基板的制作方法，包括以下步骤：
    步骤S1、提供衬底基板，在所述衬底基板上制作出呈阵列式排布的TFT，然后沉积一层覆盖所有TFT的第一钝化层；
    步骤S2、在所述第一钝化层上沉积彩色色阻并进行图案化处理，形成色阻层、第一色阻块与第二色阻块，且第一色阻块的高度大于第二色阻块的高度；
    步骤S3、在所述第一钝化层、色阻层、第一色阻块与第二色阻块上沉积覆盖第二钝化层；
    步骤S4、在所述第二钝化层上沉积覆盖黑色光阻并进行图案化处理，形成一体式的主光阻间隔物、次光阻间隔物与黑色矩阵，以及一贯穿所述黑色矩阵、第二钝化层与第一钝化层的过孔；其中，所述主光阻间隔物对应位于第一色阻块上方，所述次光阻间隔物对应位于第二色阻块上方；所述过孔被TFT的漏极完全遮挡；
    步骤S5、在所述一体式的主光阻间隔物、次光阻间隔物及黑色矩阵上沉积覆盖透明导电薄膜并进行图案化处理，形成像素电极与公共电极，所述像素电极经由所述过孔连接TFT的漏极；
    其中，所述步骤S2使用狭缝衍射型光罩对彩色色阻进行图案化处理；
    其中，所述步骤S2沉积的彩色色阻包括红色色阻、绿色色阻与蓝色色阻；
    其中，所述透明导电薄膜的材料为氧化铟锡；
    其中，所述第一钝化层与第二钝化层的材料均为氮化硅、氧化硅或二者的组合；
    其中，所述第一色阻块与第二色阻块均呈岛状。
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EP3690927A4 (en) 2021-06-16
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JP2020533626A (ja) 2020-11-19
EP3690927B1 (en) 2022-08-03
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