WO2019061214A1 - Transistor device with integrated diode - Google Patents

Transistor device with integrated diode Download PDF

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Publication number
WO2019061214A1
WO2019061214A1 PCT/CN2017/104179 CN2017104179W WO2019061214A1 WO 2019061214 A1 WO2019061214 A1 WO 2019061214A1 CN 2017104179 W CN2017104179 W CN 2017104179W WO 2019061214 A1 WO2019061214 A1 WO 2019061214A1
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Prior art keywords
region
transistor
gate
diode
transistor device
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PCT/CN2017/104179
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French (fr)
Chinese (zh)
Inventor
魏进
金峻渊
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英诺赛科(珠海)科技有限公司
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Publication of WO2019061214A1 publication Critical patent/WO2019061214A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Definitions

  • the present invention relates to the field of semiconductor devices, and more particularly to a transistor device having an integrated diode.
  • a freewheeling diode needs to be connected in parallel to the switching device. If the device itself has reverse-conduction capability, the reverse-conduction diode of the device itself can be used instead of the freewheeling diode, which reduces the number of components, reduces the cost, and reduces the parasitic capacitance of the system.
  • Transistor, GaN HEMT devices do not have body diodes.
  • the off state if a negative voltage is applied to the drain 100, the relative voltage between the gate 105 and the drain 100 is greater than the threshold voltage of the device. Then the channel of the device is turned on and the device is reversed.
  • the reverse conducting voltage of the device is related to the threshold voltage of the device. If the threshold voltage of the device is large, the reverse conducting voltage of the device is large. For an enhanced power-off device, it is often desirable to have a higher threshold voltage (greater than IV) and a lower reverse-conduction voltage. On the other hand, in many applications, it is necessary to apply a negative voltage to the gate to turn off. If the gate voltage is negative, the reverse conducting voltage of the device is further increased.
  • the present invention provides a transistor device having an integrated diode including a diode region, a transistor region and an isolation region, the diode region having a plurality of anodes, the transistor region having a gate, a drain and a plurality of a source, the plurality of sources are arranged along a length parallel to the drain, the drain and the source are divided Don't be located on both sides of the gate.
  • the source is electrically connected to the anode and is used as the source of the transistor device.
  • the isolation region is located between the diode region and the transistor region. The diode region and the transistor region are electrically isolated through the isolation region.
  • a preferred solution is that the first end of the isolation region extends to a side of the gate adjacent to the drain, and the second end of the isolation region extends to a side of the source remote from the drain.
  • a preferred solution is that the first end of the isolation region extends to a region between the gate and the drain, and the second end of the isolation region extends to a side of the source away from the drain.
  • the diode region has at least two anodes, and the transistor region has at least two sources
  • a preferred solution is that the anode and the source are alternately arranged, and the adjacent anode and the gate are electrically isolated by the isolation region.
  • a preferred solution is to use the anode of the heterojunction Schottky diode or the anode of the trench Schottky diode as the anode of the diode region.
  • a preferred solution is that the source of the field effect transistor is electrically connected to the gate of the field effect transistor and serves as the anode of the diode region.
  • the gate is a junction gate or a metal dielectric gate or a trench gate or a fluoride ion treated gate.
  • the gate voltage of the transistor device of the present invention is greater than the threshold voltage ⁇ , if a forward voltage is applied to the drain, the transistor device is turned on through the transistor region. If a negative voltage is applied to the drain, the diode region is turned on first and the current is not turned off by the gate of the transistor region, so the reverse conducting voltage of the transistor device is not limited by the threshold voltage of the transistor device. When a negative voltage is applied to the gate to turn off the transistor device, the reverse conducting voltage is also not limited by the gate negative voltage. In addition, the diode region and the transistor region share an access region between the gate and the drain, thereby reducing the forward conduction resistance and reverse conduction resistance of the transistor device.
  • FIG. 1 is a schematic structural view of a conventional gallium nitride high electron mobility transistor.
  • FIG. 2 is a schematic structural view of an embodiment of a transistor device of the present invention.
  • FIG. 3 is a cross-sectional view taken along line A-A of FIG. 2.
  • FIG. 4 is a cross-sectional view taken along line B-B of FIG. 2.
  • FIG. 5 is a schematic diagram showing the current flow inside the transistor device after the gate voltage of the transistor device embodiment of the present invention is greater than the threshold voltage ⁇ after the forward voltage is applied to the drain.
  • FIG. 6 is a transistor device embodiment of the present invention, when the transistor device is turned off, after a negative voltage is applied to the drain.
  • the gallium nitride high electron mobility transistor (GaN HEMT) device of the present embodiment includes a diode region, a transistor region, and an isolation region 16, the diode region has a plurality of anodes 11, and the transistor region has a gate electrode 15 a drain 10 and a plurality of sources 12, a plurality of sources 12 are arranged along a length direction parallel to the drain 10, and a drain 10 and a source 12 are respectively located on both sides of the gate 15, the source 12 and the anode 11 is electrically connected as a source of the transistor device of the present invention having an integrated diode, and the gate 15 serves as the gate of the transistor device of the present invention, and the drain 10 serves as the drain of the transistor device of the present invention.
  • GaN HEMT gallium nitride high electron mobility transistor
  • the isolation region 16 is located between the diode region and the transistor region, and the diode region and the transistor region are electrically isolated by the isolation region 16. When a voltage ⁇ less than the threshold voltage is applied to the gate 15, the channel region of the diode region from the anode 11 to the drain 10 of the transistor device remains conductive.
  • the first end of the isolation region 16 extends to a region between the gate 15 and the drain 10, and does not extend to the drain 10, that is, a distance between the first end of the isolation region 16 and the drain 10.
  • the second end of isolation region 16 extends to the side of source region 12 of the transistor region that is remote from the drain.
  • the first end of the isolation region 16 may also extend only to the side of the gate 15 close to the drain.
  • the anode 11 of the diode region is alternately arranged with the source 12 of the transistor region and arranged along the length direction parallel to the drain 10, and the adjacent two anodes 11 and 12 are electrically isolated by the isolation region 16.
  • the isolation region 16 can eliminate the formation of conductive channels in the region by ion implantation or etching.
  • the transistor device of the present invention is an enhanced power switching device which is an epitaxial multilayer structure fabricated on a substrate 121, including a substrate 121 and on a substrate 121.
  • a transition layer 122, a channel layer 123, a barrier layer 124, and a dielectric layer 125, which are sequentially grown from bottom to top, a source 12 and a drain 10 of the transistor region, and an anode 11 of the diode region are formed over the barrier layer 124 and are located
  • the barrier layer 124 is between the dielectric layer 125 and the dielectric layer 125.
  • a P-type gallium nitride layer 13 (p-GaN) is further formed between the barrier layer 124 and the dielectric layer 125.
  • the gate 15 of the transistor region is formed over the P-type gallium nitride layer 13, and the dielectric layer 125 is P-type.
  • a gate metal contact hole 14 is provided above the gallium nitride layer 13, and the gate electrode 15 has a downward extending portion which passes through the gate metal contact hole 14 and is connected to the P-type gallium nitride layer 13.
  • FIG. 3 is a schematic structural view of a diode region in a transistor device.
  • the anode 11 of the diode in this embodiment is an anode of a heterojunction Schottky diode.
  • the diode anode 11 can also adopt the anode of the trench type Schottky diode, and the source of the field effect transistor can be electrically connected to the gate of the field effect transistor as the anode 11 of the diode region, or other Diode anode structure.
  • FIG. 4 is a schematic structural diagram of a transistor region in a transistor device.
  • the gate 15 of the transistor region in this embodiment adopts a junction gate structure.
  • the gate 15 of the transistor region can also be processed by a metal dielectric gate (MIS gate) or a trench gate or fluoride ion. Over the gate or other gate structure.
  • MIS gate metal dielectric gate
  • a trench gate or fluoride ion Over the gate or other gate structure.
  • the reverse conducting voltage of the transistor device is not limited by the threshold voltage of the transistor device and is not limited by the negative voltage of the gate 15.
  • the diode region has at least two anodes 11 and the transistor region has at least two sources 12, the plurality of sources 12 being arranged along a length direction parallel to the drain 10, the specific number of anodes 11 and sources 12 Depending on the desired current level, the higher the current level, the greater the number of anodes 11 and sources 12.
  • the gate voltage of the transistor device with integrated diode of the present invention is greater than the threshold voltage ⁇
  • the transistor device if a forward voltage is applied to the drain, the transistor device is turned on through the transistor region. If a negative voltage is applied to the drain, the diode region is turned on first, and the current is not turned off by the gate of the transistor region, so the transistor
  • the reverse conducting voltage of the device is not limited by the threshold voltage of the transistor device, so the reverse conducting voltage of the transistor device can be designed independently of the threshold voltage. And even if a negative voltage is applied to the gate of the transistor device to turn off, the reverse conducting voltage of the transistor device is not affected.
  • the diode region and the transistor region share an access region between the gate and the drain, thereby reducing the forward conduction resistance and the reverse conduction resistance of the transistor device.
  • the transistor device of the present invention adopts a structure in which an anode and a source are alternately arranged and electrically isolated by an isolation region, so that a diode region and a transistor region share an access region between a gate and a drain, so that the transistor device is reversed.
  • the conduction voltage is not only limited by the threshold voltage, but also is not affected by the negative voltage applied to the gate.
  • the forward conduction resistance and the reverse conduction resistance of the transistor device are reduced, and the enhanced power device is improved. Performance, with good industrial applicability.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A transistor device with an integrated diode. The transistor device comprises a diode region, a transistor region and an isolation region (16), wherein there are multiple anodes (11) in the diode region; there is one gate electrode (15), one drain electrode (10) and multiple source electrodes (12) in the transistor region; the multiple source electrodes (12) are arranged along a length direction parallel to the drain electrode (10); the drain electrode (10) and the source electrodes (12) are respectively located on two sides of the gate electrode (15); the source electrodes (12) are electrically connected to the anodes (11) to serve as source electrodes of the transistor device; and the isolation region (16) is located between the diode region and the transistor region, and the diode region and the transistor region are electrically isolated by means of the isolation region (16).

Description

发明名称:具有集成二极管的晶体管器件  Title of Invention: Transistor Device with Integrated Diode
技术领域  Technical field
[0001] 本发明涉及半导体器件领域, 具体地说, 是涉及一种具有集成二极管的晶体管 器件。  [0001] The present invention relates to the field of semiconductor devices, and more particularly to a transistor device having an integrated diode.
背景技术  Background technique
[0002] 在功率幵关系统中, 经常需要为感性负载提供一个续流通道。 以电机驱动电路 为例, 需要在幵关器件上反向并联一个续流二极管。 如果幵关器件本身具有反 向导通能力, 则可以使用幵关器件本身的反向导通来替代续流二极管, 从而减 少器件数量, 降低成本, 并且可以减小系统的寄生电容。  [0002] In power-critical systems, it is often desirable to provide a freewheeling path for inductive loads. Taking the motor drive circuit as an example, a freewheeling diode needs to be connected in parallel to the switching device. If the device itself has reverse-conduction capability, the reverse-conduction diode of the device itself can be used instead of the freewheeling diode, which reduces the number of components, reduces the cost, and reduces the parasitic capacitance of the system.
[0003] 参见图 1, 传统的氮化镓高电子迁移率晶体管 (GaN High Electron Mobility [0003] See Figure 1, a conventional gallium nitride high electron mobility transistor (GaN High Electron Mobility)
Transistor, GaN HEMT) 器件不具有体二极管, 传统的 GaN ΗΕΜΤ器件在关断状 态下, 若对漏极 100施加一个负电压使得栅极 105与漏极 100之间的相对电压大于 器件的阈值电压, 则器件的沟道幵启, 器件反向导通。 然而器件的反向导通电 压与器件的阈值电压相关联, 若器件的阈值电压较大, 则器件的反向导通电压 较大。 对于一个增强型功率幵关器件, 通常希望器件的阈值电压较大 (大于 IV ) , 并且器件的反向导通电压较小。 另一方面, 在很多应用中, 需要对栅极施 加一个负电压进行关断, 如果栅极电压为负, 则器件的反向导通电压进一步增 大。 Transistor, GaN HEMT) devices do not have body diodes. In the off state, if a negative voltage is applied to the drain 100, the relative voltage between the gate 105 and the drain 100 is greater than the threshold voltage of the device. Then the channel of the device is turned on and the device is reversed. However, the reverse conducting voltage of the device is related to the threshold voltage of the device. If the threshold voltage of the device is large, the reverse conducting voltage of the device is large. For an enhanced power-off device, it is often desirable to have a higher threshold voltage (greater than IV) and a lower reverse-conduction voltage. On the other hand, in many applications, it is necessary to apply a negative voltage to the gate to turn off. If the gate voltage is negative, the reverse conducting voltage of the device is further increased.
技术问题  technical problem
[0004] 本发明的目的是提供一种具有集成二极管的晶体管器件, 该晶体管器件的反向 导通电压可以独立进行设计而不受阈值电压影响, 并且即使对晶体管器件的栅 极施加负电压进行关断, 也不会影响晶体管器件的反向导通电压。  [0004] It is an object of the present invention to provide a transistor device having an integrated diode whose reverse conducting voltage can be independently designed without being affected by a threshold voltage, and even if a negative voltage is applied to the gate of the transistor device It does not affect the reverse conducting voltage of the transistor device.
[0005] 技术解决手段  [0005] Technical solutions
[0006] 为实现上述目的, 本发明提供一种具有集成二极管的晶体管器件, 包括二极管 区、 晶体管区和隔离区, 二极管区具有多个阳极, 晶体管区具有一个栅极、 一 个漏极和多个源极, 多个源极沿着平行于漏极的长度方向布置, 漏极和源极分 别位于栅极的两侧, 源极与阳极电连接后整体作为晶体管器件的源极; 隔离区 位于二极管区与晶体管区之间, 二极管区与晶体管区通过隔离区进行电学隔离 To achieve the above object, the present invention provides a transistor device having an integrated diode including a diode region, a transistor region and an isolation region, the diode region having a plurality of anodes, the transistor region having a gate, a drain and a plurality of a source, the plurality of sources are arranged along a length parallel to the drain, the drain and the source are divided Don't be located on both sides of the gate. The source is electrically connected to the anode and is used as the source of the transistor device. The isolation region is located between the diode region and the transistor region. The diode region and the transistor region are electrically isolated through the isolation region.
[0007] 一个优选的方案是, 隔离区的第一端延伸至栅极靠近漏极的一侧, 隔离区的第 二端延伸至源极远离漏极的一侧。 [0007] A preferred solution is that the first end of the isolation region extends to a side of the gate adjacent to the drain, and the second end of the isolation region extends to a side of the source remote from the drain.
[0008] 一个优选的方案是, 隔离区的第一端延伸至栅极与漏极之间的区域, 隔离区的 第二端延伸至源极远离漏极的一侧。 [0008] A preferred solution is that the first end of the isolation region extends to a region between the gate and the drain, and the second end of the isolation region extends to a side of the source away from the drain.
[0009] 一个优选的方案是, 二极管区具有至少两个阳极, 晶体管区具有至少两个源极 [0009] A preferred solution is that the diode region has at least two anodes, and the transistor region has at least two sources
[0010] 一个优选的方案是, 阳极与源极交替排列, 相邻的阳极与栅极通过隔离区进行 电学隔离。 [0010] A preferred solution is that the anode and the source are alternately arranged, and the adjacent anode and the gate are electrically isolated by the isolation region.
[0011] 一个优选的方案是, 异质结肖特基二极管的阳极或沟槽型肖特基二极管的阳极 作为二极管区的阳极。  [0011] A preferred solution is to use the anode of the heterojunction Schottky diode or the anode of the trench Schottky diode as the anode of the diode region.
[0012] 一个优选的方案是, 场效应晶体管的源极与该场效应晶体管的栅极电连接后作 为二极管区的阳极。  [0012] A preferred solution is that the source of the field effect transistor is electrically connected to the gate of the field effect transistor and serves as the anode of the diode region.
[0013] 一个优选的方案是, 栅极为结型栅或金属介质栅或沟槽栅或氟离子处理过的栅 极。  [0013] A preferred solution is that the gate is a junction gate or a metal dielectric gate or a trench gate or a fluoride ion treated gate.
问题的解决方案  Problem solution
发明的有益效果  Advantageous effects of the invention
有益效果  Beneficial effect
[0014] 当本发明的晶体管器件的栅极电压大于阈值电压吋, 若在漏极施加正向电压, 则晶体管器件通过晶体管区导通。 若在漏极施加负电压, 则二极管区域先导通 , 电流不会被晶体管区的栅极关断, 所以晶体管器件的反向导通电压不受晶体 管器件阈值电压的制约。 当在栅极施加负电压关断晶体管器件吋, 反向导通电 压也不会受到栅极负电压的制约。 另外, 二极管区与晶体管区共享栅极与漏极 之间的接入区, 从而减小了晶体管器件的正向导通电阻与反向导通电阻。  [0014] When the gate voltage of the transistor device of the present invention is greater than the threshold voltage 吋, if a forward voltage is applied to the drain, the transistor device is turned on through the transistor region. If a negative voltage is applied to the drain, the diode region is turned on first and the current is not turned off by the gate of the transistor region, so the reverse conducting voltage of the transistor device is not limited by the threshold voltage of the transistor device. When a negative voltage is applied to the gate to turn off the transistor device, the reverse conducting voltage is also not limited by the gate negative voltage. In addition, the diode region and the transistor region share an access region between the gate and the drain, thereby reducing the forward conduction resistance and reverse conduction resistance of the transistor device.
对附图的简要说明 附图说明 Brief description of the drawing DRAWINGS
[0015] 图 1是现有的氮化镓高电子迁移率晶体管的结构示意图。  1 is a schematic structural view of a conventional gallium nitride high electron mobility transistor.
[0016] 图 2是本发明晶体管器件实施例的结构示意图。 2 is a schematic structural view of an embodiment of a transistor device of the present invention.
[0017] 图 3是图 2中 A-A处的截面图。 3 is a cross-sectional view taken along line A-A of FIG. 2.
[0018] 图 4是图 2中 B-B处的截面图。 4 is a cross-sectional view taken along line B-B of FIG. 2.
[0019] 图 5是本发明晶体管器件实施例的栅极电压大于阈值电压吋, 在漏极施加正向 电压后, 晶体管器件内部电流流向示意图。  5 is a schematic diagram showing the current flow inside the transistor device after the gate voltage of the transistor device embodiment of the present invention is greater than the threshold voltage 吋 after the forward voltage is applied to the drain.
[0020] 图 6是本发明晶体管器件实施例中当晶体管器件关断吋, 在漏极施加负电压后6 is a transistor device embodiment of the present invention, when the transistor device is turned off, after a negative voltage is applied to the drain. [0020] FIG.
, 晶体管器件内部电流流向示意图。 , a schematic diagram of the current flow inside the transistor device.
[0021] 以下结合附图及实施例对本发明作进一步说明。 [0021] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
本发明的实施方式 Embodiments of the invention
[0022] 参见图 2, 本实施例的氮化镓高电子迁移率晶体管 (GaN HEMT) 器件包括二 极管区、 晶体管区和隔离区 16, 二极管区具有多个阳极 11, 晶体管区具有一个 栅极 15、 一个漏极 10和多个源极 12, 多个源极 12沿着平行于漏极 10的长度方向 布置, 漏极 10和源极 12分别位于栅极 15的两侧, 源极 12与阳极 11电连接后整体 作为本发明具有集成二极管的晶体管器件的源极, 并且栅极 15作为本发明晶体 管器件的栅极, 漏极 10作为本发明晶体管器件的漏极。 隔离区 16位于二极管区 与晶体管区之间, 二极管区与晶体管区通过隔离区 16进行电学隔离。 当向栅极 1 5施加一个小于阈值电压的电压吋, 二极管区从阳极 11到晶体管器件的漏极 10之 间的沟道保持导通状态。  [0022] Referring to FIG. 2, the gallium nitride high electron mobility transistor (GaN HEMT) device of the present embodiment includes a diode region, a transistor region, and an isolation region 16, the diode region has a plurality of anodes 11, and the transistor region has a gate electrode 15 a drain 10 and a plurality of sources 12, a plurality of sources 12 are arranged along a length direction parallel to the drain 10, and a drain 10 and a source 12 are respectively located on both sides of the gate 15, the source 12 and the anode 11 is electrically connected as a source of the transistor device of the present invention having an integrated diode, and the gate 15 serves as the gate of the transistor device of the present invention, and the drain 10 serves as the drain of the transistor device of the present invention. The isolation region 16 is located between the diode region and the transistor region, and the diode region and the transistor region are electrically isolated by the isolation region 16. When a voltage 小于 less than the threshold voltage is applied to the gate 15, the channel region of the diode region from the anode 11 to the drain 10 of the transistor device remains conductive.
[0023] 隔离区 16的第一端延伸至栅极 15与漏极 10之间的区域, 且不延伸到漏极 10, 即 隔离区 16的第一端与漏极 10之间具有一定距离, 隔离区 16的第二端延伸至晶体 管区的源极 12远离漏极的一侧。 可选地, 隔离区 16的第一端也可只延伸至栅极 1 5靠近所述漏极的一侧。  [0023] The first end of the isolation region 16 extends to a region between the gate 15 and the drain 10, and does not extend to the drain 10, that is, a distance between the first end of the isolation region 16 and the drain 10, The second end of isolation region 16 extends to the side of source region 12 of the transistor region that is remote from the drain. Alternatively, the first end of the isolation region 16 may also extend only to the side of the gate 15 close to the drain.
[0024] 二级管区的阳极 11与晶体管区的源极 12交替排列并沿着平行于漏极 10的长度方 向布置, 相邻的两个阳极 11和源极 12通过隔离区 16进行电学隔离。 隔离区 16可 以通过离子注入或刻蚀等方式消除该区域的导电沟道形成。 [0025] 参见图 3和图 4, 本发明的晶体管器件为增强型功率幵关器件, 该晶体管器件为 制作在衬底 121上的外延多层结构, 其包括衬底 121以及在衬底 121上自下至上依 次生长的过渡层 122、 沟道层 123、 势垒层 124和介质层 125, 晶体管区的源极 12 和漏极 10以及二极管区的阳极 11形成于势垒层 124的上方并位于势垒层 124与介 质层 125之间。 势垒层 124与介质层 125之间还形成有 P型氮化镓层 13(p-GaN), 晶 体管区的栅极 15形成于 P型氮化镓层 13的上方, 介质层 125中 P型氮化镓层 13的上 方幵设有栅金属接触孔 14, 栅极 15具有向下延伸的延伸部, 该延伸部穿过栅金 属接触孔 14并与 P型氮化镓层 13相连接。 [0024] The anode 11 of the diode region is alternately arranged with the source 12 of the transistor region and arranged along the length direction parallel to the drain 10, and the adjacent two anodes 11 and 12 are electrically isolated by the isolation region 16. The isolation region 16 can eliminate the formation of conductive channels in the region by ion implantation or etching. Referring to FIGS. 3 and 4, the transistor device of the present invention is an enhanced power switching device which is an epitaxial multilayer structure fabricated on a substrate 121, including a substrate 121 and on a substrate 121. A transition layer 122, a channel layer 123, a barrier layer 124, and a dielectric layer 125, which are sequentially grown from bottom to top, a source 12 and a drain 10 of the transistor region, and an anode 11 of the diode region are formed over the barrier layer 124 and are located The barrier layer 124 is between the dielectric layer 125 and the dielectric layer 125. A P-type gallium nitride layer 13 (p-GaN) is further formed between the barrier layer 124 and the dielectric layer 125. The gate 15 of the transistor region is formed over the P-type gallium nitride layer 13, and the dielectric layer 125 is P-type. A gate metal contact hole 14 is provided above the gallium nitride layer 13, and the gate electrode 15 has a downward extending portion which passes through the gate metal contact hole 14 and is connected to the P-type gallium nitride layer 13.
[0026] 参见图 3, 图 3为晶体管器件中二极管区的结构示意图。 可选地, 本实施例中二 极管的阳极 11采用的是异质结肖特基二极管的阳极。 实际应用中二极管阳极 11 也可采用沟槽型肖特基二极管的阳极, 也可将场效应晶体管的源极与该场效应 晶体管的栅极电连接后作为二极管区的阳极 11, 或者采用其他的二极管阳极结 构。  Referring to FIG. 3, FIG. 3 is a schematic structural view of a diode region in a transistor device. Optionally, the anode 11 of the diode in this embodiment is an anode of a heterojunction Schottky diode. In practical applications, the diode anode 11 can also adopt the anode of the trench type Schottky diode, and the source of the field effect transistor can be electrically connected to the gate of the field effect transistor as the anode 11 of the diode region, or other Diode anode structure.
[0027] 参见图 4, 图 4为晶体管器件中晶体管区的结构示意图。 可选地, 本实施例中晶 体管区的栅极 15采用的是结型栅极结构, 实际应用中晶体管区的栅极 15也可采 用金属介质栅 (MIS栅) 或沟槽栅或氟离子处理过的栅极或者其他栅极结构。  [0027] Referring to FIG. 4, FIG. 4 is a schematic structural diagram of a transistor region in a transistor device. Optionally, the gate 15 of the transistor region in this embodiment adopts a junction gate structure. In practical applications, the gate 15 of the transistor region can also be processed by a metal dielectric gate (MIS gate) or a trench gate or fluoride ion. Over the gate or other gate structure.
[0028] 如图 5所示, 当晶体管器件的栅极 15电压大于阈值电压吋, 若在漏极 10施加正 向电压, 则晶体管器件通过晶体管区导通, 此吋电流方向如图中箭头方向所示 。 如图 6所示, 当晶体管器件关断吋, 若在漏极 10施加负电压, 则二极管区域先 导通, 电流不会被晶体管区的栅极 15关断, 此吋电流方向如图中箭头方向所示 , 所以晶体管器件的反向导通电压不受晶体管器件阈值电压的制约, 也不受栅 极 15的负电压的制约。  As shown in FIG. 5, when the voltage of the gate 15 of the transistor device is greater than the threshold voltage 吋, if a forward voltage is applied to the drain 10, the transistor device is turned on through the transistor region, and the current direction of the 吋 is in the direction of the arrow in the figure. Shown. As shown in FIG. 6, when the transistor device is turned off, if a negative voltage is applied to the drain 10, the diode region is turned on first, and the current is not turned off by the gate 15 of the transistor region. As shown, the reverse conducting voltage of the transistor device is not limited by the threshold voltage of the transistor device and is not limited by the negative voltage of the gate 15.
[0029] 此外, 二极管区具有至少两个阳极 11, 晶体管区具有至少两个源极 12, 多个源 极 12沿着平行于漏极 10的长度方向布置, 阳极 11与源极 12的具体数量取决于所 需的电流等级, 电流等级越高, 阳极 11和源极 12的数量越多。  Furthermore, the diode region has at least two anodes 11 and the transistor region has at least two sources 12, the plurality of sources 12 being arranged along a length direction parallel to the drain 10, the specific number of anodes 11 and sources 12 Depending on the desired current level, the higher the current level, the greater the number of anodes 11 and sources 12.
[0030] 由上可见, 当本发明的具有集成二极管的晶体管器件的栅极电压大于阈值电压 吋, 若在漏极施加正向电压, 则晶体管器件通过晶体管区导通。 若在漏极施加 负电压, 则二极管区域先导通, 电流不会被晶体管区的栅极关断, 所以晶体管 器件的反向导通电压不受晶体管器件阈值电压的制约, 因此晶体管器件的反向 导通电压可以独立进行设计而不受阈值电压影响。 并且即使对晶体管器件的栅 极施加负电压进行关断, 也不会影响晶体管器件的反向导通电压。 另外, 二极 管区与晶体管区共享栅极与漏极之间的接入区, 从而减小了晶体管器件的正向 导通电阻与反向导通电阻。 [0030] As can be seen from the above, when the gate voltage of the transistor device with integrated diode of the present invention is greater than the threshold voltage 吋, if a forward voltage is applied to the drain, the transistor device is turned on through the transistor region. If a negative voltage is applied to the drain, the diode region is turned on first, and the current is not turned off by the gate of the transistor region, so the transistor The reverse conducting voltage of the device is not limited by the threshold voltage of the transistor device, so the reverse conducting voltage of the transistor device can be designed independently of the threshold voltage. And even if a negative voltage is applied to the gate of the transistor device to turn off, the reverse conducting voltage of the transistor device is not affected. In addition, the diode region and the transistor region share an access region between the gate and the drain, thereby reducing the forward conduction resistance and the reverse conduction resistance of the transistor device.
工业实用性  Industrial applicability
[0031] 本发明的晶体管器件采用阳极与源极交替排列, 并通过隔离区进行电学隔离的 结构, 使二极管区与晶体管区共享栅极与漏极之间的接入区, 使晶体管器件的 反向导通电压不仅不受阈值电压的制约, 也不受向栅极施加的负电压的影响, 另外还减小了晶体管器件的正向导通电阻与反向导通电阻, 提高了该增强型功 率器件的性能, 具有良好的工业实用性。  [0031] The transistor device of the present invention adopts a structure in which an anode and a source are alternately arranged and electrically isolated by an isolation region, so that a diode region and a transistor region share an access region between a gate and a drain, so that the transistor device is reversed. The conduction voltage is not only limited by the threshold voltage, but also is not affected by the negative voltage applied to the gate. In addition, the forward conduction resistance and the reverse conduction resistance of the transistor device are reduced, and the enhanced power device is improved. Performance, with good industrial applicability.
[0032] 最后需要说明的是, 以上所述的仅是本发明的优选实施方式, 应当指出, 对于 本领域的普通技术人员来说, 在不脱离本发明构思的前提下, 还可以做出若干 变形和改进, 这些都属于本发明的保护范围。  [0032] Finally, it should be noted that the above description is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can also make certain several without departing from the inventive concept. Modifications and improvements are within the scope of the invention.

Claims

权利要求书 Claim
[权利要求 1] 具有集成二极管的晶体管器件, 其特征在于: 包括  [Claim 1] A transistor device having an integrated diode, characterized by:
二极管区, 所述二极管区具有多个阳极;  a diode region, the diode region having a plurality of anodes;
晶体管区, 所述晶体管区具有一个栅极、 一个漏极和多个源极, 多个 所述源极沿着平行于所述漏极的长度方向布置, 所述漏极和所述源极 分别位于所述栅极的两侧, 所述源极与所述阳极电连接后作为所述晶 体管器件的源极;  a transistor region, the transistor region has a gate, a drain and a plurality of sources, and the plurality of sources are arranged along a length direction parallel to the drain, the drain and the source respectively Located on both sides of the gate, the source is electrically connected to the anode to serve as a source of the transistor device;
隔离区, 所述隔离区位于所述二极管区与所述晶体管区之间, 所述二 极管区与所述晶体管区通过所述隔离区进行电学隔离。  An isolation region, the isolation region being located between the diode region and the transistor region, wherein the diode region and the transistor region are electrically isolated by the isolation region.
[权利要求 2] 根据权利要求 1所述的晶体管器件, 其特征在于:  [Clave 2] The transistor device according to claim 1, wherein:
所述隔离区的第一端延伸至所述栅极靠近所述漏极的一侧, 所述隔离 区的第二端延伸至所述源极远离所述漏极的一侧。  A first end of the isolation region extends to a side of the gate adjacent the drain, and a second end of the isolation region extends to a side of the source remote from the drain.
[权利要求 3] 根据权利要求 1所述的晶体管器件, 其特征在于:  [Clave 3] The transistor device according to claim 1, wherein:
所述隔离区的第一端延伸至所述栅极与所述漏极之间, 所述隔离区的 第二端延伸至所述源极远离所述漏极的一侧。  A first end of the isolation region extends between the gate and the drain, and a second end of the isolation region extends to a side of the source remote from the drain.
[权利要求 4] 根据权利要求 1至 3任一项所述的晶体管器件, 其特征在于:  [Clave 4] The transistor device according to any one of claims 1 to 3, characterized in that:
所述二极管区具有至少两个所述阳极, 所述晶体管区具有至少两个所 述源极。  The diode region has at least two of the anodes, and the transistor region has at least two of the sources.
[权利要求 5] 根据权利要求 1至 3任一项所述的晶体管器件, 其特征在于:  [Clave 5] The transistor device according to any one of claims 1 to 3, characterized in that:
所述阳极与所述源极交替排列, 相邻的所述阳极与所述栅极通过所述 隔离区进行电学隔离。  The anode and the source are alternately arranged, and the adjacent anode and the gate are electrically isolated by the isolation region.
[权利要求 6] 根据权利要求 1至 3任一项所述的晶体管器件, 其特征在于: [Clave 6] The transistor device according to any one of claims 1 to 3, characterized in that:
异质结肖特基二极管的阳极或沟槽型肖特基二极管的阳极作为所述二 极管区的阳极。  The anode of the heterojunction Schottky diode or the anode of the trench Schottky diode serves as the anode of the diode region.
[权利要求 7] 根据权利要求 1至 3任一项所述的晶体管器件, 其特征在于:  [Clave 7] The transistor device according to any one of claims 1 to 3, characterized in that:
场效应晶体管的源极与所述场效应晶体管的栅极电连接后作为所述二 极管区的阳极。  The source of the field effect transistor is electrically coupled to the gate of the field effect transistor to serve as the anode of the diode region.
[权利要求 8] 根据权利要求 1至 3任一项所述的晶体管器件, 其特征在于: 所述栅极为结型栅或金属介质栅或沟槽栅或氟离子处理过的栅极。 [Claim 8] The transistor device according to any one of claims 1 to 3, characterized in that: The gate is a junction gate or a metal dielectric gate or a trench gate or a fluoride ion treated gate.
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