WO2019052502A1 - 显示面板及其制造方法、显示装置 - Google Patents

显示面板及其制造方法、显示装置 Download PDF

Info

Publication number
WO2019052502A1
WO2019052502A1 PCT/CN2018/105454 CN2018105454W WO2019052502A1 WO 2019052502 A1 WO2019052502 A1 WO 2019052502A1 CN 2018105454 W CN2018105454 W CN 2018105454W WO 2019052502 A1 WO2019052502 A1 WO 2019052502A1
Authority
WO
WIPO (PCT)
Prior art keywords
display panel
layer
metal layer
substrate
power supply
Prior art date
Application number
PCT/CN2018/105454
Other languages
English (en)
French (fr)
Inventor
黄炜赟
承天一
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18856212.8A priority Critical patent/EP3683839A4/en
Priority to US16/337,528 priority patent/US20190229169A1/en
Publication of WO2019052502A1 publication Critical patent/WO2019052502A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H10K59/1795—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • Embodiments of the present disclosure relate to a display panel, a method of manufacturing the same, and a display device.
  • the organic light-emitting display panel has the advantages of self-luminescence, fast response, wide viewing angle, high brightness, colorful color, thinness and the like, and thus becomes an important display technology.
  • the organic light emitting display panel generally includes a plurality of pixel units, and each of the pixel units includes an Organic Light Emitting Diode (OLED).
  • OLED Organic Light Emitting Diode
  • Organic light emitting diodes typically include an anode, a cathode, and an organic functional layer between the anode and the cathode, such as a light emitting layer.
  • At least one embodiment of the present disclosure provides a display panel including: a substrate; a pixel unit on the substrate, the pixel unit including a driving circuit layer; and the driving circuit layer and the substrate Between the patterned metal layers, the metal layer includes at least a first portion of a supply voltage signal for connecting the display panel.
  • the driving circuit layer includes a power supply line that supplies a power supply voltage signal to the pixel unit, and the first portion is connected in parallel with the power supply line.
  • the power line includes a portion of a source-drain conductive layer.
  • the driving circuit layer includes a capacitor and a thin film transistor; wherein the capacitor includes a first pole and a second pole, and the metal layer further includes a second portion; a first pole between the second pole and the second portion, an orthographic projection of the first pole on the base substrate and an orthographic projection of the second portion on the base substrate At least partially overlapping; the second pole being electrically coupled to the second portion of the metal layer.
  • the first portion is electrically connected to the second portion.
  • the metal layer further includes a third portion; an orthographic projection of the third portion on the substrate substrate and an active layer of the thin film transistor are The orthographic projections on the substrate substrate at least partially overlap.
  • the display panel includes a display area and a peripheral area, a first portion of the metal layer is located in the display area, and the metal layer further includes a periphery a fourth portion of the region; the fourth portion is for transmitting signals.
  • the display panel further includes a barrier layer and a buffer layer between the substrate substrate and the driving circuit layer; wherein the metal layer is in the Between the barrier layer and the buffer layer.
  • At least one embodiment of the present disclosure provides a method of manufacturing a display panel, including: forming a patterned metal layer on a substrate; forming a pixel unit on the metal layer, wherein the pixel unit includes a driving circuit layer;
  • the metal layer includes at least a first portion for connecting a power supply voltage signal of the display panel.
  • the driving circuit layer includes a power supply line that supplies a power supply voltage signal to the pixel unit, and the first portion is formed in parallel with the power supply line.
  • the power supply line includes a portion of a source/drain conductive layer.
  • a capacitor and a thin film transistor are formed in the driving circuit layer; wherein the capacitor includes a first pole and a second pole, and the metal layer further includes a second portion; the first pole is formed between the second pole and the second portion, an orthographic projection of the first pole on the base substrate and the second portion is in the lining The orthographic projections on the base substrate at least partially overlap; the second poles are formed to be electrically connected to the second portion of the metal layer.
  • the first portion is formed to be electrically connected to the second portion.
  • the metal layer further includes a third portion; an orthographic projection of the third portion on the substrate substrate and an active of the thin film transistor The orthographic projections of the layers on the substrate substrate at least partially overlap.
  • the display panel includes a display area and a peripheral area, a first portion of the metal layer is formed in the display area, and the metal layer further includes a fourth portion formed in the peripheral region; the fourth portion is for transmitting a signal.
  • the method for manufacturing a display panel according to at least one embodiment of the present disclosure further includes forming a barrier layer and a buffer layer between the substrate substrate and the driving circuit layer; wherein the metal layer is formed on the barrier layer and Between the buffer layers.
  • a first via hole is formed in at least the driving circuit layer on the first portion such that the first portion can pass through the first via and the Power cord connection.
  • a second via hole is formed in at least the driving circuit layer on the fourth portion such that the fourth portion can pass through the second via hole and At least the power cord is connected.
  • the first via hole and the second via hole are formed by the same mask.
  • the first portion, the second portion, the third portion, and the fourth portion are formed by the same mask.
  • At least one embodiment of the present disclosure provides a display device including the display panel of any of the above.
  • FIG. 1A is a schematic diagram of a 2T1C pixel circuit
  • FIG. 1B is a schematic diagram of another 2T1C pixel circuit
  • FIG. 2 is a schematic diagram 1 of a display panel according to an embodiment of the present disclosure
  • 3A-3C are schematic diagrams 2 of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a flow chart showing a manufacturing process of a display panel according to an embodiment of the present disclosure
  • FIG. 6-11 are cross-sectional views of a display panel during a manufacturing process according to an embodiment of the present disclosure.
  • the pixel circuit in the OLED display panel generally adopts a matrix driving method, and is divided into an active matrix driving and a passive matrix driving according to whether or not a switching component is introduced in each pixel unit.
  • an active matrix OLED integrates a set of thin film transistors and storage capacitors in a pixel circuit of each pixel unit, and controls the current flowing through the OLED by driving control of the thin film transistor and the storage capacitor, thereby enabling The OLED emits light as needed.
  • the basic pixel circuit used in the AMOLED display panel is usually a 2T1C pixel circuit, that is, a basic function of driving the OLED illumination by using two thin film transistors (TFTs) and one storage capacitor Cs.
  • 1A and 1B are schematic views showing two 2T1C pixel circuits, respectively.
  • a 2T1C pixel circuit includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs.
  • the gate of the switching transistor T0 is connected to the scan line to receive the scan signal Scan1, for example, the source is connected to the data line to receive the data signal Vdata, the drain is connected to the gate of the driving transistor N0; the source of the driving transistor N0 is connected to The first voltage terminal receives the first voltage Vdd (high voltage), and the drain is connected to the positive terminal of the OLED; one end of the storage capacitor Cs is connected to the drain of the switching transistor T0 and the gate of the driving transistor N0, and the other end is connected to the driving The source of the transistor N0 and the power supply line are connected to the first voltage terminal Vdd; the negative terminal of the OLED is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the 2T1C pixel circuit is driven by controlling the brightness and darkness (gray scale) of the pixel via the two TFTs and the storage capacitor Cs.
  • the scan signal Scan1 is applied through the scan line to turn on the switching transistor T0
  • the data signal Vdata fed through the data line by the data driving circuit charges the storage capacitor Cs via the switching transistor T0, thereby storing the data signal Vdata in the storage capacitor Cs.
  • the stored data signal Vdata controls the degree of conduction of the driving transistor N0, thereby controlling the magnitude of the current flowing through the driving transistor to drive the OLED to emit light, that is, the current determines the gray scale of the pixel illumination.
  • the switching transistor T0 is an N-type transistor and the driving transistor N0 is a P-type transistor.
  • another 2T1C pixel circuit also includes a switching transistor T0, a driving transistor N0, and a storage capacitor Cs, but the connection mode thereof is slightly changed, and the driving transistor N0 is an N-type transistor.
  • the variation of the pixel circuit of FIG. 1B with respect to FIG. 1A includes that the positive terminal of the OLED is connected to the power supply line to be connected to the first voltage terminal Vdd to receive the first voltage Vdd (high voltage), and the negative terminal is connected to the driving transistor.
  • the drain of N0, the source of the driving transistor N0 is connected to the second voltage terminal to receive the second voltage Vss (low voltage, such as ground voltage).
  • the operation mode of the 2T1C pixel circuit is basically the same as that of the pixel circuit shown in FIG. 1A, and details are not described herein again.
  • the switching transistor T0 is not limited to the N-type transistor, and may be a P-type transistor, thereby controlling the polarity of the scan signal supplied from the scan control terminal Scan1 which is turned on or off. Change it accordingly.
  • the industry also provides other pixel circuits with compensation functions based on the basic pixel circuits of the above 2T1C.
  • the compensation function can be realized by voltage compensation, current compensation or hybrid compensation, or the compensation function can be compensated internally, externally compensated, etc.
  • the pixel circuit having the compensation function may be, for example, 4T1C, 4T2C, 7T1C, etc., which will not be described in detail herein.
  • the organic light-emitting display panel is developing toward a large screen, but the display uniformity of the organic light-emitting display panel tends to be affected as the size thereof becomes larger.
  • the larger the size of the display panel the longer the signal transmission path of each pixel unit of the display panel, and the greater the resistance to signal transmission. Therefore, the difference in signal at different positions of the display panel is larger, resulting in uniform display of the display panel. Sexual deterioration.
  • the display panel may, for example, be provided with a double-layer source/drain conductive layer (ie, a conductive layer including source and drain electrodes of the thin film transistor) for forming a power supply line, and thus having a layer
  • the display panel of the power supply line of the source-drain conductive layer has a smaller power supply voltage signal transmission resistance, thereby reducing the resistance voltage drop of the power supply voltage signal, thereby reducing the difference of the power supply voltage signals across the display panel, so that the display panel has Better display uniformity.
  • a layer of source-drain conductive layer to the display panel, a corresponding insulating layer needs to be added. Therefore, in the manufacturing process of the display panel, at least two lithography processes are added to form the additional layer.
  • the source and drain conductive layers make the manufacturing process of the display panel more complicated and costly.
  • At least one embodiment of the present disclosure provides a display panel including: a substrate substrate; a pixel unit on the substrate substrate, the pixel unit including a driving circuit layer; and a patterned metal between the driving circuit layer and the substrate substrate a layer comprising a first portion of at least a supply voltage signal for connecting to the display panel.
  • At least one embodiment of the present disclosure provides a method of fabricating a display panel, including: forming a patterned metal layer on a substrate; forming a pixel unit on the metal layer, the pixel unit including a driving circuit layer; wherein the metal layer includes At least for connecting the first portion of the power supply voltage signal of the display panel.
  • At least one embodiment of the present disclosure provides a display device including a display panel including: a substrate substrate; a pixel unit on the substrate substrate, the pixel unit including a driving circuit layer; and a driving circuit layer and a substrate Between the patterned metal layers, the metal layer includes at least a first portion of a supply voltage signal for connecting the display panel.
  • the display panel of the present disclosure and a method of manufacturing the same will be described below by way of several specific embodiments.
  • At least one embodiment of the present disclosure provides a display panel including a plurality of pixel units, each of which includes a light emitting diode and a corresponding pixel circuit, which may be employed, for example, or based on any of the pixel circuits described above.
  • the one of the storage capacitors in the pixel circuit is connected to the power supply voltage terminal Vdd through a power supply line as an example, but the embodiment does not limit this.
  • the display panel includes: a substrate substrate 101; a pixel unit on the substrate substrate 101, the pixel unit includes a driving circuit layer 102; the display panel further includes a driving circuit layer 102 and a substrate substrate 101. Between the patterned metal layers, the metal layer includes at least a first portion 103A for connecting a power supply voltage signal of the display panel.
  • the display panel may include, for example, a display area including a pixel unit for display, and a peripheral area including various signal lines and the like, wherein the display area includes, for example, the first A region 10 and a second region 20, the peripheral region including, for example, a third region 30.
  • a plurality of thin film transistors, capacitors, gate lines, data lines, power lines, and the like for driving the display panel may be formed in the driving circuit layer 102.
  • the plurality of thin film transistors may include driving transistors, switching transistors, and the like.
  • the gate line, the data line, the power line, and the like extend from the display area to the peripheral area, and are thereby electrically connected to the gate driving circuit, the data driving circuit, the power supply voltage terminal, and the like.
  • the power line may include, for example, a portion of the source-drain conductive layer (described later in detail); for example, the power line may include a portion of the gate conductive layer on the different layers and electrically connected to each other, and a portion of the source-drain conductive layer,
  • the power cord can be connected directly or indirectly to the supply voltage terminal.
  • the driving circuit layer 102 may include an active layer 1022, a first gate insulating layer 1023, a first gate conductive layer 1024, a second gate insulating layer 1025, and a second gate.
  • a functional layer such as a conductive layer 1026, an insulating layer 1027, and a source/drain conductive layer 1028, which together constitute a capacitor located in the first region 10, a thin film transistor located in the second region 20, and located in the third region 30
  • the thin film transistor is, for example, a drive transistor.
  • the display panel may further include a barrier layer 1011 and a buffer layer 1021 between the base substrate 101 and the driving circuit layer 102, and the patterned metal layer may be located, for example, in the barrier layer 1011 and buffered. Between layers 1021.
  • the base substrate 10 is, for example, a glass substrate, a plastic substrate or the like, and the barrier layer 1011 is formed to prevent impurities or harmful ions in the base substrate from diffusing to the drive circuit layer, resulting in deterioration of characteristics of, for example, a thin film transistor.
  • the buffer layer 1021 is overlaid on the metal layer.
  • the first gate conductive layer 1024, the second gate insulating layer 1025, and the second gate conductive layer 1026 located in the first region 10 are stacked on each other, thereby forming a first capacitor;
  • the gate conductive layer 1024 serves as a first pole of the first capacitor
  • the second gate insulating layer 1025 serves as a dielectric of the first capacitor
  • the second gate conductive layer 1026 serves as a second pole of the first capacitor.
  • the metal layer may further include a second portion 103B that is at least partially opposite to the first pole of the first capacitor (ie, the first gate conductive layer 1024); for example, an orthographic projection of the first pole on the base substrate 101 The orthographic projections of the second portion 103B on the base substrate 101 at least partially overlap.
  • the second portion 103B and the first portion 103A may be, for example, two separate portions; as shown in FIG. 3B, the second portion 103B may be electrically connected to, for example, the first portion 103A; as shown in FIG. 3C, the second portion
  • the portion 103B and the first portion 103A may also be the same same portion, that is, the second portion 103B and the first portion 103A have the same metal layer structure.
  • the second portion 103B, the buffer layer 1021, the first gate insulating layer 1023, and the first gate conductive layer 1024 included in the metal layer may constitute a second capacitor; the buffer layer 1021 and the first gate insulating layer 1023 is a medium of the second capacitor, and the second portion 103B and the first gate conductive layer 1024 serve as the first pole and the second pole of the second capacitor, respectively.
  • the second pole of the first capacitor may be electrically connected, for example, to the second portion 103B, whereby the first capacitor and the second capacitor are connected in parallel with each other. Therefore, the second portion 103B included in the metal layer can also increase the total capacitance of the capacitance of the pixel unit.
  • the increase of the capacitance can make the power supply of each pixel unit of the display panel more sufficient, thereby avoiding the phenomenon that the pixel unit is flickering during display, thereby improving the display quality of the display panel; in addition, the first capacitor and the second capacitor are connected in parallel
  • the structure can increase the capacitance per unit area of the capacitor, thereby reducing the space occupied by the capacitor when the required capacitance is constant, thereby facilitating the high resolution design of the display panel.
  • the first portion 103A and the second portion 103B of the metal layer located in the first region 10 may be two independent parts, or may be the same metal layer structure integrally formed; when the first portion 103A and the second portion 103B are In the case of the same metal layer structure, the structure can be connected to a power supply voltage signal or a capacitor together with other functional layers.
  • the source-drain conductive layer 1028 located in the first region 10 may be connected to a power supply voltage signal, for example, as a power supply line for supplying a power supply voltage signal to the pixel unit, and the first portion 103A included in the metal layer may be connected to the power supply, for example.
  • the wires are electrically connected to each other, for example, by at least one first via 1031 being electrically connected to the power supply line, that is, the source-drain conductive layer 1028, thereby, for example, the first portion 103A and the source-drain conductive layer 1028 are connected in parallel to collectively provide the pixel unit. Power supply voltage signal.
  • the addition of the first portion 103A can reduce the transmission resistance of the power supply voltage signal, thereby reducing the voltage drop generated by the power supply voltage signal during transmission, thereby reducing the difference in the power supply voltage signals across the display panel, and finally A technical effect of improving display uniformity of the display panel is achieved.
  • the source-drain conductive layer 1028 (including the source and the drain of the thin film transistor) constitutes a thin film transistor, and the source and drain of the thin film transistor can be respectively connected to the power supply line and the pixel electrode for driving the organic light emitting diode to emit light.
  • the metal layer may further include, for example, a third portion 203.
  • the orthographic projection of the third portion 203 on the substrate substrate 101 and the orthographic projection of the active layer 1022 of the thin film transistor on the substrate substrate at least partially overlap.
  • the orthographic projection of the third portion 203 of the metal layer on the base substrate 101 and the channel region of the active layer 1022 are positive on the base substrate 101.
  • the projections at least partially overlap, for example completely overlapping.
  • the orthographic projection of the third portion 203 on the base substrate 101 completely overlaps the orthographic projection of the active layer 1022 on the base substrate 101.
  • the third portion 203 of the metal layer can block external light to prevent external light from adversely affecting the channel region of the thin film transistor, for example, avoiding light incident and increasing leakage current of the thin film transistor.
  • the first gate conductive layer 1024, the second gate conductive layer 1026, and the source/drain conductive layer 1028 located in the third region 30 can be used, for example, to form peripheral signal lines, such as gate lines, data lines, and power lines.
  • the metal layer may, for example, also include a fourth portion located in the peripheral region, for example including a fourth portion 303 located in the third region 30; the fourth portion 303 is for transmitting signals.
  • the fourth portion 303 can be electrically connected to the source/drain conductive layer 1028, the first gate conductive layer 1024, and the second gate conductive layer 1026 located in the third region 30 through the at least one second via 3031.
  • the structure can be used to form a power supply line, since the resulting power supply line is composed of portions distributed over three different layers, and can be electrically connected to each other (e.g., in parallel) with at least one via, whereby the resistance of the power supply line can be reduced. Therefore, when the source-drain conductive layer 1028 located in the third region 30 is connected to the power supply voltage signal, the addition of the fourth portion can also reduce the transmission resistance of the power supply voltage signal, thereby reducing the difference in the power supply voltage signals across the display panel, and finally reaching Improve the technical effect of display panel display uniformity.
  • the fourth portion 303 included in the metal layer may further connect other signals, for example, the fourth portion 303 may also be connected to a clock signal (CLK), a reset signal (INI), and a gate high voltage. (VGH), gate low voltage (VGL), etc. Therefore, the fourth portion 303 of the metal layer can make full use of the space of the peripheral region, thereby facilitating the narrow bezel design of the display panel.
  • CLK clock signal
  • IPI reset signal
  • VGH gate high voltage
  • VGL gate low voltage
  • the material of the metal layer may be, for example, a suitable material such as titanium, titanium alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, copper or copper alloy, or a combination of these materials.
  • the material of the metal layer may be a titanium/aluminum/titanium three-layer structure, a titanium/aluminum double-layer structure, or the like, which is not limited in this embodiment.
  • the display panel may further include other functional structures such as the planarization layer 104, the pixel electrode layer 105, the pixel defining layer 106, the luminescent layer 107, the common electrode 109, and the spacer 108, which are not described in this embodiment.
  • the light emitting layer 107 is interposed between the pixel electrode layer 105 and the common electrode 109, thereby constituting an organic light emitting diode.
  • the patterned metal layer between the driving circuit layer and the substrate substrate included in the display panel provided in this embodiment may include a plurality of portions, wherein at least the first portion may be used to connect the display panel power voltage signal, so the portion may The transmission resistance of the power voltage signal is reduced, thereby reducing the voltage drop generated by the power voltage signal during transmission, so that the metal layer can reduce the difference of the power voltage signals across the display panel, so that the display brightness of each position of the display panel is more accurate.
  • the technical effect of improving the uniformity of display panel display is achieved. For example, in the case where the display panel has a large size, the metal layer can effectively improve the display uniformity of the display panel.
  • the second portion of the metal layer can be combined with the first capacitance of the display panel and form a second capacitance to increase the total capacitance of the capacitance of the pixel unit.
  • the increase of the capacitance can make the power supply of each pixel unit of the display panel more sufficient, thereby avoiding the phenomenon that the pixel unit is flickering during display, thereby improving the display quality of the display panel; in addition, the first capacitor and the second capacitor can be formed.
  • the parallel structure can increase the capacitance per unit area of the capacitor, thereby reducing the space occupied by the capacitor when the required capacitance is constant, thereby facilitating the high resolution design of the display panel.
  • the third portion of the metal layer is disposed corresponding to the thin film transistor, and the portion can effectively protect the channel region of the thin film transistor to prevent external light from entering the channel region and adversely affecting.
  • the fourth portion of the metal layer is located in the peripheral region, and the portion can be used to connect the display panel power voltage signal to improve the display panel display uniformity, and can also connect other signals, thereby fully utilizing the space of the peripheral region, thereby facilitating the narrowness of the display panel. Border design.
  • the respective portions included in the metal layer are located in the same layer, and therefore these portions can be formed in the same process step, thereby simplifying the manufacturing process of the display panel and reducing the cost.
  • At least one embodiment of the present disclosure provides a method of manufacturing a display panel, such as the display panel as described above. As shown in FIG. 4, the method includes steps S101 to S102.
  • Step S101 forming a patterned metal layer on the base substrate.
  • the display panel can be divided into a display area and a peripheral area, for example, wherein the display area can include, for example, a first area 10 and a second area 20, and the peripheral area can include, for example, a third area 30.
  • a patterned metal layer is first formed on the base substrate 101.
  • the metal layer may, for example, comprise at least a first portion 103A for connecting a display panel supply voltage signal, the first portion 103A being for example formed in the first region 10, and the first portion 103A being connectable, for example, to a power line of a display panel formed later,
  • the voltage drop generated by the power supply voltage signal during transmission is reduced, thereby reducing the difference of the power supply voltage signals across the display panel, and finally achieving the technical effect of improving the display uniformity of the display panel.
  • the metal layer may further include a second portion 103B formed in the first region 10, and the second portion 103B may be formed, for example, at a position corresponding to a capacitor to be formed later such that the first pole of the capacitor (the electrode near the second portion)
  • the orthographic projection on the base substrate 101 at least partially overlaps with the orthographic projection of the second portion 103B on the base substrate 101, so that the second portion 103B can be combined with the capacitance formed later to increase its capacitance.
  • the first portion 103A and the second portion 103B may be, for example, two independent portions that are not connected to each other; or, as shown in FIG. 5B, the first portion 103A and the second portion 103B may be, for example, Electrical connection; or alternatively, as shown in FIG. 5C, the first portion 103A and the second portion 103B may also have the same metal layer structure, for example; when the first portion 103A and the second portion 103B are of the same metal layer structure, the structure can be connected.
  • the supply voltage signal can also be combined with other functional layers to form a capacitor.
  • the metal layer may further include, for example, a third portion 203 formed in the second region 20, and the third portion 203 may correspond to, for example, a position of a thin film transistor to be formed to drive the display panel to be subsequently formed, for example, for example.
  • the position of the channel region formed in the active layer or the active layer of the thin film transistor on the substrate substrate 101 is opposite to the front projection of the third portion 203 on the substrate substrate 101 and the thin film transistor
  • the orthographic projections of the source layer 1022 on the substrate substrate at least partially overlap, so that the third portion 203 can block external light to prevent external light from adversely affecting the channel region of the thin film transistor, for example, avoiding the incidence of light and increasing the film.
  • the metal layer may, for example, further include a fourth portion 303 formed in the third region 30 for transmitting a signal.
  • the fourth portion 303 can also be connected to the power supply voltage signal, thereby reducing the transmission resistance of the power supply voltage signal, reducing the difference in the power supply voltage signals across the display panel, and improving the display panel display uniformity.
  • the fourth portion 303 included in the metal layer may further connect other signals, for example, the fourth portion 303 may also be connected to a clock signal (CLK), a reset signal (INI), and a gate high voltage. (VGH), gate low voltage (VGL), etc., so that the fourth portion 303 can make full use of the space of the peripheral region, thereby facilitating the narrow bezel design of the display panel.
  • CLK clock signal
  • II reset signal
  • VGH gate high voltage
  • VGL gate low voltage
  • the first portion 103A, the second portion 103B, the third portion 203, and the fourth portion 303 of the metal layer may be subjected to a patterning process (for example, a photolithography process) by passing the same metal thin film layer through the same mask. Formed so that the manufacturing process of the display panel can be simplified.
  • a patterning process for example, a photolithography process
  • the material of the metal layer may be, for example, a suitable material such as titanium, titanium alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, copper or copper alloy, or a combination of these materials.
  • the material of the metal layer may be a titanium/aluminum/titanium three-layer structure, a titanium/aluminum double-layer structure, or the like, which is not limited in this embodiment.
  • a barrier layer 1011 may be formed first, and then a metal layer is formed on the barrier layer 1011.
  • the barrier layer 1011 may form a metal layer or the like. protection.
  • the material of the barrier layer 1011 can be, for example, silicon nitride, silicon oxide, silicon oxynitride or the like, which is not limited in this embodiment.
  • Step S102 forming a pixel unit on the metal layer.
  • a pixel unit may be formed on the metal layer, and the pixel unit may include, for example, a driving circuit layer, an organic light emitting diode, or the like.
  • forming the driving circuit layer may include, for example, forming a plurality of thin film transistors, capacitors, gate lines, data lines, power lines, and the like for driving the display panel; the plurality of thin film transistors may include driving transistors, switching transistors, and the like.
  • the gate lines, the data lines, the power lines, and the like may extend from the display area to the peripheral area, for example, and are thereby electrically connected to the gate driving circuit, the data driving circuit, the power supply voltage terminal, and the like.
  • a capacitor may be formed in the first region 10, a thin film transistor is formed in the second region 20, and a gate line, a data line, a power supply line, or the like is formed in the third region 30 as a portion of the peripheral circuit.
  • the power line may include, for example, a portion of the source-drain conductive layer (described later in detail), for example, the power line includes a portion of the gate conductive layer formed on the different layers and electrically connected to each other, and a portion of the source-drain conductive layer, The power cord can be connected directly or indirectly to the supply voltage terminal.
  • a buffer layer 1021 may be formed on the metal layer such that the metal layer is located between the barrier layer 1011 and the buffer layer 1021.
  • an active layer material may be formed on the buffer layer 1021, and then the active layer material is patterned by, for example, a photolithography process, and finally an active source for forming a thin film transistor is formed in the second region.
  • Layer 1022 then performs a corresponding conductorization process on portions of active layer 1022 other than the channel region.
  • the buffer layer 1021 may be, for example, a suitable material such as silicon nitride, silicon oxide, or silicon oxynitride; and the active layer 1022 may be a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor (for example, IGZO). This embodiment does not limit this.
  • a first gate insulating layer 1023 is formed on the entire surface of the substrate, and then a first gate material layer is formed on the first gate insulating layer 1023, and then, for example, a photolithography process is used.
  • the first gate material layer is patterned to form a first gate conductive layer.
  • the first gate conductive layer may include, for example, a portion 1024A located in the first region 10, a portion 1024B located in the second region 20, and a portion 1024C located in the third region 30.
  • a portion 1024A is used to form a capacitor as described below, a portion 1024B is used to form a gate of a thin film transistor, and a portion 1024C is used to form a signal line or the like.
  • the first gate insulating layer 1023 may be, for example, a suitable material such as silicon nitride, silicon oxide, or silicon oxynitride; and the first gate conductive layer may be made of a conductive material such as metal, for example, molybdenum, aluminum, or titanium. Such a material is not limited in this embodiment.
  • the active layer when the active layer is polysilicon, the active layer 1022 may be doped using the gate conductive layer 1024B as a mask.
  • a second gate insulating layer 1025 may be formed on the entire substrate, and then a second gate material layer is formed on the second gate insulating layer 1025, and then, for example, photolithography is employed.
  • a second gate material layer is patterned by a process or the like to form a second gate conductive layer.
  • the second gate conductive layer may include, for example, a portion 1026A at the first region 10 and a portion 1026B at the third region 30.
  • the portion of the second gate conductive layer 1026A of the first region 10, the second gate insulating layer 1025, and the portion 1024A of the first gate conductive layer may constitute a first capacitor, and the portion 1024A of the first gate conductive layer serves as the first capacitor.
  • the first pole, the second gate insulating layer 1025 serves as a dielectric for the first capacitor, and the portion 1026A of the second gate conductive layer serves as the second pole of the first capacitor.
  • the portion 1024A of the first gate conductive layer, the buffer layer 1021, the first gate insulating layer 1023, and the second portion 103B of the metal layer may further form a second capacitor, and the second pole of the first capacitor is formed to be
  • the second portion 103B of the metal layer is electrically connected, whereby the first capacitor and the second capacitor are connected in parallel with each other.
  • the second portion 103B of the metal layer can increase the total capacitance of the capacitance of the pixel unit.
  • the second gate insulating layer 1025 may be, for example, a suitable material such as silicon nitride, silicon oxide, or silicon oxynitride; and the second gate conductive layer may be made of a conductive material such as metal, for example, molybdenum, aluminum, or the like.
  • a suitable material such as titanium is not limited in this embodiment.
  • an insulating layer 1027 is formed on the entire surface of the substrate, and then a patterning process, such as a photolithography process, may be used to form a exposed metal layer in the plurality of functional layers, respectively.
  • a plurality of vias of the gate conductive layer and the second gate conductive layer may, for example, include a first via 1031 in the first portion 103A of the first region 10 exposing the metal layer, and a second via 3031 in the fourth portion 303 of the third region 30 exposing the metal layer.
  • the third via 1032 of the first region 10 exposing the portion 1026A of the second gate is located at the fourth via 2031 and the fifth via 2032 of the second region 20 exposing the active layer 1022, in the third region a sixth via 3032 of the portion 1024C exposing the first gate and a seventh via 3033 of the portion 1024B exposing the second gate of the third region 30; and, in order to make the conductive layers on different layers Partially better parallel, it is also possible to form more vias at different locations.
  • the via holes can be formed, for example, by one patterning process.
  • the insulating layer 207 may be a suitable material such as silicon nitride or silicon oxide, which is not limited in this embodiment.
  • a source/drain metal layer is formed on the surface of the substrate, and then patterned, for example, by a photolithography process or the like to form a patterned source/drain conductive layer 1028, patterned.
  • the source/drain conductive layer 1028 is electrically connected to the exposed metal layer, the first gate conductive layer or the second gate conductive layer through the via holes.
  • the patterned source-drain conductive layer 1028 includes a portion 1028A formed in the first region 10, a portion 1028B formed in the second region 20, and a portion 1028C formed in the third region 30.
  • the portion 1028A of the source/drain conductive layer 1028 in the first region 10 can be electrically connected, for example, to the first portion 103 of the metal layer and the portion 1026A of the second gate conductive layer, and serve as a power source for supplying a power supply voltage signal to the pixel unit. Part of the line. Therefore, the first portion 103 of the metal layer can be electrically connected to the power supply lines to be connected in parallel with each other, and the parallel structure can reduce the transmission resistance of the power supply voltage signal, reduce the voltage drop generated by the power supply voltage signal during transmission, and thereby reduce the display panel. The difference in power supply voltage signals throughout the system ultimately achieves the technical effect of improving display panel uniformity.
  • the source-drain conductive layer 1028 is divided into two portions in the portion 1028B of the second region 20 and electrically connected to the active layer 1022, respectively, to form a source and a drain of the thin film transistor, and the thin film transistor can be used to drive the light-emitting element formed later ( Organic light emitting diode).
  • the source-drain conductive layer 1028 is electrically connected to the fourth portion 303 of the metal layer, the portion 1024C of the first gate conductive layer, and the portion 1026B of the second gate conductive layer in the portion 1028C of the third region 30, such that the resulting structure can be used to form
  • the power supply line since the resulting power supply line is composed of portions distributed over three different layers, and can be electrically connected to each other by at least one via (for example, in parallel), whereby the resistance of the power supply line can be reduced.
  • the portion 1028C of the source/drain conductive layer 1028 located in the third region 30 may be, for example, a part of a power supply line that supplies a power supply voltage signal to the pixel unit, such that the fourth portion 303 of the metal layer and the power supply line are electrically connected to each other to form a parallel connection.
  • the transmission resistance of the power voltage signal can be reduced, the voltage drop generated by the power voltage signal during transmission can be reduced, thereby reducing the difference of the power supply voltage signals across the display panel, and finally achieving the technical effect of improving the display uniformity of the display panel.
  • the source-drain conductive layer 1028 may be, for example, a conductive material such as metal.
  • a conductive material such as metal.
  • titanium, titanium alloy, aluminum, aluminum alloy, molybdenum, molybdenum alloy, copper, copper alloy, or the like may be used. Make a limit.
  • the manufacturing method of the display panel may further include forming a planarization layer 104 , a pixel electrode layer 105 , a pixel defining layer 106 , a light emitting layer 107 , and a spacer on the source/drain conductive layer 1028 .
  • the step of functional structure such as 108 may further form a common electrode 109 for forming a light-emitting element, a package structure (not shown), and the like, and the common electrode 109 and the pixel electrode layer 105 sandwich the light-emitting layer 107 therebetween.
  • an organic light emitting diode is formed, which will not be described in detail in this embodiment.
  • the common electrode 109 is electrically connected, for example, to another power supply voltage terminal.
  • the display panel manufactured by the method provided by the embodiment includes a patterned metal layer between the driving circuit layer and the substrate, the metal layer may include a plurality of portions, wherein at least the first portion may be used to connect the display panel power voltage Signal, so this part can reduce the transmission resistance of the power supply voltage signal, thereby reducing the voltage drop generated by the power supply voltage signal during transmission, thereby reducing the difference of the power supply voltage signals across the display panel, so that the display brightness of each position of the display panel More accurate, and ultimately achieve the technical effect of improving the uniformity of display panel display. For example, in the case where the display panel has a large size, the metal layer can effectively improve the display uniformity of the display panel.
  • the second portion of the metal layer can be combined with the first capacitance of the display panel and form a second capacitance to increase the total capacitance of the capacitance of the pixel unit.
  • the increase of the capacitance can make the power supply of each pixel unit of the display panel more sufficient, thereby avoiding the phenomenon that the pixel unit is flickering during display, thereby improving the display quality of the display panel; in addition, the first capacitor and the second capacitor can be formed.
  • the parallel structure can increase the capacitance per unit area of the capacitor, thereby reducing the space occupied by the capacitor when the required capacitance is constant, thereby facilitating the high resolution design of the display panel.
  • the third portion of the metal layer is disposed corresponding to the thin film transistor, and the channel region of the thin film transistor can be effectively protected to prevent external light from entering the channel region and adversely affecting.
  • the fourth part of the metal layer is located in the peripheral area, and can be used to connect the display panel power voltage signal to improve the display panel display uniformity, and can also connect other signals, thereby fully utilizing the space of the surrounding area, thereby facilitating the narrow border design of the display panel. .
  • the respective portions included in the metal layer are formed in the same layer of the display panel, and thus the portions may be formed in the same process step, for example, by one patterning process by the same mask; and at the same time, the implementation
  • the metal layer of the example does not need to introduce another insulating layer when forming, so that the metal layer can be prepared by adding only one step of the process. Therefore, the method provided by the embodiment can also simplify the manufacturing process of the display panel, thereby saving cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

显示面板及其制造方法、显示装置。该显示面板包括：衬底基板(101)；设置在衬底基板(101)上的像素单元，像素单元包括驱动电路层(102)；以及位于驱动电路层(102)和衬底基板(101)之间的图案化的金属层，金属层包括至少用于连接显示面板的电源电压信号的第一部分(103A)。该金属层可以减小电源电压信号的传输电阻，从而减小电源电压信号在传输时产生的压降，使得显示面板各个位置的显示亮度更加准确。

Description

显示面板及其制造方法、显示装置
本申请要求于2017年9月15日递交的中国专利申请第201710840388.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种显示面板及其制造方法、显示装置。
背景技术
有机发光显示面板具有自发光、反应快、视角广、亮度高、色彩艳、轻薄等优点，因此成为一种重要的显示技术。有机发光显示面板通常包括多个像素单元，每个像素单元包括一个有机发光二极管(Organic Light Emitting Diode，OLED)。有机发光二极管通常包括阳极、阴极以及位于阳极与阴极之间的有机功能层，例如发光层。当对有机发光二极管的阳极与阴极施加适当电压时，从阳极注入的空穴与从阴极注入的电子会在发光层中结合并激发产生光，进而实现显示。
发明内容
本公开至少一实施例提供一种显示面板，包括：衬底基板；在所述衬底基板上的像素单元，所述像素单元包括驱动电路层；位于所述驱动电路层和所述衬底基板之间的图案化的金属层，所述金属层包括至少用于连接所述显示面板的电源电压信号的第一部分。
例如，本公开至少一实施例提供的显示面板中，所述驱动电路层包括为所述像素单元提供电源电压信号的电源线，所述第一部分与所述电源线并联。
例如，本公开至少一实施例提供的显示面板中，所述电源线包括源漏导电层的一部分。
例如，本公开至少一实施例提供的显示面板中，所述驱动电路层包括电 容和薄膜晶体管；其中，所述电容包括第一极和第二极，所述金属层还包括第二部分；所述第一极在所述第二极与所述第二部分之间，所述第一极在所述衬底基板上的正投影与所述第二部分在所述衬底基板上的正投影至少部分重叠；所述第二极与所述金属层的第二部分电连接。
例如，本公开至少一实施例提供的显示面板中，所述第一部分与所述第二部分电连接。
例如，本公开至少一实施例提供的显示面板中，所述金属层还包括第三部分；所述第三部分在所述衬底基板上的正投影与所述薄膜晶体管的有源层在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示面板中，所述显示面板包括显示区和周边区域，所述金属层的第一部分位于所述显示区内，且所述金属层还包括位于所述周边区域中的第四部分；所述第四部分用于传输信号。
例如，本公开至少一实施例提供的显示面板中，所述显示面板还包括位于所述衬底基板及所述驱动电路层之间的阻挡层及缓冲层；其中，所述金属层在所述阻挡层及所述缓冲层之间。
本公开至少一实施例提供一种显示面板的制造方法，包括：在衬底基板上形成图案化的金属层；在所述金属层上形成像素单元，所述像素单元包括驱动电路层；其中，所述金属层包括至少用于连接所述显示面板的电源电压信号的第一部分。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述驱动电路层包括为所述像素单元提供电源电压信号的电源线，所述第一部分形成为与所述电源线并联。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述电源线包括源漏导电层的一部分。
例如，本公开至少一实施例提供的显示面板的制造方法中，在所述驱动电路层中形成电容和薄膜晶体管；其中，所述电容包括第一极和第二极，所述金属层还包括第二部分；所述第一极形成在所述第二极与所述第二部分之间，所述第一极在所述衬底基板上的正投影与所述第二部分在所述衬底基板上的正投影至少部分重叠；所述第二极形成为与所述金属层的第二部分电连接。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述第一部分形成为与所述第二部分电连接。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述金属层还包括第三部分；所述第三部分在所述衬底基板上的正投影与所述薄膜晶体管的有源层在所述衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述显示面板包括显示区和周边区域，所述金属层的第一部分形成于所述显示区内，且所述金属层还包括形成于所述周边区域中的第四部分；所述第四部分用于传输信号。
例如，本公开至少一实施例提供的显示面板的制造方法，还包括在衬底基板及所述驱动电路层之间形成阻挡层及缓冲层；其中，所述金属层形成于所述阻挡层及所述缓冲层之间。
例如，本公开至少一实施例提供的显示面板的制造方法中，在所述第一部分上的至少所述驱动电路层中形成第一过孔使得所述第一部分能够通过第一过孔与所述电源线连接。
例如，本公开至少一实施例提供的显示面板的制造方法中，在所述第四部分上的至少所述驱动电路层中形成第二过孔使得所述第四部分能够通过第二过孔与至少所述电源线连接。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述第一过孔和所述第二过孔通过同一掩膜板形成。
例如，本公开至少一实施例提供的显示面板的制造方法中，所述第一部分，所述第二部分，所述第三部分和所述第四部分通过同一掩膜板形成。
本公开至少一实施例提供一种显示装置，包括上述任一所述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种2T1C像素电路的示意图，图1B为另一种2T1C像素电路 的示意图；
图2为本公开一实施例提供的显示面板的示意图一；
图3A-3C为本公开一实施例提供的显示面板的示意图二；
图4为本公开一实施例提供的显示面板的制造工艺流程图；
图5A-图5C，图6-图11为本公开一实施例提供的显示面板在制造过程中的截面图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
OLED显示面板中的像素电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵驱动和无源矩阵驱动。通常有源矩阵OLED(AMOLED)在每一个像素单元的像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。
AMOLED显示面板中使用的基础像素电路通常为2T1C像素电路，即利用两个薄膜晶体管(TFT)和一个存储电容Cs来实现驱动OLED发光的基本功能。图1A和图1B分别为示出了两种2T1C像素电路的示意图。
如图1A所示，一种2T1C像素电路包括开关晶体管T0、驱动晶体管N0以及存储电容Cs。例如，该开关晶体管T0的栅极连接扫描线以接收扫描信号Scan1，例如源极连接到数据线以接收数据信号Vdata，漏极连接到驱动晶体管N0的栅极；驱动晶体管N0的源极连接到第一电压端以接收第一电压Vdd(高电压)，漏极连接到OLED的正极端；存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及电源线，从而连接到第一电压端Vdd；OLED的负极端连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。该2T1C像素电路的驱动方式是将像素的明暗(灰阶)经由两个TFT和存储电容Cs来控制。当通过扫描线施加扫描信号Scan1以开启开关晶体管T0时，数据驱动电路通过数据线送入的数据信号Vdata将经由开关晶体管T0对存储电容Cs充电，由此将数据信号Vdata存储在存储电容Cs中，且此存储的数据信号Vdata控制驱动晶体管N0的导通程度，由此控制流过驱动晶体管以驱动OLED发光的电流大小，即此电流决定该像素发光的灰阶。在图1A所示的2T1C像素电路中，开关晶体管T0为N型晶体管而驱动晶体管N0为P型晶体管。
如图1B所示，另一种2T1C像素电路也包括开关晶体管T0、驱动晶体管N0以及存储电容Cs，但是其连接方式略有改变，且驱动晶体管N0为N型晶体管。图1B的像素电路相对于图1A的变化之处包括：OLED的正极端连接到电源线从而连接到第一电压端Vdd，以接收第一电压Vdd(高电压)，而负极端连接到驱动晶体管N0的漏极，驱动晶体管N0的源极连接到第二电压端以接收第二电压Vss(低电压，例如接地电压)。存储电容Cs的一端连接到开关晶体管T0的漏极以及驱动晶体管N0的栅极，另一端连接到驱动晶体管N0的源极以及第二电压端。该2T1C像素电路的工作方式基本上与图1A所示的像素电路基本相同，这里不再赘述。
此外，对于图1A和图1B所示的像素电路，开关晶体管T0不限于N型晶体管，也可以为P型晶体管，由此控制其导通或截止的扫描控制端Scan1提供的扫描信号的极性进行相应地改变即可。此外，业界还在上述2T1C的基本像素电路的基础上提供了其他具有补偿功能的像素电路，补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，或者补偿功能可以通过内部补 偿、外部补偿等来实现，具有补偿功能的像素电路例如可以为4T1C、4T2C、7T1C等，这里不再详述。
目前，有机发光显示面板正往大屏化发展，但是有机发光显示面板的显示均匀性往往会随其尺寸的变大而受到影响。显示面板的尺寸越大，显示面板各像素单元的电源电压等信号传递的路径越长，信号传递受到的阻力越大，因此在显示面板不同位置的信号差异越大，进而导致显示面板的显示均匀性变差。
为了减小显示面板中电源电压信号的传输电阻，显示面板例如可以设置双层源漏导电层(即包括薄膜晶体管的源漏电极的导电层)以用于形成电源线，因此相对于具有一层源漏导电层的电源线的显示面板来说具有更小的电源电压信号传输电阻，从而减小电源电压信号的电阻压降，进而减小显示面板各处电源电压信号的差异，使显示面板具有更好的显示均匀性。然而，为了在显示面板中多增加一层源漏导电层，还需要相应地增加一层绝缘层，因此在该显示面板的制造过程中，至少要增加两次光刻工艺形成该增加该额外的源漏导电层，这使得显示面板的制造工艺更复杂、成本更高。
本公开至少一实施例提供一种显示面板，包括：衬底基板；在衬底基板上的像素单元，该像素单元包括驱动电路层；位于驱动电路层和衬底基板之间的图案化的金属层，该金属层包括至少用于连接显示面板的电源电压信号的第一部分。
本公开至少一实施例提供一种显示面板的制造方法，包括：在衬底基板上形成图案化的金属层；在金属层上形成像素单元，该像素单元包括驱动电路层；其中，金属层包括至少用于连接显示面板的电源电压信号的第一部分。
本公开至少一实施例提供一种显示装置，包括显示面板，该显示面板包括：衬底基板；在衬底基板上的像素单元，该像素单元包括驱动电路层；位于驱动电路层和衬底基板之间的图案化的金属层，该金属层包括至少用于连接显示面板的电源电压信号的第一部分。
下面通过几个具体的实施例对本公开的显示面板及其制造方法进行说明。
本公开至少一实施例提供一种显示面板，该显示面板包括多个像素单元，每个像素单元包括发光二极管以及相应的像素电路，该像素电路例如可 以采用或基于上述任一的像素电路。以下例如以像素电路中的存储电容的一极通过电源线与电源电压端Vdd连接为例进行描述，但是本实施例对此不作限制。
如图2所示，该显示面板包括：衬底基板101；在衬底基板101上的像素单元，该像素单元包括驱动电路层102；该显示面板还包括位于驱动电路层102和衬底基板101之间的图案化的金属层，该金属层包括至少用于连接显示面板的电源电压信号的第一部分103A。
本实施例中，如图3A-图3C所示，显示面板例如可以包括显示区和周边区域，显示区包括像素单元以用于显示，周边区域包括各种信号线等，其中显示区例如包括第一区域10和第二区域20，周边区域例如包括第三区域30。
本实施例中，驱动电路层102中例如可以形成有用于驱动显示面板的多个薄膜晶体管、电容、栅线、数据线、电源线等结构；该多个薄膜晶体管可以包括驱动晶体管、开关晶体管等，栅线、数据线、电源线等从显示区域延伸到周边区域之中，并由此与栅驱动电路、数据驱动电路、电源电压端等电连接。本实施例中，电源线例如可以包括源漏导电层的一部分(稍后详述)；例如电源线可以包括位于不同层上且彼此电连接的栅导电层的一部分以及源漏导电层的一部分，该电源线可以直接或间接连接到电源电压端。
例如，如图3A-3C所示，本实施例中，驱动电路层102可以包括有源层1022、第一栅绝缘层1023、第一栅导电层1024、第二栅绝缘层1025、第二栅导电层1026、绝缘层1027和源漏导电层1028等功能层，这些结构层或功能层共同构成位于第一区域10中的电容、位于第二区域20中的薄膜晶体管和位于第三区域30中的周边信号线等结构。该薄膜晶体管例如为驱动晶体管。
在本实施例的一个示例中，显示面板例如还可以包括在衬底基板101及驱动电路层102之间的阻挡层1011及缓冲层1021，并且图案化的金属层例如可以位于阻挡层1011及缓冲层1021之间。该衬底基板10例如为玻璃基板、塑料基板等，阻挡层1011形成来防止衬底基板中的杂质或有害离子扩散到驱动电路层而导致例如薄膜晶体管的特性劣化。缓冲层1021覆盖在金属层上。
例如，本实施例中，位于第一区域10中的第一栅导电层1024、第二栅绝缘层1025和第二栅导电层1026彼此层叠，由此可以构成第一电容；此时，第一栅导电层1024作为第一电容的第一极，第二栅绝缘层1025作为第一电容的介质，第二栅导电层1026作为第一电容的第二极。另外，该金属层还可以包括与第一电容的第一极(即第一栅导电层1024)至少部分正对的第二部分103B；例如，第一极在衬底基板101上的正投影与第二部分103B在衬底基板101上的正投影至少部分重叠。
如图3A所示，第二部分103B与第一部分103A例如可以为独立的两个部分；如图3B所示，第二部分103B例如可以与第一部分103A电连接；如图3C所示，第二部分103B与第一部分103A也可以为连续的同一部分，即第二部分103B与第一部分103A为同一金属层结构。
本实施例的一个示例中，金属层所包括的第二部分103B、缓冲层1021、第一栅绝缘层1023和第一栅导电层1024可以构成第二电容；缓冲层1021和第一栅绝缘层1023作为第二电容的介质，第二部分103B和第一栅导电层1024分别作为第二电容的第一极和第二极。此时，第一电容的第二极例如可以与第二部分103B电连接，由此第一电容和第二电容彼此并联。因此，金属层所包括的第二部分103B还可以增加该像素单元的电容的总电容量。电容量的增加可以使显示面板各个像素单元的供电量更充足，从而避免像素单元在显示时出现闪烁等不良现象，因此可以提高显示面板的显示品质；另外，第一电容和第二电容并联的结构可以提高电容的单位面积电容量，从而在所需电容一定时可以减小电容所占空间，进而有利于显示面板的高分辨率设计。
本实施例中，位于第一区域10的金属层的第一部分103A和第二部分103B可以为独立的两部分，也可以为一体形成的同一金属层结构；当第一部分103A和第二部分103B为同一金属层结构时，该结构既可以连接电源电压信号也可以与其他功能层一起构成电容。
本实施例中，位于第一区域10的源漏导电层1028例如可以连接电源电压信号，即作为为像素单元提供电源电压信号的电源线，而金属层所包括的第一部分103A例如可以与该电源线彼此电连接，例如可以通过至少一个第一过孔1031与该电源线，即源漏导电层1028进行电连接，由此将第一部分 103A与源漏导电层1028例如并联以共同为像素单元提供电源电压信号。因此，本实施例中，第一部分103A的加入可以减小电源电压信号的传输电阻，从而减小电源电压信号在传输时产生的压降，进而减小显示面板各处电源电压信号的差异，最终达到提高显示面板显示均匀性的技术效果。
本实施例中，位于第二区域20中的有源层1022、第一栅绝缘层1023、第一栅导电层1024(作为薄膜晶体管的栅极)、第二栅绝缘层1025、绝缘层1027、源漏导电层1028(包括薄膜晶体管的源极和漏极)构成薄膜晶体管，该薄膜晶体管的源极和漏极例如可以分别连接电源线和像素电极，以用于驱动有机发光二极管发光。
本实施例中，金属层例如还可以包括第三部分203，例如，第三部分203在衬底基板101上的正投影与薄膜晶体管的有源层1022在衬底基板上的正投影至少部分重叠。例如，金属层的第三部分203在衬底基板101上的正投影与有源层1022的沟道区(有源层中对应栅极的部分为沟道区)在衬底基板101上的正投影至少部分重叠，例如完全重叠。又例如，第三部分203在衬底基板101上的正投影与有源层1022在衬底基板101上的正投影完全重叠。金属层的第三部分203可以遮挡外界光线，以避免外界光线对该薄膜晶体管的沟道区产生不良影响，例如避免光线的射入而增大薄膜晶体管的漏电流等。
本实施例中，位于第三区域30中的第一栅导电层1024、第二栅导电层1026和源漏导电层1028例如可以用于形成周边信号线，例如栅线、数据线以及电源线等。金属层例如还可以包括位于周边区域中的第四部分，例如包括位于第三区域30中的第四部分303；第四部分303用于传输信号。例如，第四部分303可以通过至少一个第二过孔3031与位于第三区域30中的源漏导电层1028、第一栅导电层1024分和第二栅导电层1026电连接，这样所得到的结构可用于形成电源线，由于所得到的电源线由分布在三个不同层上的部分构成，而且彼此可以用至少一个过孔电连接(例如并联)，由此可以降低电源线的电阻。因此当位于第三区域30中的源漏导电层1028连接电源电压信号时，第四部分的加入也可以降低电源电压信号的传输电阻，进而减小显示面板各处电源电压信号的差异，最终达到提高显示面板显示均匀性的技术效果。
本实施例的其他示例中，金属层所包括的第四部分303例如还可以连接其他信号，例如，第四部分303还可以连接时钟信号(CLK)、重置信号(INI)、栅极高电压(VGH)、栅极低电压(VGL)等。因此，金属层的第四部分303可以充分利用周边区域的空间，进而有利于显示面板的窄边框设计。
本实施例中，金属层的材料例如可以为钛、钛合金、铝、铝合金、钼、钼合金、铜和铜合金等合适的材料，也可以为这些材料的组合。例如金属层的材料可以为钛/铝/钛三层结构、钛/铝双层结构等，本实施例对此不做限定。
本实施例中，显示面板例如还可以包括平坦化层104、像素电极层105、像素界定层106、发光层107、公共电极109、隔垫物108等其他功能结构，本实施例不再赘述。发光层107夹置在像素电极层105与公共电极109之间，由此构成有机发光二极管。
本实施例提供的显示面板所包括的位于驱动电路层和衬底基板之间的图案化的金属层可以包括多个部分，其中至少第一部分可以用于连接显示面板电源电压信号，因此该部分可以减小电源电压信号的传输电阻，从而减小电源电压信号在传输时产生的压降，从而该金属层可以减小显示面板各处电源电压信号的差异，使得显示面板各个位置的显示亮度更加准确，最终达到提高显示面板显示均匀性的技术效果。例如，在显示面板在具有较大尺寸的情况下，该金属层可以有效提高显示面板的显示均匀性。
本实施例中，金属层的第二部分可以与显示面板的第一电容相结合并构成第二电容以提高像素单元的电容的总电容量。电容量的增加可以使显示面板各个像素单元的供电量更充足，从而避免像素单元在显示时出现闪烁等不良现象，因此可以提高显示面板的显示品质；另外，第一电容和第二电容可以形成并联结构，该并联结构可以提高电容的单位面积电容量，从而在所需电容一定时可以减小电容所占空间，进而有利于显示面板的高分辨率设计。
本实施例中，金属层的第三部分对应于薄膜晶体管设置，该部分可以对薄膜晶体管的沟道区进行有效保护，避免外界光线射入沟道区而产生不利影响。金属层的第四部分位于周边区域，该部分可以用于连接显示面板电源电压信号以提高显示面板显示均匀性，也可以连接其他信号，从而充分利用周边区域的空间，进而有利于显示面板的窄边框设计。
另外，本实施例中，金属层所包括的各个部分位于同一层中，因此这些 部分可以在同一工艺步骤中形成，从而可以简化显示面板的制造工艺、降低成本。
本公开至少一实施例提供一种显示面板的制造方法，该显示面板例如为如上所述的显示面板，如图4所示，该方法包括步骤S101-步骤S102。
步骤S101：在衬底基板上形成图案化的金属层。
本实施例中，显示面板例如可以分为显示区和周边区域，其中，显示区例如可以包括第一区域10和第二区域20，周边区域例如可以包括第三区域30。
本实施例中，如图5A所示，首先在衬底基板101上形成图案化的金属层。金属层例如可以包括至少用于连接显示面板电源电压信号的第一部分103A，第一部分103A例如可以形成在第一区域10中，并且第一部分103A例如可以与之后形成的显示面板的电源线相连，用于降低电源电压信号的传输电阻，减小电源电压信号在传输时产生的压降，进而减小显示面板各处电源电压信号的差异，最终达到提高显示面板显示均匀性的技术效果。
例如，金属层还可以包括形成在第一区域10中的第二部分103B，第二部分103B例如可以形成在对应于之后将要形成电容的位置，使得电容的第一极(靠近第二部分的电极)在衬底基板101上的正投影与第二部分103B在衬底基板101上的正投影至少部分重叠，从而第二部分103B可以与之后形成的电容相结合，提高其电容量。
本实施例中，如图5A所示，第一部分103A和第二部分103B例如可以为互不相连的两个独立的部分；或者，如图5B所示，第一部分103A和第二部分103B例如可以电连接；又或者，如图5C所示，第一部分103A和第二部分103B例如还可以为同一金属层结构；当第一部分103A和第二部分103B为同一金属层结构时，该结构即可以连接电源电压信号也可以与其他功能层一起构成电容。
本实施例中，金属层例如还可以包括形成在第二区域20中的第三部分203，第三部分203例如可以对应形成于之后将要形成的用于驱动显示面板发光的薄膜晶体管的位置，例如形成于薄膜晶体管的有源层或有源层中的沟道区在衬底基板101上的正投影正对的位置，使得第三部分203在衬底基板101上的正投影与薄膜晶体管的有源层1022在衬底基板上的正投影至少部 分重叠，从而第三部分203可以遮挡外界光线，以避免外界光线对薄膜晶体管的沟道区产生不良影响，例如避免光线的射入而增大薄膜晶体管的漏电流等。
本实施例中，金属层例如还可以包括形成于第三区域30中的第四部分303，第四部分303用于传输信号。例如，第四部分303也可以连接电源电压信号，从而降低电源电压信号的传输电阻，减小显示面板各处电源电压信号的差异，提高显示面板显示均匀性。
本实施例的其他示例中，金属层所包括的第四部分303例如还可以连接其他信号，例如，第四部分303还可以连接时钟信号(CLK)、重置信号(INI)、栅极高电压(VGH)、栅极低电压(VGL)等，从而第四部分303可以充分利用周边区域的空间，进而有利于显示面板的窄边框设计。
本实施例中，金属层的第一部分103A、第二部分103B、第三部分203和第四部分303例如可以通过对同一金属薄膜层通过同一掩膜板，进行一次构图工艺(例如光刻工艺)形成，从而可以简化显示面板的制造工艺。
本实施例中，金属层的材料例如可以为钛、钛合金、铝、铝合金、钼、钼合金、铜和铜合金等合适的材料，也可以为这些材料的组合。例如金属层的材料可以为钛/铝/钛三层结构、钛/铝双层结构等，本实施例对此不做限定。
本实施例中，在衬底基板101上形成图案化的金属层之前，例如可以先形成一层阻挡层1011，之后在层阻挡层1011上形成金属层，阻挡层1011可以对金属层等结构形成保护。阻挡层1011的材料例如可以为氮化硅、氧化硅、氧氮化硅等合适的材料，本实施例对此不做限定。
步骤S102：在金属层上形成像素单元。
本实施例中，在金属层形成之后，可以在金属层上形成像素单元，该像素单元例如可以包括驱动电路层以及有机发光二极管等。
本实施例中，形成驱动电路层例如可以包括形成用于驱动显示面板的多个薄膜晶体管、电容、栅线、数据线、电源线等结构；该多个薄膜晶体管可以包括驱动晶体管、开关晶体管等，栅线、数据线、电源线等例如可以从显示区域延伸到周边区域之中，并由此与栅驱动电路、数据驱动电路、电源电压端等电连接。
本实施例中，例如可以将电容形成在第一区域10中，将薄膜晶体管形 成在第二区域20中，将栅线、数据线、电源线等作为周边电路的部分形成在第三区域30中。本实施例中，电源线例如可以包括源漏导电层的一部分(稍后详述)，例如电源线包括形成于不同层上且彼此电连接的栅导电层的一部分以及源漏导电层的一部分，该电源线可以直接或间接连接到电源电压端。
如图6所示，在形成驱动电路层前，例如可以在金属层上形成一层缓冲层1021，从而金属层位于阻挡层1011及缓冲层1021之间。
本实施例中，例如可以在缓冲层1021上形成一层有源层材料，然后例如采用光刻工艺等对有源层材料进行构图，最终在第二区域中形成用于构成薄膜晶体管的有源层1022，然后对有源层1022的除沟道区之外的其他部分进行相应的导体化处理。本实施例中，缓冲层1021例如可以采用氮化硅、氧化硅、氧氮化硅等合适的材料；有源层1022例如可以采用非晶硅、多晶硅、氧化物半导体(例如IGZO)等半导体材料，本实施例对此不做限定。
如图7所示，有源层1022形成后，在整个基板表面形成第一栅绝缘层1023，之后在第一栅绝缘层1023上形成第一栅极材料层，然后采用例如光刻工艺等对第一栅极材料层进行构图以形成第一栅导电层。第一栅导电层例如可以包括位于第一区域10的部分1024A、位于第二区域20的部分1024B和位于第三区域30的部分1024C。如下所述部分1024A用于形成电容，部分1024B用于形成薄膜晶体管的栅极，部分1024C用于形成信号线等。
本实施例中，第一栅绝缘层1023例如可以采用氮化硅、氧化硅、氧氮化硅等合适的材料；第一栅导电层例如可以采用金属等导电材料，例如采用钼、铝、钛等合适的材料，本实施例对此不做限定。在本实施例的一些示例中，例如在有源层为多晶硅时，还可以采用栅导电层1024B为掩模，对于有源层1022进行掺杂。
如图8所示，第一栅导电层形成后，例如可以在整个基板上形成第二栅绝缘层1025，之后在第二栅绝缘层1025上形成第二栅极材料层，然后采用例如光刻工艺等对第二栅极材料层进行构图以形成第二栅导电层。第二栅导电层例如可以包括位于第一区域10的部分1026A和位于第三区域30的部分1026B。
例如，第二栅导电层位于第一区域10的部分1026A、第二栅绝缘层1025 和第一栅导电层的部分1024A可以构成第一电容，第一栅导电层的部分1024A作为第一电容的第一极，第二栅绝缘层1025作为第一电容的介质，第二栅导电层的部分1026A作为第一电容的第二极。本实施例中，第一栅导电层的部分1024A、缓冲层1021、第一栅绝缘层1023、金属层的第二部分103B还可以形成第二电容，并且第一电容的第二极形成为与金属层的第二部分103B电连接，由此第一电容和第二电容彼此并联。因此金属层的第二部分103B可以增大像素单元的电容的总电容量。
本实施例中，第二栅绝缘层1025例如可以采用氮化硅、氧化硅、氧氮化硅等合适的材料；第二栅导电层例如可以采用金属等导电材料，例如可以采用钼、铝、钛等合适的材料，本实施例对此不做限定。
如图9所示，第二栅导电层形成后，在整个基板表面形成一层绝缘层1027，之后可以采用构图工艺，例如光刻工艺在多个功能层中分别形成暴露出金属层、第一栅导电层和第二栅导电层的多个过孔。这些过孔例如可以包括位于第一区域10的暴露出金属层的第一部分103A的第一过孔1031，位于第三区域30的暴露出金属层的第四部分303的第二过孔3031，位于第一区域10的暴露出第二栅极的部分1026A的第三过孔1032，位于第二区域20的暴露出有源层1022的第四过孔2031和第五过孔2032，位于第三区域30的暴露出第一栅极的部分1024C的第六过孔3032以及位于第三区域30的暴露出第二栅极的部分1024B的第七过孔3033；并且，为了使得位于不同层上的导电部分更好地并联，还可以在不同位置形成更多的过孔。本实施例中，这些过孔例如可以通过一次构图工艺形成。本实施例中，绝缘层207例如可以采用氮化硅、氧化硅等合适的材料，本实施例对此不做限定。
如图10所示，在多个过孔形成后，在基板表面形成一层源漏极金属层，然后例如采用光刻工艺等对其进行构图以形成图案化的源漏导电层1028，图案化的源漏导电层1028通过上述过孔与被暴露出的金属层、第一栅导电层或第二栅导电层电连接。
本实施例中，图案化的源漏导电层1028包括形成于第一区域10的部分1028A，形成于第二区域20的部分1028B和形成于第三区域30的部分1028C。
本实施例中，源漏导电层1028在第一区域10的部分1028A例如可以与 金属层的第一部分103和第二栅导电层的部分1026A电连接，并作为为像素单元提供电源电压信号的电源线的一部分。因此，金属层的第一部分103可以与电源线彼此电连接从而与其形成并联，该并联结构可以降低电源电压信号的传输电阻，减小电源电压信号在传输时产生的压降，进而减小显示面板各处电源电压信号的差异，最终达到提高显示面板显示均匀性的技术效果。
源漏导电层1028在第二区域20的部分1028B分为两部分并分别与有源层1022电连接，形成薄膜晶体管的源极和漏极，该薄膜晶体管可以用于驱动之后形成的发光元件(有机发光二极管)。
源漏导电层1028在第三区域30的部分1028C与金属层的第四部分303、第一栅导电层的部分1024C和第二栅导电层的部分1026B电连接，这样所得到的结构可用于形成电源线，由于所得到的电源线由分布在三个不同层上的部分构成，而且彼此可以用个至少一个过孔电连接(例如并联)，由此可以降低电源线的电阻。源漏导电层1028位于第三区域30的部分1028C例如可以作为为像素单元提供电源电压信号的电源线的一部分，从而金属层的第四部分303与电源线彼此电连接从而形成并联，该并联结构可以降低电源电压信号的传输电阻，减小电源电压信号在传输时产生的压降，进而减小显示面板各处电源电压信号的差异，最终达到提高显示面板显示均匀性的技术效果。
本实施例中，源漏导电层1028例如可以金属等导电材料，例如可以采用钛、钛合金、铝、铝合金、钼、钼合金、铜和铜合金等合适的材料，本实施例对此不做限定。
如图11所示，本实施例中，显示面板的制造方法例如还可以包括在源漏导电层1028上形成平坦化层104、像素电极层105、像素界定层106、发光层107、隔垫物108等功能结构的步骤，还可以进一步形成用于形成发光元件的公共电极109以及封装结构(图中未示出)等，公共电极109与像素电极层105将发光层107夹置在其之间从而形成有机发光二极管，本实施例不再赘述。公共电极109例如电连接到另一个电源电压端。
利用本实施例提供的方法制造的显示面板包括位于驱动电路层和衬底基板之间的图案化的金属层，该金属层可以包括多个部分，其中至少第一部分可以用于连接显示面板电源电压信号，因此该部分可以减小电源电压信号 的传输电阻，从而减小电源电压信号在传输时产生的压降，进而减小显示面板各处电源电压信号的差异，使得显示面板各个位置的显示亮度更加准确，最终达到提高显示面板显示均匀性的技术效果。例如，在显示面板在具有较大尺寸的情况下，该金属层可以有效提高显示面板的显示均匀性。
本实施例中，金属层的第二部分可以与显示面板的第一电容相结合并构成第二电容以提高像素单元的电容的总电容量。电容量的增加可以使显示面板各个像素单元的供电量更充足，从而避免像素单元在显示时出现闪烁等不良现象，因此可以提高显示面板的显示品质；另外，第一电容和第二电容可以形成并联结构，该并联结构可以提高电容的单位面积电容量，从而在所需电容一定时可以减小电容所占空间，进而有利于显示面板的高分辨率设计。
本实施例中，金属层的第三部分对应于薄膜晶体管设置，可以对薄膜晶体管的沟道区进行有效保护，避免外界光线射入沟道区而产生不利影响。金属层的第四部分位于周边区域，可以用于连接显示面板电源电压信号以提高显示面板显示均匀性，也可以连接其他信号，从而充分利用周边区域的空间，进而有利于显示面板的窄边框设计。
另外，本实施例中，金属层所包括的各个部分形成在显示面板的同一层中，因此这些部分可以在同一工艺步骤中形成，例如通过同一掩膜板经过一次构图工艺形成；同时，本实施例的金属层在形成时无需再引入其他绝缘层，因而仅增加一步工艺步骤即可制备得到该金属层，因此本实施例提供的方法还可以简化显示面板的制造工艺，进而节约成本。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限 于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括：
    衬底基板；
    在所述衬底基板上的像素单元，所述像素单元包括驱动电路层；
    位于所述驱动电路层和所述衬底基板之间的图案化的金属层，所述金属层包括至少用于连接所述显示面板的电源电压信号的第一部分。
  2. 根据权利要求1所述的显示面板，其中，所述驱动电路层包括为所述像素单元提供电源电压信号的电源线，所述第一部分与所述电源线并联。
  3. 根据权利要求2所述的显示面板，其中，所述电源线包括源漏导电层的一部分。
  4. 根据权利要求1-3任一所述的显示面板，其中，所述驱动电路层包括电容和薄膜晶体管；其中，所述电容包括第一极和第二极，所述金属层还包括第二部分；所述第一极在所述第二极与所述第二部分之间，所述第一极在所述衬底基板上的正投影与所述第二部分在所述衬底基板上的正投影至少部分重叠；
    所述第二极与所述金属层的第二部分电连接。
  5. 根据权利要求4所述的显示面板，其中，所述第一部分与所述第二部分电连接。
  6. 根据权利要求4或5所述的显示面板，其中，所述金属层还包括第三部分；所述第三部分在所述衬底基板上的正投影与所述薄膜晶体管的有源层在所述衬底基板上的正投影至少部分重叠。
  7. 根据权利要求1-6任一所述的显示面板，其中，所述显示面板包括显示区和周边区域，所述金属层的第一部分位于所述显示区内，且所述金属层还包括位于所述周边区域中的第四部分；所述第四部分用于传输信号。
  8. 根据权利要求1-6任一所述的显示面板，其中，所述显示面板还包括位于所述衬底基板与所述驱动电路层之间的阻挡层及缓冲层；所述金属层在所述阻挡层及所述缓冲层之间。
  9. 一种显示面板的制造方法，包括：
    在衬底基板上形成图案化的金属层；
    在所述金属层上形成像素单元，所述像素单元包括驱动电路层；
    其中，所述金属层包括至少用于连接所述显示面板的电源电压信号的第一部分。
  10. 根据权利要求9所述的显示面板的制造方法，其中，所述驱动电路层包括为所述像素单元提供电源电压信号的电源线，所述第一部分形成为与所述电源线并联。
  11. 根据权利要求10所述的显示面板的制造方法，其中，在所述驱动电路层中形成电容和薄膜晶体管；
    所述电容包括第一极和第二极，所述金属层还包括第二部分；所述第一极形成在所述第二极与所述第二部分之间，所述第一极在所述衬底基板上的正投影与所述第二部分在所述衬底基板上的正投影至少部分重叠；
    所述第二极形成为与所述金属层的第二部分电连接。
  12. 根据权利要求11所述的显示面板的制造方法，其中，所述第一部分形成为与所述第二部分电连接。
  13. 根据权利要求11所述的显示面板的制造方法，其中，所述金属层还包括第三部分；所述第三部分在所述衬底基板上的正投影与所述薄膜晶体管的有源层在所述衬底基板上的正投影至少部分重叠。
  14. 根据权利要求13所述的显示面板的制造方法，其中，所述显示面板包括显示区和周边区域，所述金属层的第一部分形成于所述显示区内，且所述金属层还包括形成于所述周边区域中的第四部分；所述第四部分用于传输信号。
  15. 根据权利要求9-13任一所述的显示面板的制造方法，还包括在衬底基板及所述驱动电路层之间形成阻挡层及缓冲层；其中，所述金属层形成于所述阻挡层及所述缓冲层之间。
  16. 根据权利要求14所述的显示面板的制造方法，其中，在所述第一部分上的至少所述驱动电路层中形成第一过孔使得所述第一部分能够通过第一过孔与所述电源线连接。
  17. 根据权利要求16所述的显示面板的制造方法，其中，在所述第四部分上的至少所述驱动电路层中形成第二过孔使得所述第四部分能够通过第二过孔与至少所述电源线连接。
  18. 根据权利要求17所述的显示面板的制造方法，其中，所述第一过孔和所述第二过孔通过同一掩膜板形成。
  19. 根据权利要求14所述的显示面板的制造方法，其中，所述第一部分，所述第二部分，所述第三部分和所述第四部分通过同一掩膜板形成。
  20. 一种显示装置，包括根据权利要求1-8任一所述的显示面板。
PCT/CN2018/105454 2017-09-15 2018-09-13 显示面板及其制造方法、显示装置 WO2019052502A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18856212.8A EP3683839A4 (en) 2017-09-15 2018-09-13 DISPLAY BOARD AND MANUFACTURING METHOD FOR IT, AND DISPLAY DEVICE
US16/337,528 US20190229169A1 (en) 2017-09-15 2018-09-13 Display panel and manufacturing method therefor, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710840388.XA CN109509768B (zh) 2017-09-15 2017-09-15 显示面板及其制造方法、显示装置
CN201710840388.X 2017-09-15

Publications (1)

Publication Number Publication Date
WO2019052502A1 true WO2019052502A1 (zh) 2019-03-21

Family

ID=65723182

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/105454 WO2019052502A1 (zh) 2017-09-15 2018-09-13 显示面板及其制造方法、显示装置

Country Status (4)

Country Link
US (1) US20190229169A1 (zh)
EP (1) EP3683839A4 (zh)
CN (1) CN109509768B (zh)
WO (1) WO2019052502A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109136833B (zh) * 2018-08-29 2021-01-19 上海天马有机发光显示技术有限公司 显示面板、掩膜板、显示面板的制作方法及显示装置
CN109147661B (zh) * 2018-09-30 2021-02-26 武汉天马微电子有限公司 一种显示面板及显示装置
CN110148599B (zh) * 2019-04-28 2023-06-30 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
EP3918635A4 (en) * 2019-05-03 2022-04-06 Samsung Electronics Co., Ltd. LIGHT EMITTING DIODE MODULE
EP4020443A4 (en) 2019-08-21 2023-01-11 BOE Technology Group Co., Ltd. DISPLAY DEVICE SUBSTRATE, METHOD OF MAKING THEREOF, AND DISPLAY DEVICE
US11900884B2 (en) 2019-08-21 2024-02-13 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate having a scan driving circuit with a plurality of shift registers and manufacturing method thereof, display device
CN112740434B (zh) 2019-08-23 2023-07-25 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN113724592B (zh) * 2021-08-27 2023-10-10 京东方科技集团股份有限公司 一种显示模组及显示装置
CN114038423B (zh) 2021-12-09 2023-03-21 京东方科技集团股份有限公司 显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544054A (zh) * 2010-12-14 2012-07-04 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN103646950A (zh) * 2013-09-12 2014-03-19 友达光电股份有限公司 像素结构
CN107039491A (zh) * 2015-12-29 2017-08-11 乐金显示有限公司 有机发光显示装置及其制造方法
CN207134358U (zh) * 2017-09-15 2018-03-23 京东方科技集团股份有限公司 显示面板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100696518B1 (ko) * 2005-05-02 2007-03-19 삼성에스디아이 주식회사 평판표시장치
US7507998B2 (en) * 2006-09-29 2009-03-24 Tpo Displays Corp. System for displaying images and method for fabricating the same
KR100964227B1 (ko) * 2008-05-06 2010-06-17 삼성모바일디스플레이주식회사 평판 표시 장치용 박막 트랜지스터 어레이 기판, 이를포함하는 유기 발광 표시 장치, 및 이들의 제조 방법
CN103309105B (zh) * 2013-07-05 2016-02-03 北京京东方光电科技有限公司 阵列基板及其制备方法、显示装置
JP6169005B2 (ja) * 2014-01-17 2017-07-26 株式会社ジャパンディスプレイ 発光素子表示装置
JP6258047B2 (ja) * 2014-01-27 2018-01-10 株式会社ジャパンディスプレイ 発光素子表示装置
KR20160005814A (ko) * 2014-07-07 2016-01-18 엘지디스플레이 주식회사 유기발광 다이오드 표시장치 및 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102544054A (zh) * 2010-12-14 2012-07-04 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN103646950A (zh) * 2013-09-12 2014-03-19 友达光电股份有限公司 像素结构
CN107039491A (zh) * 2015-12-29 2017-08-11 乐金显示有限公司 有机发光显示装置及其制造方法
CN207134358U (zh) * 2017-09-15 2018-03-23 京东方科技集团股份有限公司 显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3683839A4 *

Also Published As

Publication number Publication date
CN109509768A (zh) 2019-03-22
CN109509768B (zh) 2024-06-04
US20190229169A1 (en) 2019-07-25
EP3683839A1 (en) 2020-07-22
EP3683839A4 (en) 2021-06-09

Similar Documents

Publication Publication Date Title
WO2019052502A1 (zh) 显示面板及其制造方法、显示装置
US10038046B2 (en) Organic light emitting diode display
JP7299023B2 (ja) タッチ表示パネル及びその駆動方法、電子装置
EP3503238B1 (en) Display device
US9070896B2 (en) Organic light emitting diode display
US11552151B2 (en) Display device and method for manufacturing display device
JP4353237B2 (ja) 画素回路および表示装置、並びに画素回路の製造方法
KR102044314B1 (ko) 유기 발광 표시 장치
WO2011064819A1 (ja) 発光表示装置
US10916613B1 (en) Array substrate and OLED display device
JP2005338781A (ja) 有機電界発光表示パネル及びその製造方法
TWI730542B (zh) 顯示裝置
US11527595B2 (en) Light emitting apparatus, imaging apparatus, electronic apparatus, illumination apparatus, and mobile apparatus
JP2011114346A (ja) 発光表示装置
US10665820B2 (en) Display device
US20140097419A1 (en) Organic light emitting diode display and method for manufacturing the same
US7969391B2 (en) Pixel circuit, display device, and method of manufacturing pixel circuit
KR102029169B1 (ko) 디스플레이 장치와 이의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18856212

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018856212

Country of ref document: EP

Effective date: 20200415