WO2019051924A1 - 静电放电防护电路及其应用的显示装置 - Google Patents

静电放电防护电路及其应用的显示装置 Download PDF

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Publication number
WO2019051924A1
WO2019051924A1 PCT/CN2017/107022 CN2017107022W WO2019051924A1 WO 2019051924 A1 WO2019051924 A1 WO 2019051924A1 CN 2017107022 W CN2017107022 W CN 2017107022W WO 2019051924 A1 WO2019051924 A1 WO 2019051924A1
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Prior art keywords
switch
level line
potential
node
electrically coupled
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PCT/CN2017/107022
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English (en)
French (fr)
Inventor
何怀亮
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惠科股份有限公司
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Priority to US15/743,256 priority Critical patent/US10873182B2/en
Publication of WO2019051924A1 publication Critical patent/WO2019051924A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H05F3/02—Carrying-off electrostatic charges by means of earthing connections

Definitions

  • the present invention relates to an electrostatic discharge protection circuit and a display device using the same, and more particularly to an electrostatic discharge protection circuit composed of a plurality of switch components and a display device using the same .
  • Static electricity is a positive or negative charge formed by the surface of an object causing a charge imbalance for some reason.
  • ESD Electrostatic Discharge
  • the electrostatic voltage is 2000V, the human body does not feel it, but the electrostatic sensitive components used in our production will be damaged, because CMOS integrated circuit devices can only withstand voltages of 250 ⁇ 2000V, exceeding this voltage will cause damage.
  • Electrostatic discharge can break down the dielectric chip dielectric, fuse the core wire, increase the leakage current, accelerate the aging, change the electrical performance parameters, and so on.
  • an electrostatic discharge protection circuit is generally designed on the liquid crystal display panel.
  • the ESD protection circuit fabricated next to the pixel array must be able to conduct early to discharge the electrostatic discharge current. Therefore, the components used in the ESD protection circuit must have a lower breakdown voltage or a faster conduction speed.
  • NTFT all-N active switching
  • PTFT full P-type active switching
  • the lines of the high-level line and the low-level line are usually very thin, so that the lines connected to the upper and lower ends of the equivalent diode assembly respectively form a large equivalent resistance, so the current discharged is relatively small, which is disadvantageous for Static discharge.
  • an object of the present application is to provide an electrostatic discharge protection circuit capable of increasing a discharge path to increase the speed of electrostatic discharge.
  • the electric protection circuit includes: a first switch, the control end of the first switch is electrically coupled to the first node, the first end of the first switch is electrically coupled to the ground node, and the second end of the first switch The terminal is electrically coupled to the signal input node; the capacitor is electrically coupled between the first node and the signal input node; and the second switch is electrically coupled to the first end of the second switch a first level line, the second end of the second switch is electrically coupled to the signal input node; the third switch, the control end of the third switch is electrically coupled to the second level line, and the third switch The first end is electrically coupled to the first node, and the second end of the third switch is electrically coupled to the first level line.
  • the signal input node obtains static electricity
  • the potential of the static electricity does not meet the potential of the second level line
  • the capacitance is regulated by the static electricity to adjust the potential of the first node to open the The first switch and the third switch
  • the static electricity is discharged through the first switch and the third switch toward the ground node and the first level line.
  • the first switch, the second switch, and the third switch are N-type transistors, and the first level line is a low level line, and the second level The line is a high level line.
  • the potential of the first node is equal to the potential of the low level line, and the first switch is turned off.
  • the signal input node obtains a positive potential static electricity, and when the potential of the positive potential static electricity is between the potential between the high level line and the low level line, the first A switch and the third switch are closed.
  • the first switch, the second switch, and the third switch are P-type transistors, and the first level line is a high level line, and the second level The line is a low level line.
  • the potential of the first node is equal to the potential of the high level line, and the first switch is turned off.
  • the signal input node obtains a negative potential static electricity, and when the potential of the negative potential static electricity is between the potential between the high level line and the low level line, the first A switch and the third switch are closed.
  • the capacitor when the potential of the static electricity is between the potential of the second level line and the first level line, the capacitor forms an open circuit to lower the first node. Potential.
  • the second object of the present application is an ESD protection circuit, comprising: a first switch, the control end of the first switch is electrically coupled to the first node, and the first end of the first switch is electrically coupled to the ground a node, the second end of the first switch is electrically coupled to the signal input node; the capacitor is electrically coupled between the first node and the signal input node; and the second switch is configured by the second switch The control end is electrically coupled to the first end of the first level line, the second end of the second switch is electrically coupled to the signal input node, and the third switch is electrically coupled to the control end of the third switch.
  • the input node obtains static electricity, the potential of the static electricity does not meet the potential of the second level line, and the capacitance is regulated by the static electricity to raise the potential of the first node to Opening the first switch and the third switch to electrically couple the first node to the first level line, and the static electricity passes through the first switch and the third switch to face the first switch
  • the ground node is vented with the first level line; when the potential of the static electricity is at a potential between the first level line and the second level line, the capacitance forms an open circuit to reduce the number a potential of a node to turn off the first switch and the third switch; the ground node is electrically coupled to a ground line or a common voltage line; an operating current of the first switch and the second switch is 1 ⁇ A For the following.
  • Still another object of the present application is a display panel comprising a display panel; and an electrostatic discharge protection circuit of the technical features of any of the above embodiments.
  • the present application increases the speed and power of the electrostatic discharge by increasing the discharge path to prevent the internal wiring or components of the liquid crystal display panel from being damaged by electrostatic discharge.
  • the circuit improvement is simple and easy, and it also helps to improve the reliability of the circuit; it can be used for the manufacture of panels of various sizes, and the applicability is relatively high.
  • Figure 1a is a schematic diagram of an exemplary electrostatic discharge protection circuit.
  • Figure 1b is a schematic diagram of an exemplary electrostatic discharge protection circuit.
  • Figure 1c is a schematic diagram of a theoretical equivalent circuit of an exemplary electrostatic discharge protection circuit.
  • Figure 1d is a schematic diagram of a practical equivalent circuit of an exemplary ESD protection circuit.
  • FIG. 2a is a schematic diagram showing an embodiment of an application to an electrostatic discharge protection circuit in accordance with the method of the present application.
  • 2b is a schematic diagram showing an embodiment of an application to an electrostatic discharge protection circuit in accordance with the method of the present application.
  • 3a is a schematic diagram showing an embodiment of an application to an electrostatic discharge protection circuit in accordance with the method of the present application.
  • 3b is a schematic diagram showing an embodiment of an application to an electrostatic discharge protection circuit in accordance with the method of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means that it is above or below the target component, and not It means that it must be on the top based on the direction of gravity.
  • the display panel of the present application may include a thin film transistor (TFT) substrate and a color filter (CF) substrate.
  • TFT thin film transistor
  • CF color filter
  • the display panel of the present application may be a curved display panel.
  • the active array (TFT) and color filter layer (CF) of the present application can be formed on the same substrate.
  • FIG. 1a is a schematic diagram of an exemplary electrostatic discharge protection circuit.
  • an ESD protection circuit includes a first switch T10 and a second switch T20, all of which are N-type active switches (NTFTs).
  • the first end T11 of the first switch T10 is a drain (D)
  • the second end T12 of the first switch T10 is a source (S)
  • the control end T13 of the first switch T10 is a gate ( G)
  • the first end T21 of the second switch T20 is a drain (D)
  • the second end T22 of the second switch T20 is a source (S)
  • the control end T23 of the second switch T20 is Gate (G).
  • the control terminal T13 of the first switch T10 is connected to the first terminal T11, and the control terminal T23 of the second switch T20 is connected to the first terminal T21.
  • the second end T12 of the first switch T10 is electrically coupled to the high-level line VGH, and the first end T21 of the second switch T20 is electrically coupled to the low-level line VGL, and the first switch T10 and the second switch T20 are connected to the node. It is more connected to the signal input contact P, thus forming an electrostatic protection circuit.
  • FIG. 1b is a schematic diagram of an exemplary electrostatic discharge protection circuit.
  • an ESD protection circuit includes a first switch T10 and a second switch T20, both of which are P-type active switches (PTFTs).
  • the first end T11 of the first switch T10 is a drain (D)
  • the second end T12 of the first switch T10 is a source (S)
  • the control end T13 of the first switch T10 is a gate ( G)
  • the first end T21 of the second switch T20 is a drain (D)
  • the second end T22 of the second switch T20 is a source (S)
  • the control end T23 of the second switch T20 is Gate (G).
  • the control terminal T13 of the first switch T10 is connected to the first terminal T11, and the control terminal T23 of the second switch T20 is connected to the first terminal T21.
  • the first end T11 of the first switch T10 is electrically coupled to the high-level line VGH, the second end T22 of the second switch T20 is electrically coupled to the low-level line VGL, and the first switch T10 and the second switch T20 are connected to the node. It is more connected to the signal input contact P, thus forming an electrostatic protection circuit.
  • FIG. 1c is a schematic diagram of a theoretical equivalent circuit of an exemplary electrostatic discharge protection circuit, which is a schematic diagram of a theoretical equivalent circuit of the electrostatic discharge protection circuit shown in FIG. 1a and FIG.
  • the gate (gate) of the N-type active switch is often connected to the drain (Drain) to form an equivalent diode assembly.
  • FIG. 1d is a schematic diagram of a practical equivalent circuit of an exemplary ESD protection circuit, which is a practical equivalent circuit diagram of the ESD protection circuit shown in FIGS. 1a and 1b.
  • the line widths of the high-level line VGH and the low-level line VGL are relatively thin, so that the second terminal T12 line of the first switch T10 and the first end T21 line of the second switch T20 are generated.
  • the equivalent resistance (R1, R2) is relatively large, so the electrostatic current I1 or I2 relative to the discharge is relatively small.
  • an ESD protection circuit 300 includes a first switch T10.
  • the control terminal T13 of the first switch T10 is electrically coupled to the first node A, and the first end T11 of the first switch T10. Electrically coupled to the ground node GND, the second end T12 of the first switch T10 is electrically coupled to the signal input node P; the capacitor C is electrically coupled to the first node A and the signal input node P.
  • the second switch T20, the control terminal T23 of the second switch T20 is electrically coupled to the first level line T21, and the second end T22 of the second switch T20 is electrically coupled to the signal input node.
  • the control terminal T33 of the third switch T30 is electrically coupled to the second level line
  • the first end T31 of the third switch T30 is electrically coupled to the first node A
  • the second end T32 of the third switch T30 is electrically coupled to the first level line.
  • the signal input node P acquires static electricity
  • the potential of the static electricity does not meet the potential of the second level line
  • the capacitance C is regulated by the static electricity to adjust the potential of the first node A
  • the static electricity is discharged through the first switch T10 and the third switch T30 toward the ground node GND and the first level line .
  • the ground node GND is electrically coupled to a ground line or a common voltage line.
  • the signal input node P is electrically coupled to a line transmitting a signal or a power source, such as a data line, a gate line, and a gamma voltage line.
  • a line transmitting a signal or a power source such as a data line, a gate line, and a gamma voltage line.
  • the same, related, and similar lines such as the reference voltage line (Vref Line), the timing control line (CK Line), the enable line (OE Line), etc., but are not limited thereto, as long as the line with the transmission signal or power supply is applicable. .
  • the capacitance when the potential of the static electricity is between the potential of the second level line and the first level line, the capacitance forms an open circuit to lower the potential of the first node.
  • the first switch T10, the second switch T20, and the third switch T30 are depletion transistors.
  • the first end T11 of the first switch T10 is a drain (D)
  • the second end T12 of the first switch T10 is a source (S)
  • the control of the first switch T10 The terminal T13 is a gate (G); the first terminal T21 of the second switch T20 is a drain (D), and the second terminal T22 of the second switch T20 is a source (S), the second switch
  • the control terminal T23 of the T20 is the gate (G);
  • the first terminal T31 of the third switch T30 is the drain (D), and the second terminal T32 of the third switch T30 is the source (S),
  • the control terminal T33 of the third switch T30 is the gate (G).
  • FIG. 2b is a schematic diagram showing an embodiment of an electrostatic discharge protection circuit according to the method of the present application, which is a practical equivalent circuit diagram of the electrostatic discharge protection circuit shown in FIG. 2a.
  • the first switch T10, the second switch T20, and the third switch T30 are N-type transistors, and the first level line is a low-level line VGL, The second level line is a high level line VGH.
  • the line widths of the high-level line VGH and the low-level line VGL are relatively thin, so that the first terminal T11 line of the first switch T10 and the first end T21 line of the second switch T20 are blocked.
  • the equivalent resistance is relatively large.
  • a first equivalent resistance R1' is formed between the first switch T10 and the ground node GND, and a second equivalent is formed between the second switch T20 and the low-level line VGL. Resistor R2.
  • the signal input node P takes a positive potential electrostatic, and the potential of the positive potential electrostatic is higher than the potential of the high level line VGH.
  • the capacitor C is affected by the positive potential static electricity. In combination with the capacitive coupling effect, the voltage across the capacitor C is increased, thereby raising the potential of the first node A to open the first switch T10.
  • the drain (D) of the first switch T10 that is, the first terminal T11 is connected to the ground node GND, such as a ground line (GND) or a common voltage line (Vcom).
  • the line width of the ground line or the common voltage line is much larger than the line width of the low-level line VGL, so R1' will be smaller than R1, and the generated current I1' is also larger than the original I1.
  • the potential of the first node A is increased, which causes the third switch T30 to be turned on, thereby generating a current I3, thereby forming another electrostatic discharge path. Therefore, through the third switch T30, the positive potential static electricity introduced by the signal input node P can be discharged to the low level line VGL. Therefore, the amount of current that can be discharged by the electrostatic path is the sum of the current I1' and the current I3, and the total amount of the bleed current is much more than the current I1, so that the electrostatic energy has a better protection effect.
  • the potential of the first node A when the positive potential is electrostatically drained, the potential of the first node A will gradually decrease.
  • the first switch T10 is turned off once the potential of the first node A is equal to the potential of the low level line VGL.
  • the capacitor C can be regarded as an open circuit in the direct current, and has the characteristics of blocking DC, AC, and high frequency blocking low frequency. Therefore, when the positive potential static generated by the signal input node P is at a potential between the high-level line VGH and the low-level line VGL, the first switch T10 and the first The three switches T30 are off, and the capacitor C is open in the circuit.
  • an ESD protection circuit 300 includes a first switch T10.
  • the control terminal T13 of the first switch T10 is electrically coupled to the first node A, and the first end T11 of the first switch T10. Electrically coupled to the ground node GND, the second end T12 of the first switch T10 is electrically coupled to the signal input node P; the capacitor C is electrically coupled to the first node A and the signal input node P.
  • the second switch T20, the control terminal T23 of the second switch T20 is electrically coupled to the first level line T21, and the second end T22 of the second switch T20 is electrically coupled to the signal input node.
  • control terminal T33 of the third switch T30 is electrically coupled to the second level line
  • first end T31 of the third switch T30 is electrically coupled to the first node A
  • the second end T32 of the third switch T30 is electrically coupled to the first level line.
  • the first switch T10, the second switch T20, and the third switch T30 are P-type transistors, and the first level line is a high level line VGH, and the second power The flat line is the low level line VGL.
  • the first end T11 of the first switch T10 is a drain (D)
  • the second end T12 of the first switch T10 is a source (S)
  • the control of the first switch T10 The terminal T13 is a gate (G); the first terminal T21 of the second switch T20 is a drain (D), and the second terminal T22 of the second switch T20 is a source (S), the second switch
  • the control terminal T23 of the T20 is the gate (G);
  • the first terminal T31 of the third switch T30 is the drain (D), and the second terminal T32 of the third switch T30 is the source (S),
  • the control terminal T33 of the third switch T30 is the gate (G).
  • FIG. 3b is a schematic diagram showing an embodiment of an electrostatic discharge protection circuit according to the method of the present application, which is a practical equivalent circuit diagram of the ESD protection circuit shown in FIG. 2a.
  • the line widths of the high-level line VGH and the low-level line VGL are relatively thin, so that the line of the first end T21 of the second switch T20 and the line of the first end T11 of the first switch T10 are blocked.
  • the equivalent resistance is relatively large.
  • a first equivalent resistance R1 is formed between the second switch T20 and the high level line VGH
  • a second equivalent resistance is formed between the first switch T10 and the ground node GND. R2'.
  • the signal input node P takes a negative potential electrostatic, and the negative potential electrostatic potential is lower than the potential of the low level line VGL.
  • the capacitor C is electrostatically affected by the negative potential. In combination with the capacitive coupling effect, the voltage across the capacitor C is reduced, thereby reducing the potential of the first node A to open the first switch T10.
  • the drain (D) of the first switch T10 that is, the first terminal T11 is connected to the ground node GND, such as a ground line (GND) or a common voltage line (Vcom).
  • the line width of the ground line or the common voltage line is much larger than the line width of the low-level line VGL, so R2' will be smaller than R2, and the generated current I2' is also larger than the original I2.
  • the potential of the first node A is lowered, which causes the third switch T30 to be turned on, thereby generating a current I3, thereby forming another electrostatic discharge path. Therefore, through the third switch T30, the negative potential static electricity introduced by the signal input node P can be discharged to the high level line VGH. Therefore, the amount of current that can be discharged by the electrostatic path is the sum of the current I2' and the current I3, and the total amount of the bleed current is much more than the current I2, so that the electrostatic energy has a better protection effect.
  • the potential of the first node A when the negative potential is electrostatically drained, the potential of the first node A will gradually increase. Once the first section When the potential of the point A is equal to the potential of the high-level line VGL, the first switch T10 is turned off.
  • the capacitor C can be regarded as an open circuit in the direct current, and has the characteristics of blocking DC, AC, and high frequency blocking low frequency. Therefore, when the negative potential of the signal input node P is static, and the potential is between the potential of the high-level line VGH and the low-level line VGL, the first switch T10 and the first The three switches T30 are off, and the capacitor C is open in the circuit.
  • an ESD protection circuit of the present application includes: a first switch T10, the control terminal T13 of the first switch T10 is electrically coupled to the first node A, and the first switch T10
  • the first end T11 is electrically coupled to the ground node GND
  • the second end T12 of the first switch T10 is electrically coupled to the signal input node P
  • the capacitor C is electrically coupled to the first node A and the
  • the second switch T20, the control terminal T23 of the second switch T20 is electrically coupled to the first terminal T21, and the second terminal T22 of the second switch T20 is electrically connected.
  • the first input end T31 of the third switch T30 is electrically coupled to the first level, and the first end T31 of the third switch T30 is electrically coupled to the first The node A, the second end T32 of the third switch T30 is electrically coupled to the first level line; wherein the signal input node P acquires static electricity, and the potential of the static electricity does not meet the second level a potential of the line, the capacitor C being regulated by the static electricity to adjust a potential of the first node A to open the first opening Turning off T10 and the third switch T30, the static electricity is discharged through the first switch T10 and the third switch T30 toward the ground node GND and the first level line, the first switch The operating current of T10 and the second switch T20 is 1 ⁇ A or less.
  • a display device of the present application includes a control module, a display panel, and an electrostatic discharge protection circuit including the technical features of any of the above embodiments.
  • the control module provides a control signal and a power signal.
  • the driving circuit of the display panel receives the signals, it is necessary to transmit the necessary data and power to the display area, so that the display panel obtains the power and signal for presenting the screen. .
  • the ESD protection circuit 300 includes: a first switch T10, the control terminal T13 of the first switch T10 is electrically coupled to the first node A, and the first end T11 of the first switch T10 is electrically coupled The grounding node GND, the second end T12 of the first switch T10 is electrically coupled to the signal input node P; the capacitor C is electrically coupled between the first node A and the signal input node P; The switch T20, the control terminal T23 of the second switch T20 is electrically coupled to the first level line T21, and the second end T22 of the second switch T20 is electrically coupled to the signal input node P; a switch, the control terminal T33 of the third switch T30 is electrically coupled to the second level line, the first end T31 of the third switch T30 is electrically coupled to the first node A, and the third switch T30 The second end T32 is electrically coupled to the first level line; the potential of the first level line and the second level line connected by the electrostatic discharge protection circuit 300 is controlled by a control module;
  • the present application increases the speed and power of the electrostatic discharge by increasing the discharge path to avoid electrostatic discharge caused by the inside of the liquid crystal display panel. Damage to the line or component.
  • the circuit improvement is simple and easy, and it also helps to improve the reliability of the circuit; it can be used for the manufacture of panels of various sizes, and the applicability is relatively high.

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Abstract

一种静电放电防护电路（300）及其应用的显示装置，静电放电防护电路（300）包括第一开关（T10），第一开关（T10）的控制端（T13）电性耦接第一节点（A），第一开关（T10）的第一端（T12）电性耦接接地节点（GND），第一开关（T10）的第二端（T11）电性耦接信号输入节点（P）；电容（C），电性耦接于第一节点（A）与信号输入节点（P）之间；第二开关（T20），第二开关（T20）的控制端（T23）与第一端（T22）电性耦接低电平线路（VGL），第二开关（T20）的第二端（T21）电性耦接信号输入节点（P）；第三开关（T30），第三开关（T30）的控制端（T33）电性耦接高电平线路（VGH），第三开关（T30）的第一端（T31）电性耦接第一节点（A），第三开关（T30）的第二端（T32）电性耦接低电平线路（VGL）。通过打开第一开关（T10）与第三开关（T30），使静电朝向接地节点（GND）与第一电平线路（VGL）泄放。

Description

静电放电防护电路及其应用的显示装置 技术领域
本发明是有关于一种静电放电防护电路及使用此静电放电防护电路的显示装置，且特别是有关于一种由多个开关组件构成的静电放电防护电路及使用此静电放电防护电路的显示装置。
背景技术
静电(电荷)是物体的表面由于某种原因造成电荷不平衡而形成的正电荷或负电荷。当电荷发生转移，不同电位互相放电时，就会发生静电放电(Electrostatic Discharge，ESD)。在静电电压为2000V时，人体则感觉不到它，但是我们生产所使用的静电敏感元器件却会受其损坏，因为CMOS集成电路器件只能承受250～2000V的电压，超过此电压就会造成损坏。静电放电可使集成电路芯片介质击穿，芯线熔断，漏电流增大加速老化，电性能参数改变等等。
目前，液晶面板电路的静电放电现象比较严重，电路受到静电放电损伤的情形已经非常普遍。为防止静电放电造成液晶显示面板的内部线路或组件的毁损，特别是对于主动开关(Thin film transistor，TFT)，一般会在液晶显示面板上设计静电放电防护电路。当静电放电电压出现在画素阵列上时，制作于该画素阵列旁的ESD防护电路必须要能够及早地导通来排放静电放电电流。因此，静电防护电路内所使用的组件必须要具有较低的崩溃电压(breakdown voltage)或较快的导通速度。
就a-Si来说，不论是全N型主动开关(NTFT)或全P型主动开关(PTFT)制程下，常将主动开关的栅极与漏极相接，即可形成一个等效二极管组件，以两个等效组件为一组，两端分别电性耦接高电平线路(VGH)与低电平线路(VGL)，两组件连接的节点再连接信号线路或电源线路，如此形成静电防护电路。当高压静电进入信号线路或电源线路时，无论此高压静电是正电压或是负电压，都会有一组正向或反向的等效二极管组件与此高压静电相对应，以通过二极管单向导通的特性，将正电压或负电压排掉。
但高电平线路与低电平线路的线路通常很细，如此等效二极管组件的上下端所连接线路会分别形成较大的等效电阻，所以泄流的电流就会相对较小，不利于静电疏泄。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种静电放电防护电路，能增加泄流路径以加大静电泄流的速度。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种静电放 电防护电路，包括：第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接接地节点，所述第一开关的第二端电性耦接信号输入节点；电容，电性耦接于所述第一节点与所述信号输入节点之间；第二开关，所述第二开关的控制端与第一端电性耦接第一电平线路，所述第二开关的第二端电性耦接信号输入节点；第三开关，所述第三开关的控制端电性耦接第二电平线路，所述第三开关的第一端电性耦接所述第一节点，所述第三开关的第二端电性耦接所述第一电平线路。其中，所述信号输入节点取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容受所述静电而调压以调整所述第一节点的电位，以打开所述第一开关与所述第三开关，所述静电通过所述第一开关与所述第三开关以朝向所述接地节点与所述第一电平线路泄放。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述第一开关、所述第二开关与所述第三开关为N型晶体管，所述第一电平线路为低电平线路，所述第二电平线路为高电平线路。
在本申请的一实施例中，所述第一节点的电位等同所述低电平线路的电位，所述第一开关被关闭。
在本申请的一实施例中，所述信号输入节点取得正电位静电，所述正电位静电的电位介于所述高电平线路与所述低电平线路之间的电位时，所述第一开关与所述第三开关为关闭。
在本申请的一实施例中，所述第一开关、所述第二开关与所述第三开关为P型晶体管，所述第一电平线路为高电平线路，所述第二电平线路为低电平线路。
在本申请的一实施例中，所述第一节点的电位等同所述高电平线路的电位，所述第一开关被关闭。
在本申请的一实施例中，所述信号输入节点取得负电位静电，所述负电位静电的电位介于所述高电平线路与所述低电平线路之间的电位时，所述第一开关与所述第三开关为关闭。
在本申请的一实施例中，所述静电的电位介于所述第二电平线路与所述第一电平线路之间的电位时，所述电容形成断路以调降所述第一节点的电位。
本申请的次一目的为一种静电放电防护电路，包括：第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接接地节点，所述第一开关的第二端电性耦接信号输入节点；电容，电性耦接于所述第一节点与所述信号输入节点之间；第二开关，所述第二开关的控制端与第一端电性耦接第一电平线路，所述第二开关的第二端电性耦接信号输入节点；第三开关，所述第三开关的控制端电性耦接第二电平线路，所述第三开关的第一端电性耦接所述第一节点，所述第三开关的第二端电性耦接所述第一电平线路；其中，所述信号输入节点取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容受所述静电而调压以调升所述第一节点的电位，以打 开所述第一开关与所述第三开关，使所述第一节点电性耦接所述第一电平线路，所述静电通过所述第一开关与所述第三开关以朝向所述接地节点与所述第一电平线路泄放；所述静电的电位位于所述第一电平线路与所述第二电平线路之间电位时，所述电容形成断路以调降所述第一节点的电位，以关闭所述第一开关与所述第三开关；所述接地节点电性耦接接地线或共同电压线；所述第一开关与所述第二开关的工作电流为1μA为以下。
本申请的又一目的为一种显示面板，其包括显示面板；以及上述任何一种实施例的技术特征的静电放电防护电路。
本申请通过增加泄流路径以加大静电泄流的速度与电量，避免静电放电造成液晶显示面板的内部线路或组件的毁损。电路改进简便易行，亦有助提升电路可靠性；能使用于各种尺寸面板的制作，适用性相对较高。
附图说明
图1a为范例性的静电放电防护电路示意图。
图1b为范例性的静电放电防护电路示意图。
图1c为范例性的静电放电防护电路的理论等效电路示意图。
图1d为范例性的静电放电防护电路的实际等效电路示意图。
图2a为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图。
图2b为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图。
图3a为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图。
图3b为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见、便于理解和描述，对组件作了夸大的绘示。将理解的是，当组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不 意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种静电放电防护电路及其应用的显示装置，其具体实施方式、结构、特征及其功效，详细说明如后。
本申请的显示面板可包括主动阵列(thin film transistor，TFT)基板及彩色滤光层(color filter，CF)基板。
在一些实施例中，本申请的显示面板可为曲面型显示面板。
在一些实施例中，本申请的主动阵列(TFT)及彩色滤光层(CF)可形成于同一基板上。
图1a为范例性的静电放电防护电路示意图。请参照图1a，一种静电放电防护电路，包括第一开关T10与第二开关T20，其皆是N型主动开关(NTFT)。所述第一开关T10的第一端T11为漏极(D)，所述第一开关T10的第二端T12为源极(S)，所述第一开关T10的控制端T13为栅极(G)；所述第二开关T20的第一端T21为漏极(D)，所述第二开关T20的第二端T22为源极(S)，所述第二开关T20的控制端T23为栅极(G)。所述第一开关T10的控制端T13与第一端T11相连，所述第二开关T20的控制端T23与第一端T21相连。第一开关T10的第二端T12电性耦接高电平线路VGH，第二开关T20的第一端T21电性耦接低电平线路VGL，第一开关T10与第二开关T20所连接节点，其更连接信号输入接点P，如此形成静电防护电路。
图1b为范例性的静电放电防护电路示意图。请参照图1b，一种静电放电防护电路，包括第一开关T10与第二开关T20，其皆是P型主动开关(PTFT)。所述第一开关T10的第一端T11为漏极(D)，所述第一开关T10的第二端T12为源极(S)，所述第一开关T10的控制端T13为栅极(G)；所述第二开关T20的第一端T21为漏极(D)，所述第二开关T20的第二端T22为源极(S)，所述第二开关T20的控制端T23为栅极(G)。所述第一开关T10的控制端T13与第一端T11相连，所述第二开关T20的控制端T23与第一端T21相连。第一开关T10的第一端T11电性耦接高电平线路VGH，第二开关T20的第二端T22电性耦接低电平线路VGL，第一开关T10与第二开关T20所连接节点，其更连接信号输入接点P，如此形成静电防护电路。
图1c为范例性的静电放电防护电路的理论等效电路示意图，其为图1a与图1b所示静电放电防护电路的理论等效电路示意图。就a-Si来说，全N型主动开关(NTFT)制程下，常将N型主动开关的栅极(Gate)与漏极(Drain)相接，即可形成一个等效二极管组件。所以，所述第一开关T10的控制端T13与第一端T11相连与所述第二开关T20的控制端T23与第一端T21相连后，所述第一开关T10与所述第二开关T20分别形成一个等效二极管组件，以两个等效组件为一组，其两端分别电性耦接高电平线路VGH与低电平线路VGL，两组件连接的节点再连接信号输入接点P。就a-Si 来说，全P型主动开关(PTFT)制程下，常将P型主动开关的栅极(Gate)与漏极(Drain)相接，即可形成一个等效二极管组件。所以，所述第一开关T10的控制端T13与第一端T11相连与所述第二开关T20的控制端T23与第一端T21相连后，所述第一开关T10与所述第二开关T20分别形成一个等效二极管组件，以两个等效组件为一组，其两端分别电性耦接高电平线路VGH与低电平线路VGL，两组件连接的节点再连接信号输入接点P。
当高压静电进入所述信号输入接点P时，无论所述高压静电是正电压或是负电压，都会有一组正向或反向的等效二极管组件与所述高压静电相对应。通过二极管单向导通的特性，所述高压静电的正、负电荷即可迅速通往高电平线路和低电平线路泄放，以将正电压或负电压排掉。
图1d为范例性的静电放电防护电路的实际等效电路示意图，其为图1a与图1b所示静电放电防护电路的实际等效电路示意图。如图1c所示，一般高电平线路VGH和低电平线路VGL的线宽比较细，因此所述第一开关T10的第二端T12线路与第二开关T20的第一端T21线路会产生阻值相对较大的等效电阻(R1，R2)，所以相对泄流的静电电流I1或I2就相对较小。
图2a为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图。请参照图2a，一种静电放电防护电路300，包括：第一开关T10，所述第一开关T10的控制端T13电性耦接第一节点A，所述第一开关T10的第一端T11电性耦接接地节点GND，所述第一开关T10的第二端T12电性耦接信号输入节点P；电容C，电性耦接于所述第一节点A与所述信号输入节点P之间；第二开关T20，所述第二开关T20的控制端T23与第一端T21电性耦接第一电平线路，所述第二开关T20的第二端T22电性耦接信号输入节点P；第三开关，所述第三开关T30的控制端T33电性耦接第二电平线路，所述第三开关T30的第一端T31电性耦接所述第一节点A，所述第三开关T30的第二端T32电性耦接所述第一电平线路。其中，所述信号输入节点P取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容C受所述静电而调压以调整所述第一节点A的电位，以打开所述第一开关T10与所述第三开关T30，所述静电通过所述第一开关T10与所述第三开关T30以朝向所述接地节点GND与所述第一电平线路泄放。
在一些实施例中，所述接地节点GND电性耦接接地线或共同电压线。
在一些实施例中，所述信号输入节点P电性耦接传输信号或电源的线路，此线路包括如数据线(Data Line)、栅极线(Gate Line)、伽马电压线路(Gamma Line)、参考电压线路(Vref Line)、时序控制线路(CK Line)、使能线路(OE Line)…等相同、相关、相类似的线路，但不限于此，只要具传输信号或电源的线路皆适用。
在一些实施例中，所述静电的电位介于所述第二电平线路与所述第一电平线路之间的电位时，所述电容形成断路以调降所述第一节点的电位。
在一些实施例中，所述第一开关T10、所述第二开关T20与所述第三开关T30为耗尽型晶体管。
在一些实施例中，所述第一开关T10的第一端T11为漏极(D)，所述第一开关T10的第二端T12为源极(S)，所述第一开关T10的控制端T13为栅极(G)；所述第二开关T20的第一端T21为漏极(D)，所述第二开关T20的第二端T22为源极(S)，所述第二开关T20的控制端T23为栅极(G)；所述第三开关T30的第一端T31为漏极(D)，所述第三开关T30的第二端T32为源极(S)，所述第三开关T30的控制端T33为栅极(G)。
图2b为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图，其为图2a所示静电放电防护电路的实际等效电路示意图。
在本申请的一实施例中，所述第一开关T10、所述第二开关T20与所述第三开关T30为N型晶体管，所述第一电平线路为低电平线路VGL，所述第二电平线路为高电平线路VGH。
如先前所述，一般高电平线路VGH和低电平线路VGL的线宽比较细，因此所述第一开关T10的第一端T11线路与第二开关T20的第一端T21线路会产生阻值相对较大的等效电阻，此例中，第一开关T10与接地节点GND之间形成第一等效电阻R1'，第二开关T20连接低电平线路VGL之间形成有第二等效电阻R2。
在一些实施例中，所述信号输入节点P取得正电位静电，所述正电位静电的电位高于所述高电平线路VGH的电位。所述电容C受所述正电位静电影响，结合电容耦合特效，所述电容C的跨压有所提升，从而提升所述第一节点A的电位，以打开所述第一开关T10。然而，第一开关T10的漏极(D)，即第一端T11是接到接地节点GND，例如接地线(GND)或共同电压线(Vcom)。通常接地线或共同电压线的线宽都远远大于低电平线路VGL的线宽，所以R1'会小于R1，而产生的电流I1'也比原本的I1来的大。其次，所述第一节点A的电位提升，会使第三开关T30导通，从而产生电流I3，从而形成另一静电泄流路径。因此，通过所述第三开关T30，所述信号输入节点P引入的正电位静电即可往低电平线路VGL泄流。因此，静电路径可泄流的电流量为电流I1'与电流I3的总和，泄流电流总量相对电流I1多出不少，因此对静电能有更好的保护效果
在一些实施例中当正电位静电泄流时，所述第一节点A的电位会逐渐下降。一旦所述第一节点A的电位等同所述低电平线路VGL的电位时，所述第一开关T10被关闭。
在一些实施例中，所述电容C在直流电流中可视为开路，具有隔直流、通交流，通高频阻低频的特性。所以，所述信号输入节点P所取得的正电位静电，其电位介于所述高电平线路VGH与所述低电平线路VGL之间的电位时，所述第一开关T10与所述第三开关T30为关闭，所述电容C于电路中形同开路。
图3a为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图。请参照图3a，一种静电放电防护电路300，包括：第一开关T10，所述第一开关T10的控制端T13电性耦接第一节点A，所述第一开关T10的第一端T11电性耦接接地节点GND，所述第一开关T10的第二端T12电性耦接信号输入节点P；电容C，电性耦接于所述第一节点A与所述信号输入节点P之间；第二开关T20，所述第二开关T20的控制端T23与第一端T21电性耦接第一电平线路，所述第二开关T20的第二端T22电性耦接信号输入节点P；第三开关，所述第三开关T30的控制端T33电性耦接第二电平线路，所述第三开关T30的第一端T31电性耦接所述第一节点A，所述第三开关T30的第二端T32电性耦接所述第一电平线路。
在一些实施例中，所述第一开关T10、所述第二开关T20与所述第三开关T30为P型晶体管，所述第一电平线路为高电平线路VGH，所述第二电平线路为低电平线路VGL。
在一些实施例中，所述第一开关T10的第一端T11为漏极(D)，所述第一开关T10的第二端T12为源极(S)，所述第一开关T10的控制端T13为栅极(G)；所述第二开关T20的第一端T21为漏极(D)，所述第二开关T20的第二端T22为源极(S)，所述第二开关T20的控制端T23为栅极(G)；所述第三开关T30的第一端T31为漏极(D)，所述第三开关T30的第二端T32为源极(S)，所述第三开关T30的控制端T33为栅极(G)。
图3b为显示依据本申请的方法，一实施例应用于静电放电防护电路示意图，其为图2a所示静电放电防护电路的实际等效电路示意图。如先前所述，一般高电平线路VGH和低电平线路VGL的线宽比较细，因此所述第二开关T20的第一端T21线路与第一开关T10的第一端T11线路会产生阻值相对较大的等效电阻，此例中，第二开关T20与高电平线路VGH之间形成第一等效电阻R1，第一开关T10连接接地节点GND之间形成有第二等效电阻R2'。
在一些实施例中，所述信号输入节点P取得负电位静电，所述负电位静电的电位低于所述低电平线路VGL的电位。所述电容C受所述负电位静电影响，结合电容耦合特效，所述电容C的跨压有所降低，从而降低所述第一节点A的电位，以打开所述第一开关T10。然而，第一开关T10的漏极(D)，即第一端T11是接到接地节点GND，例如接地线(GND)或共同电压线(Vcom)。通常接地线或共同电压线的线宽都远远大于低电平线路VGL的线宽，所以R2'会小于R2，而产生的电流I2'也比原本的I2来的大。其次，所述第一节点A的电位降低，会使第三开关T30导通，从而产生电流I3，从而形成另一静电泄流路径。因此，通过所述第三开关T30，所述信号输入节点P引入的负电位静电即可往高电平线路VGH泄流。因此，静电路径可泄流的电流量为电流I2'与电流I3的总和，泄流电流总量相对电流I2多出不少，因此对静电能有更好的保护效果
在一些实施例中当负电位静电泄流时，所述第一节点A的电位会逐渐提升。一旦所述第一节 点A的电位等同所述高电平线路VGL的电位时，所述第一开关T10被关闭。
在一些实施例中，所述电容C在直流电流中可视为开路，具有隔直流、通交流，通高频阻低频的特性。所以，所述信号输入节点P所取得的负电位静电，其电位介于所述高电平线路VGH与所述低电平线路VGL之间的电位时，所述第一开关T10与所述第三开关T30为关闭，所述电容C于电路中形同开路。
在本申请一实施例中，本申请的一种静电放电防护电路，包括：第一开关T10，所述第一开关T10的控制端T13电性耦接第一节点A，所述第一开关T10的第一端T11电性耦接接地节点GND，所述第一开关T10的第二端T12电性耦接信号输入节点P；电容C，电性耦接于所述第一节点A与所述信号输入节点P之间；第二开关T20，所述第二开关T20的控制端T23与第一端T21电性耦接第一电平线路，所述第二开关T20的第二端T22电性耦接信号输入节点P；第三开关，所述第三开关T30的控制端T33电性耦接第二电平线路，所述第三开关T30的第一端T31电性耦接所述第一节点A，所述第三开关T30的第二端T32电性耦接所述第一电平线路；其中，所述信号输入节点P取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容C受所述静电而调压以调整所述第一节点A的电位，以打开所述第一开关T10与所述第三开关T30，所述静电通过所述第一开关T10与所述第三开关T30以朝向所述接地节点GND与所述第一电平线路泄放，所述第一开关T10与所述第二开关T20的工作电流为1μA为以下。
在本申请一实施例中，本申请的一种显示装置，其包括控制模块，显示面板，以及包括上述任何一种实施例的技术特征的静电放电防护电路。所述控制模块提供控制信号及电源信号，所显示面板的驱动电路接收此等信号时，将必要性将必要性的数据与电源传输于显示区，从而使得显示面板获得呈现画面需求的电源、信号。其中，所述静电放电防护电路300包括：第一开关T10，所述第一开关T10的控制端T13电性耦接第一节点A，所述第一开关T10的第一端T11电性耦接接地节点GND，所述第一开关T10的第二端T12电性耦接信号输入节点P；电容C，电性耦接于所述第一节点A与所述信号输入节点P之间；第二开关T20，所述第二开关T20的控制端T23与第一端T21电性耦接第一电平线路，所述第二开关T20的第二端T22电性耦接信号输入节点P；第三开关，所述第三开关T30的控制端T33电性耦接第二电平线路，所述第三开关T30的第一端T31电性耦接所述第一节点A，所述第三开关T30的第二端T32电性耦接所述第一电平线路；所述静电放电防护电路300连接的第一电平线路、第二电平线路的电位由控制模块所控制；所述接地节GND点电性耦接接地线或共同电压线；所述显示面板包括相对设置的第一面板与第二面板，所述静电放电防护电路300可设置于所述第一面板与所述第二面板中至少一者。
本申请通过增加泄流路径以加大静电泄流的速度与电量，避免静电放电造成液晶显示面板的内 部线路或组件的毁损。电路改进简便易行，亦有助提升电路可靠性；能使用于各种尺寸面板的制作，适用性相对较高。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (20)

  1. 一种静电放电防护电路，包括：
    第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接接地节点，所述第一开关的第二端电性耦接信号输入节点；
    电容，电性耦接于所述第一节点与所述信号输入节点之间；
    第二开关，所述第二开关的控制端与第一端电性耦接第一电平线路，所述第二开关的第二端电性耦接信号输入节点；
    第三开关，所述第三开关的控制端电性耦接第二电平线路，所述第三开关的第一端电性耦接所述第一节点，所述第三开关的第二端电性耦接所述第一电平线路；
    其中，所述信号输入节点取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容受所述静电而调压以调整所述第一节点的电位，以打开所述第一开关与所述第三开关，所述静电通过所述第一开关与所述第三开关以朝向所述接地节点与所述第一电平线路泄放。
  2. 如权利要求1所述的静电放电防护电路，其中，所述第一开关、所述第二开关与所述第三开关为N型晶体管，所述第一电平线路为低电平线路，所述第二电平线路为高电平线路。
  3. 如权利要求2所述的静电放电防护电路，其中，所述第一节点的电位等同所述低电平线路的电位，所述第一开关被关闭。
  4. 如权利要求2所述的静电放电防护电路，其中，所述信号输入节点取得正电位静电，所述正电位静电的电位介于所述高电平线路与所述低电平线路之间的电位时，所述第一开关与所述第三开关为关闭。
  5. 如权利要求1所述的静电放电防护电路，其中，所述第一开关、所述第二开关与所述第三开关为P型晶体管，所述第一电平线路为高电平线路，所述第二电平线路为低电平线路。
  6. 如权利要求5所述的静电放电防护电路，其中，所述第一节点的电位等同所述高电平线路的电位，所述第一开关被关闭。
  7. 如权利要求5所述的静电放电防护电路，其中，所述信号输入节点取得负电位静电，所述负电位静电的电位介于所述高电平线路与所述低电平线路之间的电位时，所述第一开关与所述第三开关为关闭。
  8. 如权利要求1所述的静电放电防护电路，其中，所述静电的电位介于所述第二电平线路与所述第一电平线路之间的电位时，所述电容形成断路以调降所述第一节点的电位。
  9. 如权利要求1所述的静电放电防护电路，其中，所述第一开关与所述第二开关的工作电流为1微安以下。
  10. 一种静电放电防护电路，包括：
    第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接接地节点，所述第一开关的第二端电性耦接信号输入节点；
    电容，电性耦接于所述第一节点与所述信号输入节点之间；
    第二开关，所述第二开关的控制端与第一端电性耦接第一电平线路，所述第二开关的第二端电性耦接信号输入节点；
    第三开关，所述第三开关的控制端电性耦接第二电平线路，所述第三开关的第一端电性耦接所述第一节点，所述第三开关的第二端电性耦接所述第一电平线路；
    其中，所述信号输入节点取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容受所述静电而调压以调升所述第一节点的电位，以打开所述第一开关与所述第三开关，使所述第一节点电性耦接所述第一电平线路，所述静电通过所述第一开关与所述第三开关以朝向所述接地节点与所述第一电平线路泄放；
    所述静电的电位位于所述第一电平线路与所述第二电平线路之间电位时，所述电容形成断路以调降所述第一节点的电位，以关闭所述第一开关与所述第三开关；
    所述接地节点电性耦接接地线或共同电压线；
    所述第一开关与所述第二开关的工作电流为1微安以下。
  11. 一种显示装置，包括：
    显示面板；以及
    静电放电防护电路，包括：
    第一开关，所述第一开关的控制端电性耦接第一节点，所述第一开关的第一端电性耦接接地节点，所述第一开关的第二端电性耦接信号输入节点；
    电容，电性耦接于所述第一节点与所述信号输入节点之间；
    第二开关，所述第二开关的控制端与第一端电性耦接第一电平线路，所述第二开关的第二端电性耦接信号输入节点；
    第三开关，所述第三开关的控制端电性耦接第二电平线路，所述第三开关的第一端电性耦接所述第一节点，所述第三开关的第二端电性耦接所述第一电平线路；
    其中，所述信号输入节点取得静电，所述静电的电位不符合所述第二电平线路的电位，所述电容受所述静电而调压以调整所述第一节点的电位，以打开所述第一开关与所述第三开关，所述静电通过所述第一开关与所述第三开关以朝向所述接地节点与所述第一电平线路泄放。
  12. 如权利要求11所述的显示装置，其中，所述第一开关、所述第二开关与所述第三开关为N型晶体管，所述第一电平线路为低电平线路，所述第二电平线路为高电平线路。
  13. 如权利要求12所述的显示装置，其中，所述第一节点的电位等同所述低电平线路的电位，所述第一开关被关闭。
  14. 如权利要求12所述的显示装置，其中，所述信号输入节点取得正电位静电，所述正电位静电的电位介于所述高电平线路与所述低电平线路之间的电位时，所述第一开关与所述第三开关为关闭。
  15. 如权利要求11所述的显示装置，其中，所述第一开关、所述第二开关与所述第三开关为P型晶体管，所述第一电平线路为高电平线路，所述第二电平线路为低电平线路。
  16. 如权利要求15所述的显示装置，其中，所述第一节点的电位等同所述高电平线路的电位，所述第一开关被关闭。
  17. 如权利要求15所述的显示装置，其中，所述信号输入节点取得负电位静电，所述负电位静电的电位介于所述高电平线路与所述低电平线路之间的电位时，所述第一开关与所述第三开关为关闭。
  18. 如权利要求11所述的显示装置，其中，所述静电的电位介于所述第二电平线路与所述第一电平线路之间的电位时，所述电容形成断路以调降所述第一节点的电位。
  19. 如权利要求11所述的显示装置，其中，所述接地节点电性耦接接地线或共同电压线。
  20. 如权利要求11所述的显示装置，其中，所述第一开关与所述第二开关的工作电流为1微安以下。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009003916A (ja) * 2007-05-18 2009-01-08 Seiko Epson Corp センシング回路、その駆動方法、表示装置および電子機器
CN102655145A (zh) * 2012-01-12 2012-09-05 京东方科技集团股份有限公司 一种静电释放保护电路及其工作方法
CN103944154A (zh) * 2013-12-11 2014-07-23 厦门天马微电子有限公司 一种静电保护电路及液晶显示器
US20150085406A1 (en) * 2013-09-20 2015-03-26 The Regents Of The University Of Michigan Electrostatic Discharge Clamp Circuit For Ultra-Low Power Applications
CN106932987A (zh) * 2017-05-09 2017-07-07 惠科股份有限公司 一种显示面板和显示装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW589600B (en) * 2002-07-25 2004-06-01 Au Optronics Corp Driving circuit of display able to prevent electrostatic charge
US7848068B2 (en) * 2006-09-07 2010-12-07 Industrial Technology Research Institute ESD protection circuit using self-biased current trigger technique and pumping source mechanism
TWI350422B (en) * 2007-04-25 2011-10-11 Au Optronics Corp Active device array substrate
JP2009054851A (ja) * 2007-08-28 2009-03-12 Panasonic Corp 半導体集積回路
CN101707368A (zh) * 2009-05-15 2010-05-12 彩优微电子(昆山)有限公司 一种具有噪声免疫功能的静电破坏防护装置及控制方法
US8673426B2 (en) * 2011-06-29 2014-03-18 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit
CN103515941B (zh) * 2012-06-21 2015-12-02 京东方科技集团股份有限公司 静电放电保护电路、阵列基板和显示装置
CN102967973B (zh) * 2012-11-08 2015-10-14 京东方科技集团股份有限公司 一种静电放电保护电路及驱动方法和显示面板
CN105304645B (zh) * 2015-10-16 2018-02-27 京东方科技集团股份有限公司 一种阵列基板、其静电释放方法及相应装置
CN106959562B (zh) * 2017-05-09 2021-01-08 惠科股份有限公司 一种显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009003916A (ja) * 2007-05-18 2009-01-08 Seiko Epson Corp センシング回路、その駆動方法、表示装置および電子機器
CN102655145A (zh) * 2012-01-12 2012-09-05 京东方科技集团股份有限公司 一种静电释放保护电路及其工作方法
US20150085406A1 (en) * 2013-09-20 2015-03-26 The Regents Of The University Of Michigan Electrostatic Discharge Clamp Circuit For Ultra-Low Power Applications
CN103944154A (zh) * 2013-12-11 2014-07-23 厦门天马微电子有限公司 一种静电保护电路及液晶显示器
CN106932987A (zh) * 2017-05-09 2017-07-07 惠科股份有限公司 一种显示面板和显示装置

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