WO2019047741A1 - 比特交织、解交织方法及装置 - Google Patents
比特交织、解交织方法及装置 Download PDFInfo
- Publication number
- WO2019047741A1 WO2019047741A1 PCT/CN2018/102559 CN2018102559W WO2019047741A1 WO 2019047741 A1 WO2019047741 A1 WO 2019047741A1 CN 2018102559 W CN2018102559 W CN 2018102559W WO 2019047741 A1 WO2019047741 A1 WO 2019047741A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- information bit
- bit sequence
- sequence
- interleaving
- column
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
Definitions
- the present invention relates to the field of communications, and in particular, to a bit interleaving and deinterleaving method and apparatus.
- the interleaver plays a vital role in the communication system.
- the main function of the interleaver is to change the order of the elements in the input data sequence to maximize the disruption of the association between elements to disperse the possible errors.
- the role of the interleaver is especially important in high-order modulation.
- a conventional rectangular interleaver is a global interleaver whose interleaving depth varies with the sequence length of the input interleaver, and the longer the interleaved sequence, the larger the delay.
- each bit in the modulation symbol has different protection capabilities.
- QAM Quadrature Amplitude Modulation
- the bits in each symbol are represented as ⁇ b 0 . b 1 , b 2 , b 3 ⁇
- the protection ability of ⁇ b 0 , b 1 ⁇ is higher than ⁇ b 2 , b 3 ⁇ (or the probability of error is low).
- LLR log-like radio
- the embodiments of the present invention provide a bit interleaving and deinterleaving method and apparatus to solve at least the technical problem of low interleaving efficiency in the related art.
- a bit interleaving method including: performing bit interleaving when a specified condition is met, wherein the specified condition includes at least one of the following:
- CSI channel state information
- Carrier frequency carrying the information bit sequence carrying the information bit sequence.
- the information bit sequence described in the present invention is a bit sequence that needs to be input to an interleaver.
- a bit deinterleaving method is provided, which is applied to a receiving end, comprising: receiving a matrix array to be deinterleaved; reading a bit sequence in columns in the matrix array; and performing the matrix array on the matrix array The bits within each modulation symbol are deinterleaved, wherein each column of the matrix array corresponds to at most one modulation symbol.
- a bit interleaving apparatus including: an interleaving module, configured to perform bit interleaving when a specified condition is met, wherein the specified condition includes at least one of the following:
- CCE Control Channel Element
- Carrier frequency carrying the information bit sequence carrying the information bit sequence.
- a bit deinterleaving apparatus comprising: a receiving module, configured to receive a matrix array to be deinterleaved; and a reading module, configured to read bits in columns in the matrix array a sequence deinterleaving module for deinterleaving bits within each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to at most one modulation symbol.
- a storage medium is also provided.
- the storage medium is arranged to store program code for performing the following steps:
- bit interleaving is performed, wherein the specified condition includes at least one of the following:
- Carrier frequency carrying the information bit sequence carrying the information bit sequence.
- bit interleaving it is determined whether bit interleaving is required according to specified conditions.
- bit interleaving bit sequences to be interleaved are written into a matrix array in columns, and bits in each modulation symbol in the matrix array are interleaved.
- Each of the columns of the matrix array corresponds to one modulation symbol.
- FIG. 1 is a flowchart of a bit interleaving method according to an embodiment of the present invention
- FIG. 2 is a flowchart of a bit deinterleaving method according to an embodiment of the present invention
- FIG. 3 is a block diagram showing the structure of a bit interleaving apparatus according to an embodiment of the present invention.
- FIG. 4 is a block diagram showing the structure of a bit deinterleaving apparatus according to an embodiment of the present invention.
- FIG. 5 is a schematic diagram of outputting using an interleaving pattern according to an embodiment of the present invention.
- FIG. 6 is a schematic structural diagram of hardware components of an electronic device according to an embodiment of the present invention.
- FIG. 1 is a flowchart of a bit interleaving method according to an embodiment of the present invention. As shown in FIG. 1, the process includes the following steps:
- Step S102 Perform bit interleaving when the specified condition is met, where the specified condition includes at least one of the following:
- the carrier frequency carrying the sequence of information bits.
- the information bit sequence is a bit sequence to be interleaved of the input interleaver.
- the link direction of the transmission information bit sequence (uplink or downlink, for example, the interleaver is not used in the downlink, the interleaver is used in the uplink),
- the code bit rate used by the information bit sequence (for example, the code rate is higher than a preset value without using an interleaver), the user equipment type (URLLC (Ultra-reliable and Low Latency Communication), eMBB (enhanced type) Mobile Internet (enhance Mobile Broadband), mMTC (massive machine type communication) users, channel types (control channels or traffic channels) transmitted by information bit sequences, application scenarios of information bit sequences, and control channel bearers
- the format of the information bit sequence (such as the long format of the Physical Uplink Control Channel (PUCCH) for interleaving, the short format without interleaving, etc.), and the degree of aggregation of the control channel elements carrying the information bit sequence (such as low aggregation) Degree class uses interlea
- the high frequency band does not use an interleaver
- the low frequency band uses an interleaver, etc.
- the MCS level of the information bit sequence for example, the extremely high and very low MCS levels are not interleaved, the medium MCS level is interleaved
- the root Whether the encoded bit rate information e.g., a higher rate and a lower rate is not interleaved, the interleaved moderate-rate, etc.
- the interleaving method proposed in this embodiment is used.
- the bits within each modulation symbol in the matrix array are interleaved, wherein each column of the matrix array corresponds to one modulation symbol.
- bit interleaving it is determined whether bit interleaving is required according to the specified condition.
- bit interleaving the bit sequence to be interleaved is written into a matrix array in columns, and the bits in each modulation symbol in the matrix array are interleaved.
- Each of the columns of the matrix array corresponds to one modulation symbol.
- the execution body of the foregoing steps may be a base station, a terminal, an interleaver, a transmitter, etc., but is not limited thereto.
- the method further comprises: outputting the interleaved sequence in columns.
- the number of rows of the matrix array is m, and the number of columns is n, wherein m is one of: modulation order (number of bits included in one modulation symbol), modulation order allowed by the system
- n is the smallest positive integer satisfying m*n ⁇ M, where M is a preset positive integer and is the number of bits to be interleaved.
- interleaving the bits within each modulation symbol in the matrix array includes:
- generating an interlace pattern for each column of the matrix array includes one of the following:
- the interleaving pattern of the remaining columns except the first column is cyclically shifted using the cyclic shift value on the basis of the specified interleaving pattern;
- the remaining columns except the first column are cyclically shifted using the cyclic shift value on the basis of the previous column;
- An interleaved pattern that is not associated with each other is used in each column of the matrix array.
- the cyclic shift value is one of the following: an agreed value; a cyclic shift value for each column is represented using the specified pseudo-random sequence.
- interleaving the bits in each modulation symbol in the matrix array includes:
- the set of interlaced patterns is set in the form of a table.
- the method further comprises: performing column permutation in a specified column of the matrix array, and then outputting after the permutation.
- a pseudo-random sequence is generated using the specified random number seed, and an interleaved pattern is generated using a pseudo-random sequence.
- the random number is the same as the random number used by the de-interleaving terminal, wherein the de-interleaving terminal is configured to receive and decode the bit-interleaved bit sequence.
- the pseudo-random sequence includes one of the following: a Gold sequence, a PN sequence, an m-sequence, an M-sequence, a Golay sequence, and a Frank sequence, respectively generated by the same random number seed generated by the transmitting end and the receiving end of the sequence. Random sequence.
- the mutually unrelated interleaving patterns include: generating an interleaving pattern from a specified pseudo-random sequence.
- Generating the interleaving pattern from a specified pseudo-random sequence includes: sequentially extracting log2(m) bits from one of the following random sequences, respectively corresponding to the first value of each column of the interleaving pattern: Gold sequence, PN sequence (pseudo noise sequence),
- the m sequence, the M sequence, the Golay sequence, and the Frank sequence are pseudo-random sequences generated by a specified random number seed at the transmitting end of the sequence; wherein the interleaving pattern of each column has a corresponding relationship with the first value.
- the correspondence includes one of the following: an incremental relationship, a decreasing relationship.
- the interlaced pattern is a pattern of cycles.
- the first half of a column uses the same pattern as the second half of the sequence.
- FIG. 2 is a flowchart of a bit deinterleaving method according to an embodiment of the present invention. As shown in FIG. 2, the process includes the following steps:
- Step S202 receiving a matrix array to be deinterleaved
- Step S204 reading a bit sequence by column in the matrix array
- Step S206 deinterleaving the bits in each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to at most one modulation symbol.
- deinterleaving the bits in each modulation symbol in the matrix array includes: generating a pseudo-random sequence specified by the transmitting end, obtaining an interleaving pattern according to a manner specified by the transmitting end; or, using the specified random number The number of seeds generates a pseudo-random number array to obtain an interleaving pattern; the interleaving pattern is used to deinterleave the received data to recover the uninterleaved data at the transmitting end.
- the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
- the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a storage medium (such as ROM/RAM, disk,
- the optical disc includes a number of instructions for causing a terminal device (which may be a cell phone, a computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.
- a bit interleaving and deinterleaving device is also provided.
- the device is used to implement the foregoing embodiments and preferred embodiments, and details are not described herein.
- the term "module” may implement a combination of software and/or hardware of a predetermined function.
- the devices described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
- FIG. 3 is a structural block diagram of a bit interleaving apparatus according to an embodiment of the present invention. As shown in FIG. 3, the apparatus includes:
- the interleaving module 30 is configured to perform bit interleaving when the specified condition is met, wherein the specified condition includes at least one of the following:
- the carrier frequency carrying the sequence of information bits.
- the interleaving module 30 includes: a writing unit configured to write a bit sequence to be interleaved into a matrix array in columns; and an interleaving unit configured to interleave bits in each modulation symbol in the matrix array, wherein the matrix array Each column corresponds to a modulation symbol.
- the apparatus further includes: an output module configured to output the interleaved sequence in columns after the interleaving module interleaves the bits within each of the modulation symbols in the matrix array.
- the number of rows of the matrix array is m, and the number of columns is n, wherein m is one of: modulation order, maximum value of modulation order allowed by the system, n is satisfying m*n ⁇ M is the smallest positive integer, where M is the preset positive integer.
- FIG. 4 is a structural block diagram of a bit deinterleaving apparatus according to an embodiment of the present invention. As shown in FIG. 4, the apparatus includes:
- the receiving module 40 is configured to receive a matrix array to be deinterleaved
- the reading module 42 is configured to read the bit sequence in columns in the matrix array
- the deinterleaving module 44 is configured to deinterleave bits within each modulation symbol in the matrix array, wherein each column of the matrix array corresponds to at most one modulation symbol.
- each of the above modules may be implemented by software or hardware.
- the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are in any combination.
- the forms are located in different processors.
- This embodiment is an optional embodiment according to the present invention, and is used to describe the present application in detail with reference to specific examples:
- the bit interleaving is performed when the specified condition is met, and the specified condition may be one or more, optionally, according to the working mode of the current information bit sequence, and the link direction of the transmitted information bit sequence (uplink or downlink).
- Link for example, the downlink does not use an interleaver, the uplink uses an interleaver), the code rate used by the information bit sequence (for example, the code rate is higher than a certain preset value without using an interleaver), and the user equipment type (URLLC) , eMBB or mMTC users, etc.), the channel type (control channel or traffic channel) transmitted by the information bit sequence, the application scenario of the information bit sequence, and the format of the information bit sequence carried by the control channel (eg, long format interleaving of PUCCH, short format) Not interleaving, etc.), a degree of aggregation of control channel elements carrying the information bit sequence (such as a low degree of aggregation using an interleaver, a high degree of aggregation
- modulation coding MCS level of information bit sequence eg, very high and very low MCS levels are not interleaved, medium MCS level is interleaved
- the coding rate of the information bits eg higher code rate and The lower code rate is not interleaved, the medium code rate is interleaved, etc.
- the transmitting end is based on the working mode of the current information bit sequence, the link direction of the transmitting information bit sequence, the encoding bit rate used by the information bit sequence, the user equipment type, the channel type transmitted by the information bit sequence, the application scenario of the information bit sequence, and the control channel. a format of a carried information bit sequence, a degree of aggregation of a control channel unit carrying the information bit sequence, a search space of a control channel unit carrying the information bit sequence, a scrambling manner of the information bit sequence, and the information bit sequence.
- the number of transmissions, the channel state CSI process corresponding to the information bit sequence, the set of subframes carrying the information bit sequence, the carrier frequency carrying the information bit sequence, and the like, determine whether interleaving is required. If interleaving is required, the implementation of the interleaver proposed by the present invention is described below.
- the interleaver proposed in this embodiment is a "local" interleaver which first writes the bit sequences to be interleaved into a rectangular interleaver in columns such that the bits in each column are within one modulation symbol. The bits within each symbol are then interleaved.
- the closer the interlaced pattern is to the random number the better the interleaving effect.
- This embodiment proposes performing bit interleaving within one modulation symbol and using a pseudo-random sequence to represent the interleaving pattern, thereby realizing that the interleaving pattern is completely randomized or very close to a random number.
- the interleaver proposed by the present invention interleaves only in one symbol, the interleaving depth is small, the processing delay is small, and the requirement of NR can be better satisfied.
- the interleaving method proposed by the present invention is to write the sequences to be interleaved into a rectangular array in columns, interleave the bits in each modulation symbol (per column), and then output them in columns.
- the sequence to be interleaved is written in columns into a matrix whose number of rows is m (m modulation order or the maximum value of the modulation order allowed by the system), and the number of columns n of the matrix is the minimum positive satisfying m*n ⁇ M Integer.
- the modulation order can be the number of bits carried by one modulation symbol.
- the matrix of this embodiment is as follows:
- an interleaving pattern I For each column, an interleaving pattern I is generated.
- the manner in which the interlaced pattern is generated may be one of the following ways.
- the first column (the first symbol) uses a specified interleaving pattern, such as [m-1 m-2 m-3,...,0], and the remaining columns are cyclically shifted based on the first column or the previous column.
- Bit cyclic shift to the left or right
- the cyclic shift value is represented by v shift
- the value of v shift is 0 to m-1.
- the cyclic shift value may be an agreed value.
- each column is cyclically shifted to the right by 1 bit on the basis of the previous column, for example, the interleaving pattern used in the first column is [m -1 m-2 m-3,...,0], the interleaving pattern of the second column is cyclically shifted to the right by 1 bit and is [m-2 m-3,...,0,m-1] .
- the cyclic shift value can also be generated using a random number.
- the length of the sequence c is log2(m)*(n-1), and the binary representation of the shift value of the second column is c(0), c(1),...,c(log2(m)-1) ).
- the interleaving pattern used in the first column may be removed from the specified interleaving pattern.
- the sequence for generating the shift value may be a Gold sequence, a Golay sequence, an m sequence, an M sequence, a PN sequence, a Frank sequence, etc., or may be calculated according to a Hash function. It can also be a sequence generated by the transmitting end for the pilot.
- x 1 (n+31) (x 1 (n+3)+x 1 (n)) mod 2
- x 2 (n+31) (x 2 (n+3)+x 2 (n+2)+x 2 (n+1)+x 2 (n)) mod 2
- the sequence initialization may be a cell ID, a UE ID, or the like, or may be a specified value.
- the shift value is represented by the generated Gold sequence
- the shift value of the second column is 1
- the shift values of the third column and the fourth column are all 0, and the shift value of the fifth column is Yes 2
- the shift value of column 6 is 0,
- the shift value of column 7 is 3, and so on.
- the interleaving pattern of the first column is designated as [b3, b2, b1, b0]
- each column is cyclically shifted on the basis of the previous column from the second column
- the order of the second column after interleaving is [b2, B1, b0, b3].
- the shift values of the third column and the fourth column are 0, and the order after they are interleaved is [b2, b1, b0, b3].
- the pattern after the fifth column is interleaved is [b0, b3, b2, b1], and so on.
- the receiving end after receiving the data, the receiving end also writes the received data into a matrix according to the column, and generates the same Gold sequence to obtain the shift value of each column.
- the reverse order output can get the actual coding order.
- the data is cyclically shifted to the left by 1 bit and then reversed to obtain the actual coding order, and so on.
- Each column uses an interleaving pattern with no associations between the columns.
- the transmitting end and the receiving end stipulate a specified random number seed, and the transmitting end uses the seed to generate an array formed by random numbers equal to the size of the writing array.
- each column is an interlaced pattern.
- the interlaced pattern can be generated for a specified sequence.
- the specified sequence may be a Gold sequence, a Golay sequence, an m sequence, an M sequence, a Frank sequence, and the like.
- the generated sequence length may be not less than the required length, or may be a specified length, and the sequence of the specified length is used to repeat the pattern required for the entire interlaced matrix. If a repeated interleaving pattern is used, the output sequence may be output in column order, or the data using the same interleaving pattern may be output in parallel by symbols or by column interleaving.
- FIG. 5 is a schematic diagram of outputting using an interleaving pattern according to an embodiment of the present invention. As shown in FIG.
- the entire sequence is divided into two segments, and the interleaving pattern used in the previous segment and the interleaving pattern used in the subsequent segment are consistent, and the parallel output is schematic.
- the data can be divided into more than 2 segments, each segment uses the same interleaving pattern, and then sequentially output in columns or in columns.
- the Gold sequence generated in Example 1 is still taken as an example for description.
- the resulting Gold sequence is used to represent the first index in the interleaving pattern, and the remaining indices are inferred from this index, for example, incrementing to m-1, and the remaining bit positions are sorted from small to large.
- the first value of the interleaving pattern of the first column is 1, the interleaving pattern of the first column is [1 2 3 0], and the interleaving pattern of the second column and the third column is [0 1 2 3], the interleaving pattern of the fourth column is [2 3 0 1] and the like.
- the generated pseudo-random sequence is [0 1 0 0 0 0 1 0 0 0 1 1...]
- the index of the first column is [0 1 0 0 0]
- the corresponding decimal is 4, then, use the fourth in the table, and so on.
- QPSK Quadrature Phase Shift Keyin
- the column begins with a binary pseudo-random sequence (the pseudo-random sequence mentioned in the first method) to represent the index value in the used interleaving pattern table.
- the table can also be made to the size of the highest modulation order allowed by the system.
- the interleaving pattern obtained by looking up the table is modulo m, m is the modulation order currently used, and the value of more than m is removed to obtain the actually used interleaving pattern.
- the transmitting end and the receiving end use the same random number seed.
- Each column uses a random number to produce an interleaving pattern.
- column permutation can also be performed in the specified column.
- Embodiments of the present invention also provide a storage medium.
- the foregoing storage medium may be configured to store program code for performing the following steps:
- the carrier frequency carrying the sequence of information bits.
- the processor performs bit interleaving when the specified condition is met according to the stored program code in the storage medium, where the specified condition includes at least one of the following:
- the carrier frequency carrying the sequence of information bits.
- FIG. 6 is a schematic structural diagram of hardware components of an electronic device (network device or UE) according to an embodiment of the present invention.
- the electronic device 700 includes: at least one processor 701, a memory 702, and at least one network interface 704.
- the various components in electronic device 700 are coupled together by a bus system 705. It will be appreciated that the bus system 705 is used to implement connection communication between these components.
- the bus system 705 includes a power bus, a control bus, and a status signal bus in addition to the data bus. However, for clarity of description, various buses are labeled as bus system 705 in FIG.
- memory 702 can be either volatile memory or non-volatile memory, and can include both volatile and nonvolatile memory.
- the non-volatile memory may be a ROM, a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), or an electrically erasable device.
- EEPROM Electrically Erasable Programmable Read-Only Memory
- FRAM Ferromagnetic random access memory
- Flash Memory Magnetic Surface Memory, Optical Disk, or Read Only Disc (CD) -ROM, Compact Disc Read-Only Memory
- the magnetic surface memory may be a disk storage or a tape storage.
- the volatile memory can be a random access memory (RAM) that acts as an external cache.
- RAM Static Random Access Memory
- SSRAM Synchronous Static Random Access Memory
- SSRAM Dynamic Random Access
- DRAM Dynamic Random Access Memory
- SDRAM Synchronous Dynamic Random Access Memory
- DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
- ESDRAM enhancement Enhanced Synchronous Dynamic Random Access Memory
- SLDRAM Synchronous Dynamic Random Access Memory
- DRRAM Direct Memory Bus Random Access Memory
- the memory 702 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic device 700.
- Examples of such data include any computer program, such as application 7022, for operating on electronic device 700.
- a program implementing the method of the embodiment of the present invention may be included in the application 7022.
- Processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 701 or an instruction in a form of software.
- the processor 701 described above may be a general purpose processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like.
- DSP digital signal processor
- the processor 701 can implement or perform the various methods, steps, and logic blocks disclosed in the embodiments of the present invention.
- a general purpose processor can be a microprocessor or any conventional processor or the like.
- the steps of the method disclosed in the embodiment of the present invention may be directly implemented as a hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
- the software module can reside in a storage medium located in memory 702, which reads the information in memory 702 and, in conjunction with its hardware, performs the steps of the foregoing method.
- the electronic device 700 may be configured by one or more Application Specific Integrated Circuits (ASICs), DSPs, Programmable Logic Devices (PLDs), and Complex Programmable Logic Devices (CPLDs). , Complex Programmable Logic Device), FPGA, general purpose processor, controller, MCU, MPU, or other electronic component implementation for performing the aforementioned methods.
- ASICs Application Specific Integrated Circuits
- DSPs Digital Signal processors
- PLDs Programmable Logic Devices
- CPLDs Complex Programmable Logic Devices
- FPGA field-programmable Logic Device
- controller MCU
- MPU or other electronic component implementation for performing the aforementioned methods.
- the embodiment of the present application further provides a storage medium for storing a computer program.
- the computer program causes the computer to execute the corresponding processes in the various methods in the embodiments of the present application.
- the computer program causes the computer to execute the corresponding processes in the various methods in the embodiments of the present application.
- modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
- the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
- the invention is not limited to any specific combination of hardware and software.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
本发明提供了一种比特交织、解交织方法及装置,其中,比特交织方法,应用在发射端,包括:在满足指定的条件时,进行比特交织。通过本发明,解决了相关技术中交织效率低的技术问题。
Description
相关申请的交叉引用
本申请基于申请号为201710814404.8、申请日为2017年09月11日的中国专利申请提出,并要求该中国专利申请的优先权,该中国专利申请的全部内容在此引入本申请作为参考。
本发明涉及通信领域,具体而言,涉及一种比特交织、解交织方法及装置。
交织器在通信系统中起着至关重要的作用,交织器的主要作用就是改变输入数据序列中元素的顺序,以最大化打乱元素之间的关联来分散可能发生的错误。在高阶调制中,交织器的作用尤其重要。传统的矩形交织器是一种全局交织器,交织深度随着输入交织器的序列长度而变化,交织的序列越长、延迟越大。
在辐值调制系统中,调制符号中的每个比特都具有不同的保护能力,以16正交振幅调制(Quadrature Amplitude Modulation,QAM)为例,假定每个符号内的比特表示为{b
0,b
1,b
2,b
3},那么{b
0,b
1}的保护能力就比{b
2,b
3}高(或出错概率低)。相关技术中,在NR(new radio access technology)使用的Polar码编解码系统中,具有不同可靠度的接收数据或对数似然比LLR(log-like radio)对解码性能也有着很大的影响,如何在新无线(New Radio,NR)系统中采用高效的交织方式,目前尚未有解决方案。
针对相关技术中存在的上述问题,目前尚未发现有效的解决方案。
发明内容
本发明实施例提供了一种比特交织、解交织方法及装置,以至少解决相关技术中交织效率低的技术问题。
根据本发明的一个实施例,提供了一种比特交织方法,包括:在满足指定的条件时,进行比特交织,其中,所述指定的条件包括以下至少之一:
所述信息比特序列的工作模式;
所述信息比特序列的应用场景;
所述信息比特序列的链路方向;
所述信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
所述信息比特序列的调制编码(Modulation and Coding Scheme,MCS)等级;
承载所述信息比特序列的控制信道单元的聚合等级;
承载所述信息比特序列的资源单元组(Resource Element Group,REG)的包的大小bundle size;
所述信息比特序列对应的搜索空间;
所述信息比特序列的加扰方式;
所述信息比特序列的传输次数;
承载所述信息比特序列的信道类型;
所述信息比特序列对应的控制信息格式;
所述信息比特序列对应的信道状态信息(Chanel State Information,CSI)进程;
承载所述信息比特序列的子帧集合;
承载所述信息比特序列的载波频率。
本发明中所述的信息比特序列就是需要输入交织器的比特序列。
根据本发明的一个实施例,提供了一种比特解交织方法,应用在接收端,包括:接收待解交织的矩阵阵列;在所述矩阵阵列中按列读取比特序列;对所述矩阵阵列中的每个调制符号内的比特进行解交织,其中,所述矩阵阵列的每列至多对应一个调制符号。
根据本发明的另一个实施例,提供了一种比特交织装置,包括:交织模块,用于在满足指定的条件时,进行比特交织,其中,所述指定的条件包括以下至少之一:
所述信息比特序列的工作模式;
所述信息比特序列的应用场景;
所述信息比特序列的链路方向;
所述信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
所述信息比特序列的MCS等级;
承载所述信息比特序列的控制信道单元(Control Channel Element,CCE)的聚合等级;
承载所述信息比特序列的REG的bundle size;
所述信息比特序列对应的搜索空间;
所述信息比特序列的加扰方式;
所述信息比特序列的传输次数;
承载所述信息比特序列的信道类型;
所述信息比特序列对应的控制信息格式;
所述信息比特序列对应的CSI进程;
承载所述信息比特序列的子帧集合;
承载所述信息比特序列的载波频率。
根据本发明的另一个实施例,提供了一种比特解交织装置,包括:接收模块,用于接收待解交织的矩阵阵列;读取模块,用于在所述矩阵阵列中按列读取比特序列;解交织模块,用于对所述矩阵阵列中的每个调制符号内的比特进行解交织,其中,所述矩阵阵列的每列至多对应一个调制符号。
根据本发明的又一个实施例,还提供了一种存储介质。该存储介质设置为存储用于执行以下步骤的程序代码:
在满足指定的条件时,进行比特交织,其中,所述指定的条件包括以下至少之一:
所述信息比特序列的工作模式;
所述信息比特序列的应用场景;
所述信息比特序列的链路方向;
所述信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
所述信息比特序列的MCS等级;
承载所述信息比特序列的CCE的聚合等级;
承载所述信息比特序列的REG的bundle size;
所述信息比特序列对应的搜索空间;
所述信息比特序列的加扰方式;
所述信息比特序列的传输次数;
承载所述信息比特序列的信道类型;
所述信息比特序列对应的控制信息格式;
所述信息比特序列对应的CSI进程;
承载所述信息比特序列的子帧集合;
承载所述信息比特序列的载波频率。
通过本发明,根据指定的条件确定是否需要进行比特交织,在进行比特交织时,将待交织的比特序列按列写入一个矩阵阵列中,对矩阵阵列中的每个调制符号内的比特进行交织,其中,矩阵阵列的每列对应一个调制符号,通过在一个符号内进行交织,交织深度很小,处理时延小,能够更好地满足NR的需求,解决了相关技术中交织效率低的技术问题,提高了交织效率。
此处所说明的附图用来提供对本发明的进一步理解,构成本申请的一部分,本发明的示意性实施例及其说明用于解释本发明,并不构成对本发明的不当限定。在附图中:
图1是根据本发明实施例的比特交织方法的流程图;
图2是根据本发明实施例的比特解交织方法的流程图;
图3是根据本发明实施例的比特交织装置的结构框图;
图4是根据本发明实施例的比特解交织装置的结构框图;
图5是本发明实施例使用交织图样输出的示意图;
图6是本发明实施例电子设备的硬件组成结构示意图。
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。
需要说明的是,本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。
在本实施例中提供了一种比特交织方法,图1是根据本发明实施例的比特交织方法的流程图,如图1所示,该流程包括如下步骤:
步骤S102,在满足指定的条件时,进行比特交织,其中,指定的条件包括以下至少之一:
信息比特序列的工作模式;
信息比特序列的应用场景;
信息比特序列的链路方向;
信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
信息比特序列的MCS等级;
承载信息比特序列的CCE的聚合等级;
承载信息比特序列的REG的bundle size;
信息比特序列对应的搜索空间;
信息比特序列的加扰方式;
信息比特序列的传输次数;
承载信息比特序列的信道类型;
信息比特序列对应的控制信息格式;
信息比特序列对应的CSI进程;
承载信息比特序列的子帧集合;
承载信息比特序列的载波频率。
在本实施例中,信息比特序列为输入交织器的待交织的比特序列。
在上述指定的条件中,根据当前信息比特序列的工作模式、发射信息比特序列的链路方向(上行链路或下行链路,例如下行链路不使用交织器,上行链路使用交织器)、信息比特序列使用的编码码率(例如码率高于某一 预设值不使用交织器)、用户设备类型(URLLC(低时延高可靠,Ultra-reliable and Low Latency Communication)、eMBB(增强型移动互联网,enhance Mobile Broadband)、mMTC(海量机器类通信,massive Machine Type Communication)用户等)、信息比特序列发射的信道类型(控制信道或业务信道)、信息比特序列的应用场景、控制信道承载的信息比特序列的格式(如物理上行控制信道(Physical Uplink Control Channel,PUCCH)的长格式做交织、短格式不做交织等)、承载信息比特序列的控制信道单元的聚合度等级(如低的聚合度等级使用交织器,高的聚合度等级不使用交织器等)、承载信息比特序列的REG的bundle size(例如bundle size是2的做交织,bundle size是6的不做交织)、信息比特序列的MCS等级、承载信息比特序列的控制信道单元的搜索空间(公共搜索空间做交织,UE特定搜索空间不交织)、信息比特序列的加扰方式(例如使用寻呼小区无线网络临时标识(Paging Radio Network Temporary Identifier,简称P-RNTI)、系统消息SI-RNTI、T-RNTI(临时的C-RNTI)加扰的信息比特序列进行交织,使用用户业务C-RNTI加扰的信息比特序列不交织)、信息比特序列的传输次数(初传使用交织器,重传不使用交织器等)、信息比特序列对应的信道状态CSI进程、承载信息比特序列的子帧集合(指定某些子帧使用交织器等)、承载信息比特序列的载波频率等等(高频段不使用交织器,低频段使用交织器等)、信息比特序列的MCS等级(例如极高和极低的MCS等级不做交织,中等MCS等级的做交织)、根据信息比特的编码速率(如较高码率和较低码率的不做交织,中等码率的进行交织等)判断是否需要进行交织。如果需要交织,则使用本实施例提出的交织方法。
在进行比特交织时,包括:
将待交织的比特序列按列写入一个矩阵阵列中;
对矩阵阵列中的每个调制符号内的比特进行交织,其中,矩阵阵列的 每列对应一个调制符号。
通过上述步骤,根据指定的条件确定是否需要进行比特交织,在进行比特交织时,将待交织的比特序列按列写入一个矩阵阵列中,对矩阵阵列中的每个调制符号内的比特进行交织,其中,矩阵阵列的每列对应一个调制符号,通过在一个符号内进行交织,交织深度很小,处理时延小,能够更好地满足NR的需求,解决了相关技术中交织效率低的技术问题,提高了交织效率。
在一些可选实施例中,上述步骤的执行主体可以为基站、终端、交织器、发射机等,但不限于此。
在一些可选实施例中,在对矩阵阵列中的每个调制符号内的比特进行交织之后,还包括:按列输出交织后的序列。
在一些可选实施例中,矩阵阵列的行数为m,列数为n,其中,m为以下之一:调制阶数(一个调制符号内包含的比特数)、系统允许使用的调制阶数的最大值,n是满足m*n≥M的最小正整数,其中,M为预设的正整数,是待交织的比特数。
在一些可选实施例中,对矩阵阵列中的每个调制符号内的比特进行交织包括:
S11,对于矩阵阵列的每一列产生一个交织图样;
S12,使用交织图样对每个调制符号内的比特进行交织。
在本实施例中,对于矩阵阵列的每一列产生一个交织图样包括以下之一:
在矩阵阵列的第一列使用一个指定交织图样,除第一列之外的其余列的交织图样在指定交织图样的基础上使用循环移位值进行循环移位;
在矩阵阵列的第一列使用一个指定交织图样,除第一列之外的其余列在前一列的基础上使用循环移位值进行循环移位;
在矩阵阵列的每一列使用一个互不关联的交织图样。
在本实施例中,循环移位值为以下之一:约定的值;使用指定的伪随机序列表示每一列的循环移位值。
可选的,对矩阵阵列中的每个调制符号内的比特进行交织包括:
S21,调用预设的交织图样集合;
S22,根据随机数指示当前列选择交织图样;
S23,遍历使用选择的交织图样对每个调制符号内的比特进行交织。
在一些可选实施例中,交织图样集合通过表格的形式进行设置。
在一些可选实施例中,在对矩阵阵列中的每个调制符号内的比特进行交织之后,方法还包括:在矩阵阵列的指定列进行列置换,置换之后再输出。
在一些可选实施例中,使用指定的随机数种子产生一个伪随机序列,使用伪随机序列产生交织图样。
在一些可选实施例中,随机数与解交织端使用的随机数相同,其中,解交织端用于接收并解码按列交织后的比特序列。
在本实施例中,伪随机序列包括以下之一:Gold序列、PN序列、m序列、M序列、Golay序列、Frank序列,由序列的发射端和接收端使用相同的随机数种子分别产生的伪随机序列。
在一些可选实施例中,互不关联的交织图样包括:由一个指定的伪随机序列产生交织图样。由一个指定的伪随机序列产生交织图样包括:从以下随机序列之一中依次取出log2(m)比特分别对应着每一列交织图样的第一个值:Gold序列、PN序列(伪噪声序列)、m序列、M序列、Golay序列、Frank序列,由序列的发射端一个指定的随机数种子产生的伪随机序列;其中,每一列的交织图样与第一个值有对应关系。具体的,对应关系包括以下之一:递增关系、递减关系。
在一些可选实施例中,交织图样是周期的图样。如,一列的前一半序列与后一半序列使用相同的图样。
在本实施例中提供了一种比特解交织方法,图2是根据本发明实施例的比特解交织方法的流程图,如图2所示,该流程包括如下步骤:
步骤S202,接收待解交织的矩阵阵列;
步骤S204,在矩阵阵列中按列读取比特序列;
步骤S206,对矩阵阵列中的每个调制符号内的比特进行解交织,其中,矩阵阵列的每列至多对应一个调制符号。
在一些可选实施例中,对矩阵阵列中的每个调制符号内的比特进行解交织包括:产生发射端指定的伪随机序列,根据发射端指定的方式得到交织图样;或,使用指定的随机数种子产生伪随机数阵列,得到交织图样;使用交织图样对接收数据进行解交织即可恢复出发射端未交织的数据。
通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现,当然也可以通过硬件,但很多情况下前者是更佳的实施方式。基于这样的理解,本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中,包括若干指令用以使得一台终端设备(可以是手机,计算机,服务器,或者网络设备等)执行本发明各个实施例所述的方法。
在本实施例中还提供了一种比特交织、解交织装置,该装置用于实现上述实施例及优选实施方式,已经进行过说明的不再赘述。如以下所使用的,术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现,但是硬件,或者软件和硬件的组合的实现也是可能并被构想的。
图3是根据本发明实施例的比特交织装置的结构框图,如图3所示,该装置包括:
交织模块30,配置为在满足指定的条件时,进行比特交织,其中,指定的条件包括以下至少之一:
信息比特序列的工作模式;
信息比特序列的应用场景;
信息比特序列的链路方向;
信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
信息比特序列的MCS等级;
承载信息比特序列的CCE的聚合等级;
承载信息比特序列的REG的bundle size;
信息比特序列对应的搜索空间;
信息比特序列的加扰方式;
信息比特序列的传输次数;
承载信息比特序列的信道类型;
信息比特序列对应的控制信息格式;
信息比特序列对应的CSI进程;
承载信息比特序列的子帧集合;
承载信息比特序列的载波频率。
交织模块30包括:写入单元,配置为将待交织的比特序列按列写入一个矩阵阵列中;交织单元,配置为对矩阵阵列中的每个调制符号内的比特进行交织,其中,矩阵阵列的每列对应一个调制符号。
在一些可选实施例中,装置还包括:输出模块,配置为在交织模块对 矩阵阵列中的每个调制符号内的比特进行交织之后,按列输出交织后的序列。
在一些可选实施例中,矩阵阵列的行数为m,列数为n,其中,m为以下之一:调制阶数、系统允许使用的调制阶数的最大值,n是满足m*n≥M的最小正整数,其中,M为预设的正整数。
图4是根据本发明实施例的比特解交织装置的结构框图,如图4所示,该装置包括:
接收模块40,配置为接收待解交织的矩阵阵列;
读取模块42,配置为在矩阵阵列中按列读取比特序列;
解交织模块44,配置为对矩阵阵列中的每个调制符号内的比特进行解交织,其中,矩阵阵列的每列至多对应一个调制符号。
需要说明的是,上述各个模块是可以通过软件或硬件来实现的,对于后者,可以通过以下方式实现,但不限于此:上述模块均位于同一处理器中;或者,上述各个模块以任意组合的形式分别位于不同的处理器中。
本实施例是根据本发明的可选实施例,用于结合具体实例对本申请进行详细说明:
本实施例是在满足指定的条件时进行比特交织,指定的条件可以是一个多个,可选的,根据当前信息比特序列的工作模式、发射信息比特序列的链路方向(上行链路或下行链路,例如下行链路不使用交织器,上行链路使用交织器)、信息比特序列使用的编码码率(例如码率高于某一预设值不使用交织器)、用户设备类型(URLLC、eMBB或mMTC用户等)、信息比特序列发射的信道类型(控制信道或业务信道)、信息比特序列的应用场景、控制信道承载的信息比特序列的格式(如PUCCH的长格式做交织、短格式不做交织等)、承载所述信息比特序列的控制信道单元的聚合度等级(如低的聚合度等级使用交织器,高的聚合度等级不使用交织器等)、承载 所述信息比特序列的REG的bundle size(例如bundle size是2的做交织,bundle size是6的不做交织)、信息比特序列的调制编码MCS等级、承载所述信息比特序列的控制信道单元的搜索空间(公共搜索空间做交织,UE特定搜索空间不交织)、信息比特序列的加扰方式(例如使用P-RNTI、SI-RNTI、T-RNTI加扰的信息比特序列进行交织,使用C-RNTI加扰的信息比特序列不交织)、所述信息比特序列的传输次数(初传使用交织器,重传不使用交织器等)、所述信息比特序列对应的信道状态CSI进程、承载所述信息比特序列的子帧集合(指定某些子帧使用交织器等)、承载所述信息比特序列的载波频率等等(高频段不使用交织器,低频段使用交织器等)、信息比特序列的调制编码MCS等级(例如极高和极低的MCS等级不做交织,中等MCS等级的做交织)、根据所述信息比特的编码速率(如较高码率和较低码率的不做交织,中等码率的进行交织等)判断是否需要进行交织。如果需要交织,则使用本发明提出的交织方法。
发射端根据当前信息比特序列的工作模式、发射信息比特序列的链路方向、信息比特序列使用的编码码率、用户设备类型、信息比特序列发射的信道类型、信息比特序列的应用场景、控制信道承载的信息比特序列的格式、承载所述信息比特序列的控制信道单元的聚合度等级、承载所述信息比特序列的控制信道单元的搜索空间、信息比特序列的加扰方式、所述信息比特序列的传输次数、所述信息比特序列对应的信道状态CSI进程、承载所述信息比特序列的子帧集合、承载所述信息比特序列的载波频率等等,判断是否需要进行交织。如果需要交织,本发明提出的交织器实现细节描述如下。
本实施例提出的交织器是一种“局部”的交织器,它先将待交织的比特序列按列写入一个矩形交织器中,这样每一列内的比特都在一个调制符号内。然后对每个符号内的比特进行交织。理论上,交织图样越接近于随 机数,交织效果越好。
本实施例提出在一个调制符号内进行比特交织并使用一种伪随机序列表示交织图样,从而实现了交织图样完全随机化或很接近于随机数。同时,本发明提出的这种交织器仅在一个符号内进行交织,交织深度很小,处理时延小,能够更好地满足NR的需求。本发明提出的交织方法是:将待交织的序列按列写入一个矩形阵列中,对每个调制符号(每列)内的比特进行交织,然后按列输出。
将待交织的序列按列写入一个行数为m(m调制阶数或者是系统允许使用的调制阶数的最大值)的矩阵,矩阵的列数n是满足m*n≥M的最小正整数。调制阶数可以是一个调制符号承载的比特数。本实施例的矩阵如下式所示:
对于交织图样的确定和产生,包括如下方式:
方式一:
第一列(第一个符号)使用一个指定的交织图样,例如[m-1 m-2 m-3,...,0],其余列在第一列或前一列的基础上进行循环移位(向左或向右循环移位),所述循环移位值用v
shift表示,v
shift的取值是0~m-1。所述循环移位值可以是一个约定的值,例如,从第2列开始,每列都在前一列的基础上向右循环移位1位等,例如第1列使用的交织图样是[m-1 m-2 m-3,...,0],则第2列的交织图样向右循环移位1位后是[m-2 m-3,...,0,m-1]。
所述循环移位值也可以使用一个随机数产生。序列c的长度为 log2(m)*(n-1),第2列的移位值的二进制表示是c(0),c(1),...,c(log2(m)-1))。
特别地,如果所述矩阵的行数是系统允许使用的最大的调制阶数,则,假定实际使用的调制阶数是m′,第一列使用的交织图样可以是所述指定交织图样中去掉大于m′的值。其余列相对于第1列的移位值为v
shift=(c(0) c(1) … c(log
2m-1))mod m'。
所述产生移位值的序列可以是Gold序列、Golay序列,m序列、M序列、PN序列、Frank序列等,也可以是根据Hash函数计算得到。还可以是发射端产生的用于导频的序列。对于Gold序列c(n),使用两个m序列x1和x2相加(模2)得到,假定c(n)的序列长度为M
PN,n=0,1,...,M
PN-1,
c(n)=(x
1(n+N
C)+x
2(n+N
C))mod 2
x
1(n+31)=(x
1(n+3)+x
1(n))mod 2
x
2(n+31)=(x
2(n+3)+x
2(n+2)+x
2(n+1)+x
2(n))mod 2
假定x2使用小区ID为6的初始化,得到的Gold序列为:
[0 1 0 0 0 0 1 0 0 0 1 1......],
则如果使用16QAM,使用所述产生的Gold序列表示移位值,则第2列的移位值是1,第3列和第4列的移位值都是0,第5列的移位值是2,第6列的移位值是0,第7列的移位值是3,等等。如果指定第1列的交织图样是[b3,b2,b1,b0],从第2列开始每列都在前一列的基础上进行循环移位,则第2列交织后的顺序是[b2,b1,b0,b3]。第3列和第4列的移位值是0则他们交织后的顺序是[b2,b1,b0,b3]。第5列交织后的图样是[b0,b3,b2,b1],等等。
对交织后的矩阵,按列输出。
对应的,接收端接收到数据后,也将接收数据按列写入一个矩阵中, 产生相同的Gold序列,得到每列的移位值。对于第一列,倒序输出即可得到实际的编码顺序,对于第2列,将其数据向左循环移位1位再倒序输出即可得到实际的编码顺序,其它的依次类推。
方式二:
每一列都使用一个交织图样,各列之间没有关联。发射端和接收端约定一个指定的随机数种子,发射端使用所述种子产生一个与写入阵列大小一样的随机数形成的阵列,所述随机数形成的阵列中,每一列即是一个交织图样。使用所述随机数形成的阵列对所述待交织序列进行交织;接收端接收到发射端发射的数据后,也使用所述指定的种子数产生所需长度的随机数形成的阵列,即可解交织(恢复)出没有交织的信息比特序列。所述交织图样可以是某一指定序列产生的。所述指定序列可以是Gold序列、Golay序列,m序列、M序列、Frank序列等。对于所述序列,产生的序列长度可以是不小于所需长度的,也可以是指定长度的,使用时用所述指定长度的序列进行重复得到整个交织矩阵需要的图样。如果使用的是重复的交织图样,输出序列可以是按列顺序输出,也可以是将使用相同交织图样的数据按符号或者按列交错并行输出。图5是本发明实施例使用交织图样输出的示意图,如图5给出的是整个序列分为2段,前一段使用的交织图样和后一段序列使用的交织图样一致,并行输出的示意图。实际中也可以对数据分成大于2段,每段使用相同的交织图样,再顺序按列输出或按列并行输出。
为了更详细地说明本方案。仍然以实施例1产生的Gold序列为例进行说明。用产生的所述Gold序列表示交织图样中的第1个索引,其余索引由此索引推断产生,例如,递增到m-1,其余的比特位置从小到大排序。假定使用的是16QAM,则第1列的交织图样的第1个值是1,则第1列的交织图样是[1 2 3 0],第2列和第3列的交织图样为[0 1 2 3],第4列的交织图样 为[2 3 0 1]等。
方式三:
给出所有可能的交织图样,并做成表格的形式。使用随机数指示当前列使用的交织器图样。具体地,以16QAM为例,进行说明。每个调制符号内有4个比特,比特排序有24种可能,则表格中有24个元素,需要24个索引。需要产生的随机数序列长度为5×M/4,从第1列开始,每次选取5比特,即是当前列的索引,实际中会出现索引值大于24的情况,这时候,将其值模24得到对应的索引。例如,假定产生的伪随机序列是[0 1 0 0 0 0 1 0 0 0 1 1......],则,第一列的索引是[0 1 0 0 0],对应的十进制是4,则,使用表格中的第4个,等等。例如,若以正交相移键控(Quadrature Phase Shift Keyin,QPSK)为例,则交织图样的表格只有2种:I
0=[0 1]和I
1=[1 0];则从第1列开始依次从二进制的伪随机序列(所述方式一中提到的伪随机序列)即可表示使用的交织图样表格中的索引值。
表格也可做成系统允许的最高调制阶数的大小。将查表得到的交织图样再模m,m是当前使用的调制阶数,并去掉大于m的值即可得到实际使用的交织图样。
在本实施例中,发射端和接收端使用相同的随机数种子。每列都使用一个随机数产生一个交织图样。
可选的在进行符号内的交织之后,也可以在指定列进行列置换。
本发明的实施例还提供了一种存储介质。可选地,在本实施例中,上述存储介质可以被设置为存储用于执行以下步骤的程序代码:
S1,在满足指定的条件时,进行比特交织,其中,指定的条件包括以下至少之一:
信息比特序列的工作模式;
信息比特序列的应用场景;
信息比特序列的链路方向;
信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
信息比特序列的调制编码MCS等级;
承载信息比特序列的CCE的聚合等级;
承载信息比特序列的REG的bundle size;
信息比特序列对应的搜索空间;
信息比特序列的加扰方式;
信息比特序列的传输次数;
承载信息比特序列的信道类型;
信息比特序列对应的控制信息格式;
信息比特序列对应的CSI进程;
承载信息比特序列的子帧集合;
承载信息比特序列的载波频率。
可选地,在本实施例中,处理器根据存储介质中已存储的程序代码执行在满足指定的条件时,进行比特交织,其中,指定的条件包括以下至少之一:
信息比特序列的工作模式;
信息比特序列的应用场景;
信息比特序列的链路方向;
信息比特序列的长度;
信息比特序列对应的母码长度;
信息比特序列对应的码率;
信息比特序列的MCS等级;
承载信息比特序列的CCE的聚合等级;
承载信息比特序列的REG的bundle size;
信息比特序列对应的搜索空间;
信息比特序列的加扰方式;
信息比特序列的传输次数;
承载信息比特序列的信道类型;
信息比特序列对应的控制信息格式;
信息比特序列对应的CSI进程;
承载信息比特序列的子帧集合;
承载信息比特序列的载波频率。
可选地,本实施例中的具体示例可以参考上述实施例及可选实施方式中所描述的示例,本实施例在此不再赘述。
图6是本发明实施例的电子设备(网络设备或UE)的硬件组成结构示意图,电子设备700包括:至少一个处理器701、存储器702和至少一个网络接口704。电子设备700中的各个组件通过总线系统705耦合在一起。可理解,总线系统705用于实现这些组件之间的连接通信。总线系统705除包括数据总线之外,还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见,在图6中将各种总线都标为总线系统705。
可以理解,存储器702可以是易失性存储器或非易失性存储器,也可包括易失性和非易失性存储器两者。其中,非易失性存储器可以是ROM、可编程只读存储器(PROM,Programmable Read-Only Memory)、可擦除可编程只读存储器(EPROM,Erasable Programmable Read-Only Memory)、电可擦除可编程只读存储器(EEPROM,Electrically Erasable Programmable Read-Only Memory)、磁性随机存取存储器(FRAM,ferromagnetic random access memory)、快闪存储器(Flash Memory)、磁表面存储器、光盘、或 只读光盘(CD-ROM,Compact Disc Read-Only Memory);磁表面存储器可以是磁盘存储器或磁带存储器。易失性存储器可以是随机存取存储器(RAM,Random Access Memory),其用作外部高速缓存。通过示例性但不是限制性说明,许多形式的RAM可用,例如静态随机存取存储器(SRAM,Static Random Access Memory)、同步静态随机存取存储器(SSRAM,Synchronous Static Random Access Memory)、动态随机存取存储器(DRAM,Dynamic Random Access Memory)、同步动态随机存取存储器(SDRAM,Synchronous Dynamic Random Access Memory)、双倍数据速率同步动态随机存取存储器(DDRSDRAM,Double Data Rate Synchronous Dynamic Random Access Memory)、增强型同步动态随机存取存储器(ESDRAM,Enhanced Synchronous Dynamic Random Access Memory)、同步连接动态随机存取存储器(SLDRAM,SyncLink Dynamic Random Access Memory)、直接内存总线随机存取存储器(DRRAM,Direct Rambus Random Access Memory)。本发明实施例描述的存储器702旨在包括但不限于这些和任意其它适合类型的存储器。
本发明实施例中的存储器702用于存储各种类型的数据以支持电子设备700的操作。这些数据的示例包括:用于在电子设备700上操作的任何计算机程序,如应用程序7022。实现本发明实施例方法的程序可以包含在应用程序7022中。
上述本发明实施例揭示的方法可以应用于处理器701中,或者由处理器701实现。处理器701可能是一种集成电路芯片,具有信号的处理能力。在实现过程中,上述方法的各步骤可以通过处理器701中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器701可以是通用处理器、数字信号处理器(DSP,Digital Signal Processor),或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。处理器701可以实现 或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本发明实施例所公开的方法的步骤,可以直接体现为硬件译码处理器执行完成,或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于存储介质中,该存储介质位于存储器702,处理器701读取存储器702中的信息,结合其硬件完成前述方法的步骤。
在示例性实施例中,电子设备700可以被一个或多个应用专用集成电路(ASIC,Application Specific Integrated Circuit)、DSP、可编程逻辑器件(PLD,Programmable Logic Device)、复杂可编程逻辑器件(CPLD,Complex Programmable Logic Device)、FPGA、通用处理器、控制器、MCU、MPU、或其他电子元件实现,用于执行前述方法。
本申请实施例还提供了一种存储介质,用于存储计算机程序。
可选的,该计算机程序使得计算机执行本申请实施例的各个方法中的相应流程,为了简洁,在此不再赘述。
显然,本领域的技术人员应该明白,上述的本发明的各模块或各步骤可以用通用的计算装置来实现,它们可以集中在单个的计算装置上,或者分布在多个计算装置所组成的网络上,可选地,它们可以用计算装置可执行的程序代码来实现,从而,可以将它们存储在存储装置中由计算装置来执行,并且在某些情况下,可以以不同于此处的顺序执行所示出或描述的步骤,或者将它们分别制作成各个集成电路模块,或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样,本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明 的保护范围之内。
Claims (19)
- 一种比特交织方法,应用在发射端,包括:在满足指定的条件时,进行比特交织,其中,所述指定的条件包括以下至少之一:信息比特序列的工作模式;信息比特序列的应用场景;所述信息比特序列的链路方向;所述信息比特序列的长度;信息比特序列对应的母码长度;信息比特序列对应的码率;所述信息比特序列的调制编码MCS等级;承载所述信息比特序列的控制信道单元CCE的聚合等级;承载所述信息比特序列的资源单元组REG的包的大小bundle size;信息比特序列对应的搜索空间;信息比特序列的加扰方式;信息比特序列的传输次数;承载信息比特序列的信道类型;信息比特序列对应的控制信息格式;信息比特序列对应的信道状态信息CSI进程;承载信息比特序列的子帧集合;承载信息比特序列的载波频率。
- 根据权利要求1所述的方法,其中,进行比特交织包括:将待交织的比特序列按列写入一个矩阵阵列中;对所述矩阵阵列中的每个调制符号内的比特进行交织,其中,所述矩阵阵列的每列至多对应一个调制符号。
- 根据权利要求2所述的方法,其中,在对所述矩阵阵列中的每个调制符号内的比特进行交织之后,所述方法还包括:按列输出交织后的序列。
- 根据权利要求2所述的方法,其中,所述矩阵阵列的行数为m,列数为n,其中,m为以下之一:调制阶数、系统允许使用的调制阶数的最大值,n是满足m*n≥M的最小正整数,其中,M为预设的正整数,为待交织的比特数。
- 根据权利要求2所述的方法,其中,对所述矩阵阵列中的每个调制符号内的比特进行交织包括:对于所述矩阵阵列的每一列产生一个交织图样;使用对应的交织图样对每列的调制符号内的比特进行交织。
- 根据权利要求5所述的方法,其中,对于所述矩阵阵列的每一列产生一个交织图样包括以下之一:在所述矩阵阵列的第一列使用一个指定交织图样,除所述第一列之外的其余列的交织图样是在所述指定交织图样的基础上使用循环移位值进行循环移位得到;在所述矩阵阵列的第一列使用一个指定交织图样,除所述第一列之外的其余列所使用的交织图样是在前一列所使用的交织图样的基础上使用循环移位值进行循环移位得到;在所述矩阵阵列的每一列使用一个互不关联的交织图样。
- 根据权利要求6所述的方法,其中,所述循环移位值为以下之一:约定的值;使用指定的伪随机序列表示每一列的循环移位值。
- 根据权利要求2所述的方法,其中,对所述矩阵阵列中的每个调制符号内的比特进行交织包括:调用预设的交织图样集合;根据随机数指示当前列选择交织图样;使用对应的交织图样对每列的调制符号内的比特进行交织。
- 根据权利要求2所述的方法,其中,在对所述矩阵阵列中的每个调制符号内的比特进行交织之后,所述方法还包括:在所述矩阵阵列的指定列进行列置换。
- 根据权利要求8所述的方法,其中,使用指定的随机数种子产生一个伪随机序列,使用所述伪随机序列产生交织图样。
- 根据权利要求6所述的方法,其中,所述互不关联的交织图样包括:由一个指定的伪随机序列产生交织图样。
- 根据权利要求11所述的方法,其中,由一个指定的伪随机序列产生交织图样包括:从以下随机序列之一中依次取出log2(m)比特分别对应着每一列交织图样的第一个值:Gold序列、伪随机PN序列、m序列、M序列、Golay序列、Frank序列,由序列的发射端一个指定的随机数种子产生的伪随机序列;其中,所述每一列的交织图样与所述第一个值有对应关系。
- 根据权利要求5、6、8、11-12任一项所述的方法,其中,所述交织图样是周期的图样。
- 一种比特解交织方法,应用在接收端,包括:接收待解交织的矩阵阵列;在所述矩阵阵列中按列读取比特序列;对所述矩阵阵列中的每个调制符号内的比特进行解交织,其中,所述矩阵阵列的每列至多对应一个调制符号。
- 根据权利要求14所述的方法,其中,对所述矩阵阵列中的每 个调制符号内的比特进行解交织包括:产生发射端指定的伪随机序列,根据发射端指定的方式得到交织图样;或,使用指定的随机数种子产生伪随机数阵列,得到交织图样;使用所述交织图样对接收数据进行解交织即可恢复出发射端未交织的数据。
- 一种比特交织装置,包括:交织模块,配置为在满足指定的条件时,进行比特交织,其中,所述指定的条件包括以下至少之一:信息比特序列的工作模式;信息比特序列的应用场景;信息比特序列的链路方向;信息比特序列的长度;信息比特序列对应的母码长度;信息比特序列对应的码率;信息比特序列的调制编码MCS等级;承载信息比特序列的控制信道单元CCE的聚合等级;承载信息比特序列的资源单元组REG的包的大小bundle size;信息比特序列对应的搜索空间;信息比特序列的加扰方式;信息比特序列的传输次数;承载信息比特序列的信道类型;信息比特序列对应的控制信息格式;信息比特序列对应的信道状态信息CSI进程;承载信息比特序列的子帧集合;承载信息比特序列的载波频率。
- 一种比特解交织装置,包括:接收模块,配置为接收待解交织的矩阵阵列;读取模块,配置为在所述矩阵阵列中按列读取比特序列;解交织模块,配置为对所述矩阵阵列中的每个调制符号内的比特进行解交织,其中,所述矩阵阵列的每列至多对应一个调制符号。
- 一种存储介质,所述存储介质包括存储的程序,其中,所述程序运行时执行权利要求1至15中任一项所述的方法。
- 一种处理器,所述处理器用于运行程序,其中,所述程序运行时执行权利要求1至15中任一项所述的方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710814404.8A CN109495209B (zh) | 2017-09-11 | 2017-09-11 | 比特交织、解交织方法及装置 |
CN201710814404.8 | 2017-09-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2019047741A1 true WO2019047741A1 (zh) | 2019-03-14 |
Family
ID=65633559
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2018/102559 WO2019047741A1 (zh) | 2017-09-11 | 2018-08-27 | 比特交织、解交织方法及装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN109495209B (zh) |
WO (1) | WO2019047741A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111641417A (zh) * | 2020-06-09 | 2020-09-08 | 电子科技大学 | 一种基于fpga的完成矩阵列置换交织的装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116846512B (zh) * | 2023-06-09 | 2024-09-27 | 奉加科技(上海)股份有限公司 | 数据传输方法、数据发送端、数据接收端和存储介质 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090164866A1 (en) * | 2006-03-24 | 2009-06-25 | Mitsubishi Electric Corporation | Interleaving method and communication apparatus |
CN101860412A (zh) * | 2009-04-13 | 2010-10-13 | 中兴通讯股份有限公司 | 子包处理方法、编码调制方法、处理器、调制编码系统 |
WO2013023600A1 (zh) * | 2011-08-17 | 2013-02-21 | 国家广播电影电视总局广播科学研究院 | 数字音频广播系统中业务描述信息的发送接收方法及装置 |
CN104618068A (zh) * | 2015-02-16 | 2015-05-13 | 中国科学院上海高等研究院 | 用于无线广播通信系统的比特交织编码调制装置及方法 |
CN106160971A (zh) * | 2015-04-07 | 2016-11-23 | 电信科学技术研究院 | 一种数据传输、接收信号检测的方法和设备 |
CN106330403A (zh) * | 2016-09-05 | 2017-01-11 | 北京邮电大学 | 一种编译码方法及系统 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101399554B (zh) * | 2007-09-30 | 2012-03-21 | 华为技术有限公司 | 一种基于ldpc码的交织方法和解交织方法及其装置 |
-
2017
- 2017-09-11 CN CN201710814404.8A patent/CN109495209B/zh active Active
-
2018
- 2018-08-27 WO PCT/CN2018/102559 patent/WO2019047741A1/zh active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090164866A1 (en) * | 2006-03-24 | 2009-06-25 | Mitsubishi Electric Corporation | Interleaving method and communication apparatus |
CN101860412A (zh) * | 2009-04-13 | 2010-10-13 | 中兴通讯股份有限公司 | 子包处理方法、编码调制方法、处理器、调制编码系统 |
WO2013023600A1 (zh) * | 2011-08-17 | 2013-02-21 | 国家广播电影电视总局广播科学研究院 | 数字音频广播系统中业务描述信息的发送接收方法及装置 |
CN104618068A (zh) * | 2015-02-16 | 2015-05-13 | 中国科学院上海高等研究院 | 用于无线广播通信系统的比特交织编码调制装置及方法 |
CN106160971A (zh) * | 2015-04-07 | 2016-11-23 | 电信科学技术研究院 | 一种数据传输、接收信号检测的方法和设备 |
CN106330403A (zh) * | 2016-09-05 | 2017-01-11 | 北京邮电大学 | 一种编译码方法及系统 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111641417A (zh) * | 2020-06-09 | 2020-09-08 | 电子科技大学 | 一种基于fpga的完成矩阵列置换交织的装置 |
CN111641417B (zh) * | 2020-06-09 | 2023-03-31 | 电子科技大学 | 一种基于fpga的完成矩阵列置换交织的装置 |
Also Published As
Publication number | Publication date |
---|---|
CN109495209B (zh) | 2022-03-18 |
CN109495209A (zh) | 2019-03-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108282246B (zh) | 信息处理的方法、设备和通信系统 | |
RU2742912C1 (ru) | Способ и устройство кодирования данных, носитель данных и процессор | |
JP6871396B2 (ja) | 情報を処理するための方法および装置、通信デバイス、ならびに通信システム | |
US11171741B2 (en) | Polar code transmission method and apparatus | |
WO2019158031A1 (zh) | 编码的方法、译码的方法、编码设备和译码设备 | |
JP2023014085A (ja) | 情報処理方法および通信装置 | |
US11075652B2 (en) | Polar code transmission method and apparatus | |
KR102338508B1 (ko) | 고차 변조를 사용하는 통신 또는 방송 시스템에서 부호화/복호화 방법 및 장치 | |
AU2018285297A1 (en) | Rate matching method and apparatus, and rate de-matching method and apparatus | |
TWI675566B (zh) | 一種確定校驗矩陣的方法及裝置、電腦存儲介質 | |
JP7221999B2 (ja) | 情報処理方法および通信装置 | |
JP2022174079A (ja) | 符号化方法、復号方法、装置、および装置 | |
JP2020502899A (ja) | 情報処理方法、装置、通信デバイスおよび通信システム | |
US9954696B2 (en) | Method and apparatus for encoding uplink control information | |
CN110663189B (zh) | 用于极化编码的方法和装置 | |
CN111200442A (zh) | 编译码方法、编码译码装置以及系统 | |
CN111446969A (zh) | 一种级联crc码的极化码编码方法及装置 | |
WO2019047741A1 (zh) | 比特交织、解交织方法及装置 | |
WO2019042370A1 (zh) | 数据传输方法及装置 | |
WO2018218471A1 (zh) | 信息处理的方法和通信装置 | |
GB2509073A (en) | Low Density Parity Checking using Interleaver Address Mappings | |
CN111525980B (zh) | 译码方法及装置 | |
US10972220B2 (en) | Interleaving method and apparatus | |
CN111181572B (zh) | Ldpc码字的交织映射方法及解交织解映射方法 | |
CN108574555B (zh) | 干扰随机化方法及设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 18853957 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 18853957 Country of ref document: EP Kind code of ref document: A1 |