WO2019047648A1 - 一种测量电容系统及其测量方法 - Google Patents

一种测量电容系统及其测量方法 Download PDF

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Publication number
WO2019047648A1
WO2019047648A1 PCT/CN2018/098949 CN2018098949W WO2019047648A1 WO 2019047648 A1 WO2019047648 A1 WO 2019047648A1 CN 2018098949 W CN2018098949 W CN 2018098949W WO 2019047648 A1 WO2019047648 A1 WO 2019047648A1
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capacitor
latch
signal
output
level signal
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PCT/CN2018/098949
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English (en)
French (fr)
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王强
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乐鑫信息科技（上海）有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables

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  • the present invention relates to the field of capacitance measurement, and in particular to a capacitance measurement method and a measurement capacitance system.
  • Capacitance measurement technology is widely used in various fields, such as touch sensing and distance sensing.
  • the existing technology separately measures the charging or discharging time of the capacitor when measuring the capacitance value, which has certain limitations, which is not conducive to the accumulation of errors and the improvement of measurement accuracy.
  • the object of the present invention is to provide a measuring capacitance system and a measuring method thereof.
  • the charging and discharging of the capacitor to be tested are controlled by a latch, so that the charging and discharging processes of the capacitor to be tested are quickly connected, which facilitates the accumulation of measurement errors and improves.
  • the purpose of measuring the accuracy is to provide a measuring capacitance system and a measuring method thereof.
  • a measuring capacitance system comprising: a charging current source, one end of which is connected to a current voltage VDD; the other end is electrically connected to a first end of the capacitor to be tested through a first control switch; and the second end of the capacitor to be tested is grounded;
  • the charging current source is used to charge the capacitor to be tested.
  • the discharge current source is grounded at one end, and the other end is electrically connected to the first end of the capacitor to be tested through a second control switch; the discharge current source is used to discharge the capacitor to be tested.
  • the comparator group has an input end connected to the first end of the capacitor to be tested to obtain a voltage value V cap of the capacitor to be tested, and is compared with a set reference voltage threshold in the comparator group.
  • the latch has an input end electrically connected to the output end of the comparator group; a first output end of the latch is connected to the first control switch, and a second output end is connected to the second control switch. And a counter group corresponding to any one of the outputs of the latch for counting the period of the level signal output by the latch and the period of the clock signal clk input to the counter group. And according to the comparison result provided by the comparator group, the latch outputs a signal for switching the first and second control switches to be turned on, so that the charging current source and the discharging current source periodically charge and discharge the capacitance to be measured. Until the counter group completes counting.
  • the comparator group further includes: a first comparator and a second comparator; a non-inverting input of the first comparator inputs a first reference voltage threshold V refh , an inverting input of the first comparator And the non-inverting input end of the second comparator is electrically connected to the first end of the capacitor to be tested; the inverting input end of the second comparator inputs a second reference voltage threshold V refl ; A reference voltage threshold V refh > a second reference voltage threshold V refl .
  • the output of the first comparator outputs a level signal d1 that is coupled to the first input of the latch.
  • the output of the second comparator outputs a level signal d2 that is coupled to the second input of the latch.
  • the first output of the latch outputs a level signal d3, and the second output thereof outputs a level signal d4.
  • the counter group includes: a first counter; a clk end of the first counter is electrically connected to a first output end or a second output end of the latch; and a reset end rstb is connected to the trigger latch.
  • the start signal of the operation; the input terminal din is used for setting the number of times of the period of the level signal d3 outputted by the first output terminal of the latch or the period of the level signal d4 outputted by the second output terminal;
  • the end out is used to output a finish signal indicating that the test is completed.
  • the counter group further includes an AND gate, a second counter connected through the AND gate and the first counter.
  • the three input ends of the AND gate are respectively connected to the clock signal clk, the start signal, and the inverted signal of the finish signal, and the output end of the AND gate is connected to the clock terminal clk of the second counter;
  • the reset terminal rstb is connected to the start signal, and the output terminal out outputs the number N of cycles of the clock pulse signal clk between the start signal and the finish signal recorded by the second counter.
  • the measuring capacitance system is further provided with a calculating unit for solving the capacitance value C test of the capacitor to be measured based on the following formula;
  • M is the set count value.
  • the counter group counts the period T d3 until the count value reaches M, and the counter group also has the period T of the accessed clock pulse signal clk. Clk counts, recorded as the value N;
  • the charging current source is replaced with a charging voltage source in series with the first resistor; the discharging current source is replaced with a discharging voltage source in series with the second resistor.
  • the measuring capacitance system is further provided with a calculating unit for solving the capacitance value C test of the capacitor to be measured based on the following formula;
  • M is the set count value.
  • the counter group counts the period T d3 until the count value reaches M, and the counter group also has the period T of the accessed clock pulse signal clk. Clk is counted and recorded as the value N.
  • Another technical solution of the present invention is a capacitance measuring method based on the above-described measuring capacitance system, which comprises the following process: periodic charging and discharging of a capacitor to be measured is realized by two power sources of a known size. The period of the level signal output by the latch and the period of the clock signal clk are counted.
  • the power source of the known size is a current source, the capacitance value C test of the capacitor to be measured is solved based on the following formula;
  • the respective current value of the periodic signal level latch output T d3, charging current source and discharging current source I b1 and I b2; V refh, V refl two reference voltages is a threshold set in the comparator group And, by being compared with the voltage value V cap of each capacitor to be tested, after latching, it is used to control charging and discharging.
  • the period of the period signal T d3 of the level signal is:
  • M is the set count value.
  • the counter group counts the period T d3 of the level signal until the count value reaches M, and stops, and the counter group also accesses the clock pulse signal.
  • the period T clk of clk is counted and recorded as the value N.
  • the capacitance value C test of the capacitance to be measured is solved based on the following formula:
  • the invention controls the charging and discharging of the capacitor to be tested through the latch, so that the charging and discharging processes of the capacitor to be tested are quickly connected, which facilitates the accumulation of measurement errors.
  • the sampling accuracy is increased by increasing the sampling time.
  • the invention has the advantages of simple circuit structure, simple and convenient measurement method and low measurement cost.
  • FIG. 1 is a schematic structural diagram of a circuit for measuring a capacitance system according to the present invention
  • FIG. 2 is a schematic diagram of waveforms of a comparator and a latch output signal of a measuring capacitance system during measurement according to the present invention
  • FIG. 3 is a schematic diagram showing the number of cycles of a clock signal pulse from the beginning to the end of a counter for measuring a capacitance system according to the present invention
  • FIG. 4 is a schematic diagram showing the circuit structure of an embodiment of a measuring capacitance system according to the present invention.
  • a measuring capacitance system of the present invention comprises: a charging current source I b1 , one end of which is connected to a current voltage VDD ; the other end is electrically connected to a first end of the capacitor to be tested through a first control switch SW1 ; The second end of the capacitor to be tested is grounded.
  • the discharge current source I b2 has one end grounded and the other end electrically connected to the first end of the capacitor to be tested through the second control switch SW2.
  • the comparator group 1 has an input terminal connected to the first end of the capacitor to be tested; the capacitor to be tested provides an initial comparison voltage value for the comparator group 1, that is, a voltage value V cap of the capacitor to be tested.
  • the comparator group 1 further includes a first comparator comp1 and a second comparator comp2; the non-inverting input terminal of the first comparator comp1 inputs an in-phase input voltage V refh , an inverting input terminal of the first comparator comp1 , and the foregoing
  • the non-inverting input terminals of the comparators comp2 are respectively electrically connected to the first end of the capacitor to be tested; the inverting terminal input voltage of the inverting input terminal of the second comparator comp2 is V refl .
  • the output terminal of the first comparator comp1 outputs a level signal d1 which is connected to the R terminal of the latch.
  • the output terminal of the second comparator comp2 outputs a level signal d2 which is connected to the S terminal of the latch.
  • the latch 2 has an input terminal electrically connected to the output end of the comparator group 1; a first output terminal thereof is connected to the first control switch SW1; and a second output terminal is connected to the second control switch SW2.
  • the first output of the latch 2 outputs a level signal d3, and the second output thereof outputs a level signal d4.
  • the invention further comprises a counter group 3 comprising a first counter and a second counter connected to the first counter via the AND gate; the clk terminal of the first counter and the first output or the second output of the latch.
  • the first and second counter reset terminals rstb, and the trigger terminal of the latch 2 simultaneously access a start signal that triggers the latch to start operation.
  • the input terminal din of the first counter is used to set a period for counting the level signal d3 outputted by the first output terminal of the latch 2 or the level signal d4 outputted by the second output terminal.
  • the clk end of the first counter is electrically connected to the first output end of the latch. It counts the period of the level signal d3 outputted from the first output of the latch 2.
  • the output terminal out of the first counter is configured to output a test completion signal, that is, a finish signal, when the first counter records a period of M d3 signals.
  • the three input terminals of the AND gate respectively access the start signal, the clock pulse signal clk, and the signal inverted by the finish signal output by the first counter.
  • the output of the AND gate is connected to the clock terminal clk of the second counter.
  • the output terminal out of the second counter outputs a dout signal.
  • the input terminal din of the first counter is set to record the period of the level signal d3 M times; the start signal is connected, the trigger latch 2 starts to work, and the first counter is triggered to start the period of the level signal d3.
  • the finish signal is always a low level signal during the operation of the first counter, and the three input terminals of the AND gate are input with a high level signal after the inversion, the output signal of the AND gate outputs a high level signal.
  • the second counter counts the clock pulse clk cycle; when the first counter ends counting, the output finish signal is a rising edge signal, and after being inverted, input to the AND gate, the AND gate output Outputting a low level signal, at this time, the second counter ends counting the period of the clock pulse signal clk, and outputs the clock from the start signal to the finish signal recorded by the second counter through the out end of the second counter
  • the number of cycles of the pulse signal clk is N.
  • the overall test capacitor pair of the test capacitor system of the present invention works by charging or discharging a capacitor to be measured by a reference current source of a known magnitude. When the voltage is higher or lower than a certain threshold, charging or discharging is stopped, and the capacitor is started immediately.
  • the other reference current source discharges (or charges) the capacitance to be measured, and repeats the above process, so that the voltage of the capacitor to be tested periodically fluctuates; and further, by measuring the period of the voltage, the magnitude of the capacitance to be measured is obtained.
  • the present invention also discloses a method for testing capacitance; the following process is included:
  • the initial value is 0;
  • the non-inverting terminal input voltage V refh >V cap of the first comparator; the level signal d1 1 outputted by the first comparator is a high level signal.
  • the inverting terminal of the second comparator inputs the voltage V refl >V cap ; the level signal d2 of the second comparator outputs is a low level signal.
  • the first control switch SW1 is turned on, and the second control switch SW2 is turned off; the charging current source I b1 charges the capacitor to be tested through the turned-on first control switch SW1.
  • the slope of the capacitor voltage rise is I b1 /C test .
  • the capacitor to be tested remains in the charging state.
  • V refh V cap of the first comparator
  • the inverting terminal of the second comparator inputs the voltage V cap >V refl ; the level signal d2 of the second comparator outputs is a signal that remains high.
  • the first control switch SW1 is turned off, the second control switch SW2 is turned on, and the discharge current source I b2 is passed.
  • the second control switch SW2 discharges the above-mentioned charged capacitor to be tested, and the slope of the voltage drop of the capacitor to be tested is I b2 /C test ; due to the comparator group 1, the latch 2 and the above two control switches The delay is small.
  • the inverting terminal of the second comparator inputs the voltage V refl ⁇ V cap ; the level signal d2 of the second comparator output is 1, and the high level signal is maintained.
  • a complete process of charging and discharging the capacitor to be tested is completed. Repeating this process until the first counter counts the period of the d3 periodic signal outputted by the first output of the latch 2 to the set value M times, then the output detection completion signal finish signal, that is, the end of the measurement;
  • the counter outputs the number N of cycles of the clock signal clk for this short period from the start of measurement to the end of measurement.
  • the relationship between the period T d3 of the d3 signal outputted by the first output terminal of the latch 2 and the period T clk of the clock signal clk is as follows:
  • the relationship between the period T d3 of the d3 signal outputted by the first output terminal of the latch 2 and the capacitance value C test of the capacitance to be tested and the above-mentioned charging and discharging current source is:
  • the capacitance value can be determined above measured capacitance C test.
  • the above measurement method further comprises the following process: increasing the sampling time, since the counter 3 can only perform the cumulative counting of the whole cycle or the half cycle, when the error is less than one cycle or half cycle, it is ignored; then the signal d 3 is set.
  • clock signal clk period T d3 can be recorded in the second counter represents a period T d3, as follows:
  • C is the integer part recorded by the second counter
  • ⁇ is the negated fractional part, 0 ⁇ ⁇ ⁇ 1.
  • the counter When the first counter records M times for one period T d3 of the signal d 3 ; according to the equation (4), the counter actually obtains the value MCT clk , ignoring the error portion M ⁇ in the above equation (4), and the ignored portion is It is possible to be greater than 1.
  • each cycle of the signal d3 is connected to facilitate the accumulation of errors, and by increasing the sampling time, that is, by increasing the value of M, the error accumulation time is prolonged, and the capacitance measurement is improved. Precision. That is, for the same measurement capacitance, the measurement accuracy can be increased by 1 bit for every doubling of the M value.
  • Another embodiment of the present invention is: replacing the charging current source I b1 with a charging voltage source V h in series with the first resistor R1 based on the capacitance measuring system described above; replacing the discharging current source I b2 with The discharge voltage source V 1 in series with the second resistor R2; the remainder is identical in structure to the capacitance measuring system described above.
  • the working principle is that the capacitance to be measured is charged by the charging voltage source V h and the first resistor R1, and V h >V refh ; the capacitance to be measured is discharged by the discharging voltage source V 1 and the second resistor R2, and V 1 ⁇ V refl . At this time, since the manner of the RC response rises and falls, the slope of the charge and discharge curves of the voltage V cap of the capacitor to be tested is not fixed.
  • the resistance values R 1 and R 2 of the first resistor and the second resistors R1 and R2 are known; the voltage values V h and V 1 of the voltage source of the charge and discharge are known; the initial voltages V refl and V of the comparator The value of refh is known.
  • the capacitance value C test of the capacitor to be tested can be calculated.
  • the measurement accuracy can also be improved by increasing the number of cycles of charge and discharge of the capacitor to be tested.

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Abstract

本发明公开了一种测量电容系统及其测量方法，包含：充电电流源，其对待测电容进行充电；放电电流源，其对所述待测电容进行放电；比较器组，其输入端与所述待测电容的第一端连接；所述待测电容为比较器组提供初始比较电压值，即待测电容的电压值Vcap；锁存器，其输入端与比较器组的输出端电性连接；其第一输出端对应与所述第一控制开关连接；其第二输出端与所述第二控制开关连接；计数器组，其与所述锁存器的输出端连接，用于对锁存器输出的电平信号的一个周期进行计数。本发明具有电路结构简单，测量方法简单便捷，测量成本低廉，测量精度高的优点。

Description

一种测量电容系统及其测量方法 技术领域
本发明涉及电容测量领域，具体涉及一种电容测量方法与测量电容系统。
背景技术
电容测量技术广泛应用于各种领域之中，比如触摸感应、距离感应等。现有的技术在测量电容值时，对电容充电或放电时间单独测量，这存在一定的局限性，不利于误差的累积和测量精度的提高。
发明内容
本发明的目的是提供一种测量电容系统及其测量方法；通过锁存器来控制待测电容的充放电，使得待测电容的充电和放电的过程迅速衔接，便于测量误差的累积，达到提高测量的精度的目的。
为了实现以上目的，本发明通过以下技术方案实现：
一种测量电容系统，包含：充电电流源，其一端接入电流电压VDD；另一端通过第一控制开关与待测电容的第一端电性连接；所述待测电容的第二端接地；所述充电电流源用于对所述待测电容进行充电。放电电流源，其一端接地，另一端通过第二控制开关与所述待测电容的第一端电性连接；所述放电电流源用于对所述待测电容进行放电。比较器组，其输入端与所述待测电容的第一端连接，以获取待测电容的电压值V cap，在比较器组中与设定的参考电压阈值进行比较。锁存器，其输入端与比较器组的输出端电性连接；锁存器的第一输出端对应与所述第一控制开关连接，第二输出端与所述第二控制开关连接。计数器组，其对应与所述锁存器的任意一个输出端连接，用于对锁存器输出的电平信号的周期以及输入到计数器组的时钟脉冲信号clk的周期进行计数。根据所述比较器组提供的比较结果，所述锁存器输出使第一与第二控制开关切换导通的信号，使得所述充电电流源与放电电流源周期性地对待测电容进行充放电，直至所述计数器组完成计数。
优选地，所述比较器组进一步包含：第一比较器与第二比较器；所述 第一比较器的同相输入端输入第一参考电压阈值V refh，所述第一比较器的反相输入端和所述第二比较器的同相输入端分别与待测电容的第一端电性连接；所述第二比较器的反相输入端输入第二参考电压阈值V refl；其中，所述第一参考电压阈值V refh＞第二参考电压阈值V refl。
优选地，所述第一比较器的输出端输出电平信号d1，其与锁存器的第一输入端连接。所述第二比较器的输出端输出电平信号d2，其与锁存器的第二输入端连接。所述锁存器的第一输出端输出电平信号d3，其第二输出端输出电平信号d4。当V refh＞V cap，V refl＞V cap时，所述比较器组输出电平信号d1＝1，d2＝0；所述锁存器组输出电平信号d3＝1，d4＝0；所述第一控制开关导通，第二控制开关断开，待测电容充电。当待测电容的电压值V cap＝V refl时，所述电平信号d1＝1，d2＝1；所述电平信号d3＝1，d4＝0；待测电容继续充电。当待测电容的电压值V cap＝V refh时，所述电平信号d1＝0，d2＝1；所述电平信号d3＝0，d4＝1；所述第一控制开关断开，第二控制开关导通，待测电容放电；此时，V refh＞V cap＞V refl，所述电平信号d1＝1，d2＝1；所述电平信号d3＝0，d4＝1，待测电容继续放电。当待测电容的电压值V cap＝V refl时，所述电平信号d1＝1，d2＝0；所述电平信号d3＝1，d4＝0，待测电容充电。
优选地，所述计数器组包含：第一计数器；所述第一计数器的clk端与锁存器的第一输出端或第二输出端电性连接；其复位端rstb接入触发锁存器开始工作的start信号；其输入端din用于设置对锁存器的第一输出端输出的电平信号d3的周期或第二输出端输出的电平信号d4的周期进行计数的次数M；其输出端out用于输出表示测试完成的finish信号。
优选地，所述计数器组还包含与门，通过该与门和所述第一计数器连接的第二计数器。所述与门的三个输入端分别接入时钟脉冲信号clk、start信号、finish信号的反相信号，所述与门的输出端与第二计数器的时钟端clk连接；所述第二计数器的复位端rstb接入start信号，其输出端out输出第二计数器所记录的从start信号至finish信号之间的时钟脉冲信号clk的周期数N。
优选地，所述测量电容系统还设有一计算单元，基于以下算式对待测电容的电容值C test进行求解；
Figure PCTCN2018098949-appb-000001
其中，锁存器输出的电平信号的周期T d3，充电电流源和放电电流源各自的电流值I b1与I b2；
周期T d3的算式为：
NT clk＝M T d3
式中，M是设定的计数值，触发锁存器开始工作起，计数器组对周期T d3进行计数直到计数值达到M后停止，期间计数器组还对接入的时钟脉冲信号clk的周期T clk进行计数，记为数值N；
优选地，所述充电电流源替换为与第一电阻串联的充电电压源；所述放电电流源替换为与第二电阻串联的放电电压源。
优选地，所述测量电容系统还设有一计算单元，基于以下算式对待测电容的电容值C test进行求解；
Figure PCTCN2018098949-appb-000002
其中，锁存器输出的电平信号的周期T d3，充电电压源和放电电压源各自的电压值V h与V 1；第一电阻和第二电阻的阻值R 1与R 2。
周期T d3的算式为：
NT clk＝M T d3
式中，M是设定的计数值，触发锁存器开始工作起，计数器组对周期T d3进行计数直到计数值达到M后停止，期间计数器组还对接入的时钟脉冲信号clk的周期T clk进行计数，记为数值N。
本发明另一个技术方案为一种基于上文所述的测量电容系统的电容测量方法，包含以下过程：通过已知大小的两个电源，实现对待测电容的周期性充放电。对锁存器输出的电平信号的周期以及时钟脉冲信号clk的周期进行计数。当所述已知大小的电源为电流源时，基于以下算式对待测电容的电容值C test进行求解；
Figure PCTCN2018098949-appb-000003
其中，锁存器输出的电平信号的周期T d3，充电电流源和放电电流源各自的电流值I b1与I b2；V refh、V refl是比较器组中设定的两个参考电压阈值，且通过各自与待测电容的电压值V cap的比较结果、经锁存后用来对充放电进行控 制。
电平信号的周期T d3的算式为：
NT clk＝M T d
式中，M是设定的计数值，触发锁存器开始工作起，计数器组对电平信号的周期T d3进行计数直到计数值达到M后停止，期间计数器组还对接入的时钟脉冲信号clk的周期T clk进行计数，记为数值N。
优选地，当所述已知大小的电源为带有串联电阻的电压源时，基于以下算式对待测电容的电容值C test进行求解：
Figure PCTCN2018098949-appb-000004
式中，锁存器输出的电平信号的周期T d3，充电电压源和放电电压源各自的电压值V h与V 1；R 1、R 2分别为与充或放电电压源串联的电阻的阻值；V refh、V refl是比较器组中设定的两个参考电压阈值，且通过各自与待测电容的电压值V cap的比较结果、经锁存后用来对充放电进行控制。
本发明与现有技术相比具有以下优点：
本发明通过锁存器来控制待测电容的充放电，使得待测电容的充电和放电的过程迅速衔接，便于测量误差的累积，在测量同一电容时，通过增加采样时间具有提高测量的精度的优点。
本发明具有电路结构简单，测量方法简单便捷，测量成本低廉的优点。
附图说明
图1为本发明一种测量电容系统的电路结构示意图；
图2为本发明一种测量电容系统在测量时比较器与锁存器输出信号的波形示意图；
图3为本发明一种测量电容系统的计数器从开始至结束时的时钟信号脉冲的周期数的示意图；
图4为本发明一种测量电容系统的一个实施例的电路结构示意图。
具体实施方式
以下结合附图，通过详细说明一个较佳的具体实施例，对本发明做进一步阐述。
如图1所示，本发明一种测量电容系统，包含：充电电流源I b1，其一 端接入电流电压VDD；另一端通过第一控制开关SW1与待测电容的第一端电性连接；所述待测电容的第二端接地。
放电电流源I b2，其一端接地，另一端通过第二控制开关SW2与待测电容的第一端电性连接。
比较器组1，其输入端与上述待测电容的第一端连接；上述待测电容为比较器组1提供初始比较电压值，即待测电容的电压值V cap。
上述比较器组1进一步包含第一比较器comp1与第二比较器comp2；上述第一比较器comp1的同相输入端输入同相端输入电压V refh，第一比较器comp1的反相输入端和上述第二比较器comp2的同相输入端分别与待测电容的第一端电性连接；上述第二比较器comp2的反相输入端的反相端输入电压为V refl。
上述第一比较器comp1的输出端输出电平信号d1，其与锁存器的R端连接。上述第二比较器comp2的输出端输出电平信号d2，其与锁存器的S端连接。
锁存器2，其输入端与比较器组1的输出端电性连接；其第一输出端对应与第一控制开关SW1连接；其第二输出端与第二控制开关SW2连接。所述锁存器2的第一输出端输出电平信号d3，其第二输出端输出电平信号d4。
本发明还设有一计数器组3，其包含第一计数器，以及通过与门与第一计数器连接的第二计数器；第一计数器的clk端与锁存器的第一输出端或者第二输出端电性连接；第一与第二计数器的复位端rstb，以及所述锁存器2的触发端同时接入触发锁存器开始工作的start信号。第一计数器的输入端din用于设置对锁存器2的第一输出端输出的电平信号d3或者第二输出端输出的电平信号d4的周期进行计数。
在本实施例中，上述第一计数器的clk端与锁存器的第一输出端电性连接。其为对锁存器2的第一输出端输出的电平信号d3的周期进行计数。
第一计数器的输出端out用于当上述第一计数器在记录M个d3信号的周期时，输出测试完成信号，即finish信号。
上述与门的三个输入端分别接入start信号、时钟脉冲信号clk、对第一计数器输出的finish信号取反后的信号。上述与门的输出端与第二计数器的 时钟端clk连接。第二计数器的输出端out输出dout信号。
在本实施例中，设置第一计数器的输入端din对电平信号d3的周期记录M次；接入start信号，触发锁存器2开始工作，触发第一计数器开始对电平信号d3的周期进行计数，触发第二计数器开始对时钟脉冲信号clk的周期进行计数；当第一计数器计数M次时，上述第一计数器的输出端out输出测试完成信号即finish信号。此时，由于finish信号在第一计数器工作期间一直为低电平信号，取反后上述与门的三个输入端均输入高电平信号，则上述与门输出端输出高电平信号，所述第二计数器对时钟脉冲信号clk周期进行计数；当第一计数器结束计数时，输出的finish信号为一个上升沿信号，对其取反后，输入至上述与门中，则上述与门输出端输出低电平信号，此时，所述第二计数器结束对时钟脉冲信号clk的周期进行计数，并通过第二计数器的out端输出第二计数器所记录的从start信号至finish信号之间的时钟脉冲信号clk的周期数N。
本发明测试电容系统的总体测试电容对的工作原理为：通过已知大小的基准电流源对待测电容进行充电或放电，当电压高于或低于某一阈值时，停止充电或放电，立刻启动另一基准电流源对待测电容进行放电(或充电)，重复上述过程，使得上述待测电容的电压进行周期性波动；进而通过测量该电压的周期，得到上述待测电容值的大小。
基于上述的测试电容系统，本发明还公开了一种测试电容的方法；包含以下过程：
设置待测电容上的电压V cap初始值，在本实施例中，另其初始值为0；
设置第一计数器对锁存器的第一输出端输出的d3信号的周期进行计数M次；
如图2所示，此时，第一比较器的同相端输入电压V refh＞V cap；第一比较器输出的电平信号d1＝1，为高电平信号。
第二比较器的反相端输入电压V refl＞V cap；第二比较器输出的电平信号d2＝0，为低电平信号。
当输入的start信号从低电平变成高电平时，其形成的上升沿触发锁存器开始工作；同时，如图3所示，当输入的start信号从低电平变成高电平时，第二计数器开始输入的时钟脉冲信号clk的周期进行计数。
由于输入的电平信号d1＝1，d2＝0，则锁存器对应输出的电平信号为第一输出端输出的电平信号d3＝1，第二输出端输出的电平信号d4＝0，此时，第一控制开关SW1导通，第二控制开关SW2断开；充电电流源I b1通过导通的第一控制开关SW1对上述待测电容充电，此时，电容电压上升的斜率为I b1/C test。
当上述待测电容的电压V cap＝V refl时，第一比较器的同相端输入电压V refh＞V cap；第一比较器输出的电平信号d1＝1，仍保持为高电平信号。
第二比较器的反相端输入电压V refl＝V cap；第二比较器输出的电平信号d2＝1，瞬时跳转为高电平信号。
此时，锁存器输出的电平信号保持不变，即第一输出端输出的电平信号d3＝1，第二输出端输出的电平信号d4＝0。
此时，待测电容保持充电状态，当待测电容的电压上升到V refh时，第一比较器的同相端输入电压V refh＝V cap；第一比较器输出的电平信号d1＝0，瞬时转变为低电平信号。
第二比较器的反相端输入电压V cap＞V refl；第二比较器输出的电平信号d2＝1，为保持为高电平信号。
锁存器2的两个输出端输出的电平信号分别为d3＝0，d4＝1，此时，第一控制开关SW1断开，第二控制开关SW2导通；放电电流源I b2通过第二控制开关SW2对上述充过电的待测电容进行放电，该待测电容电压下降的斜率为I b2/C test；由于比较器组1、锁存器2的和上述两个控制开关造成的延迟很小。在待测电容开始放电时，待测电容电压立刻下降至V refh以下，即V refl＜V cap＜V refh；因此，第一比较器的同相端输入电压V refh＞V cap；第一比较器输出的电平信号d1＝1，为高电平信号。
第二比较器的反相端输入电压V refl＜V cap；第二比较器输出的电平信号d2＝1，保持高电平信号。
此时，锁存器的两个输出端分别输出的信号d3＝0，d4＝1；上述第一控制开关SW1保持断开；第二控制开关SW2保持导通；上述放电电流源I b2继续对待测电容进行放电。
当待测电容电压下降至V refl时；即V cap＝V refl，第一比较器的同相端输入电压V refh＞V cap；第一比较器输出的电平信号d1＝1，保持为高电平信号。
第二比较器的反相端输入电压V refl＝V cap；第二比较器输出的电平信号d2＝0，转换成低电平信号。
此时，锁存器的两个输出端分别输出的信号d3＝1，d4＝0；上述第一控制开关SW1导通；第二控制开关SW2断开；上述充电电流源I b1对待测电容进行充电。此时完成对待测电容的充放电的一个完整的过程。重复此过程，直至第一计数器对锁存器2的第一输出端输出的d3周期性信号的周期计数到达设定值M次，则其输出检测完成信号finish信号，即代表测量结束；第二计数器输出在开始测量到测量结束时，此短期间的时钟脉冲信号clk的周期数N。上述的锁存器2的第一输出端输出的d3信号的周期T d3与上述时钟脉冲信号clk的周期T clk的关系为：
NT clk＝MT d3           (1)
根据上述的测量系统，则锁存器2的第一输出端输出的d3信号的周期T d3与上述待测电容的电容值C test以及上述充电和放电电流源的关系式为：
Figure PCTCN2018098949-appb-000005
结合公式(1)与(2)由于充电与放电电流源输出的电流值是已知的，因此即可求出上述待测电容的电容值C test。
上述测量方法进一步包含以下过程：增加采样时间，由于上述计数器3只能进行整周期或者半周期的累加计数，当误差小于一个周期或者半个周期时，就会忽略不计；则设信号d 3的周期T d3可以用第二计数器记录的时钟脉冲信号clk的周期T d3表示，具体如下：
T d3＝CT clk+δ          (3)
其中，C是被上述第二计数器记录的整数部分，δ是被忽略的小数部分，0＜δ＜1。
将式(3)等式两边同乘以M，得到：
MT d3＝MCT clk+Mδ         (4)
当第一计数器对信号d 3的一个周期T d3记录了M次时；根据式(4)，计数器实际得到值为MCT clk，忽略上式(4)中的误差部分Mδ，被忽略的部分是有可能大于1的。
这样通过使用锁存器控制上文中的控制开关，将信号d3的每个周期连接起来，有利于误差的累积，通过增加采样时间，即通过增加M的值，延 长误差累积的时间，提高电容测量精度。即对同样的测量电容，M值每增加一倍，测量精度可以提高1bit。
本发明的另一个实施例为：基于上文所述的电容测量系统，将上述充电电流源I b1替换为与第一电阻R1串联的充电电压源V h；将上述放电电流源I b2替换为与第二电阻R2串联的放电电压源V 1；其余部分与上文中所述的电容测量系统的结构相同。
其工作原理为通过充电电压源V h和第一电阻R1对待测电容充电，且V h＞V refh；通过放电电压源V 1和第二电阻R2对待测电容放电，且V 1＜V refl。此时，由于RC响应的方式上升和下降，即待测电容的电压V cap的充电与放电曲线斜率不是固定的。
此时，信号d 3的周期T d3与待测电容的电容值C test之间的关系式为：
Figure PCTCN2018098949-appb-000006
因此，由于第一电阻与第二电阻R1、R2的电阻值R 1、R 2已知；充放电的电压源输出的电压值V h与V 1已知；比较器的初始电压V refl与V refh的值已知，此时，计数器测得了信号d 3的周期T d3后，即可算出待测电容的电容值C test。
在本实施例中，也可以通过增加待测电容充放电的周期数，来提高测量精度。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (10)

  1. 一种测量电容系统，其特征在于，包含：
    充电电流源，其一端接入电流电压VDD；另一端通过第一控制开关与待测电容的第一端电性连接；所述待测电容的第二端接地；所述充电电流源用于对所述待测电容进行充电；
    放电电流源，其一端接地，另一端通过第二控制开关与所述待测电容的第一端电性连接；所述放电电流源用于对所述待测电容进行放电；
    比较器组，其输入端与所述待测电容的第一端连接，以获取待测电容的电压值V cap，在比较器组中与设定的参考电压阈值进行比较；
    锁存器，其输入端与比较器组的输出端电性连接；锁存器的第一输出端对应与所述第一控制开关连接，第二输出端与所述第二控制开关连接；
    计数器组，其对应与所述锁存器的任意一个输出端连接，用于对锁存器输出的电平信号的周期以及输入到计数器组的时钟脉冲信号clk的周期进行计数；
    根据所述比较器组提供的比较结果，所述锁存器输出使第一与第二控制开关切换导通的信号，使得所述充电电流源与放电电流源周期性地对待测电容进行充放电，直至所述计数器组完成计数。
  2. 如权利要求1所述的测量电容系统，其特征在于，
    所述比较器组进一步包含：第一比较器与第二比较器；所述第一比较器的同相输入端输入第一参考电压阈值V refh，所述第一比较器的反相输入端和所述第二比较器的同相输入端分别与待测电容的第一端电性连接；所述第二比较器的反相输入端输入第二参考电压阈值V refl；其中，所述第一参考电压阈值V refh＞第二参考电压阈值V refl。
  3. 如权利要求2所述的测量电容系统，其特征在于，
    所述第一比较器的输出端输出电平信号d1，其与锁存器的第一输入端连接；
    所述第二比较器的输出端输出电平信号d2，其与锁存器的第二输入端连 接；
    所述锁存器的第一输出端输出电平信号d3，其第二输出端输出电平信号d4；
    当V refh＞V cap，V refl＞V cap时，所述比较器组输出电平信号d1＝1，d2＝0；所述锁存器组输出电平信号d3＝1，d4＝0；所述第一控制开关导通，第二控制开关断开，待测电容充电；
    当待测电容的电压值V cap＝V refl时，所述电平信号d1＝1，d2＝1；所述电平信号d3＝1，d4＝0；待测电容继续充电；
    当待测电容的电压值V cap＝V refh时，所述电平信号d1＝0，d2＝1；所述电平信号d3＝0，d4＝1；所述第一控制开关断开，第二控制开关导通，待测电容放电；
    此时，V refh＞V cap＞V refl，所述电平信号d1＝1，d2＝1；所述电平信号d3＝0，d4＝1，待测电容继续放电；
    当待测电容的电压值V cap＝V refl时，所述电平信号d1＝1，d2＝0；所述电平信号d3＝1，d4＝0，待测电容充电。
  4. 如权利要求1所述的测量电容系统，其特征在于，
    所述计数器组包含：第一计数器；所述第一计数器的clk端与锁存器的第一输出端或第二输出端电性连接；其复位端rstb接入触发锁存器开始工作的start信号；其输入端din用于设置对锁存器的第一输出端输出的电平信号d3的周期或第二输出端输出的电平信号d4的周期进行计数的次数M；其输出端out用于输出表示测试完成的finish信号。
  5. 如权利要求4所述的测量电容系统，其特征在于，
    所述计数器组还包含与门，通过该与门和所述第一计数器连接的第二计数器；
    所述与门的三个输入端分别接入时钟脉冲信号clk、start信号、finish信号的反相信号，所述与门的输出端与第二计数器的时钟端clk连接；所述第二计数器的复位端rstb接入start信号，其输出端out输出第二计数器所记录的从start信号至finish信号之间的时钟脉冲信号clk的周期数N。
  6. 如权利要求1所述的测量电容系统，其特征在于，所述测量电容系统还设有一计算单元，基于以下算式对待测电容的电容值C test进行求解；
    Figure PCTCN2018098949-appb-100001
    其中，锁存器输出的电平信号的周期T d3，充电电流源和放电电流源各自的电流值I b1与I b2；
    周期T d3的算式为：
    NT clk＝MT d3
    式中，M是设定的计数值，触发锁存器开始工作起，计数器组对周期T d3进行计数直到计数值达到M后停止，期间计数器组还对接入的时钟脉冲信号clk的周期T clk进行计数，记为数值N。
  7. 如权利要求1-6中任意一项所述的测量电容系统，其特征在于，
    所述充电电流源替换为与第一电阻串联的充电电压源；所述放电电流源替换为与第二电阻串联的放电电压源。
  8. 如权利要求7所述的测量电容系统，其特征在于，所述测量电容系统还设有一计算单元，基于以下算式对待测电容的电容值C test进行求解；
    Figure PCTCN2018098949-appb-100002
    其中，锁存器输出的电平信号的周期T d3，充电电压源和放电电压源各自的电压值V h与V l；第一电阻和第二电阻的阻值R 1与R 2；
    周期T d3的算式为：
    NT clk＝MT d3
    式中，M是设定的计数值，触发锁存器开始工作起，计数器组对周期T d3进行计数直到计数值达到M后停止，期间计数器组还对接入的时钟脉冲信号clk的周期T clk进行计数，记为数值N。
  9. 一种基于权要求1～8任意一项所述的测量电容系统的电容测量方法，其特征在于，包含以下过程：
    通过已知大小的两个电源，实现对待测电容的周期性充放电；
    对锁存器输出的电平信号的周期以及时钟脉冲信号clk的周期进行计数；
    当所述已知大小的电源为电流源时，基于以下算式对待测电容的电容值C test进行求解；
    Figure PCTCN2018098949-appb-100003
    其中，锁存器输出的电平信号的周期T d3，充电电流源和放电电流源各自的电流值I b1与I b2；V refh、V refl是比较器组中设定的两个参考电压阈值，且通过各自与待测电容的电压值V cap的比较结果、经锁存后用来对充放电进行控制；
    电平信号的周期T d3的算式为：
    NT clk＝MT d3
    式中，M是设定的计数值，触发锁存器开始工作起，计数器组对电平信号的周期T d3进行计数直到计数值达到M后停止，期间计数器组还对接入的时钟脉冲信号clk的周期T clk进行计数，记为数值N；
  10. 如权利要求9所述的电容测量方法，其特征在于，当所述已知大小的电源为带有串联电阻的电压源时，基于以下算式对待测电容的电容值C test进行求解：
    Figure PCTCN2018098949-appb-100004
    式中，锁存器输出的电平信号的周期T d3，充电电压源和放电电压源各自的电压值V h与V l；R 1、R 2分别为与充或放电电压源串联的电阻的阻值；V refh、V refl是比较器组中设定的两个参考电压阈值，且通过各自与待测电容的电压值V cap的比较结果、经锁存后用来对充放电进行控制。
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