WO2019041898A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2019041898A1
WO2019041898A1 PCT/CN2018/088012 CN2018088012W WO2019041898A1 WO 2019041898 A1 WO2019041898 A1 WO 2019041898A1 CN 2018088012 W CN2018088012 W CN 2018088012W WO 2019041898 A1 WO2019041898 A1 WO 2019041898A1
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Prior art keywords
reflective
layer
region
array substrate
film
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PCT/CN2018/088012
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English (en)
French (fr)
Inventor
操彬彬
艾力
张辉
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18852376.5A priority Critical patent/EP3678179B1/en
Priority to US16/335,995 priority patent/US10871685B2/en
Publication of WO2019041898A1 publication Critical patent/WO2019041898A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0232—Optical elements or arrangements associated with the device
    • H01L31/02327—Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133371—Cells with varying thickness of the liquid crystal layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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    • G02—OPTICS
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    • G02F2203/00—Function characteristic
    • G02F2203/09—Function characteristic transflective

Definitions

  • At least one example of the present disclosure relates to an array substrate, a method of fabricating the same, and a display device.
  • the light source of the liquid crystal display is mainly a backlight, and the backlight is greatly reduced in the utilization of the backlight through the substrate, the color filter, etc., and the display image on the screen cannot be seen even in a room with strong light.
  • the industry has developed a transflective display.
  • At least one example of the present disclosure relates to an array substrate, a method of fabricating the same, and a display device to improve a diffuse reflection effect of a reflective region.
  • At least one example of the present disclosure provides an array substrate including:
  • a substrate substrate including a pixel region, the pixel region including a reflective region
  • a reflective layer layer structure including a particle layer in the reflective region, the particle layer being configured to have a grainy rough surface on a side of the reflective region layer structure away from the substrate substrate;
  • a reflective electrode is on the particle layer.
  • the reflective region layer structure includes a base portion, the particle layer is located on a side of the base portion away from the base substrate, and is in contact with the base portion .
  • the material of the base portion includes a conductive material or a semiconductor material.
  • the substrate of the base portion includes a metal oxide
  • the material of the particle layer includes a metal
  • the metal oxide includes at least one of indium tin oxide (ITO) and indium gallium zinc oxide (IGZO).
  • ITO indium tin oxide
  • IGZO indium gallium zinc oxide
  • the particle layer has a particle diameter of less than or equal to 100 nm.
  • the pixel region further includes a transmissive region including a transmissive electrode, the reflective region layer structure being in the same layer as the transmissive electrode.
  • An array substrate further comprising a thin film transistor, wherein the thin film transistor includes a semiconductor active layer and a source and drain layer, and the reflective region layer structure and the semiconductor have The source layer is located in the same layer, and the reflective electrode is located in the same layer as the source and drain layers.
  • At least one example of the present disclosure further provides a method for fabricating an array substrate, including:
  • the substrate comprising a pixel region, the pixel region comprising a reflective region, the reflective region film being formed in the reflective region;
  • a reflective electrode is formed on the particle layer.
  • the reflective region film material comprises a conductive material or a semiconductor material.
  • the reflective region film material includes a metal oxide
  • the granular layer material includes a metal
  • the metal oxide includes at least one of indium tin oxide (ITO) and indium gallium zinc oxide (IGZO).
  • roughening the side of the reflective film that is away from the substrate to form a particle layer includes: performing a reduction process on the reflective film At least the metal oxide of the surface of the reflective film is reduced to metal particles, and the particle layer is configured to have a grainy rough surface on a side of the reflective film away from the substrate.
  • the reflective film is subjected to a reduction treatment such that the metal oxide of the reflective film is all reduced to metal particles.
  • the reflective film is subjected to a reduction treatment using a plasma.
  • the plasma is a reducing plasma
  • the reducing plasma includes at least one of a hydrogen plasma and an ammonia plasma.
  • the particle layer has a particle diameter of less than or equal to 100 nm.
  • the pixel region further includes a transmissive region including a transmissive electrode, the reflective region film being in the same layer as the transmissive electrode.
  • the fabrication method further includes forming a thin film transistor, wherein the thin film transistor includes a semiconductor active layer and a source and drain layer, and the reflective region film and the semiconductor have The source layer is located in the same layer, and the reflective electrode is located in the same layer as the source and drain layers.
  • At least one example of the present disclosure also provides a display device including any of the above array substrates.
  • FIG. 1 is a schematic structural view of a transflective array substrate
  • FIG. 2 is a top plan view of a pixel region, a reflective region, and a transmissive region in an array substrate according to an example of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of an array substrate according to an example of the present disclosure.
  • FIG. 4A is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • FIG. 4B is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • FIG. 5 is a cross-sectional view of an array substrate according to another example of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an example of the present disclosure.
  • FIGS. 8A-8E are flowcharts of a method for fabricating an array substrate according to an example of the present disclosure.
  • 9A-9E are flowcharts of a method of fabricating an array substrate according to another example of the present disclosure.
  • 10A-10C are flowcharts of a method of fabricating an array substrate according to another example of the present disclosure.
  • 11A-11C are flowcharts of a method of fabricating an array substrate according to another example of the present disclosure.
  • FIG. 12 is a schematic diagram of a display device according to an example of the present disclosure.
  • FIG. 1 is a schematic view showing the structure of a transflective array substrate.
  • the array substrate includes a pixel region (Pixel Region, PR), and the pixel region PR includes a reflective region (RR) and a transmissive region (TR).
  • pixel Region Pixel Region
  • RR reflective region
  • TR transmissive region
  • the array substrate includes a base substrate 101 and a thin film transistor (TFT) disposed thereon.
  • the TFT includes a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, and a source and drain layer 105.
  • the source drain layer 105 includes a drain 1051 and a source 1052.
  • a passivation layer 106 is disposed on the TFT. In the reflection region RR, the passivation layer 106 is provided with a resin layer 107, the resin layer 107 has a concave-convex surface 1071 on a side away from the base substrate 101, and a reflective electrode 108 is provided on the resin layer 107.
  • a transmissive electrode 118 is provided on the passivation layer 106 in the transmissive region TR.
  • the transmissive electrode 118 is electrically connected to the drain electrode 1051 through a via penetrating through the passivation layer 106.
  • the transmissive electrode 118 may be electrically connected to the reflective electrode 108, but is not limited thereto.
  • the transmissive electrode 118 may be insulated from the reflective electrode 108 from each other and controlled by a different TFT.
  • the surface of the reflective electrode (for example, made of metal Al) is designed to have an uneven shape, so that the incident light is diffusely reflected. If the mirror surface of the smooth reflective electrode is used as the reflective electrode, the observer's own face is reflected.
  • a resin having a rugged surface can be prepared by a semi-transparent mask to form a reflective electrode surface of a corresponding shape, which is limited by the exposure precision of the negative photoresist, and the organic resin is not continuously uneven.
  • the specular reflection component the diffuse reflection effect is poor, affecting the visual effect of the viewing angle and the reflection area.
  • negative photoresist exposure accuracy is on the order of microns.
  • a negative photoresist may have an exposure accuracy of up to about 5 ⁇ m.
  • FIG. 2 is a top plan view showing a pixel region PR, a reflective region RR, and a transmissive region TR in an array substrate.
  • a pixel region PR a pixel region PR, a reflective region RR, and a transmissive region TR in an array substrate.
  • R red
  • G green
  • B blue
  • Three pixel areas PR are shown in FIG.
  • Each of the pixel regions PR includes a reflective region RR and a transmissive region TR.
  • FIG. 3 is a schematic cross-sectional view of an array substrate according to an example of the present disclosure. As shown in FIG. 3, at least one example of the present disclosure provides an array substrate, including:
  • the substrate substrate 101 includes a pixel region PR, and the pixel region PR includes a reflective region RR;
  • the reflective region layer structure 1110 is within the reflective region RR; and includes a particle layer 112 configured to have a reflective roughened surface 1111 on a side of the reflective region layer structure 1110 away from the base substrate 101; for example, a granular layer 112 a portion of the reflective layer structure 1110 away from the substrate 101;
  • Reflective electrode 108 is on particle layer 112.
  • the reflective electrode 108 is in contact with the particle layer 112.
  • the particle layer is disposed such that the reflective electrode has a continuously distributed minute uneven surface, and the uneven surface has a continuous irregular shape, so that the reflective electrode has better diffuse reflection.
  • the effect is that the specular reflection effect of the reflection area can be sufficiently reduced, and the visual effect of the viewing angle and the reflection area can be improved.
  • a reflective region layer structure 1110 includes a base portion 110 and a particle layer 112 that are sequentially disposed on a base substrate 101.
  • the particle layer 112 is in contact with the base portion 110 of the reflective layer structure 1110.
  • the particle layer 112 may be obtained by surface roughening treatment of the reflective film 111 (refer to the method example, for example, Fig. 8C, hereinafter the same).
  • the material of the base portion 110 includes a conductive material or a semiconductor material.
  • the material of the base portion 110 includes a metal oxide
  • the material of the particle layer 112 includes a metal.
  • the metal oxide includes at least one of indium tin oxide (ITO) and indium gallium zinc oxide (IGZO), but is not limited thereto.
  • the particle layer 112 can be obtained by subjecting at least the surface of the reflective film 111 of the metal oxide material to a surface thereof.
  • the material of the base portion 110 may be a reflective film that is not granulated.
  • the material of the base portion 110 may be a metal oxide that has not been reduced.
  • the particle layer 112 is on the nanometer scale and the particle layer 112 has a particle size less than or equal to 100 nm.
  • the nano-sized particle layer 112 can reduce the distance between adjacent concave portions or adjacent convex portions in the rough surface (concave surface) 1111, improve the precision of the uneven surface, and thereby improve the unevenness of the reflective electrode, thereby improving The diffuse reflection effect of the reflective electrode.
  • a recess 0108 of the reflective electrode, a recess 01111 of the rough surface 1111 is shown in FIG.
  • the particle size of the particle layer 112 ranges from 10 to 100 nm.
  • Metal particles of less than 10 nm are prone to agglomeration, which is disadvantageous for the formation of minute particles, and metal particles of less than or equal to 100 nm facilitate the progress of the process steps.
  • the particle diameter of the metal forming the reflective film 111 is within the particle size range of the above-mentioned particle layer to facilitate formation of the particle layer of the above particle size.
  • the reflective film 111 may be formed by a magnetron sputtering method, but is not limited thereto.
  • the pixel region PR further includes a transmissive region TR, so that a transflective array substrate can be formed.
  • the transmissive area TR includes a transmissive electrode 118, and the reflective layer structure 1110 is located in the same layer as the transmissive electrode 118.
  • the reflective film 111 and the transmissive electrode 118 may be formed by the same patterning process using the same film.
  • the pixel region PR may also not include the transmissive region TR.
  • a reflective array substrate can be formed.
  • an array substrate further includes a thin film transistor TFT.
  • the TFT includes a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, and a source and drain layer 105.
  • the source drain layer 105 includes a drain 1051 and a source 1052.
  • a passivation layer 106 is disposed on the TFT.
  • a resin layer 107 is provided on the passivation layer 106.
  • the upper surface of the resin layer 107 is a flat surface.
  • FIG. 4A is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • the upper surface of the resin layer 107 is an uneven surface 1071.
  • the resin layer 107 having the uneven surface 1071 and the particle layer 112 act together the diffuse reflection effect of the reflective electrode can be further improved.
  • FIG. 4B is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • the reflective region layer structure 1110 does not include the base portion 110 and includes only the particle layer 112, as compared with the array substrate shown in FIG.
  • FIG. 5 is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • the reflective region layer structure 1110 can be coplanar with the transmissive electrode 118.
  • the reflective electrode 108 is located in the same layer as the source and drain layers 105.
  • the reflective film 111 and the transmissive electrode 118 are formed by the same film through the same patterning process.
  • the array substrate provided by this example can be used in a liquid crystal display device of a high aperture advanced super dimension exchange switching (HADS) mode.
  • HADS high aperture advanced super dimension exchange switching
  • FIG. 6 is a schematic cross-sectional view of an array substrate according to another example of the present disclosure.
  • the reflective region layer structure 1110 and the semiconductor active layer 104 may be located in the same layer.
  • the reflective electrode 108 and the source and drain layers 105 may be in the same layer.
  • the reflective film 111 and the semiconductor active layer 104 are formed by the same film through the same patterning process.
  • the reflective electrode 108 and the source and drain layers 105 are formed by the same film through the same patterning process.
  • the transmissive electrode 118 and the drain electrode 1051 in FIG. 6 are in direct contact.
  • a passivation layer may also be disposed between the transmissive electrode 118 and the source and drain layers 105 in FIG. 6, and the transmissive electrode 118 may be electrically connected to the drain electrode 1051 through a via penetrating through the passivation layer.
  • the array substrate provided by this example can be used for a liquid crystal display device in which an oxide semiconductor is used as an active layer.
  • FIG. 7 is a flowchart of a method for fabricating an array substrate according to an example of the present disclosure. As shown in FIG. 7 , at least one example of the present disclosure further provides a method for fabricating an array substrate, including:
  • the substrate substrate 101 includes a pixel region PR, the pixel region PR includes a reflective region RR, the reflective region film 111 is formed in the reflective region RR;
  • a reflective electrode 108 is formed on the particle layer 112.
  • the material of the reflective region film 111 comprises a conductive material or a semiconductor material.
  • the material of the reflective region film 111 includes a metal oxide
  • the material of the granular layer 112 includes a metal.
  • the metal oxide includes at least one of indium tin oxide (ITO) and indium gallium zinc oxide (IGZO).
  • roughening the side of the reflective film 111 away from the substrate 101 to form the particle layer 112 includes: reducing the reflective film 111 to at least the reflective region.
  • the metal oxide on the surface of the film 111 is reduced to metal particles, and the particle layer 112 is disposed such that the side of the reflective film 111 away from the substrate 101 has a granular rough surface.
  • the reflective film 111 is subjected to a reduction treatment to completely reduce the metal oxide of the reflective film 111 into metal particles, so that the reflective film 111 is no longer present in the array substrate. Thereby, an array substrate as shown in FIG. 4B can be formed.
  • the reflective region film 111 is subjected to a reduction treatment using a plasma.
  • the plasma is a reducing plasma
  • the reducing plasma includes at least one of a hydrogen plasma and an ammonia plasma.
  • the particle size of the particle layer 112 is less than or equal to 100 nm.
  • the specific case of the particle layer 112 can be referred to the relevant description in the array substrate.
  • FIGS. 8A-8E are flowcharts of a method of fabricating an array substrate according to an example of the present disclosure. The fabrication method provided in accordance with one or more examples of the present disclosure is illustrated in Figures 8A-8E.
  • FIG. 8A shows that a TFT is formed on the base substrate 101, and the TFT can be referred to the foregoing description.
  • a passivation layer 106 is formed on the TFT, and a resin layer 107 is formed in the reflective region RR, and the surface of the resin layer 107 away from the substrate 101 is planar.
  • a transparent conductive film (for example, ITO) 1180 made of a metal oxide is formed on the passivation layer 106 and the resin layer 107, a photoresist film is formed on the transparent conductive film 1180, and a semi-transparent mask is used.
  • the photoresist film 180 is exposed and developed to obtain a photoresist layer 121.
  • the transflective mask 180 includes a semi-permeable region 1801, a full impermeable region 1802, and a full transmissive region 1803.
  • a region corresponding to the formation of the reflective electrode is a semi-transmissive region 1801.
  • the area corresponding to the formation of the transmissive electrode 118 is the fully impermeable region 1802.
  • the remaining area is the full transmissive area 1803, and no photoresist remains after development.
  • the photoresist layer 121 includes a first thickness photoresist 1211 and a second thickness photoresist 1212. The thickness of the first thickness photoresist 1211 is greater than the thickness of the second thickness photoresist 1212.
  • the transparent conductive film 1180 is etched by using the photoresist layer 121 as a mask (for example, wet etching) to obtain a patterned transparent conductive film 1181, and the photoresist layer 121 is formed. Ashing, the first thickness photoresist 1211 is removed, and the ashed photoresist 1210 is obtained, and only the region corresponding to the formation of the transmissive electrode 118 has photoresist remaining.
  • the patterned transparent conductive film 1181 includes a reflective region film 111 and a transmissive electrode 118, and the ashed photoresist 1210 overlies the transmissive electrode 118.
  • the reflective region film 111 is subjected to a reduction treatment by plasma, so that the metal oxide of the reflective region film 111 at least away from the surface of the substrate 101 is reduced.
  • the metal particles form a particle layer 112.
  • the unreduced reflective film 111 is the base portion 110, whereby the particle layer 112 and the base portion 110 together form a reflective layer structure 1110 (also shown in FIG. 3).
  • the ashed photoresist 1210 is stripped.
  • plasma treatment of hydrogen (H 2 ) or ammonia (NH 3 ) may be employed, so that the metal oxide is reduced, and its surface morphology becomes rough and appears granular.
  • the array substrate as shown in FIG. 3 can be obtained.
  • the pixel region PR further includes a transmissive region TR including a transmissive electrode 118, and the reflective region film 111 is located in the same layer as the transmissive electrode 118.
  • a fabrication method provided in accordance with one or more examples of the present disclosure further includes forming a thin film transistor TFT including a semiconductor active layer 104 and a source and drain layer 105.
  • FIGS. 9A-9E are flowcharts of a method of fabricating an array substrate according to another example of the present disclosure.
  • this example differs from the example shown in FIGS. 8A-8E in that the surface of the resin layer 107 away from the substrate 101 is an uneven surface.
  • the uneven surface of the resin layer 107 can be obtained by exposure using a negative photoresist.
  • the array substrate as shown in FIG. 4A can be obtained.
  • FIGS. 10A-10C are flowcharts of a method of fabricating an array substrate according to another example of the present disclosure.
  • the resin layer 107 may not be formed.
  • the reflective film 111 may be in the same plane as the transmissive electrode 118, and may be formed by the same film layer through the same patterning process.
  • the reflective electrode 108 is located in the same layer as the source and drain layers 105, and can be formed by the same film layer through the same patterning process.
  • the reflective region film 111 may be in the same layer as the semiconductor active layer 104, and the reflective region film 111 and the semiconductor active layer 104 may be formed by the same film.
  • the same patterning process is formed.
  • the reflective electrode 108 is located in the same layer as the source and drain layers 105, and the reflective electrode 108 and the source and drain layer 105 are formed by the same film through the same patterning process.
  • the surface of the semiconductor active layer 104 of the TFT region is flat.
  • At least one example of the present disclosure also provides a display device including an array substrate provided by at least one example of the present disclosure.
  • the display device includes a liquid crystal display device, but is not limited thereto.
  • FIG. 12 is a schematic diagram of a display device according to an example of the present disclosure.
  • the liquid crystal display device includes an array substrate 01 and a counter substrate 02, and a liquid crystal 03 sealed therebetween.
  • the cell thickness (Cell Gap, CG) CG1 at the transmissive area TR is the same as the cell thickness CG2 at the reflective area RR.

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Abstract

提供一种阵列基板及其制作方法、显示装置。该阵列基板包括衬底基板(101)、反射区层结构(1110)和反射电极(108)。衬底基板(101)包括像素区(PR)，所述像素区(PR)包括反射区(RR)。反射区层结构(1110)在所述反射区(RR)内，包括颗粒层(112)，所述颗粒层(112)被配置为使所述反射区层结构(1110)远离所述衬底基板(101)的一侧具有颗粒状的粗糙表面(1111)。反射电极(108)在所述颗粒层(112)上。该阵列基板可提高反射区的漫反射效果。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本专利申请要求于2017年8月31日递交的中国专利申请第201710774031.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本公开的示例的一部分。
技术领域
本公开至少一示例涉及一种阵列基板及其制作方法、显示装置。
背景技术
液晶显示器的光源主要为背光，而背光源通过基底、彩色滤光片等使得背光的利用率大大降低，甚至在光线较强的室外都无法看清屏幕上的显示图像。为了获得在室内和光线较强的室外都有较好的显示效果，业界开发出了半反半透式显示屏。
发明内容
本公开的至少一示例涉及一种阵列基板及其制作方法、显示装置，以提高反射区的漫反射效果。
本公开的至少一示例提供一种阵列基板，包括：
衬底基板，包括像素区，所述像素区包括反射区；
反射区层结构，在所述反射区内，包括颗粒层，所述颗粒层被配置为使所述反射区层结构远离所述衬底基板的一侧具有颗粒状的粗糙表面；
反射电极，在所述颗粒层上。
根据本公开的一个或多个示例提供的阵列基板，所述反射区层结构包括基础部，所述颗粒层位于所述基础部远离所述衬底基板的一侧，并与所述基础部接触。
根据本公开的一个或多个示例提供的阵列基板，所述基础部的材质包括导电材料或半导体材料。
根据本公开的一个或多个示例提供的阵列基板，所述基础部的材质包括 金属氧化物，所述颗粒层材质包括金属。
根据本公开的一个或多个示例提供的阵列基板，所述金属氧化物包括氧化铟锡(ITO)和氧化铟镓锌(IGZO)中至少之一。
根据本公开的一个或多个示例提供的阵列基板，所述颗粒层的粒径小于或等于100nm。
根据本公开的一个或多个示例提供的阵列基板，所述像素区还包括透射区，所述透射区包括透射电极，所述反射区层结构与所述透射电极位于同一层。
根据本公开的一个或多个示例提供的阵列基板，该阵列基板还包括薄膜晶体管，其中，所述薄膜晶体管包括半导体有源层和源漏极层，所述反射区层结构与所述半导体有源层位于同一层，所述反射电极与所述源漏极层位于同一层。
本公开的至少一示例还提供一种阵列基板的制作方法，包括：
在衬底基板上形成反射区薄膜，所述衬底基板包括像素区，所述像素区包括反射区，所述反射区薄膜形成在所述反射区；
对所述反射区薄膜远离所述衬底基板的一面进行粗糙化处理，以形成颗粒层；
在所述颗粒层上形成反射电极。
根据本公开的一个或多个示例提供的制作方法，所述反射区薄膜材质包括导电材料或半导体材料。
根据本公开的一个或多个示例提供的制作方法，所述反射区薄膜材质包括金属氧化物，所述颗粒层材质包括金属。
根据本公开的一个或多个示例提供的制作方法，所述金属氧化物包括氧化铟锡(ITO)和氧化铟镓锌(IGZO)中至少之一。
根据本公开的一个或多个示例提供的制作方法，对所述反射区薄膜远离所述衬底基板的一面进行粗糙化处理，以形成颗粒层包括：对所述反射区薄膜进行还原处理，使至少所述反射区薄膜表面的所述金属氧化物被还原成金属颗粒，所述颗粒层被配置为使所述反射区薄膜远离所述衬底基板的一侧具有颗粒状的粗糙表面。
根据本公开的一个或多个示例提供的制作方法，对所述反射区薄膜进行 还原处理，使所述反射区薄膜的所述金属氧化物全部被还原成金属颗粒。
根据本公开的一个或多个示例提供的制作方法，利用等离子体对所述反射区薄膜进行还原处理。
根据本公开的一个或多个示例提供的制作方法，所述等离子体为还原性等离子体，所述还原性等离子体包括氢等离子体和氨等离子体中的至少一种。
根据本公开的一个或多个示例提供的制作方法，所述颗粒层的粒径小于或等于100nm。
根据本公开的一个或多个示例提供的制作方法，所述像素区还包括透射区，所述透射区包括透射电极，所述反射区薄膜与所述透射电极位于同一层。
根据本公开的一个或多个示例提供的制作方法，该制作方法还包括形成薄膜晶体管，其中，所述薄膜晶体管包括半导体有源层和源漏极层，所述反射区薄膜与所述半导体有源层位于同一层，所述反射电极与所述源漏极层位于同一层。
本公开的至少一示例还提供一种显示装置，包括上述任一阵列基板。
附图说明
为了更清楚地说明本公开示例的技术方案，下面将对示例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些示例，而非对本公开的限制。
图1为一种半反半透阵列基板的结构示意图；
图2为本公开一示例提供的一种阵列基板中像素区、反射区和透射区的俯视示意图；
图3为本公开一示例提供的一种阵列基板的剖视示意图；
图4A为本公开另一示例提供的一种阵列基板的剖视示意图；
图4B为本公开另一示例提供的一种阵列基板的剖视示意图；
图5为本公开另一示例提供的一种阵列基板的剖视示意图；
图6为本公开另一示例提供的一种阵列基板的剖视示意图；
图7为本公开一示例提供的一种阵列基板的制作方法的流程图；
图8A-8E为本公开一示例提供的一种阵列基板的制作方法的流程图；
图9A-9E为本公开另一示例提供的一种阵列基板的制作方法的流程图；
图10A-10C为本公开另一示例提供的一种阵列基板的制作方法的流程图；
图11A-11C为本公开另一示例提供的一种阵列基板的制作方法的流程图；
图12为本公开一示例提供的显示装置的示意图。
具体实施方式
为使本公开示例的目的、技术方案和优点更加清楚，下面将结合本公开示例的附图，对本公开示例的技术方案进行清楚、完整地描述。显然，所描述的示例是本公开的一部分示例，而不是全部的示例。基于所描述的本公开的示例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他示例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示出了一种半反半透阵列基板的结构示意图。如图1所示，阵列基板包括像素区(Pixel Region，PR)，像素区PR包括反射区(Reflecting Region，RR)和透射区(Transmitting Region，TR)。
如图1所示，阵列基板包括衬底基板101和设置在其上的薄膜晶体管(Thin Film Transistor，TFT)。TFT包括栅极102、栅极绝缘层103、半导体有源层104和源漏极层105。源漏极层105包括漏极1051和源极1052。TFT上设有钝化层106。在反射区RR，钝化层106上设有树脂层107，树脂层107远离衬底基板101的一侧具有凹凸面1071，在树脂层107上设有反射电极108。在透射区TR，钝化层106上设有透射电极118。透射电极118通过贯 穿钝化层106的过孔与漏极1051电连接。例如，透射电极118可与反射电极108电连接，但不限于此。例如，透射电极118可与反射电极108彼此绝缘，通过不同的TFT控制。
为增加反射率和视角，同时避免出现镜面反射现象，反射电极(例如，材质为金属Al)的表面被设计成凹凸不平的形状，使得入射光发生漫反射。而若用光滑的反射电极的镜面作为反射电极，反射出来的是观察者自己的面孔。例如，可通过半透掩膜版制备具有凹凸不平的表面的树脂(resin)，以形成相应形状的反射电极表面，受负性光刻胶曝光精度的限制，有机树脂并非连续分布的凹凸不平状，仍有很大一部分镜面反射的成分，漫反射效果较差，影响可视角和反射区的视觉效果。例如，负性光刻胶曝光精度在微米级别。例如，负性光刻胶曝光精度最高可为5μm左右。
图2示出了一种阵列基板中像素区PR、反射区RR和透射区TR的俯视示意图。图2中以像素区PR内设置红(R)、绿(G)或蓝(B)三原色中的一种为例进行说明。图2中示出了三个像素区PR。每个像素区PR包括反射区RR和透射区TR。
图3为本公开一示例提供的一种阵列基板的剖视示意图。如图3所示，本公开至少一示例提供一种阵列基板，包括：
衬底基板101，衬底基板101包括像素区PR，像素区PR包括反射区RR；
反射区层结构1110，在反射区RR内；包括颗粒层112，颗粒层112被配置为使反射区层结构1110远离衬底基板101的一侧具有颗粒状的粗糙表面1111；例如，颗粒层112为反射区层结构1110远离衬底基板101的部分；
反射电极108，在颗粒层112上。例如，反射电极108与颗粒层112接触。
本公开至少一示例提供的阵列基板，颗粒层的设置可使得反射电极具有连续分布的微小的凹凸不平的表面，凹凸不平的表面具有连续不规则的形状，能使反射电极具有较好的漫反射效果，能够充分减少反射区的镜面反射效应，提高可视角和反射区的可视效果。
如图3所示，根据本公开一个或多个示例提供的阵列基板，反射区层结构1110包括依次位于衬底基板101上的基础部110和颗粒层112。颗粒层112与反射区层结构1110的基础部110接触。例如，颗粒层112可通过反射区薄 膜111(可参照方法示例，例如图8C，以下与此相同)表面粗糙化处理而得。
根据本公开一个或多个示例提供的阵列基板，基础部110的材质包括导电材料或半导体材料。例如，基础部110的材质包括金属氧化物，颗粒层112材质包括金属。例如，金属氧化物包括氧化铟锡(ITO)和氧化铟镓锌(IGZO)中至少之一，但不限于此。
例如，颗粒层112可通过金属氧化物材质的反射区薄膜111的至少其表面经还原处理处理而得。例如，基础部110的材质可为没被颗粒化的反射区薄膜。例如，基础部110的材质可为没被还原的金属氧化物。
根据本公开一个或多个示例提供的阵列基板，颗粒层112在纳米级别，颗粒层112的粒径小于或等于100nm。纳米级别的颗粒层112可使得粗糙表面(凹凸面)1111中的相邻凹部或相邻凸部之间的距离减小，提高凹凸面的精度，进而提高反射电极的凹凸不平的效果，以提高反射电极的漫反射效果。图3中示出了反射电极的凹部0108，粗糙表面1111的凹部01111。
例如，颗粒层112的粒径范围在10-100nm。小于10nm的金属颗粒易于团聚，不利于微小颗粒的形成，小于或等于100nm的金属颗粒利于工艺步骤的进行。例如，形成反射区薄膜111的金属的粒径在上述颗粒层的粒径范围内，以利于形成上述粒径的颗粒层。例如，反射区薄膜111可采用磁控溅射方法形成，但不限于此。
如图3所示，根据本公开一个或多个示例提供的阵列基板，像素区PR还包括透射区TR，从而，可形成半反半透的阵列基板。透射区TR包括透射电极118，反射区层结构1110与透射电极118位于同一层。例如，反射区薄膜111与透射电极118可采用同一薄膜经同一构图工艺形成。本公开的示例中，像素区PR也可不包括透射区TR。一个示例中，可形成反射式的阵列基板。
如图3所示，根据本公开一个或多个示例提供的阵列基板，该阵列基板还包括薄膜晶体管TFT。TFT包括栅极102、栅极绝缘层103、半导体有源层104和源漏极层105。源漏极层105包括漏极1051和源极1052。TFT上设有钝化层106。在反射区RR，钝化层106上设有树脂层107。例如，树脂层107的上表面为平面。
图4A为本公开另一示例提供的一种阵列基板的剖视示意图。如图4A所 示，根据本公开一个或多个示例提供的阵列基板，树脂层107的上表面为凹凸面1071。具有凹凸面1071的树脂层107与颗粒层112共同作用下，可进一步提高反射电极的漫反射效果。
图4B为本公开另一示例提供的一种阵列基板的剖视示意图。如图4B所示，与图3所示的阵列基板相比，图4B所示的阵列基板中，反射区层结构1110不包括基础部110，仅包括颗粒层112。
图5为本公开另一示例提供的一种阵列基板的剖视示意图。如图5所示，根据本公开一个或多个示例提供的阵列基板，反射区层结构1110可与透射电极118位于同一平面。例如，如图5所示，反射电极108与源漏极层105位于同一层。例如，反射区薄膜111与透射电极118由同一薄膜经同一构图工艺形成。例如，该示例提供的阵列基板可用于高开口率高级超维场转换技术(High aperture Advanced super Dimensional Switching，HADS)模式的液晶显示装置。
图6为本公开另一示例提供的一种阵列基板的剖视示意图。如图6所示，根据本公开一个或多个示例提供的阵列基板，反射区层结构1110与半导体有源层104可位于同一层。例如，反射电极108与源漏极层105可位于同一层。例如，反射区薄膜111与半导体有源层104由同一薄膜经同一构图工艺形成。例如，反射电极108与源漏极层105由同一薄膜经同一构图工艺形成。图6中的透射电极118和漏极1051直接接触。例如，图6中的透射电极118和源漏极层105之间也可设置钝化层，透射电极118可通过贯穿钝化层的过孔与漏极1051电连接。例如，该示例提供的阵列基板可用于氧化物半导体作为有源层的液晶显示装置。
图7为本公开一示例提供的一种阵列基板的制作方法的流程图。如图7所示，本公开至少一示例还提供一种阵列基板的制作方法，包括：
在衬底基板101上形成反射区薄膜111，衬底基板101包括像素区PR，像素区PR包括反射区RR，反射区薄膜111形成在反射区RR；
对反射区薄膜111远离衬底基板101的一面进行粗糙化处理，以形成颗粒层112；以及
在颗粒层112上形成反射电极108。
根据本公开一个或多个示例提供的制作方法，反射区薄膜111材质包括 导电材料或半导体材料。例如，反射区薄膜111材质包括金属氧化物，颗粒层112材质包括金属。例如，金属氧化物包括氧化铟锡(ITO)和氧化铟镓锌(IGZO)中至少之一。
根据本公开一个或多个示例提供的制作方法，对反射区薄膜111远离衬底基板101的一面进行粗糙化处理，以形成颗粒层112包括：对反射区薄膜111进行还原处理，使至少反射区薄膜111表面的金属氧化物被还原成金属颗粒，颗粒层112被配置为使反射区薄膜111远离衬底基板101的一侧具有颗粒状的粗糙表面。
根据本公开一个或多个示例提供的制作方法，对反射区薄膜111进行还原处理，使反射区薄膜111的金属氧化物全部被还原成金属颗粒，从而阵列基板中不再有反射区薄膜111。从而，可形成如图4B所示的阵列基板。
根据本公开一个或多个示例提供的制作方法，利用等离子体对反射区薄膜111进行还原处理。例如，等离子体为还原性等离子体，还原性等离子体包括氢等离子体和氨等离子体中的至少一种。
根据本公开一个或多个示例提供的制作方法，颗粒层112的粒径范围小于或等于100nm。颗粒层112的具体情形可参照阵列基板中的相关描述。
图8A-8E为本公开一示例提供的一种阵列基板的制作方法的流程图。根据本公开一个或多个示例提供的制作方法，如图8A-8E所示。
图8A示出了在衬底基板101上形成TFT，TFT可参见之前描述。在TFT上形成钝化层106，在反射区RR形成树脂层107，树脂层107远离衬底基板101的表面为平面。
如图8B所示，在钝化层106和树脂层107上形成金属氧化物材质的透明导电薄膜(例如可为ITO)1180，在透明导电薄膜1180上形成光刻胶薄膜，并采用半透掩膜版180对光刻胶薄膜进行曝光、显影，得到光刻胶层121。半透掩膜版180包括半透区1801，全不透区1802和全透区1803。对应形成反射电极的区域为半透区1801。对应形成透射电极118的区域为全不透区1802。剩余区域为全透区1803，显影后无光刻胶剩余。光刻胶层121包括第一厚度光刻胶1211和第二厚度光刻胶1212。第一厚度光刻胶1211的厚度大于第二厚度光刻胶1212的厚度。
如图8C所示，以光刻胶层121为掩膜对透明导电薄膜1180进行刻蚀(例 如可采用湿法刻蚀)，得到图形化的透明导电薄膜1181，并对光刻胶层121进行灰化，去除第一厚度光刻胶1211，得到灰化后的光刻胶1210，仅对应形成透射电极118的区域有光刻胶剩余。图形化的透明导电薄膜1181包括反射区薄膜111和透射电极118，灰化后的光刻胶1210覆盖在透射电极118上。
如图8D所示，以灰化后的光刻胶1210为掩膜，采用等离子体对反射区薄膜111进行还原处理，使得反射区薄膜111至少远离衬底基板101的表面的金属氧化物被还原成金属颗粒，形成颗粒层112。未被还原的反射区薄膜111为基础部110，从而，颗粒层112和基础部110共同构成反射区层结构1110(也可如图3所示)。
如图8E所示，剥离灰化后的光刻胶1210。
例如，可采用氢气(H 2)或氨气(NH 3)的等离子体(plasma)处理，使得金属氧化物被还原，其表面形貌变得粗糙，呈现颗粒状。
在图8E的基础上，在反射区RR的颗粒层112上形成反射电极108后，即可得到如图3所示的阵列基板。
如图8D-8E所示，根据本公开一个或多个示例提供的制作方法，像素区PR还包括透射区TR，透射区TR包括透射电极118，反射区薄膜111与透射电极118位于同一层。
如图8A-8E所示，根据本公开一个或多个示例提供的制作方法，还包括形成薄膜晶体管TFT，薄膜晶体管TFT包括半导体有源层104和源漏极层105。
图9A-9E为本公开另一示例提供的一种阵列基板的制作方法的流程图。根据本公开一个或多个示例提供的制作方法，如图9A-9E所示，该示例与图8A-8E所示示例的区别在于树脂层107远离衬底基板101的表面为凹凸面。例如，树脂层107的凹凸面可采用负性光刻胶经曝光而得。可参照图8A-8E所示示例的叙述，在此不再赘述。该示例在图9E的基础上，在反射区RR的颗粒层112上形成反射电极108后，即可得到如图4A所示的阵列基板。
图10A-10C为本公开另一示例提供的一种阵列基板的制作方法的流程图。根据本公开一个或多个示例提供的制作方法，如图10A-10C所示，也可不形成树脂层107。如图10B所示，反射区薄膜111可与透射电极118位于同一平面，可由同一膜层经同一构图工艺形成。如图10C所示，反射电极108 与源漏极层105位于同一层，可由同一膜层经同一构图工艺形成。
图11A-11C为本公开另一示例提供的一种阵列基板的制作方法的流程图。根据本公开一个或多个示例提供的制作方法，如图11A-11C所示，反射区薄膜111可与半导体有源层104位于同一层，反射区薄膜111与半导体有源层104由同一薄膜经同一构图工艺形成。例如，反射电极108与源漏极层105位于同一层，反射电极108与源漏极层105由同一薄膜经同一构图工艺形成。例如，该示例中，TFT区域的半导体有源层104表面平整。
本公开至少一示例还提供一种显示装置，包括本公开至少一示例提供的阵列基板。
例如，该显示装置包括液晶显示装置，但不限于此。
图12为本公开一示例提供的显示装置的示意图。例如，如图12所示，液晶显示装置包括阵列基板01和对置基板02，以及密封在其间的液晶03。例如，透射区TR处的盒厚(Cell Gap，CG)CG1与反射区RR处的盒厚CG2相同。
需要说明的是，为了清晰起见，在用于描述本公开的示例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在不冲突的情况下，本公开的同一示例及不同示例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，包括像素区，所述像素区包括反射区；
    反射区层结构，在所述反射区内，包括颗粒层，所述颗粒层被配置为使所述反射区层结构远离所述衬底基板的一侧具有颗粒状的粗糙表面；
    反射电极，在所述颗粒层上。
  2. 根据权利要求1所述的阵列基板，其中，所述反射区层结构包括基础部，所述颗粒层位于所述基础部远离所述衬底基板的一侧，并与所述基础部接触。
  3. 根据权利要求1或2所述的阵列基板，其中，所述基础部的材质包括导电材料或半导体材料。
  4. 根据权利要求1-3任一项所述的阵列基板，其中，所述基础部的材质包括金属氧化物，所述颗粒层材质包括金属。
  5. 根据权利要求4所述的阵列基板，其中，所述金属氧化物包括氧化铟锡(ITO)和氧化铟镓锌(IGZO)中至少之一。
  6. 根据权利要求1-5任一项所述的阵列基板，其中，所述颗粒层的粒径小于或等于100nm。
  7. 根据权利要求1-6任一项所述的阵列基板，其中，所述像素区还包括透射区，所述透射区包括透射电极，所述反射区层结构与所述透射电极位于同一层。
  8. 根据权利要求1-6任一项所述的阵列基板，还包括薄膜晶体管，其中，所述薄膜晶体管包括半导体有源层和源漏极层，所述反射区层结构与所述半导体有源层位于同一层，所述反射电极与所述源漏极层位于同一层。
  9. 一种阵列基板的制作方法，包括：
    在衬底基板上形成反射区薄膜，所述衬底基板包括像素区，所述像素区包括反射区，所述反射区薄膜形成在所述反射区；
    对所述反射区薄膜远离所述衬底基板的一面进行粗糙化处理，以形成颗粒层；
    在所述颗粒层上形成反射电极。
  10. 根据权利要求9所述的制作方法，其中，所述反射区薄膜材质包括 导电材料或半导体材料。
  11. 根据权利要求9或10所述的制作方法，其中，所述反射区薄膜材质包括金属氧化物，所述颗粒层材质包括金属。
  12. 根据权利要求11所述的制作方法，其中，所述金属氧化物包括氧化铟锡(ITO)和氧化铟镓锌(IGZO)中至少之一。
  13. 根据权利要求9-12任一项所述的制作方法，对所述反射区薄膜远离所述衬底基板的一面进行粗糙化处理，以形成颗粒层包括：对所述反射区薄膜进行还原处理，使至少所述反射区薄膜表面的所述金属氧化物被还原成金属颗粒，所述颗粒层被配置为使所述反射区薄膜远离所述衬底基板的一侧具有颗粒状的粗糙表面。
  14. 根据权利要求9-13任一项所述的制作方法，其中，对所述反射区薄膜进行还原处理，使所述反射区薄膜的所述金属氧化物全部被还原成金属颗粒。
  15. 根据权利要求13或14所述的制作方法，其中，利用等离子体对所述反射区薄膜进行还原处理。
  16. 根据权利要求15所述的制作方法，其中，所述等离子体为还原性等离子体，所述还原性等离子体包括氢等离子体和氨等离子体中的至少一种。
  17. 根据权利要求9-16任一项所述的制作方法，其中，所述颗粒层的粒径小于或等于100nm。
  18. 根据权利要求9-17任一项所述的制作方法，其中，所述像素区还包括透射区，所述透射区包括透射电极，所述反射区薄膜与所述透射电极位于同一层。
  19. 根据权利要求9-17任一项所述的制作方法，还包括形成薄膜晶体管，其中，所述薄膜晶体管包括半导体有源层和源漏极层，所述反射区薄膜与所述半导体有源层位于同一层，所述反射电极与所述源漏极层位于同一层。
  20. 一种显示装置，包括权利要求1-8任一项所述的阵列基板。
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