WO2019037513A1 - 显示基板及其制造方法、显示面板、显示装置 - Google Patents

显示基板及其制造方法、显示面板、显示装置 Download PDF

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Publication number
WO2019037513A1
WO2019037513A1 PCT/CN2018/090177 CN2018090177W WO2019037513A1 WO 2019037513 A1 WO2019037513 A1 WO 2019037513A1 CN 2018090177 W CN2018090177 W CN 2018090177W WO 2019037513 A1 WO2019037513 A1 WO 2019037513A1
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Prior art keywords
substrate
gate
type transistor
pattern
traces
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PCT/CN2018/090177
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English (en)
French (fr)
Inventor
沈灿
许志财
徐波
刘兴洪
侯帅
冉博
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Priority to US16/328,410 priority Critical patent/US10928942B2/en
Publication of WO2019037513A1 publication Critical patent/WO2019037513A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display

Definitions

  • the present disclosure relates to the field of display technology, and specifically discloses a display substrate and a method of manufacturing the same, a display panel, and a display device.
  • each pixel unit includes one driving transistor and one pixel electrode, and driving transistors located in the same row of pixel units are connected to one gate line.
  • the gate driving circuit outputs a gate driving signal to one gate line, a driving transistor in a row of pixel cells connected to the gate line may be turned on by such driving, and thereby charge the pixel electrode.
  • a driving signal outputted from a gate driving circuit to each gate line is generally a clock signal. Since the voltage difference between the high level and the low level of the clock signal is large, when the level of the clock signal jumps, the gate line voltage changes greatly, and coupling noise is often generated on the surface of the display panel.
  • the display panel is generally a touch display panel integrated with a touch function.
  • the touch display panel is used to detect the touch signal, the detection may be interfered by the coupling noise on the surface of the touch display panel, thereby affecting the touch precision of the touch display panel.
  • a display substrate includes: a substrate substrate; a plurality of gate lines disposed on the substrate; and a plurality of gate traces disposed away from the substrate a film structure on one side; and a plurality of conductive lines disposed on a side of the film structure away from the substrate.
  • an orthographic projection of each gate trace on the substrate substrate at least partially overlaps with an orthographic projection of a corresponding one of the conductive traces on the substrate, and is used for each conductive trace
  • the signal transmitted on is inverted with the signal used to transmit on the corresponding one of the gate traces.
  • the display substrate provided by the embodiment of the present disclosure further includes a plurality of inverters. Specifically, an input end of each of the inverters is connected to a gate trace, and an output end of each of the inverters is connected to a conductive trace, and a gate connected to the same inverter is taken.
  • the orthographic projections of the lines and conductive traces on the substrate substrate at least partially overlap.
  • an orthographic projection of each gate trace on the substrate substrate and an orthographic projection of a corresponding one of the conductive traces on the substrate substrate coincide.
  • each of the inverters includes an N-type transistor and a P-type transistor. Specifically, a gate of the N-type transistor and a gate of the P-type transistor are connected to a gate trace, a second pole of the N-type transistor and a second pole of the P-type transistor and a conductive A trace connection, a first pole of the P-type transistor is connected to the first power line, and a first pole of the N-type transistor is connected to the second power line. Further, the first power line is supplied with a first power signal of a first potential, and the second power line is supplied with a second power signal of a second potential, wherein the first potential is relative to the second The potential is high.
  • the N-type transistor and the P-type transistor are both thin film transistors.
  • each of the inverters includes: a gate layer, a gate insulating layer, an active layer, and a source sequentially disposed on the base substrate Missing layers.
  • the gate layer is configured to serve as a gate of the N-type transistor and the P-type transistor.
  • the active layer includes an N-type semiconductor pattern and a P-type semiconductor pattern which are spaced apart.
  • the source drain layer includes a first source pattern, a second source pattern, and a drain pattern disposed at intervals, wherein the first source pattern is configured to serve as a first pole of the N-type transistor, The second source pattern is configured to serve as a first pole of the P-type transistor, and the drain pattern is configured to serve as a second pole of the N-type transistor and the P-type transistor.
  • the gate layer is electrically connected to a gate trace, the first source pattern is electrically connected to the second power line, and the second source pattern is electrically connected to the first power line, and
  • the drain pattern is electrically connected to a conductive trace.
  • an orthographic projection of the first source pattern on the substrate substrate and a positive of the N-type semiconductor pattern on the substrate substrate The projections at least partially overlap.
  • An orthographic projection of the second source pattern on the substrate substrate at least partially overlaps with an orthographic projection of the P-type semiconductor pattern on the substrate substrate.
  • An orthographic projection of the drain pattern on the substrate substrate at least partially overlaps with an orthographic projection of the N-type semiconductor pattern on the substrate substrate, and the P-type semiconductor pattern is on the substrate
  • the orthographic projections on the substrate at least partially overlap.
  • an orthographic projection of the gate layer on the substrate substrate at least partially overlaps with an orthographic projection of the N-type semiconductor pattern on the substrate substrate, and the P-type semiconductor pattern is The orthographic projections on the substrate substrate at least partially overlap.
  • each of the inverters is disposed at one end of a corresponding one of the gate traces for connection with the gate driving circuit.
  • the film layer structure includes a plurality of driving thin film transistors.
  • the display substrate provided by the embodiment of the present disclosure further includes: a driving circuit for the plurality of conductive traces.
  • the driving circuit is configured to transmit a signal inverted from a signal transmitted on a corresponding one of the gate traces on each of the conductive traces.
  • a method of manufacturing a display substrate includes the steps of: forming a plurality of gate traces on a base substrate; forming a film layer structure on a side of the plurality of gate traces away from the base substrate; A plurality of conductive traces are formed on a side of the film structure away from the substrate.
  • an orthographic projection of each gate trace on the substrate substrate at least partially overlaps with an orthographic projection of a corresponding one of the conductive traces on the substrate substrate, and is used on each conductive trace
  • the transmitted signal is inverted with the signal used to transmit on the corresponding one of the gate traces.
  • a manufacturing method for a display substrate further includes a step of forming a plurality of inverters on the base substrate. Specifically, an input end of each of the inverters is connected to a gate trace, and an output end of each of the inverters is connected to a conductive trace, and a gate connected to the same inverter is taken.
  • the orthographic projections of the lines and conductive traces on the substrate substrate at least partially overlap.
  • the step of forming a plurality of conductive traces on a side of the film layer structure away from the substrate substrate includes: The plurality of conductive traces are formed on a side of the film structure away from the base substrate on a mask forming the plurality of gate traces.
  • each of the inverters includes an N-type transistor and a P-type transistor.
  • the step of forming a plurality of inverters on the base substrate includes forming a plurality of sets of transistors on the base substrate, wherein each set of transistors includes an N-type transistor and a P-type transistor .
  • the gate of the N-type transistor and the gate of the P-type transistor in each group of transistors are connected to one gate trace, and the second pole of the N-type transistor and the second pole of the P-type transistor in each group of transistors are A conductive trace is connected, a first pole of the P-type transistor in each set of transistors is connected to the first power line, and a first pole of the N-type transistor in each set of transistors is connected to the second power line.
  • the first power line is supplied with a first power signal of a first potential
  • the two power lines are supplied with a second power signal of a second potential, the first potential being high with respect to the second potential Potential.
  • the N-type transistor and the P-type transistor are both thin film transistors.
  • the step of forming a plurality of sets of transistors on the base substrate includes: simultaneously forming the plurality of sets of transistors in forming the driving thin film transistor.
  • each group of transistors is formed by forming a gate layer on the substrate substrate such that the gate pattern
  • the layer is electrically connected to a gate trace and serves as a gate of the N-type transistor and the P-type transistor; a gate insulating layer is sequentially formed on a side of the gate layer away from the base substrate and a source layer, the active layer including an N-type semiconductor pattern and a P-type semiconductor pattern formed at intervals; and a source/drain layer formed on a side of the active layer away from the base substrate, the source drain pattern
  • the layer includes a first source pattern, a second source pattern, and a drain pattern formed at intervals.
  • the first source pattern is electrically connected to the second power line
  • the second source pattern is electrically connected to the first power line
  • the drain pattern is electrically connected to a conductive trace .
  • the first source pattern is formed to serve as a first pole of the N-type transistor
  • the second source pattern is formed to serve as a first pole of the P-type transistor
  • the drain pattern is formed To serve as the second pole of the N-type transistor and the P-type transistor.
  • the first source pattern is formed such that an orthographic projection on the base substrate and the N-type semiconductor pattern are The orthographic projections on the substrate substrate at least partially overlap.
  • the second source pattern is formed such that an orthographic projection on the base substrate at least partially overlaps with an orthographic projection of the P-type semiconductor pattern on the base substrate.
  • the drain pattern is formed such that an orthographic projection on the base substrate at least partially overlaps with an orthographic projection of the N-type semiconductor pattern on the base substrate, and the P-type semiconductor pattern is The orthographic projections on the substrate substrate at least partially overlap.
  • the gate layer is formed such that an orthographic projection on the base substrate at least partially overlaps with an orthographic projection of the N-type semiconductor pattern on the base substrate, and the P-type semiconductor The orthographic projections of the patterns on the substrate substrate at least partially overlap.
  • a manufacturing method for a display substrate provided by an embodiment of the present disclosure further includes the steps of: providing a driving circuit for the plurality of conductive traces so that transmission and transmission are performed on each conductive trace A signal that is inverted by a signal transmitted on a corresponding gate trace.
  • a display panel is also proposed. Specifically, the display panel includes: the display substrate described in any of the foregoing embodiments.
  • a display device is also proposed.
  • the display device includes the display panel described in any of the preceding embodiments.
  • FIG. 1 is a schematic structural view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic view showing a temporal change of a transmission signal in a display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing an equivalent circuit of an inverter in a display substrate according to an embodiment of the present disclosure
  • FIG. 4 is a schematic view showing a film layer structure of an inverter in a display substrate according to an embodiment of the present disclosure
  • FIG. 5 is a plan view showing a film layer structure of an inverter in a display substrate according to an embodiment of the present disclosure
  • 6-1 is a flowchart of a method of manufacturing a display substrate in accordance with an embodiment of the present disclosure
  • 6-2 is a flowchart of a process for forming a set of transistors on a base substrate, in accordance with an embodiment of the present disclosure
  • 6-3 is a schematic diagram of a structure after sequentially forming a gate insulating layer and an active layer on a side of a gate layer away from a substrate substrate, according to an embodiment of the present disclosure
  • 6-4 is a schematic diagram of a structure after a source/drain layer is formed on a side of an active layer away from a substrate substrate, according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of a display substrate in accordance with an embodiment of the present disclosure.
  • the display substrate may include a plurality of gate traces 02 disposed on the base substrate 01.
  • a film layer structure 00 is further disposed on a side of the plurality of gate traces 02 away from the base substrate 01.
  • the film layer structure 00 may include a plurality of driving thin film transistors for driving the pixel electrodes.
  • a plurality of conductive traces 03 are further disposed on a side of the film layer structure 00 away from the base substrate 01.
  • an orthographic projection of each gate trace 02 on the substrate substrate 01 and an orthographic projection of a corresponding one of the conductive traces 03 on the base substrate 01 (shown by a thick solid line S in FIG. 1) )overlapping.
  • the orthographic projection of each conductive trace 03 on the base substrate 01 overlaps only with the orthographic projection of one gate trace 02 to avoid orthographic projection of the conductive trace 03 on the base substrate 01.
  • the signal Vin for transmission on the gate trace 02 is a clock signal
  • the signal Vout for transmission on the conductive trace 03 can also be a clock signal, in particular, a clock.
  • the clock signal in which the signal Vin is inverted.
  • the plurality of gate traces can be arranged in an array. This means that multiple conductive traces can likewise be arranged in an array.
  • a display substrate is provided. Specifically, by providing a plurality of conductive traces and a plurality of gate traces on the base substrate, and inverting signals transmitted on each of the conductive traces and inverting signals transmitted on the corresponding one of the gate traces, The coupling noise generated on the display panel due to the drive signal transmitted on the gate traces is cancelled.
  • the provided display substrate can also be applied to a touch display panel. In this case, since the coupling noise on the surface of the panel has been reduced, the interference of the touch signal received by the touch display panel due to the coupling noise can be effectively reduced, thereby improving the touch precision of the touch display panel. .
  • the display substrate may further include a plurality of inverters 04 .
  • each inverter 04 is connected to a gate trace 02, and the output of each inverter 04 is connected to a conductive trace 03.
  • the gate traces 02 and the conductive traces 03 connected to the same inverter 04 are overlapped on the underlying substrate 01 (shown by the thick solid line S in FIG. 1).
  • the expression "the overlap of the gate trace 02 and the conductive trace 03 connected to the same inverter 04 on the base substrate 01” may mean partial overlap or may mean Completely overlapping. Such an interpretation applies equally to the term "overlapping" as it appears anywhere else in this document.
  • the number of the inverters 04 and the number of the conductive traces 03 are equal, that is, equal to the number of the gate traces 02.
  • the plurality of inverters 04 are also connected in one-to-one correspondence with the plurality of gate traces 02, and at the same time, are connected in one-to-one correspondence with the plurality of conductive traces 03.
  • each of the inverters 04 is shown sandwiched between the corresponding gate traces 02 and the conductive traces 03 in FIG. 1, this does not represent any limitation to the present disclosure. . In fact, those skilled in the art should be able to contemplate any suitable location for the plurality of inverters 04 in accordance with the teachings of the present disclosure, as long as the corresponding gate traces 02 and conductive traces 03 can be implemented, respectively, and inverted.
  • the electrical connection of the device 04 is sufficient. That is, the arrangement of the inverters 04 shown in FIG. 1 is merely an exemplary arrangement for achieving the objectives of the present disclosure, which may present, for example, a number of advantages, such as facilitating formation, simplifying processes, reducing costs, etc. .
  • the orthogonal projections of the gate traces 02 and the conductive traces 03 connected to the same inverter 04 on the base substrate 01 may completely coincide. That is, the width and arrangement direction of each of the conductive traces 03 and their corresponding gate traces 02 are exactly the same.
  • the conductive traces 03 may be formed using a conductive material for forming the gate traces 02.
  • the conductive traces 03 and the gate traces 02 may each be formed of a metal material. Therefore, it can be ensured that the signal transmitted on the conductive trace 03 can completely cancel the coupling noise generated by the signal transmitted on the corresponding gate trace 02, thereby effectively improving the touch precision of the touch panel.
  • the inverter 04 may include an N-type transistor TN and a P-type transistor TP.
  • the gate of the N-type transistor TN and the gate of the P-type transistor TP are connected to a gate trace 02, the second pole of the N-type transistor TN and the second pole of the P-type transistor TP and a strip
  • the conductive traces 03 are connected, the first pole of the P-type transistor TP is connected to the first power supply line VGH, and the first pole of the N-type transistor TN is connected to the second power supply line VGL.
  • the first power line VGH may be supplied with a first power signal of the first potential V1
  • the second power line VGL may be provided with a second power signal of the second potential V2, wherein the first potential V1 is relative to The second potential V2 is at a high potential.
  • the first pole can be the source and the second pole can be the drain. Of course, in other embodiments, for each transistor, it may also be a first extreme drain and a second anode.
  • the N-type transistor TN and the gate of the P-type transistor TP constitute an input terminal of the inverter 04 (on which the signal Vin is input), and the N-type transistor TN and the P-type transistor The second pole of the TP constitutes the output of the inverter 04 (which is used for the output signal Vout).
  • Vth is the threshold voltage of the N-type transistor TN
  • the output of the inverter 04 is turned on with the second power supply line VGL, so that the signal Vout supplied from its output terminal to the conductive trace 03 will have the second potential V2 supplied from the second power supply line VGL.
  • the second potential V2 is opposite to the potential V1 of the signal provided by the gate trace 02.
  • the signal Vin supplied from the gate trace 02 to the input terminal of the inverter 04 has a low potential V2.
  • the output of the inverter 04 is turned on with the first power supply line VGH, so that the signal Vout supplied from its output terminal to the conductive trace 03 will have the first potential V1 supplied from the first power supply line VGH. .
  • the first potential V1 is opposite to the potential V2 of the signal provided by the gate trace 02.
  • each of the inverters 04 may be disposed at one end of the gate trace 02 for connection with the gate driving circuit, wherein the gate driving circuit is used to trace each gate 02 provides a drive signal. Therefore, the end of the gate trace 02 for connecting to the gate driving circuit is also the input end of the gate trace 02.
  • the inverter 04 By setting the inverter 04 at the input end of the gate trace 02, when the gate driving circuit outputs a driving signal to the gate trace 02, the inverter 04 can promptly move to the corresponding conductive trace 03. Output inverted signal. Thereby, it is possible to ensure timely noise reduction of the coupling noise generated by the signal transmitted on the gate trace 02.
  • the inverter 04 can also be disposed at the other end of the gate trace 02, that is, the end away from the connection end of the gate trace 02 and the gate driving circuit, and the embodiment of the present disclosure does not limit this. .
  • the film layer structure 00 further includes a driving thin film transistor for driving the pixel electrode
  • the N-type transistor TN and the P-type transistor TP may also be selected as a thin film transistor.
  • the inverter 04 can be formed in synchronization with the driving thin film transistor in the original structure, thereby reducing the manufacturing difficulty of the display substrate.
  • FIG. 4 is a schematic diagram showing a film layer structure of an inverter 04 according to an embodiment of the present disclosure.
  • the film structure of the inverter 04 may include a gate layer 011, a gate insulating layer 012, an active layer 013, and a source/drain layer 014 which are sequentially disposed on the base substrate 01.
  • the gate layer 011 serves as a gate of the N-type transistor TN and the P-type transistor TP.
  • the active layer 013 includes an N-type semiconductor pattern 015 and a P-type semiconductor pattern 016 which are disposed at intervals
  • the source/drain layer 014 includes a first source pattern 017, a second source pattern 018, and a drain which are spaced apart from each other.
  • the first source pattern 017 serves as a first pole of the N-type transistor TN
  • the second source pattern 018 serves as a first pole of the P-type transistor TP
  • the drain pattern 019 serves as the N-type transistor TN and the The second pole of the P-type transistor TP.
  • FIG. 5 is a plan view showing a film layer structure of an inverter 04 of an embodiment of the present disclosure.
  • the gate layer 011 is electrically connected to a gate trace 02.
  • the first source pattern 017 is electrically connected to the second power line VGL, and the second source pattern 018 and the first The power line VGH is electrically connected, and the drain pattern 019 is electrically connected to one of the conductive traces 03.
  • the orthographic projection of the first source pattern 017 on the base substrate 01 overlaps with the orthographic projection of the N-type semiconductor pattern 015 on the base substrate 01. That is, the first source pattern 017 is in contact with the N-type semiconductor pattern 015.
  • the orthographic projection of the second source pattern 018 on the base substrate 01 overlaps with the orthographic projection of the P-type semiconductor pattern 016 on the base substrate 01. That is, the second source pattern 018 is in contact with the P-type semiconductor pattern 016.
  • an orthographic projection of the drain pattern 019 on the base substrate 01 overlaps with an orthographic projection of the N-type semiconductor pattern 015 on the base substrate 01, and the P-type semiconductor pattern 016 is on the base substrate 01.
  • the orthographic projections on the top overlap. That is, the drain pattern 019 is in contact with the N-type semiconductor pattern 015 and is in contact with the P-type semiconductor pattern 016. Further, an orthographic projection of the gate layer 011 on the base substrate 01 overlaps with an orthographic projection of the N-type semiconductor pattern 015 on the base substrate 01, and the P-type semiconductor pattern 016 is on the substrate. The orthographic projections on the substrate overlap. That is, the gate layer 011 is in contact with the N-type semiconductor pattern 015 and is in contact with the P-type semiconductor pattern 016.
  • the gate layer 011, the gate insulating layer 012, the P-type semiconductor pattern 016, the second source pattern 018, and the drain pattern 019 together constitute a P-type transistor TP.
  • the gate layer 011, the gate insulating layer 012, the N-type semiconductor pattern 015, the first source-level pattern 017, and the drain pattern 019 together constitute an N-type transistor TN.
  • the P-type transistor TP and the N-type transistor TN may share one gate layer 011 as a gate, and may share one drain pattern 019 as a second pole (eg, a drain).
  • the second source pattern 018 is the first pole (eg, the source) of the P-type transistor TP
  • the first source pattern 017 is the first pole (eg, the source) of the N-type transistor TN.
  • the inverter transmits the signal transmitted on the gate trace and inverts the inverted signal to the conductive trace as an example in the above embodiment
  • the present disclosure is absolutely Not limited to this.
  • a separate drive circuit can also be used to provide a plurality of conductive traces with signals that are inverted from signals on corresponding gate traces. That is, in accordance with such an embodiment, in the resulting display substrate or display panel, there will be two different drive circuits for driving a plurality of gate traces and a plurality of conductive traces, respectively.
  • a gate drive circuit for gate traces can be provided to enable transmission of a first signal across a plurality of gate traces, and at the same time, another drive circuit for conductive traces is provided to conduct multiple conductive traces A second signal is transmitted on the trace, wherein the first signal and the second signal are inverted.
  • driving circuits for a plurality of conductive traces can be provided to enable transmission of a first signal across a plurality of gate traces, and at the same time, another drive circuit for conductive traces is provided to conduct multiple conductive traces A second signal is transmitted on the trace, wherein the first signal and the second signal are inverted.
  • those skilled in the art should be able to flexibly select various deployment positions of driving circuits for a plurality of conductive traces according to actual needs, provided that they benefit from the teachings of the present disclosure, as long as they It is possible to drive a plurality of conductive traces to respectively transmit signals inverted from the signals on the corresponding gate traces. Accordingly, the present disclosure is intended to cover all of
  • embodiments of the present disclosure provide a display substrate. Specifically, by providing a plurality of conductive traces and a plurality of gate traces on the base substrate, and inverting signals transmitted on each of the conductive traces and inverting signals transmitted on the corresponding one of the gate traces, The coupling noise generated on the display panel due to the drive signal transmitted on the gate traces is cancelled.
  • the display substrate can be applied to a touch display panel. In this case, since the coupling noise on the surface of the display panel has been reduced, the interference of the touch signal received by the touch display panel due to the coupling noise can be effectively reduced, thereby improving the touch precision of the touch display panel.
  • Embodiments of the present disclosure also provide a method of manufacturing a display substrate.
  • a flow chart of a method of manufacturing a display substrate in accordance with an embodiment of the present disclosure is illustrated. As shown in FIG. 6-1, the manufacturing method may include the following steps.
  • Step 601 forming a plurality of gate traces on the base substrate.
  • a conductive material having a certain thickness may be deposited on the substrate to obtain a conductive material layer. After that, the conductive material layer is processed by a patterning process to obtain a plurality of gate traces.
  • a patterning process can include photoresist coating, exposure, development, etching, and photoresist stripping.
  • the conductive material used to form the gate traces may include, for example, metallic molybdenum (Mo), metallic copper (Cu), metallic aluminum (Al), alloy materials thereof, and the like.
  • the plurality of gate traces formed on the substrate may be arranged in an array or in other forms, and the embodiment of the present disclosure does not limit this.
  • Step 602 Form a film structure including a plurality of driving thin film transistors on a side of the plurality of gate traces away from the substrate.
  • the driving thin film transistor in the film layer structure may be a transistor for driving the pixel electrode, and the driving thin film transistor may be formed using a patterning process.
  • Step 603 forming a plurality of conductive traces on a side of the film structure away from the substrate.
  • a plurality of conductive traces may be continuously formed on the substrate substrate on which the film layer structure is formed by the method shown in the above step 601.
  • An orthographic projection of each gate trace on the substrate substrate overlaps with an orthographic projection of a corresponding one of the conductive traces on the substrate.
  • the signals transmitted on each of the conductive traces are inverted from the signals transmitted on the corresponding one of the gate traces. In this way, it is ensured that the coupling noise can be completely cancelled, thereby improving the touch precision of the display panel.
  • a mask for forming the plurality of gate traces may be employed, and the plurality of conductive traces may continue to be formed on the substrate substrate on which the film layer structure is formed.
  • the orthographic projection of the conductive traces on the substrate can be completely coincident with the orthographic projection of the gate traces. That is, each conductive trace has exactly the same width and arrangement direction as its corresponding gate trace.
  • the conductive traces for forming the gate traces can also be formed using conductive materials.
  • the conductive traces and the gate traces may each be formed of a metal material. Therefore, it can be ensured that the coupling noise generated by the signal transmitted on the corresponding gate trace can be completely canceled by the signal transmitted on the conductive trace, thereby effectively improving the sensitivity of the touch signal of the touch panel.
  • embodiments of the present disclosure provide a method of manufacturing a display substrate. Specifically, by disposing a plurality of conductive traces and a plurality of gate traces on the base substrate, and inverting signals transmitted on each of the conductive traces and inverting signals transmitted on the corresponding one of the gate traces, offsetting The coupling noise generated on the display panel due to the drive signal transmitted on the gate trace.
  • the display substrate can be applied to a touch display panel. In this case, since the coupling noise on the surface of the display panel is greatly reduced, the interference of the touch signal received by the touch display panel can be effectively reduced, thereby improving the touch precision of the touch display panel.
  • the above manufacturing method further includes the following steps before the above step 603.
  • Step 604 forming a plurality of inverters on the base substrate.
  • each inverter can be connected to one gate trace, and the output of each inverter can be connected to a conductive trace formed later.
  • the orthographic projections of the gate traces and the conductive traces connected to the same inverter on the substrate are overlapped.
  • a plurality of inverters may be formed on the base substrate using a patterning process.
  • a plurality of inverter chips may be disposed directly on the base substrate, and the input ends of each of the inverters are connected to one gate trace.
  • each of the conductive traces can be connected to the output of a corresponding one of the inverters.
  • the number of the inverters is equal to the number of the gate traces, and the input ends of the plurality of inverters are connected in one-to-one correspondence with the plurality of gate traces.
  • each of the inverters is composed of an N-type transistor TN and a P-type transistor TP
  • a plurality of sets of transistors can be formed on the base substrate, wherein each group
  • the transistor includes an N-type transistor and a P-type transistor.
  • the gate of the N-type transistor TN and the gate of the P-type transistor TP may be connected to a gate trace, and the first pole of the P-type transistor TP is connected to the first power line VGH.
  • the first pole of the N-type transistor TN is connected to the second power source line VGL.
  • the second pole of the N-type transistor TN and the second pole of the P-type transistor TP may be connected to one conductive trace.
  • the first power line VGH is supplied with a first power signal of a first potential V1
  • the second power line VGL is supplied with a second power signal of a second potential V2, wherein the first potential V1 is relative to the The second potential V2 is at a high potential.
  • the transistor in the inverter when the transistor in the inverter is a thin film transistor, the plurality of sets of transistors may be formed in synchronization in forming a driving thin film transistor for driving the pixel electrode. That is, step 604 can be performed in synchronization with step 602, whereby the manufacturing process can be simplified.
  • 6-2 is a flow chart illustrating a process for forming a set of transistors in an inverter on a substrate substrate, in accordance with an embodiment of the present disclosure.
  • the process of forming a group of transistors in the inverter in the above step 604 may include the following steps.
  • Step 6041 Form a gate layer on the base substrate such that the gate layer is electrically connected to a gate trace.
  • the gate layer may be formed as a gate of the N-type transistor TN and the P-type transistor TP.
  • the process of forming the gate layer reference may be made to step 601 above, and no further details are provided herein.
  • the gate layer and the gate traces may be disposed in the same layer. Therefore, the plurality of gate traces and the gate layer can be formed synchronously on the base substrate.
  • Step 6042 sequentially forming a gate insulating layer and an active layer on a side of the gate layer away from the base substrate, wherein the active layer comprises an N-type semiconductor pattern and a P-type semiconductor pattern formed at intervals.
  • a layer of insulating material having a certain thickness may be continuously deposited on the substrate substrate on which the gate layer is formed, thereby obtaining a gate insulating film layer. After that, the gate insulating film layer may be baked to form a gate insulating layer.
  • the insulating material may be silicon oxide, silicon nitride, or a mixed material of silicon oxide and silicon nitride.
  • an active thin film material for example, an amorphous silicon material having a certain thickness may be deposited on a side of the gate insulating layer away from the substrate substrate to obtain an active thin film material layer.
  • the active thin film material layer is processed by one patterning process to obtain two active layer patterns spaced apart.
  • each pattern is doped with N-type ions (such as phosphorus, arsenic) and P-type ions (such as boron, gallium) to obtain an N-type semiconductor pattern and a P-type semiconductor pattern, respectively.
  • N-type semiconductor pattern and the P-type semiconductor pattern constitute an active layer.
  • FIG. 6-3 a schematic diagram of a structure after sequentially forming the gate insulating layer 012 and the active layer 013 on the side of the gate layer 011 away from the base substrate 01 is shown.
  • the active layer 013 includes an N-type semiconductor pattern 015 and a P-type semiconductor pattern 016 which are formed at intervals.
  • Step 6043 forming a source/drain layer on a side of the active layer away from the base substrate, wherein the source drain layer comprises a first source pattern, a second source pattern and a drain pattern formed at intervals.
  • a conductive material having a certain thickness may be deposited on a side of the active layer away from the substrate to obtain a conductive thin film layer (for example, a metal film layer).
  • the conductive thin film layer is then processed by a patterning process to obtain a first source pattern, a second source pattern, and a drain pattern.
  • the first source pattern is electrically connected to a second power line in the display substrate
  • the second source pattern is electrically connected to the first power line in the display substrate
  • the drain pattern is electrically connected to a conductive trace connection.
  • an orthographic projection of the first source pattern on the substrate substrate overlaps with an orthographic projection of the N-type semiconductor pattern on the substrate, and an orthographic projection of the second source pattern on the substrate
  • An orthographic projection of the P-type semiconductor pattern on the base substrate overlaps.
  • an orthographic projection of the drain pattern on the base substrate overlaps with an orthographic projection of the N-type semiconductor pattern on the base substrate, and overlaps with an orthographic projection of the P-type semiconductor pattern on the base substrate .
  • an orthographic projection of the gate layer on the substrate substrate overlaps with an orthographic projection of the N-type semiconductor pattern on the substrate substrate, and overlaps with an orthographic projection of the P-type semiconductor pattern on the substrate substrate .
  • the first source pattern constitutes a first pole (eg, a source) of the N-type transistor TN
  • the second source pattern constitutes a first pole (eg, a source) of the P-type transistor TP
  • FIG. 6-4 shows a schematic diagram of a specific structure after the source/drain layer 014 is formed on the side of the active layer 013 away from the base substrate 01, wherein the source/drain layer 014 includes a space.
  • a first source pattern 017, a second source pattern 018, and a drain pattern 019 are formed.
  • each of the inverters 04 may be disposed at one end of the gate trace 02 for connecting with the gate driving circuit, wherein the gate driving circuit is used for each A gate trace 02 provides a drive signal. Therefore, the end of the gate trace 02 for connecting to the gate driving circuit is also the input end of the gate trace 02.
  • the inverter 04 By setting the inverter 04 at the input end of the gate trace 02, when the driving signal is output from the gate driving circuit to the gate trace 02, the inverter 04 can promptly move to the corresponding conductive trace 03. Output inverted signal. In this way, it is ensured that the coupling noise generated by the signal transmitted on the gate trace 02 is timely denoised.
  • embodiments of the present disclosure provide a method of manufacturing a display substrate. Specifically, by disposing a plurality of conductive traces and a plurality of gate traces on the base substrate, and inverting signals transmitted on each of the conductive traces and inverting signals transmitted on the corresponding one of the gate traces, offsetting The coupling noise generated on the display panel due to the drive signal transmitted on the gate trace. Moreover, the display substrate can be applied to a touch display panel. In this case, since the coupling noise on the surface of the display panel is significantly reduced, the interference of the touch signal received by the touch display panel can be effectively reduced, thereby improving the touch precision of the touch display panel. .
  • Embodiments of the present disclosure also provide a display panel.
  • the display panel may include, for example, the display substrate shown in FIG. 1, wherein the display substrate may include an inverter such as that shown in any of FIGS. 3 to 5.
  • the display panel may be a touch display panel.
  • the display panel can be any display panel that includes a product or component that has a display function and can be touched, such as a liquid crystal panel, a cell phone, a tablet, a notebook computer, a digital camera, and the like.
  • Embodiments of the present disclosure also provide a display device.
  • the display device may include the display panel described above, wherein the display panel may include a display substrate as shown in FIG.
  • the display device may be any device having a display function, such as a mobile phone, a tablet, a notebook computer, a digital camera, or the like.

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Abstract

本公开涉及显示技术领域，并且提出了显示基板及其制造方法、显示面板以及显示装置。显示基板包括：衬底基板；设置在所述衬底基板上的多条栅极走线，设置在该多条栅极走线远离衬底基板的一侧上的膜层结构，以及设置在该膜层结构远离衬底基板的一侧上的多条导电走线。在以上显示基板中，每条栅极走线在所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影至少部分地重叠，并且用于在每条导电走线上传输的信号与用于在对应的一条栅极走线上传输的信号反相。

Description

显示基板及其制造方法、显示面板、显示装置
对相关申请的交叉引用
本申请要求2017年8月25日提交的中国专利申请号201710741195.9的优先权，该中国专利申请以其整体通过引用并入本文。
技术领域
本公开涉及显示技术领域，并且具体地公开了显示基板及其制造方法、显示面板以及显示装置。
背景技术
对于典型的显示装置，在显示图像时，一般需要利用栅极驱动电路(gate driving circuit)对显示面板中的多行像素单元进行逐行扫描。具体地，每个像素单元包括一个驱动晶体管和一个像素电极，并且位于同一行像素单元中的驱动晶体管与一条栅线连接。当栅极驱动电路向一条栅线输出栅极驱动信号时，与该条栅线连接的一行像素单元中的驱动晶体管可以由于这种驱动而开启，并且由此为像素电极充电。
在相关技术中，由栅极驱动电路向每条栅线输出的驱动信号一般为时钟信号。由于该时钟信号的高电平和低电平之间的压差较大，因此在时钟信号的电平跳变时，栅线电压的变化较大，往往会在显示面板的表面上产生耦合噪音。
目前，显示面板一般为集成有触控功能的触控显示面板。当使用该触控显示面板对触控信号进行检测时，检测可能会受到触控显示面板表面上的耦合噪音的干扰，进而影响该触控显示面板的触控精度。
发明内容
根据本公开的一个方面，提出了一种显示基板。具体地，所述显示基板包括：衬底基板；设置在所述衬底基板上的多条栅极走线(gate line)；设置在所述多条栅极走线远离所述衬底基板的一侧上的膜层结构(film structure)；以及设置在所述膜层结构远离所述衬底基板的一侧上的多条导电走线(conductive line)。进一步地，每条栅极走线在 所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影至少部分地重叠，并且用于在每条导电走线上传输的信号与用于在对应的一条栅极走线上传输的信号反相。
根据具体实现方式，由本公开的实施例提供的显示基板还包括多个反相器。具体地，每个所述反相器的输入端与一条栅极走线连接，每个所述反相器的输出端与一条导电走线连接，并且与同一个反相器连接的栅极走线和导电走线在所述衬底基板上的正投影至少部分地重叠。
根据具体实现方式，在本公开的实施例提供的显示基板中，每条栅极走线在所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影重合。
根据具体实现方式，在本公开的实施例提供的显示基板中，每个所述反相器包括N型晶体管和P型晶体管。具体地，所述N型晶体管的栅极和所述P型晶体管的栅极与一条栅极走线连接，所述N型晶体管的第二极和所述P型晶体管的第二极与一条导电走线连接，所述P型晶体管的第一极与第一电源线连接，并且所述N型晶体管的第一极与第二电源线连接。此外，所述第一电源线提供有第一电位的第一电源信号，并且所述第二电源线提供有第二电位的第二电源信号，其中，所述第一电位相对于所述第二电位为高电位。
根据具体实现方式，在本公开的实施例提供的显示基板中，所述N型晶体管和所述P型晶体管均为薄膜晶体管。
根据具体实现方式，在本公开的实施例提供的显示基板中，每个所述反相器包括：依次设置在所述衬底基板上的栅极图层、栅绝缘层、有源层和源漏图层。所述栅极图层配置为充当所述N型晶体管和所述P型晶体管的栅极。所述有源层包括间隔设置的N型半导体图案和P型半导体图案。所述源漏图层包括间隔设置的第一源极图案、第二源极图案和漏极图案，其中，所述第一源极图案配置为充当所述N型晶体管的第一极，所述第二源极图案配置为充当所述P型晶体管的第一极，并且所述漏极图案配置为充当所述N型晶体管和所述P型晶体管的第二极。所述栅极图层与一条栅极走线电连接，所述第一源极图案与所述第二电源线电连接，所述第二源极图案与所述第一电源线电连接，并且所述漏极图案与一条导电走线电连接。
根据具体实现方式，在本公开的实施例提供的显示基板中，所述第一源极图案在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠。所述第二源极图案在所述衬底基板上的正投影与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。所述漏极图案在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。此外，所述栅极图层在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。
根据具体实现方式，在本公开的实施例提供的显示基板中，每个所述反相器设置在对应的一条栅极走线的用于与栅极驱动电路连接的一端处。
根据具体实现方式，在本公开的实施例提供的显示基板中，所述膜层结构包括多个驱动薄膜晶体管(driving thin film transistor)。
根据具体实现方式，由本公开的实施例提供的显示基板，还包括：用于所述多条导电走线的驱动电路。具体地，所述驱动电路配置为使得在每条导电走线上传输与在对应的一条栅极走线上传输的信号反相的信号。
根据本公开的另一方面，还提出了一种用于显示基板的制造方法。具体地，所述制造方法包括以下步骤：在衬底基板上形成多条栅极走线；在所述多条栅极走线远离所述衬底基板的一侧上形成膜层结构；以及在所述膜层结构远离所述衬底基板的一侧上形成多条导电走线。此外，每条栅极走线在所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影至少部分地重叠，并且用于在每条导电走线上传输的信号与用于在对应的一条栅极走线上传输的信号反相。
根据具体实现方式，由本公开的实施例提供的用于显示基板的制造方法还包括在所述衬底基板上形成多个反相器的步骤。具体地，每个所述反相器的输入端与一条栅极走线连接，每个所述反相器的输出端与一条导电走线连接，并且与同一个反相器连接的栅极走线和导电走线在所述衬底基板上的正投影至少部分地重叠。
根据具体实现方式，在本公开的实施例提供的用于显示基板的制 造方法中，在所述膜层结构远离所述衬底基板的一侧上形成多条导电走线的步骤包括：采用用于形成所述多条栅极走线的掩膜板，在所述膜层结构远离所述衬底基板的一侧上形成所述多条导电走线。
根据具体实现方式，在本公开的实施例提供的用于显示基板的制造方法中，每个所述反相器包括N型晶体管和P型晶体管。在这样的情况下，在所述衬底基板上形成多个反相器的步骤包括：在所述衬底基板上形成多组晶体管，其中，每组晶体管包括一个N型晶体管和一个P型晶体管。进一步地，每组晶体管中的N型晶体管的栅极和P型晶体管的栅极与一条栅极走线连接，每组晶体管中的N型晶体管的第二极和P型晶体管的第二极与一条导电走线连接，每组晶体管中的P型晶体管的第一极与第一电源线连接，并且每组晶体管中的N型晶体管的第一极与第二电源线连接。此外，所述第一电源线提供有第一电位的第一电源信号，并且所述二电源线提供有第二电位的第二电源信号，所述第一电位相对于所述第二电位为高电位。
根据具体实现方式，在本公开的实施例提供的用于显示基板的制造方法中，所述N型晶体管和所述P型晶体管均为薄膜晶体管。在这样的情况下，在所述衬底基板上形成多组晶体管的步骤包括：在形成所述驱动薄膜晶体管的过程中，同步形成所述多组晶体管。
根据具体实现方式，在本公开的实施例提供的用于显示基板的制造方法中，通过以下过程形成每一组晶体管：在所述衬底基板上形成栅极图层，使得所述栅极图层与一条栅极走线电连接并且充当所述N型晶体管和所述P型晶体管的栅极；在所述栅极图层远离所述衬底基板的一侧上依次形成栅绝缘层和有源层，所述有源层包括间隔形成的N型半导体图案和P型半导体图案；以及在所述有源层远离所述衬底基板的一侧上形成源漏图层，所述源漏图层包括间隔形成的第一源极图案、第二源极图案和漏极图案。具体地，所述第一源极图案与所述第二电源线电连接，所述第二源极图案与所述第一电源线电连接，并且所述漏极图案与一条导电走线电连接。进一步地，所述第一源极图案形成为充当所述N型晶体管的第一极，所述第二源极图案形成为充当所述P型晶体管的第一极，并且所述漏极图案形成为充当所述N型晶体管和所述P型晶体管的第二极。
根据具体实现方式，在本公开的实施例提供的用于显示基板的制 造方法中，所述第一源极图案形成为在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠。进一步地，所述第二源极图案形成为在所述衬底基板上的正投影与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。此外，所述漏极图案形成为在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。同样地，所述栅极图层形成为在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。
根据具体实现方式，由本公开的实施例提供的用于显示基板的制造方法，还包括以下步骤：提供用于所述多条导电走线的驱动电路，使得在每条导电走线上传输与在对应的一条栅极走线上传输的信号反相的信号。根据本公开的又一方面，还提出了一种显示面板。具体地，所述显示面板包括：在前面的任一个实施例中描述的显示基板。
根据本公开的再一方面，还提出了一种显示装置。具体地，所述显示装置包括：在前面的任一个实施例中描述的显示面板。
附图说明
为了更清楚地说明本公开的实施例中的技术方案，下面将对实施例的描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅代表本公开的一些实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1是根据本公开的实施例的显示基板的结构示意图；
图2是示出了根据本公开的实施例的显示基板中的传输信号的时序变化的示意图；
图3是示出了根据本公开的实施例的显示基板中的反相器的等效电路的示意图；
图4是示出了根据本公开的实施例的显示基板中的反相器的膜层结构的示意图；
图5是示出了根据本公开的实施例的显示基板中的反相器的膜层 结构的俯视图；
图6-1是根据本公开的实施例的用于显示基板的制造方法的流程图；
图6-2是根据本公开的实施例的用于在衬底基板上形成一组晶体管的过程的流程图；
图6-3是根据本公开的实施例的在栅极图层远离衬底基板的一侧上依次形成栅绝缘层和有源层之后的结构的示意图；以及
图6-4是根据本公开的实施例的在有源层远离衬底基板的一侧上形成源漏图层之后的结构的示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开的实施方式作进一步地详细描述。
图1是根据本公开的实施例的显示基板的示意图。如图1所示，该显示基板可以包括设置在衬底基板01上的多条栅极走线02。进一步地，在该多条栅极走线02远离该衬底基板01的一侧上还设置有膜层结构00。可选地，该膜层结构00可以包括用于驱动像素电极的多个驱动薄膜晶体管。此外，在该膜层结构00远离该衬底基板01的一侧上还设置有多条导电走线03。具体地，每条栅极走线02在该衬底基板01上的正投影与对应的一条导电走线03在该衬底基板01上的正投影(如图1中的粗实线S所示)重叠。通常，每条导电走线03在该衬底基板01上的正投影仅与一条栅极走线02的正投影重叠，以避免由于该导电走线03在该衬底基板01上的正投影与其他栅极走线02在该衬底基板01上的正投影重叠而带来的更大耦合噪音。
如图2所示，如果用于在栅极走线02上传输的信号Vin为时钟信号，则用于在该导电走线03上传输的信号Vout也可以为时钟信号，特别地，是与时钟信号Vin反相的时钟信号。此外，本领域技术人员应当理解到，该多条栅极走线可以呈阵列设置。这意味着，多条导电走线同样地可以呈阵列设置。
综上所述，根据本公开的实施例，提供了一种显示基板。具体地，通过在衬底基板上设置多条导电走线和多条栅极走线，并且使每条导电走线上传输的信号与对应的一条栅极走线上传输的信号反相，可以 抵消由于栅极走线上传输的驱动信号而在显示面板上产生的耦合噪音。此外，根据本公开的实施例，所提供的显示基板还可以应用于触控显示面板中。在这样的情况下，因为面板表面上的耦合噪音已经降低，所以可以有效地降低由于耦合噪音而对触控显示面板所接收的触控信号的干扰，从而提高了触控显示面板的触控精度。
可选地，如图1所示，该显示基板还可以包括多个反相器04。
具体地，每个反相器04的输入端与一条栅极走线02连接，并且每个反相器04的输出端与一条导电走线03连接。此外，与同一个反相器04连接的栅极走线02和导电走线03在该衬底基板01上的正投影(如图1中的粗实线S所示)重叠。此处，需要指出的是，表述“与同一个反相器04连接的栅极走线02和导电走线03在该衬底基板01上的正投影重叠”可以是指部分重叠也可以是指完全重叠。这样的解释同样地适用于出现在本文任何其它地方的用语“重叠”。
需要说明的是，在本公开的实施例中，反相器04的个数和导电走线03的个数相等，即，均等于该栅极走线02的个数。此外，该多个反相器04还与该多条栅极走线02一一对应地连接，并且同时，与该多条导电走线03一一对应地连接。
此处，需要说明的是，虽然在图1中将每一个反相器04示出了夹在对应的栅极走线02和导电走线03之间，但是这并不代表对本公开的任何限制。事实上，根据本公开的教导，本领域技术人员应当能够设想到用于多个反相器04的任何适合的位置，只要能够实现对应的栅极走线02和导电走线03分别与反相器04的电连接即可。也就是说，在图1中示出的反相器04的布置仅仅是用于实现本公开的目标的一种示例性布置，其例如可以呈现诸多优势，诸如方便形成、简化工艺、降低成本等。
进一步地，如图1所示，与同一个反相器04连接的栅极走线02和导电走线03在该衬底基板01上的正投影可以完全重合。也即是，每条导电走线03与其对应的栅极走线02的宽度和排布方向完全相同。而且，可以采用用于形成该栅极走线02的导电材料来形成该导电走线03。例如，该导电走线03和栅极走线02可以均采用金属材料形成。由此，可以保证在导电走线03上传输的信号可以完全抵消由其对应的栅极走线02上传输的信号所产生的耦合噪音，从而可以有效提高触控 面板的触控精度。
参照图3，示意性示出了根据本公开的实施例的反相器04的等效电路图。如图3所示，该反相器04可以包括N型晶体管TN和P型晶体管TP。
具体地，该N型晶体管TN的栅极和该P型晶体管TP的栅极与一条栅极走线02连接，该N型晶体管TN的第二极和该P型晶体管TP的第二极与一条导电走线03连接，该P型晶体管TP的第一极与第一电源线VGH连接，并且该N型晶体管TN的第一极与第二电源线VGL连接。此外，该第一电源线VGH可以提供有第一电位V1的第一电源信号，并且该第二电源线VGL可以提供有第二电位V2的第二电源信号，其中，该第一电位V1相对于该第二电位V2为高电位。作为示例，对于以上提及的每个晶体管，第一极可以为源极，并且第二极可以为漏极。当然，在其它实施例中，对于每一个晶体管而言，也可以是，第一极为漏极，而第二极为阳极。
从图3可以看出，该N型晶体管TN和该P型晶体管TP的栅极即构成反相器04的输入端(在其上输入信号Vin)，并且该N型晶体管TN和该P型晶体管TP的第二极即构成反相器04的输出端(其用于输出信号Vout)。
假设由栅极走线02向该反相器04的输入端提供的信号Vin具有高电位V1。此时，由于P型晶体管TP的源极的电位是由第一电源线VGH提供的第一电位V1，所以P型晶体管TP的栅源电压差Vgs1满足：Vgs1＝V1-V1＝0，从而导致P型晶体管TP截止。与此同时，由于N型晶体管TN的源极的电位是由第二电源线VGL提供的第二电位V2，所以此时N型晶体管TN的栅源电压差Vgs2满足：Vgs2＝V1-V2＞Vth(其中，Vth为N型晶体管TN的阈值电压)，从而导致N型晶体管TN导通。在这样的情况下，反相器04的输出端与第二电源线VGL导通，因此从其输出端向导电走线03提供的信号Vout将具有由第二电源线VGL提供的第二电位V2。显然，该第二电位V2与该栅极走线02提供的信号的电位V1相反。
假设由栅极走线02向该反相器04的输入端提供的信号Vin具有低电位V2。此时，由于P型晶体管TP的源极的电位是由第一电源线VGH提供的第一电位V1，所以P型晶体管TP的栅源电压差Vgs1满 足：Vgs1＝V2-V1＜0，从而导致P型晶体管TP导通。与此同时，由于N型晶体管TN的源极的电位是由第二电源线VGL提供的第二电位V2，所以此时N型晶体管TN的栅源电压差Vgs2满足：Vgs2＝V2-V2＝0，从而导致N型晶体管TN截止。在这样的情况下，反相器04的输出端与第一电源线VGH导通，因此从其输出端向导电走线03提供的信号Vout将具有由第一电源线VGH提供的第一电位V1。显然，该第一电位V1与该栅极走线02提供的信号的电位V2相反。
在本公开的实施例中，每个反相器04可以设置在栅极走线02的用于与栅极驱动电路连接的一端，其中，该栅极驱动电路用于为每条栅极走线02提供驱动信号。因此，该栅极走线02的用于与栅极驱动电路连接的一端也即是该栅极走线02的输入端。通过将该反相器04设置在该栅极走线02的输入端，使得当栅极驱动电路向栅极走线02上输出驱动信号时，反相器04可以及时向对应的导电走线03输出反相信号。由此，可以保证对在栅极走线02上传输的信号所产生的耦合噪音进行及时降噪。
当然，该反相器04也可以设置在栅极走线02的另一端，即，远离栅极走线02与栅极驱动电路的连接端的那一端，并且本公开的实施例对此不做限定。
需要说明的是，由于该膜层结构00还包括用于驱动像素电极的驱动薄膜晶体管，因此该N型晶体管TN和该P型晶体管TP也可以选择为薄膜晶体管。由此，该反相器04可以与原结构中的驱动薄膜晶体管同步地形成，从而降低显示基板的制造难度。
图4是示出了根据本公开的实施例的反相器04的膜层结构的示意图。如图4所示，该反相器04的膜层结构可以包括：依次设置在该衬底基板01上的栅极图层011、栅绝缘层012、有源层013和源漏图层014。具体地，该栅极图层011充当N型晶体管TN和P型晶体管TP的栅极。此外，该有源层013包括间隔设置的N型半导体图案015和P型半导体图案016，并且该源漏图层014包括间隔设置的第一源极图案017、第二源极图案018和漏极图案019。该第一源极图案017充当该N型晶体管TN的第一极，该第二源极图案018充当该P型晶体管TP的第一极，并且该漏极图案019充当该N型晶体管TN和该P型晶体管TP的第二极。
图5是示出了本公开的实施例的反相器04的膜层结构的俯视图。如图5所示，该栅极图层011与一条栅极走线02电连接，该第一源极图案017与该第二电源线VGL电连接，该第二源极图案018与该第一电源线VGH电连接，并且该漏极图案019与一条导电走线03电连接。
参考图5，还可以看出的是，该第一源极图案017在该衬底基板01上的正投影与该N型半导体图案015在该衬底基板01上的正投影重叠。即，该第一源极图案017与该N型半导体图案015接触。而且，该第二源极图案018在该衬底基板01上的正投影与该P型半导体图案016在该衬底基板01上的正投影重叠。即，该第二源极图案018与该P型半导体图案016接触。此外，该漏极图案019在该衬底基板01上的正投影与该N型半导体图案015在该衬底基板01上的正投影重叠，并且与该P型半导体图案016在该衬底基板01上的正投影重叠。即，该漏极图案019与该N型半导体图案015接触，并且与该P型半导体图案016接触。进一步地，该栅极图层011在该衬底基板01上的正投影与该N型半导体图案015在该衬底基板01上的正投影重叠，并且与该P型半导体图案016在该衬底基板上的正投影重叠。也就是说，该栅极图层011与该N型半导体图案015接触，并且与该P型半导体图案016接触。
结合图3至图5，还可以看出的是，在该反相器04中，栅极图层011、栅绝缘层012、P型半导体图案016、第二源极图案018和漏极图案019一起构成一个P型晶体管TP。对应地，该栅极图层011、栅绝缘层012、N型半导体图案015、第一源级图案017和漏极图案019一起构成一个N型晶体管TN。具体地，P型晶体管TP和N型晶体管TN可以共用一个栅极图层011作为栅极，并且可以共用一个漏极图案019作为第二极(例如，漏极)。此外，第二源极图案018即为该P型晶体管TP的第一极(例如，源极)，并且第一源极图案017为该N型晶体管TN的第一极(例如，源极)。
此处，需要说明的是，虽然在以上实施例中作为示例而使用反相器将在栅极走线上传输的信号反相并且将经反相的信号引导至导电走线，但是本公开绝不仅限于此。例如，在可替换的其它实施例中，还可以使用单独的驱动电路来为多条导电走线提供与对应栅极走线上的信号反相的信号。也就是说，依照这样的实施例，在最终形成的显示 基板或显示面板中，将存在两个不同的驱动电路，它们分别用于驱动多条栅极走线和多条导电走线。作为示例，可以提供用于栅极走线的栅极驱动电路使得能够在多条栅极走线上传输第一信号，并且同时，提供用于导电走线的另一驱动电路以便在多条导电走线上传输第二信号，其中，所述第一信号和所述第二信号反相。另外，还需要指出的是，在获益于本公开的教导的前提下，本领域技术人员应当能够根据实际需要灵活地选择用于多条导电走线的驱动电路的各种部署位置，只要其能够驱动多条导电走线以便分别传输与对应栅极走线上的信号反相的信号即可。因此，本公开旨在涵盖适用于多条导电走线的驱动电路的所有这些可行的部署位置。
综上所述，本公开的实施例提供了一种显示基板。具体地，通过在衬底基板上设置多条导电走线和多条栅极走线，并且使每条导电走线上传输的信号与对应的一条栅极走线上传输的信号反相，可以抵消由于栅极走线上传输的驱动信号而在显示面板上产生的耦合噪音。此外，该显示基板可以应用于触控显示面板中。在这样的情况下，因为显示面板表面上的耦合噪音已经降低，所以可以有效降低由于耦合噪音对触控显示面板所接收的触控信号的干扰，从而提高了触控显示面板的触控精度。
本公开的实施例还提供了一种用于显示基板的制造方法。参照图6-1，示出了根据本公开的实施例的用于显示基板的制造方法的流程图。如图6-1所示，该制造方法可以包括以下步骤。
步骤601、在衬底基板上形成多条栅极走线。
在本公开的实施例中，可以在衬底基板上沉积一层具有一定厚度的导电材料，从而得到导电材质层。在此之后，通过一次构图工艺对导电材质层进行处理以得到多条栅极走线。
例如，一次构图工艺可以包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。用于形成栅极走线的导电材料可以例如包括金属钼(Mo)、金属铜(Cu)、金属铝(Al)及其合金材料等。
在衬底基板上形成的多条栅极走线可以是阵列排布的，也可以是其他形式的排布，并且本公开的实施例对此不做限定。
步骤602、在该多条栅极走线远离衬底基板的一侧上形成包括多个驱动薄膜晶体管的膜层结构。
该膜层结构中的驱动薄膜晶体管可以是用于驱动像素电极的晶体管，并且该驱动薄膜晶体管可以采用构图工艺形成。
步骤603、在该膜层结构远离衬底基板的一侧上形成多条导电走线。
进一步地，可以采用上述步骤601所示的方法，在形成有该膜层结构的衬底基板上继续形成多条导电走线。每条栅极走线在该衬底基板上的正投影与对应的一条导电走线在该衬底基板上的正投影重叠。而且，在每条导电走线上传输的信号与在对应的一条栅极走线上传输的信号反相。以这样的方式，保证了能够完全抵消耦合噪音，从而提高显示面板的触控精度。
在本公开的实施例中，可以采用用于形成该多条栅极走线的掩膜板，在形成有该膜层结构的衬底基板上继续形成该多条导电走线。以这样的方式，使得该导电走线在该衬底基板上的正投影可以与栅极走线的正投影完全重合。也即是，每条导电走线与其对应的栅极走线的宽度和排布方向完全相同。而且，还可以采用用于形成该栅极走线的导电材料来形成该导电走线。例如，该导电走线和栅极走线可以均采用金属材料形成。由此，可以保证通过在导电走线上传输的信号，可以完全抵消由于其对应的栅极走线上传输的信号而产生的耦合噪音，从而有效提高触控面板的触控信号的灵敏度。
综上所述，本公开的实施例提供了一种用于显示基板的制造方法。具体地，通过在衬底基板上设置多条导电走线和多条栅极走线，并且使每条导电走线上传输的信号与对应的一条栅极走线上传输的信号反相，抵消了由于栅极走线上传输的驱动信号而在显示面板上产生的耦合噪音。此外，该显示基板可以应用于触控显示面板中。在这样的情况下，因为显示面板表面上的耦合噪音大幅降低，所以可以有效降低由于耦合噪音对触控显示面板所接收的触控信号的干扰，从而提高了触控显示面板的触控精度。
可选地，上述制造方法还包括在上述步骤603之前的以下步骤。
步骤604、在衬底基板上形成多个反相器。
具体地，每个反相器的输入端可以与一条栅极走线连接，并且每个反相器的输出端可以与之后形成的一条导电走线连接。此外，与同一个反相器连接的栅极走线和导电走线在该衬底基板上的正投影重 叠。
在本公开的实施例中，可以采用构图工艺在该衬底基板上形成多个反相器。可替换地，也可以直接在该衬底基板上设置多个反相器芯片，并且将每个反相器的输入端与一条栅极走线连接。在此之后，在形成多条导电走线时，可以将每条导电走线与对应的一个反相器的输出端连接。具体地，该反相器的个数与栅极走线的条数相等，并且该多个反相器的输入端与多条栅极走线一一对应地连接。
参考图3，由于每个反相器由一个N型晶体管TN和P型晶体管TP组成而成，因此在形成多个反相器时，可以在衬底基板上形成多组晶体管，其中，每组晶体管包括一个N型晶体管和一个P型晶体管。在形成过程中，可以将该N型晶体管TN的栅极和该P型晶体管TP的栅极与一条栅极走线连接，将该P型晶体管TP的第一极与第一电源线VGH连接，并且将该N型晶体管TN的第一极与第二电源线VGL连接。在形成导电走线后，进一步地，可以将该N型晶体管TN的第二极和P型晶体管TP的第二极与一条导电走线连接。作为示例，该第一电源线VGH提供有第一电位V1的第一电源信号，并且该第二电源线VGL提供有第二电位V2的第二电源信号，其中，该第一电位V1相对于该第二电位V2为高电位。
在本公开的实施例中，当该反相器中的晶体管为薄膜晶体管时，在形成用于驱动像素电极的驱动薄膜晶体管的过程中，可以同步地形成该多组晶体管。也就是说，步骤604可以与步骤602同步执行，由此可以简化制造工艺。
图6-2是示出了根据本公开的实施例的用于在衬底基板上形成反相器中的一组晶体管的过程的流程图。参考图6-2，在上述步骤604中形成反相器中的一组晶体管的过程可以包括以下步骤。
步骤6041、在该衬底基板上形成栅极图层，使得该栅极图层与一条栅极走线电连接。
具体地，该栅极图层可以形成为该N型晶体管TN和该P型晶体管TP的栅极。用于形成该栅极图层的过程可以参考上述步骤601，并且在此不做赘述。
需要说明的是，在实际应用中，该栅极图层与栅极走线可以同层设置。因此，可以在衬底基板上同步地形成该多条栅极走线和该栅极 图层。
步骤6042、在该栅极图层远离该衬底基板的一侧上依次形成栅绝缘层和有源层，其中，该有源层包括间隔形成的N型半导体图案和P型半导体图案。
在本公开的实施例中，可以在形成有栅极图层的衬底基板上继续沉积一层具有一定厚度的绝缘材料，从而得到栅绝缘薄膜层。在此之后，可以对该栅绝缘薄膜层进行烘烤处理以形成栅绝缘层。可选地，该绝缘材料可以为氧化硅、氮化硅或者氧化硅和氮化硅的混合材料等。
进一步地，可以在栅绝缘层远离衬底基板的一侧上沉积一层具有一定厚度的有源薄膜材料(例如，非晶硅材料)，以得到有源薄膜材料层。在此之后，通过一次构图工艺对该有源薄膜材料层进行处理，以得到间隔设置的两个有源层图案。紧接着，分别对每个图案进行N型离子(诸如，磷、砷)掺杂和P型离子(诸如，硼、镓)掺杂，以得到N型半导体图案和P型半导体图案。由此，该N型半导体图案和P型半导体图案即构成有源层。
示例性地，参考图6-3，其示出了在该栅极图层011远离该衬底基板01的一侧上依次形成栅绝缘层012和有源层013之后的结构的示意图。该有源层013包括间隔形成的N型半导体图案015和P型半导体图案016。
步骤6043、在该有源层远离该衬底基板的一侧上形成源漏图层，其中，该源漏图层包括间隔形成的第一源极图案、第二源极图案和漏极图案。
进一步地，可以在有源层远离衬底基板的一侧上沉积一层具有一定厚度的导电材料，以得到导电薄膜层(例如，金属膜层)。在此之后，然后通过一次构图工艺对该导电薄膜层进行处理，以得到第一源极图案、第二源极图案和漏极图案。具体地，该第一源极图案与显示基板中的第二电源线电连接，该第二源极图案与显示基板中的第一电源线电连接，并且该漏极图案与一条导电走线电连接。此外，该第一源极图案在该衬底基板上的正投影与该N型半导体图案在该衬底基板上的正投影重叠，并且该第二源极图案在该衬底基板上的正投影与该P型半导体图案在该衬底基板上的正投影重叠。进一步地，该漏极图案在该衬底基板上的正投影与该N型半导体图案在该衬底基板上的正投 影重叠，并且与该P型半导体图案在该衬底基板上的正投影重叠。而且，该栅极图层在该衬底基板上的正投影与该N型半导体图案在该衬底基板上的正投影重叠，并且与该P型半导体图案在该衬底基板上的正投影重叠。
该第一源极图案即构成N型晶体管TN的第一极(例如，源极)，第二源极图案即构成P型晶体管TP的第一极(例如，源极)，并且该漏极图案即构成N型晶体管TN和P型晶体管TP的第二极(例如，漏极)。
示例性地，图6-4示出了在该有源层013远离该衬底基板01的一侧上形成源漏图层014之后的具体结构的示意图，其中，该源漏图层014包括间隔形成的第一源极图案017、第二源极图案018和漏极图案019。
需要说明的是，在本公开的实施例中，每个反相器04可以设置在栅极走线02的用于与栅极驱动电路连接的一端，其中，该栅极驱动电路用于为每条栅极走线02提供驱动信号。因此，该栅极走线02的用于与栅极驱动电路连接的一端也即是该栅极走线02的输入端。通过将该反相器04设置在该栅极走线02的输入端，使得当由栅极驱动电路向栅极走线02输出驱动信号时，反相器04可以及时向对应的导电走线03输出反相信号。以这样的方式，可以保证对栅极走线02上传输的信号所产生的耦合噪音进行及时降噪。
需要说明的是，在由本公开的实施例提供的用于显示基板的上述制造方法中，各个步骤的先后顺序可以根据需要适当地调整，并且也可以根据实际情况相应地增加或减少某些步骤。在本公开揭露的技术范围内，本领域技术人员可以容易设想到各种经变化的方法，并且它们都应涵盖在本公开的保护范围之内。
综上所述，本公开的实施例提供了一种用于显示基板的制造方法。具体地，通过在衬底基板上设置多条导电走线和多条栅极走线，并且使每条导电走线上传输的信号与对应的一条栅极走线上传输的信号反相，抵消了由于栅极走线上传输的驱动信号而在显示面板上产生的耦合噪音。而且，该显示基板可以应用于触控显示面板。在这样的情况下，因为显示面板表面上的耦合噪音显著降低，所以可以有效地降低由于耦合噪音对触控显示面板所接收的触控信号的干扰，从而提高了 触控显示面板的触控精度。
本公开的实施例还提供了一种显示面板。该显示面板可以包括例如在图1中示出的显示基板，其中，该显示基板中可以包括例如在图3至图5任一个中所示的反相器。在本公开的实施例中，该显示面板可以为触控显示面板。示例性地，该显示面板可以是包括具有显示功能且可以触控的产品或部件的任何显示面板，诸如，液晶面板、手机、平板电脑、笔记本电脑、数码相机等。
本公开的实施例还提供了一种显示装置。该显示装置可以包括以上所述的显示面板，其中，该显示面板可以包括如图1所示的显示基板。该显示装置可以为具有显示功能的任何装置，诸如，手机、平板电脑、笔记本电脑、数码相机等。
以上所述仅为本公开的较佳实施例，并且不用以限制本公开。凡在本公开的精神和原则之内所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示基板，包括：
    衬底基板；
    设置在所述衬底基板上的多条栅极走线；
    设置在所述多条栅极走线远离所述衬底基板的一侧上的膜层结构；以及
    设置在所述膜层结构远离所述衬底基板的一侧上的多条导电走线，其中
    每条栅极走线在所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影至少部分地重叠，并且
    用于在每条导电走线上传输的信号与用于在对应的一条栅极走线上传输的信号反相。
  2. 根据权利要求1所述的显示基板，还包括：多个反相器，其中
    每个所述反相器的输入端与一条栅极走线连接，
    每个所述反相器的输出端与一条导电走线连接，并且
    与同一个反相器连接的栅极走线和导电走线在所述衬底基板上的正投影至少部分地重叠。
  3. 根据权利要求2所述的显示基板，其中
    每条栅极走线在所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影重合。
  4. 根据权利要求2所述的显示基板，其中，每个所述反相器包括N型晶体管和P型晶体管，其中
    所述N型晶体管的栅极和所述P型晶体管的栅极与一条栅极走线连接，
    所述N型晶体管的第二极和所述P型晶体管的第二极与一条导电走线连接，
    所述P型晶体管的第一极与第一电源线连接，并且
    所述N型晶体管的第一极与第二电源线连接，
    其中，所述第一电源线提供有第一电位的第一电源信号，并且所述第二电源线提供有第二电位的第二电源信号，所述第一电位相对于所述第二电位为高电位。
  5. 根据权利要求4所述的显示基板，其中
    所述N型晶体管和所述P型晶体管均为薄膜晶体管。
  6. 根据权利要求5所述的显示基板，其中，每个所述反相器包括：依次设置在所述衬底基板上的栅极图层、栅绝缘层、有源层和源漏图层，其中
    所述栅极图层配置为充当所述N型晶体管和所述P型晶体管的栅极，
    所述有源层包括间隔设置的N型半导体图案和P型半导体图案，
    所述源漏图层包括间隔设置的第一源极图案、第二源极图案和漏极图案，其中，所述第一源极图案配置为充当所述N型晶体管的第一极，所述第二源极图案配置为充当所述P型晶体管的第一极，并且所述漏极图案配置为充当所述N型晶体管和所述P型晶体管的第二极，以及
    所述栅极图层与一条栅极走线电连接，所述第一源极图案与所述第二电源线电连接，所述第二源极图案与所述第一电源线电连接，并且所述漏极图案与一条导电走线电连接。
  7. 根据权利要求6所述的显示基板，其中
    所述第一源极图案在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，
    所述第二源极图案在所述衬底基板上的正投影与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠，
    所述漏极图案在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠，以及
    所述栅极图层在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。
  8. 根据权利要求2至7中任一所述的显示基板，其中，
    每个所述反相器设置在对应的一条栅极走线的用于与栅极驱动电路连接的一端处。
  9. 根据权利要求1至7中任一项所述的显示基板，其中
    所述膜层结构包括多个驱动薄膜晶体管。
  10. 根据权利要求1所述的显示基板，还包括：
    用于所述多条导电走线的驱动电路，所述驱动电路配置为使得在每条导电走线上传输与在对应的一条栅极走线上传输的信号反相的信号。
  11. 一种用于显示基板的制造方法，包括：
    在衬底基板上形成多条栅极走线；
    在所述多条栅极走线远离所述衬底基板的一侧上形成膜层结构；以及
    在所述膜层结构远离所述衬底基板的一侧上形成多条导电走线，其中，每条栅极走线在所述衬底基板上的正投影与对应的一条导电走线在所述衬底基板上的正投影至少部分地重叠，并且
    用于在每条导电走线上传输的信号与用于在对应的一条栅极走线上传输的信号反相。
  12. 根据权利要求11所述的制造方法，还包括：
    在所述衬底基板上形成多个反相器，其中
    每个所述反相器的输入端与一条栅极走线连接，
    每个所述反相器的输出端与一条导电走线连接，并且
    与同一个反相器连接的栅极走线和导电走线在所述衬底基板上的正投影至少部分地重叠。
  13. 根据权利要求11所述的制造方法，其中，在所述膜层结构远离所述衬底基板的一侧上形成多条导电走线的步骤包括：
    采用用于形成所述多条栅极走线的掩膜板，在所述膜层结构远离所述衬底基板的一侧上形成所述多条导电走线。
  14. 根据权利要求12所述的制造方法，其中，每个所述反相器包括N型晶体管和P型晶体管，并且在所述衬底基板上形成多个反相器的步骤包括：
    在所述衬底基板上形成多组晶体管，每组晶体管包括一个N型晶体管和一个P型晶体管，其中
    每组晶体管中的N型晶体管的栅极和P型晶体管的栅极与一条栅极走线连接，
    每组晶体管中的N型晶体管的第二极和P型晶体管的第二极与一条导电走线连接，
    每组晶体管中的P型晶体管的第一极与第一电源线连接，并且
    每组晶体管中的N型晶体管的第一极与第二电源线连接，
    其中，所述第一电源线提供有第一电位的第一电源信号，并且所述二电源线提供有第二电位的第二电源信号，所述第一电位相对于所述第二电位为高电位。
  15. 根据权利要求14所述的制造方法，其中，所述N型晶体管和所述P型晶体管均为薄膜晶体管，并且在所述衬底基板上形成多组晶体管的步骤包括：
    在形成所述驱动薄膜晶体管的过程中，同步形成所述多组晶体管。
  16. 根据权利要求15所述的制造方法，其中，通过以下过程形成每一组晶体管：
    在所述衬底基板上形成栅极图层，使得所述栅极图层与一条栅极走线电连接并且充当所述N型晶体管和所述P型晶体管的栅极；
    在所述栅极图层远离所述衬底基板的一侧上依次形成栅绝缘层和有源层，所述有源层包括间隔形成的N型半导体图案和P型半导体图案；以及
    在所述有源层远离所述衬底基板的一侧上形成源漏图层，所述源漏图层包括间隔形成的第一源极图案、第二源极图案和漏极图案，
    其中，所述第一源极图案与所述第二电源线电连接，所述第二源极图案与所述第一电源线电连接，并且所述漏极图案与一条导电走线电连接，
    其中，所述第一源极图案形成为充当所述N型晶体管的第一极，所述第二源极图案形成为充当所述P型晶体管的第一极，并且所述漏极图案形成为充当所述N型晶体管和所述P型晶体管的第二极。
  17. 根据权利要求16所述的制造方法，其中
    所述第一源极图案形成为在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，
    所述第二源极图案形成为在所述衬底基板上的正投影与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠，
    所述漏极图案形成为在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠，以及
    所述栅极图层形成为在所述衬底基板上的正投影与所述N型半导体图案在所述衬底基板上的正投影至少部分地重叠，并且与所述P型半导体图案在所述衬底基板上的正投影至少部分地重叠。
  18. 根据权利要求11所述的制造方法，还包括：
    提供用于所述多条导电走线的驱动电路，使得在每条导电走线上传输与在对应的一条栅极走线上传输的信号反相的信号。
  19. 一种显示面板，包括：
    根据权利要求1至10中任一所述的显示基板。
  20. 一种显示装置，包括：
    如权利要求19所述的显示面板。
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