WO2019037185A1 - 显示面板和显示面板的制备方法 - Google Patents

显示面板和显示面板的制备方法 Download PDF

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Publication number
WO2019037185A1
WO2019037185A1 PCT/CN2017/102588 CN2017102588W WO2019037185A1 WO 2019037185 A1 WO2019037185 A1 WO 2019037185A1 CN 2017102588 W CN2017102588 W CN 2017102588W WO 2019037185 A1 WO2019037185 A1 WO 2019037185A1
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Prior art keywords
display panel
insulating layer
sub
thickness
electrode
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PCT/CN2017/102588
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English (en)
French (fr)
Inventor
何怀亮
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HKC Co Ltd
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HKC Co Ltd
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Priority to US16/640,953 priority Critical patent/US11276358B2/en
Publication of WO2019037185A1 publication Critical patent/WO2019037185A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display panel and a method for preparing the display panel.
  • the overall load of the display panel is related to its parasitic capacitance.
  • the parasitic capacitance includes the capacitance generated between the data line and the scan line of the display panel. By increasing the thickness of the insulating layer between the data line and the scan line, the parasitic capacitance can be reduced.
  • the gate dielectric layer in the display panel driving transistor is integrally formed with the insulating layer in a one-step process, and the increase in the thickness of the insulating layer simultaneously leads to an increase in the thickness of the gate dielectric layer, so that the driving The performance of the transistor is degraded, resulting in a weakened performance of the display panel.
  • the main purpose of the present application is to provide a display panel, which aims to solve the problem that the thickness of the insulating layer is increased to cause an increase in the thickness of the gate dielectric layer, and the performance of the display panel is improved.
  • the display panel of the present application includes a plurality of sub-pixels disposed on a substrate of the display panel, the sub-pixels including a driving transistor, a storage capacitor, a first insulating layer, and a second insulating layer.
  • the driving transistor includes a gate dielectric layer; the storage capacitor includes a capacitor dielectric layer; the first insulating layer is disposed between the data line of the display panel and the scan line of the display panel; the second insulating layer is disposed on the Between the data line and the common line of the display panel; the gate dielectric layer, the first insulating layer, the capacitor dielectric layer, and the second insulating layer are integrally formed by a halftone mask or a gray mask process An insulating film having a thickness smaller than a thickness of the first insulating layer.
  • the thickness of the capacitive dielectric layer is less than the thickness of the second insulating layer.
  • the thickness of the first insulating layer is equal to the thickness of the second insulating layer.
  • the sub-pixel further includes a passivation film covering the driving transistor, the data line, the scan line, and the common line, and the passivation film includes a through hole, and a sub-pixel Pixel electrode Provided on the passivation film, the sub-pixel electrode is electrically connected to a drain electrode of the driving transistor through the through hole.
  • the material of the insulating film comprises at least one of silicon oxide, silicon nitride, aluminum oxide or cerium oxide.
  • a plurality of the sub-pixels are arranged in a rectangular array, at least one of the sub-pixels forms a pixel, and the sub-pixels of the same pixel are arranged in a longitudinal direction; and the plurality of the data lines extend in a longitudinal direction and laterally Arranging; a plurality of the scan lines extending in a lateral direction and longitudinally; the sub-pixels of the same pixel are connected to the same data line, and are respectively connected to a different scan line.
  • the present application further provides a method for preparing a display panel, which is used to prepare a display panel.
  • the display panel includes a plurality of sub-pixels disposed on a substrate of the display panel, the sub-pixels including a driving transistor, a storage capacitor, and a first insulation. a layer and a second insulating layer.
  • the driving transistor includes a gate dielectric layer; the storage capacitor includes a capacitor dielectric layer; the first insulating layer is disposed between the data line of the display panel and the scan line of the display panel; the second insulating layer is disposed on the Between the data line and the common line of the display panel; the gate dielectric layer, the first insulating layer, the capacitor dielectric layer, and the second insulating layer are integrally formed by a halftone mask or a gray mask process a thickness of the insulating film, the thickness of the gate dielectric layer is smaller than the thickness of the first insulating layer; the method for preparing the display panel comprises the steps of: depositing a first conductive pattern on the substrate of the display panel, the first conductive The pattern includes a gate electrode and a scan line; depositing an insulating film pattern on the first conductive pattern by a halftone mask or a gray scale mask process, the insulating film pattern including a gate dielectric layer and a first insulating layer, the gate a thickness of the dielectric layer is less than
  • the first conductive pattern further includes a second electrode and a common line;
  • the insulating film pattern further includes a capacitor dielectric layer and a second insulating layer, the capacitor dielectric layer having a thickness smaller than that of the second insulating layer
  • the method of manufacturing the display panel further includes the step of depositing a passivation film pattern on the second conductive pattern, the passivation film including a via hole; and a third conductive pattern on the passivation film pattern, the third conductive pattern including a first electrode and a sub-pixel electrode, the sub-pixel electrode being electrically connected to the drain electrode through the through hole .
  • the step of depositing an insulating film pattern on the first conductive pattern by a halftone mask or a gray scale mask process comprises: depositing an insulating film on the first conductive pattern; on the insulating film Depositing a photoresist; exposing the photoresist through a halftone mask or a gray scale mask; developing the photoresist to form a pattern corresponding to the insulating film pattern on the photoresist a photoresist pattern, wherein a portion of the photoresist pattern corresponding to the gate dielectric layer has a thickness smaller than a thickness of a portion of the photoresist pattern corresponding to the first insulating layer; and etching the light
  • the adhesive and the insulating film are engraved to form the insulating film pattern.
  • the step of etching the photoresist and the insulating film comprises: ashing a photoresist to remove a photoresist having a minimum thickness in the photoresist pattern; dry etching Etching the insulating film; and returning the ashing photoresist to remove a portion of the photoresist pattern having the smallest thickness in the photoresist pattern.
  • the display panel includes a plurality of sub-pixels disposed on the substrate of the display panel, and the sub-pixels include a driving transistor, a data line, a scan line, a sub-pixel electrode, a common line, a storage capacitor, a first insulating layer, and a first a second insulating layer
  • the driving transistor comprises a channel, a source electrode, a drain electrode, a gate dielectric layer and a gate electrode, wherein the source electrode and the drain electrode are respectively connected to the two ends of the channel, and the gate dielectric layer is disposed on the channel, the source electrode, the drain electrode and Between the gate electrodes, the gate electrode is insulated from the channel, the source electrode and the drain electrode, respectively;
  • the data line is electrically connected to the source electrode;
  • the scan line is electrically connected to the gate electrode;
  • the sub-pixel electrode is electrically connected to the drain electrode; the common line and the scan
  • the extension direction of the line is uniform, and the common line is insulated from the scan line; the
  • the gate electrode level of the driving transistor is changed by the level of the scanning line input, thereby controlling the opening and closing of the channel.
  • the display gray level of the sub-pixel is controlled by the level of the data line input to realize The display of the image.
  • the gate capacitance of the driving transistor and the parasitic capacitance formed between the data line and the scanning line are similar to the parallel plate capacitor. In the parallel plate capacitor, the size of the capacitor decreases as the distance between the two parallel plates increases. Therefore, as the gate dielectric layer is thinned, the gate capacitance is increased, and the gate electrode has better control effect on the driving transistor; and as the first insulating layer is thickened, the parasitic capacitance generated between the data line and the scanning line is reduced.
  • the gate dielectric layer and the first insulating layer are integrally insulated by a halftone mask or a gray mask process membrane.
  • a halftone mask or grayscale mask process a mask pattern corresponding to an insulating film pattern is formed on a halftone mask or a grayscale mask, a halftone mask or a different portion of a grayscale mask
  • the light transmittance is different, and an insulating film pattern having a different thickness is formed.
  • the gate dielectric layer and the first insulating layer having different thicknesses are integrally formed by a halftone mask or a grayscale mask process.
  • the thickness of the gate dielectric layer can be flexibly adjusted according to the performance requirements of the driving transistor, and does not affect the performance of the driving transistor, specifically, does not affect the on-state current of the driving transistor, and further Optimizing the thickness of the gate dielectric layer can further improve the response speed of the display panel, and improve the resolution of the data line level corresponding to the image gray scale, thereby improving the resolution of the display panel;
  • the thickness of the first insulating layer can be According to the requirement of the parasitic capacitance between the data line and the scan line, the parasitic capacitance between the data line and the scan line can be reduced by increasing the thickness of the first insulating layer, thereby reducing the overall load of the display panel, thereby improving the display panel. performance.
  • FIG. 1 is a schematic structural diagram of a sub-pixel in an embodiment of a display panel of the present application
  • Figure 2 is a side view of the sub-pixel in the direction of the arrow in Figure 1;
  • FIG. 3 is a schematic structural view of an embodiment of a display panel of the present application.
  • FIG. 4 is a schematic structural view of another embodiment of a display panel of the present application.
  • FIG. 5 is a schematic structural view of still another embodiment of a display panel of the present application.
  • FIG. 6 is a schematic flow chart of an embodiment of a method for preparing a display panel of the present application
  • FIG. 7 is a schematic flowchart of the refinement of step S200 in FIG. 6;
  • FIG. 8 is a schematic diagram of the refinement process of step S250 in FIG. 7.
  • the directional indication is only used to explain in a certain posture (as shown in the drawing)
  • first”, “second”, etc. in the embodiments of the present application, the description of "first”, “second”, etc. is used for descriptive purposes only, and is not to be construed as an Its relative importance or implicit indication of the number of technical features indicated.
  • features defining “first” and “second” may include at least one of the features, either explicitly or implicitly.
  • the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. Nor is it within the scope of protection required by this application.
  • the application proposes a display panel.
  • the display panel includes a plurality of sub-pixels disposed on the substrate of the display panel, the sub-pixels including the driving transistor 100, the data line 200, the scan line 300, and the sub-pixel electrode 500.
  • a common line 600 a storage capacitor 700, a first insulating layer 400, and a second insulating layer 800.
  • the driving transistor 100 includes a channel 110, a source electrode 120, a drain electrode 130, a gate dielectric layer 140, and a gate electrode 150, and a source electrode 120 and
  • the drain electrodes 130 are respectively connected to the two ends of the channel 110, and the gate dielectric layer 140 is disposed between the channel 110, the source electrode 120, the drain electrode 130 and the gate electrode 150, so that the gate electrode 150 and the channel 110 and the source electrode 120 are respectively
  • the drain electrode 130 is insulated; the data line 200 is electrically connected to the source electrode 120; the scan line 300 is electrically connected to the gate electrode 150; the sub-pixel electrode 500 is electrically connected to the drain electrode 130; the common line 600 is aligned with the extending direction of the scan line 300, and The common line 600 is insulated from the scan line 300.
  • the storage capacitor 700 includes a first electrode 710, a second electrode 720, and a capacitive dielectric layer 730.
  • the first electrode 710 is electrically connected to the sub-pixel electrode 500
  • the second electrode 720 is electrically connected to the common line 600.
  • capacitor Layer 730 disposed on the first electrode 710 and the second electrode 720, so that the first electrode 710 and second electrode 720 insulated; a second insulating layer 800 is provided between the data line 600 and the common line 200,
  • the first insulating layer 400 is disposed between the data line 200 and the scan line 300 to insulate the data line 200 from the scan line 300; the gate dielectric layer 140, the first insulating layer 400,
  • the capacitive dielectric layer 730 and the second insulating layer 800 integrally form an insulating film by a halftone mask or a gradation mask process, and the thickness of the gate dielectric layer 140 is smaller than the thickness of the first insulating layer 400.
  • the driving transistor 100 is configured to control the display gradation of the sub-pixel, wherein the scan line 300 is used to control the opening and closing of the driving transistor 100, and the level of the data line 200 corresponds to the image information.
  • the gate electrode level electrically connected to the scan line 300 is changed under the input level control of the data line 200, and when the gate electrode level control drive transistor channel 110 is turned on, the data line 200 connected to the source electrode 120 inputs image information to The transistor 100 is driven to control the display gradation of the sub-pixel to realize display of an image.
  • the source electrode 120 and the drain electrode 130 of the driving transistor may include more than one layer of conductive material, wherein a work function of the underlying conductive material in direct contact with the channel 110 matches a work function of the channel material to reduce contact resistance,
  • the performance of the driving transistor 100 is improved, and the conductive material of the upper layer may be selected from a conductive metal material to have a high electrical conductivity.
  • the performance of the driving transistor 100 is related to the thickness of the gate dielectric layer 140. The thinner the thickness, the larger the gate capacitance, the better the gate control capability, and the larger the on-state current of the driving transistor 100, so that the sub-pixel has a faster response speed and Better gray-scale resolution, reduced delay and distortion during display, and improved performance.
  • a first insulating layer 400 is disposed between the data line 200 and the scan line 300, and the first insulating layer 400 is disposed. At least at the intersection of the data line 200 and the scan line 300, of course, the distribution range of the first insulating layer 400 may also be larger than the intersection range of the data line 200 and the scan line 300.
  • a structure similar to a parallel plate capacitor is formed, and as the thickness of the first insulating layer 400 increases, the data line 200, the first insulating layer 400, and The capacitance capacity formed by the scan line 300 is reduced, so that the parasitic capacitance of the sub-pixel is reduced, the response speed of the sub-pixel is improved, and the overall load is reduced.
  • the gate dielectric layer 140 and the first insulating layer 400 integrally form an insulating film by a halftone mask or a gradation mask process.
  • a halftone mask or gray scale mask process a mask pattern corresponding to the insulating film pattern is formed on a halftone mask or a gray scale mask, and in the halftone mask, according to different patterns
  • different transmittances are formed at different positions according to the pattern, thereby forming photoresist patterns having different thicknesses in the photolithography process, and then forming thickness by etching or the like.
  • Different insulating film patterns In the present application, a halftone mask or a gray mask process is used.
  • the gate dielectric layer 140 and the first insulating layer 400 having different thicknesses are formed, and the insulating film is prevented from being deposited multiple times in order to form the gate dielectric layer 140 and the first insulating layer 400 having different thicknesses, thereby avoiding the possibility of causing multiple deposition processes.
  • a defect in the interface of the adjacent insulating film which may cause introduction of interface charges at the interface, affecting the display performance of the sub-pixel.
  • the thickness h1 of the gate dielectric layer 140 is smaller than the thickness h2 of the first insulating layer 400, on the one hand, the gate control requirement of the driving transistor 100 is satisfied, and on the other hand, the parasitic capacitance between the data line 200 and the scanning line 300 is reduced. The overall load of the display panel is reduced, thereby improving the performance of the display panel.
  • the display panel includes a plurality of sub-pixels disposed on the substrate of the display panel, and the sub-pixels include the driving transistor 100, the data line 200, the scan line 300, the sub-pixel electrode 500, the common line 600, the storage capacitor 700, and the first The insulating layer 400 and the second insulating layer 800, wherein the driving transistor 100 includes a channel 110, a source electrode 120, a drain electrode 130, a gate dielectric layer 140, and a gate electrode 150. The source electrode 120 and the drain electrode 130 are respectively connected to the channel 110.
  • the gate dielectric layer 140 is disposed between the channel 110, the source electrode 120, the drain electrode 130, and the gate electrode 150 to insulate the gate electrode 150 from the channel 110, the source electrode 120, and the drain electrode 130, respectively; Electrically connected to the source electrode 120; the scan line 300 is electrically connected to the gate electrode 150; the sub-pixel electrode 500 is electrically connected to the drain electrode 130; the common line 600 is aligned with the extending direction of the scan line 300, and the common line 600 is insulated from the scan line 300;
  • the storage capacitor 700 includes a first electrode 710, a second electrode 720, and a capacitor dielectric layer 730.
  • the first electrode 710 is electrically connected to the sub-pixel electrode 500
  • the second electrode 720 is electrically connected to the common line 600
  • the capacitor dielectric layer 730 is disposed at
  • the first electrode 710 and the second electrode 720 are insulated between the electrode 710 and the second electrode 720
  • the second insulating layer 800 is disposed between the data line 200 and the common line 600 to insulate the data line 200 from the common line 600.
  • the first insulating layer 400 is disposed between the data line 200 and the scan line 300 to insulate the data line 200 from the scan line 300.
  • the level of the gate electrode of the driving transistor 100 is changed by the level input by the scanning line 300, thereby controlling the opening and closing of the channel 110, and when the channel 110 is turned on, the level of the input through the data line 200 controls the display of the sub-pixel. Grayscale to achieve image display.
  • the gate capacitance of the driving transistor 100 and the parasitic capacitance formed between the data line 200 and the scanning line 300 are similar to those of a parallel plate capacitor. In the parallel plate capacitor, the size of the capacitor increases with the distance between the two parallel plates.
  • Gate dielectric layer 140, first insulating layer 400, capacitive dielectric layer 730, and The second insulating layer 800 integrally forms an insulating film by a halftone mask or a gradation mask process.
  • a mask pattern corresponding to the insulating film pattern is formed on a halftone mask or a gradation mask, thereby forming an insulating film pattern having a different thickness.
  • the gate dielectric layer 140 and the first insulating layer 400 having different thicknesses are integrally formed by a halftone mask or a grayscale mask process.
  • the driving transistor 100 is not affected.
  • the response speed of the display panel can be further improved, and the resolution of the data line level corresponding to the image gradation can be improved, thereby improving the resolution of the display panel;
  • the thickness of the first insulating layer 400 can be flexibly adjusted according to the requirement of the parasitic capacitance between the data line 200 and the scan line 300, and the parasitic capacitance between the data line 200 and the scan line 300 can be reduced by increasing the thickness of the first insulating layer. Reduce the overall load of the display panel to improve the performance of the display panel.
  • the thickness of the capacitor dielectric layer 730 is smaller than the thickness of the second insulating layer 800.
  • the driving transistor 100 is charged and discharged to the sub-pixel electrode 500 through the drain electrode 130.
  • the first substrate of the display panel where the sub-pixel electrode 500 is located and the second substrate of the display panel are filled with liquid crystal, and the sub-pixel electrode 500 is Under the action of the electric field between the common electrodes of the second substrate, the alignment direction of the liquid crystal is deflected, thereby controlling the display gradation of the sub-pixels to generate a display image.
  • the storage capacitor 700 is further included in the sub-pixel.
  • the storage capacitor 700 is disposed in parallel with the liquid crystal capacitor to maintain the electric field and maintain the deflection of the liquid crystal.
  • the display image is stable.
  • a storage capacitor may be formed between the sub-pixel electrode and a scan line not connected to the sub-pixel, or a common line may be separately provided so that a storage capacitor is formed between the sub-pixel electrode and the common line.
  • the first electrode 710 of the storage capacitor 700 is electrically connected to the sub-pixel electrode 500
  • the second electrode 720 is electrically connected to the common line 600
  • the capacitor dielectric layer 730 is disposed between the first electrode 710 and the second electrode 720.
  • the common line 600 may be disposed in parallel or approximately parallel with the scan line 300. To prevent conduction between the common line 600 and the data line 200 due to intersection, a line is provided between the common line 600 and the data line 200.
  • the second insulating layer 800 is disposed at least at the intersection of the common line 600 and the data line 200. Of course, the distribution range of the second insulating layer 800 may also be greater than the intersecting range of the common line 600 and the data line 200.
  • a structure similar to a parallel plate capacitor is formed, and as the thickness of the second insulating layer 800 increases, the common line 600, the second insulating layer 800, and The capacitance value formed by the data line 200 is reduced, so that the parasitic capacitance of the sub-pixel is reduced, the response speed of the sub-pixel is improved, and the overall load is reduced.
  • the gate dielectric layer 140, the first insulating layer 400, the capacitor dielectric layer 730, and the second insulating layer 800 integrally form an insulating film by a halftone mask or a gradation mask process.
  • a halftone mask or grayscale mask process a mask pattern corresponding to the insulating film pattern is formed on a halftone mask or a grayscale mask, in a halftone mask or a grayscale mask.
  • Membrane pattern a mask pattern corresponding to the insulating film pattern is formed on a halftone mask or a grayscale mask, in a halftone mask or a grayscale mask.
  • the gate dielectric layer 140, the first insulating layer 400, the capacitor dielectric layer 730, and the second insulating layer 800 having different thicknesses are integrally formed by a halftone mask or a grayscale mask process, thereby avoiding multiple depositions and causing an increase in process steps, and production
  • the cost is increased, and interface defects that may be caused during multiple deposition processes are avoided, thereby avoiding the influence of interface charge on the display performance of the sub-pixels.
  • the thickness h3 of the capacitor dielectric layer 730 is smaller than the thickness h4 of the second insulating layer 800.
  • the thickness h2 of the first insulating layer 400 is equal to the thickness h4 of the second insulating layer 800. Since the main functions of the first insulating layer 400 and the second insulating layer 800 are both insulating and the thickness is equal, the process can be reduced. The cost of making halftone masks or grayscale masks in the process, which in turn reduces production costs.
  • the thickness h1 of the gate dielectric layer 140 is related to the performance requirement of the driving transistor 100.
  • the thickness h3 of the capacitor dielectric layer is related to the capacitance requirement of the storage capacitor 700. Therefore, the thicknesses h1 and h3 may be different from the thicknesses h2 and h4.
  • the sub-pixel further includes a passivation film 900 covering the driving transistor 100, the data line 200, the scan line 300, and the common line 600 to avoid oxygen and water in the air. Vapor or the like affects the performance of the sub-pixels, particularly the performance of the driving transistor 100 and the respective wires in the sub-pixels.
  • the passivation film 900 includes a via hole, the sub-pixel electrode 500 is disposed on the passivation film 900, and the sub-pixel electrode 500 is electrically connected to the drain electrode 130 through the through hole, and is disposed by lamination.
  • the aperture ratio of the sub-pixel is increased, thereby reducing the required backlight power, resulting in a reduction in power consumption of the display panel.
  • the material of the insulating film includes at least one of silicon oxide, silicon nitride, aluminum oxide, or cerium oxide.
  • silicon oxide can be directly produced on the silicon channel material by a process such as thermal oxidation, and has a simple and reliable process; and the silicon nitride, aluminum oxide or yttria material has a higher dielectric constant than silicon oxide, thereby driving Transistors and storage capacitors have better electrical performance.
  • the process forms a gate dielectric layer and a dielectric dielectric layer comprising only silicon nitride, aluminum oxide or tantalum oxide to improve the performance of the drive transistor and the storage capacitor while forming a first layer comprising silicon nitride, aluminum oxide or tantalum oxide and silicon oxide
  • the insulating layer and the second insulating layer reduce the material cost of the insulating film while improving the insulating properties of the first insulating layer and the second insulating layer.
  • the display panel has a variety of architectural approaches.
  • the plurality of sub-pixels are arranged in a rectangular array, and at least one sub-pixel forms a pixel.
  • one pixel includes three sub-pixels that respectively control three color light displays of red, green, and blue.
  • one pixel may also include four sub-pixels, and the sub-pixels have various arrangements.
  • the data lines of the display panel extend in the longitudinal direction and are arranged in the horizontal direction, and the scanning lines are arranged in the lateral direction and in the longitudinal direction.
  • FIG. 3 it is a display panel of a conventional architecture, in which three sub-pixels of the same pixel are arranged in a lateral direction; a plurality of data lines 200 extend in a longitudinal direction and are laterally arranged; and a plurality of scanning lines 300 extends in the lateral direction and is longitudinally arranged; the sub-pixels of the same pixel are connected to the same scan line 300 and are respectively connected to a different data line 200.
  • FIG. 4 is a display panel of a half source driving architecture, in which two sub-pixels are grouped, and two sub-pixels in a group are connected to the same a scan line 300 is connected to a different data line 200, and sub-pixels in the adjacent group are respectively connected to a different scan line 300, and adjacent sub-pixels in the adjacent group share a data line 200.
  • the half-source drive architecture has twice the scanning frequency of the traditional architecture.
  • a display panel of a triple gate structure three sub-pixels of the same pixel are arranged in a longitudinal direction; sub-pixels of the same pixel are connected to the same data line. 200, and respectively connected to a different scan line 300.
  • the number of costly data lines 200 is reduced, production costs are reduced, and compared to conventional racks.
  • the display panel has a scanning frequency that is three times that of the traditional architecture.
  • the overall load of the display panel is also greatly increased, so it is necessary to provide insulating films with different thicknesses to meet the corresponding performance requirements.
  • the present application also provides a method for preparing a display panel for preparing the above display panel. As shown in FIG. 6, the method for preparing the display panel includes the following steps:
  • Step S100 depositing a first conductive pattern on the substrate of the display panel
  • the first conductive pattern includes a gate electrode 150 and a scan line 300, and the gate electrode 150 is electrically connected to the scan line 300 to control the opening and closing of the driving transistor 100 by the level of the scan line 300.
  • Step S200 depositing an insulating film pattern on the first conductive pattern by a halftone mask or a gray mask process
  • the insulating film pattern includes a gate dielectric layer 140 and a first insulating layer 400.
  • the thickness of the gate dielectric layer 140 is smaller than the thickness of the first insulating layer 400.
  • the gate control performance of the driving transistor 100 is ensured, and the driving state of the driving transistor 100 is improved.
  • the current is used to increase the corresponding speed and improve the resolution of the display gray scale; on the other hand, the parasitic capacitance generated by the data line 200 and the scan line 300 is lowered, and the overall load of the display panel is reduced.
  • Step S300 depositing a second conductive pattern on the insulating film pattern
  • the second conductive pattern includes the channel 110, the source electrode 120, the drain electrode 130, and the data line 200. Since the materials of the channel 110, the source electrode 120, the drain electrode 130, and the data line 200 may be different, step S300 may include multiple The sub-process is to form the channel 110, the source electrode 120, the drain electrode 130, and the data line 200, respectively.
  • the mask pattern corresponding to the corresponding material layer pattern is first transferred into a photoresist pattern by photolithography, and then subjected to a sacrificial layer etching process or a plating stripping method. The process transfers the photoresist pattern to a corresponding material layer pattern.
  • the first conductive pattern further includes a second electrode 720 and a common line 600; the second electrode 720 and the common line 600 are simultaneously deposited in step S100; the insulating film pattern further includes a capacitor dielectric layer 730 and a second insulating layer 800, and The thickness of the capacitive dielectric layer 730 is smaller than the thickness of the second insulating layer 800; the capacitive dielectric layer 730 and the second insulating layer 800 are integrally formed by a halftone mask or a grayscale mask process in step S200 to reduce process steps and reduce production. cost.
  • the method for preparing the display panel further includes the following steps:
  • Step S400 depositing a pattern of the passivation film 900 on the second conductive pattern
  • the passivation film 900 includes a through hole.
  • the passivation film 900 is used to reduce the influence of oxygen, water vapor, and the like in the air on the performance of the driving transistor 100 and the wires, thereby improving the stability of the display panel and extending the use of the display panel. life.
  • Step S500 depositing a third conductive pattern on the passivation film 900 pattern.
  • the third conductive pattern includes a first electrode 710 and a sub-pixel electrode 500.
  • the sub-pixel electrode 500 is electrically connected to the drain electrode 130 through the through hole, and on the other hand, the sub-pixel electrode 500 is insulated from other portions of the sub-pixel.
  • the aperture ratio of the sub-pixel is increased to avoid occupying too much area of the circuit, thereby reducing the brightness of the required backlight, thereby reducing the power consumption of the display panel.
  • step S200 includes:
  • Step S210 depositing an insulating film on the first conductive pattern
  • the deposition of the insulating film can be achieved by processes such as thermal oxidation, sputtering, evaporation, epitaxy, etc.
  • the insulating films of different materials correspond to different deposition processes.
  • Step S220 depositing a photoresist on the insulating film
  • the photoresist can be deposited on the insulating film by a process such as spin coating curing, and the interface can be processed correspondingly before and after the photoresist deposition to improve the deposition quality.
  • Step S230 exposing the photoresist through a halftone mask or a gray mask
  • a halftone mask or a grayscale mask is a mask having a plurality of transmittances, which are exposed to a photoresist by a halftone mask or a grayscale mask, and the light source may be an ultraviolet light source or an X-ray light source. Etc., transfer the mask pattern to the photoresist. Due to the difference in light transmittance, the thickness of the exposed photoresist is large in the portion where the light transmittance is high, and the thickness of the exposed photoresist is small in the portion where the light transmittance is low, or even substantially no photoresist. Was exposed.
  • Step S240 developing the photoresist to form a photoresist pattern corresponding to the insulating film pattern on the photoresist;
  • the mask pattern is transferred to a photoresist pattern, and the photoresist pattern corresponds to the insulating film pattern.
  • the thickness of a portion of the photoresist pattern corresponding to the gate dielectric layer 140 is smaller than the thickness of a portion of the photoresist pattern corresponding to the first insulating layer 400.
  • Step S250 etching the photoresist and the insulating film to form an insulating film pattern.
  • the photoresist is over the insulating film and has a certain anti-etching property. As the etching process progresses, the thickness of the photoresist is simultaneously thinned, and the insulating film is further etched in a region where part of the photoresist is completely removed. In the area where some of the photoresist remains, the insulating film is retained, and finally the thickness is different.
  • the insulating film pattern meets the performance requirements of the display panel.
  • step S250 includes:
  • Step S251 ashing photoresist (PR ashing) to remove a portion of the photoresist pattern having the smallest thickness in the photoresist pattern;
  • the ashing photoresist is a process of etching the photoresist, and the thickness of the photoresist is uniformly thinned in the above process, wherein the thinnest part of the photoresist pattern corresponds to the thinnest part of the insulating film pattern in the finished product,
  • the photoresist is first completely etched away.
  • Step S252 dry etching the insulating film
  • the insulating film is etched by dry etching to form an insulating film pattern corresponding to the photoresist pattern.
  • the photoresist is ashed to the portion of the current minimum thickness, that is, the photoresist having the second smallest thickness of the photoresist is removed.
  • the portion of the insulating film having the smallest thickness is also simultaneously etched, and after the etching is completed, two different thicknesses are formed on the insulating film. Corresponding pattern. The above steps are repeated until all the insulating film patterns are completed.

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Abstract

一种显示面板和显示面板的制备方法，其中，显示面板包括多个子像素设置于显示面板的基板上，子像素包括驱动晶体管（100），驱动晶体管（100）包括栅介质层（140）；存储电容（700），存储电容（700）包括电容介质层（730）；第一绝缘层（400），第一绝缘层（400）设于显示面板的数据线（200）与显示面板的扫描线（300）之间；第二绝缘层（800），第二绝缘层（800）设于数据线（200）与显示面板的公共线（600）之间；栅介质层（140）、第一绝缘层（400）、电容介质层（730）和第二绝缘层（800）通过半色调掩膜或灰度掩膜工艺一体形成不同厚度的绝缘膜，栅介质层（140）的厚度小于第一绝缘层（400）的厚度。

Description

显示面板和显示面板的制备方法 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板和显示面板的制备方法。
背景技术
随着显示面板分辨率和扫描频率的提高，其整体负载也不断增大，进而导致显示面板的功耗增大、使用寿命降低。显示面板的整体负载与其寄生电容相关，寄生电容包括显示面板的数据线和扫描线之间产生的电容，通过增大数据线和扫描线之间的绝缘层厚度，可以减小寄生电容。然而，为了节约显示面板的工艺流程，显示面板驱动晶体管中的栅介质层是与绝缘层在一步工艺中一体形成的，绝缘层厚度的增大同时导致了栅介质层厚度的增大，使得驱动晶体管的性能降低，导致显示面板的性能减弱。
发明内容
本申请的主要目的是提出一种显示面板，旨在解决上述绝缘层厚度增加导致栅介质层厚度增大的问题，改善显示面板的性能。
为实现上述目的，本申请提出的显示面板包括多个子像素设置于所述显示面板的基板上，所述子像素包括驱动晶体管、存储电容、第一绝缘层以及第二绝缘层。所述驱动晶体管包括栅介质层；所述存储电容包括电容介质层；所述第一绝缘层设于显示面板的数据线与显示面板的扫描线之间；所述第二绝缘层设于所述数据线与显示面板的公共线之间；所述栅介质层、所述第一绝缘层、所述电容介质层和所述第二绝缘层通过半色调掩膜或灰度掩膜工艺一体形成不同厚度的绝缘膜，所述栅介质层的厚度小于所述第一绝缘层的厚度。
可选地，所述电容介质层的厚度小于所述第二绝缘层的厚度。
可选地，所述第一绝缘层的厚度等于所述第二绝缘层的厚度。
可选地，所述子像素还包括钝化膜，所述钝化膜覆盖所述驱动晶体管、所述数据线、所述扫描线和所述公共线，所述钝化膜包括通孔，子像素电极 设于所述钝化膜上，所述子像素电极通过所述通孔与所述驱动晶体管的漏电极电连接。
可选地，所述绝缘膜的材料包括氧化硅、氮化硅、氧化铝或氧化铪中的至少一种。
可选地，多个所述子像素呈矩形阵列状排列，至少一所述子像素形成一像素，同一所述像素的所述子像素沿纵向排列；多条所述数据线沿纵向延伸、横向排列；多条所述扫描线沿横向延伸、纵向排列；同一所述像素的所述子像素连接于同一所述数据线，并分别与一不同的所述扫描线连接。
本申请进一步提出一种显示面板的制备方法，用以制备显示面板，所述显示面板包括多个子像素设置于所述显示面板的基板上，所述子像素包括驱动晶体管、存储电容、第一绝缘层以及第二绝缘层。所述驱动晶体管包括栅介质层；所述存储电容包括电容介质层；所述第一绝缘层设于显示面板的数据线与显示面板的扫描线之间；所述第二绝缘层设于所述数据线与显示面板的公共线之间；所述栅介质层、所述第一绝缘层、所述电容介质层和所述第二绝缘层通过半色调掩膜或灰度掩膜工艺一体形成不同厚度的绝缘膜，所述栅介质层的厚度小于所述第一绝缘层的厚度；所述显示面板的制备方法包括以下步骤：在显示面板的基板上沉积第一导电图案，所述第一导电图案包括栅电极和扫描线；在所述第一导电图案上通过半色调掩膜或灰度掩膜工艺沉积绝缘膜图案，所述绝缘膜图案包括栅介质层和第一绝缘层，所述栅介质层的厚度小于所述第一绝缘层的厚度；以及在所述绝缘膜图案上沉积第二导电图案，所述第二导电图案包括沟道、源电极、漏电极和数据线。
可选地，所述第一导电图案还包括第二电极与公共线；所述绝缘膜图案还包括电容介质层和第二绝缘层，所述电容介质层的厚度小于所述第二绝缘层的厚度；在所述绝缘膜图案上沉积第二导电图案的步骤之后，所述显示面板的制备方法还包括以下步骤：在所述第二导电图案上沉积钝化膜图案，所述钝化膜包括通孔；以及在所述钝化膜图案上沉积第三导电图案，所述第三导电图案包括第一电极与子像素电极，所述子像素电极通过所述通孔与所述漏电极电连接。
可选地，在所述第一导电图案上通过半色调掩膜或灰度掩膜工艺沉积绝缘膜图案的步骤包括：在所述第一导电图案上沉积绝缘膜；在所述绝缘膜上 沉积光刻胶；通过半色调掩膜版或灰度掩膜版对所述光刻胶曝光；对所述光刻胶显影，以在所述光刻胶上形成与所述绝缘膜图案对应的光刻胶图案，其中，与所述栅介质层对应的部分所述光刻胶图案的厚度小于与所述第一绝缘层对应的部分所述光刻胶图案的厚度；以及刻蚀所述光刻胶和所述绝缘膜，以形成所述绝缘膜图案。
可选地，所述刻蚀所述光刻胶和所述绝缘膜的步骤包括：灰化光刻胶，以清除所述光刻胶图案中当前厚度最小的部分的光刻胶；干法刻蚀所述绝缘膜；以及返回所述灰化光刻胶，以清除所述光刻胶图案中当前厚度最小的部分的光刻胶的步骤。
本申请技术方案中，显示面板包括多个子像素设置于所述显示面板的基板上，子像素包括驱动晶体管、数据线、扫描线、子像素电极、公共线、存储电容、第一绝缘层以及第二绝缘层，驱动晶体管包括沟道、源电极、漏电极、栅介质层以及栅电极，源电极和漏电极分别连接于沟道两端，栅介质层设于沟道、源电极、漏电极与栅电极之间，以使栅电极分别和沟道、源电极及漏电极绝缘；数据线与源电极电连接；扫描线与栅电极电连接；子像素电极与漏电极电连接；公共线与扫描线的延伸方向一致，且公共线与扫描线绝缘；存储电容包括第一电极、第二电极以及电容介质层，第一电极与子像素电极电连接，第二电极与公共线电连接，电容介质层设于第一电极与第二电极之间，以使第一电极和第二电极绝缘；第一绝缘层设于数据线与扫描线之间，以使数据线和扫描线绝缘；第二绝缘层设于数据线与公共线之间，以使数据线和公共线绝缘；栅介质层、第一绝缘层、电容介质层和第二绝缘层通过半色调掩膜或灰度掩膜工艺一体形成绝缘膜，栅介质层的厚度小于第一绝缘层的厚度。通过扫描线输入的电平改变驱动晶体管的栅电极电平，从而控制沟道的打开和关断，当沟道打开时，通过数据线输入的电平控制该子像素的显示灰度，以实现图像的显示。驱动晶体管的栅电容，以及数据线与扫描线之间形成的寄生电容的结构近似于平行板电容器，在平行板电容器中，电容的大小随着两平行板之间距离的增大而减小，因此，随着栅介质层的减薄，栅电容增大，栅电极对驱动晶体管的控制效果更好；而随着第一绝缘层的增厚，数据线与扫描线之间产生的寄生电容减小，从而降低了显示面板的整体负载。栅介质层和第一绝缘层通过半色调掩膜或灰度掩膜工艺一体形成绝缘 膜。在半色调掩膜或灰度掩膜工艺中，与绝缘膜图案对应的掩膜图案形成在半色调掩膜版或灰度掩膜版上，半色调掩膜版或灰度掩膜版不同部分的透光率不同，进而形成厚度不同的绝缘膜图案。本申请中，通过半色调掩膜或灰度掩膜工艺一体形成厚度不同的栅介质层和第一绝缘层，第一，避免了多次沉积绝缘膜导致的工艺复杂度的提高，降低了生产成本，且避免了可能产生的界面缺陷；第二，栅介质层的厚度可根据驱动晶体管的性能要求灵活调整，不影响驱动晶体管的性能，具体的，不影响驱动晶体管的开态电流，通过进一步优化栅介质层厚度，还能够进一步提高显示面板的响应速度，以及提高与图像灰度相应的数据线电平的分辨率，从而提高显示面板的分辨率；第三，第一绝缘层的厚度可根据数据线与扫描线之间的寄生电容的要求灵活调整，通过增大第一绝缘层厚度能够减小数据线与扫描线之间的寄生电容，降低显示面板的整体负载，从而提高显示面板的性能。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示面板一实施例中子像素的结构示意图；
图2为图1中沿虚线箭头方向的子像素侧视结构示意图；
图3为本申请显示面板一实施例的结构示意图；
图4为本申请显示面板另一实施例的结构示意图；
图5为本申请显示面板又一实施例的结构示意图；
图6为本申请显示面板的制备方法一实施例的流程示意图；
图7为图6中步骤S200的细化流程示意图；以及
图8是图7中步骤S250的细化流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示(诸如上、下、左、右、前、后……)，则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种显示面板。
在本申请实施例中，如图1和图2所示，显示面板包括多个子像素设置于显示面板的基板上，该子像素包括驱动晶体管100、数据线200、扫描线300、子像素电极500、公共线600、存储电容700、第一绝缘层400和第二绝缘层800，驱动晶体管100包括沟道110、源电极120、漏电极130、栅介质层140以及栅电极150，源电极120和漏电极130分别连接于沟道110两端，栅介质层140设于沟道110、源电极120、漏电极130与栅电极150之间，以使栅电极150分别和沟道110、源电极120、漏电极130绝缘；数据线200与源电极120电连接；扫描线300与栅电极150电连接；子像素电极500与漏电极130电连接；公共线600与扫描线300的延伸方向一致，且公共线600与扫描线300绝缘；存储电容700包括第一电极710、第二电极720以及电容介质层730，第一电极710与子像素电极500电连接，第二电极720与公共线600电连接，电容介质层730设于第一电极710与第二电极720之间，以使第一电极710和第二电极720绝缘；第二绝缘层800设于数据线200与公共线600之间， 以使数据线200和公共线600绝缘；第一绝缘层400设于数据线200与扫描线300之间，以使数据线200和扫描线300绝缘；栅介质层140、第一绝缘层400、电容介质层730和第二绝缘层800通过半色调掩膜或灰度掩膜工艺一体形成绝缘膜，栅介质层140的厚度小于第一绝缘层400的厚度。
具体的，驱动晶体管100用以控制子像素的显示灰度，其中，扫描线300用以控制驱动晶体管100的打开和关断，而数据线200的电平与图像信息相对应。与扫描线300电连接的栅电极电平在数据线200的输入电平控制下改变，当栅电极电平控制驱动晶体管沟道110打开时，连接于源电极120的数据线200输入图像信息至驱动晶体管100，以控制该子像素的显示灰度，进而实现图像的显示。驱动晶体管的源电极120和漏电极130可以包括一层以上的导电材料，其中，与沟道110直接接触的下层导电材料的功函数与沟道材料的功函数相匹配，以减小接触电阻，提高驱动晶体管100的性能，而上层的导电材料可选择导电的金属材料，以具有较高的电导率。驱动晶体管100的性能与栅介质层140的厚度有关，厚度越薄，栅电容越大，栅控能力越好，驱动晶体管100的开态电流越大，从而使得子像素具有更快的响应速度和更好的灰阶分辨率，显示过程中的延迟与失真现象减弱，性能提高。
由于数据线200和扫描线300在空间分布上存在交叉，为了避免数据线200和扫描线300导通，在数据线200与扫描线300之间设有第一绝缘层400，第一绝缘层400至少分布在数据线200和扫描线300的交叉处，当然，第一绝缘层400的分布范围也可以大于数据线200与扫描线300的交叉范围。在数据线200、第一绝缘层400和扫描线300相层叠的部分，形成近似于平行板电容器的结构，随着第一绝缘层400厚度的增大，数据线200、第一绝缘层400和扫描线300所形成的电容容值减小，从而使得子像素的寄生电容减小，提高了子像素的响应速度，减小了整体负载。
栅介质层140和第一绝缘层400通过半色调掩膜或灰度掩膜工艺一体形成绝缘膜。在半色调掩膜或灰度掩膜工艺中，与绝缘膜图案对应的掩膜图案形成在半色调掩膜版或灰度掩膜版上，在半色调掩膜版中，根据不同的图案形成透光率不同的部分，在灰度掩膜版中，根据图案在不同位置形成变化的透光率，从而在光刻过程中形成厚度不同的光刻胶图案，再通过刻蚀等工艺形成厚度不同的绝缘膜图案。本申请中，通过半色调掩膜或灰度掩膜工艺一 体形成厚度不同的栅介质层140和第一绝缘层400，避免为了形成厚度不同的栅介质层140和第一绝缘层400而多次沉积绝缘膜，进而避免了在多次沉积过程中可能导致的相邻层绝缘膜介面上的缺陷，这种缺陷可能导致在界面上引入界面电荷，影响子像素的显示性能。并且，栅介质层140的厚度h1小于第一绝缘层400的厚度h2，一方面满足了驱动晶体管100的栅控要求，另一方面减小了数据线200与扫描线300之间的寄生电容，降低了显示面板的整体负载，从而提高了显示面板的性能。
本申请技术方案中，显示面板包括多个子像素设置于显示面板的基板上，子像素包括驱动晶体管100、数据线200、扫描线300、子像素电极500、公共线600、存储电容700、第一绝缘层400和第二绝缘层800，其中，驱动晶体管100包括沟道110、源电极120、漏电极130、栅介质层140以及栅电极150，源电极120和漏电极130分别连接于沟道110两端，栅介质层140设于沟道110、源电极120、漏电极130与栅电极150之间，以使栅电极150分别和沟道110、源电极120、漏电极130绝缘；数据线200与源电极120电连接；扫描线300与栅电极150电连接；子像素电极500与漏电极130电连接；公共线600与扫描线300的延伸方向一致，且公共线600与扫描线300绝缘；存储电容700包括第一电极710、第二电极720以及电容介质层730，第一电极710与子像素电极500电连接，第二电极720与公共线600电连接，电容介质层730设于第一电极710与第二电极720之间，以使第一电极710和第二电极720绝缘；第二绝缘层800设于数据线200与公共线600之间，以使数据线200和公共线600绝缘；第一绝缘层400设于数据线200与扫描线300之间，以使数据线200和扫描线300绝缘。通过扫描线300输入的电平改变驱动晶体管100的栅电极电平，从而控制沟道110的打开和关断，当沟道110打开时，通过数据线200输入的电平控制该子像素的显示灰度，以实现图像的显示。驱动晶体管100的栅电容，以及数据线200与扫描线300之间形成的寄生电容的结构近似于平行板电容器，在平行板电容器中，电容的大小随着两平行板之间距离的增大而减小，因此，随着栅介质层140的减薄，栅电容增大，栅电极150对驱动晶体管100的控制效果更好；而随着第一绝缘层400的增厚，数据线200与扫描线300之间产生的寄生电容减小，从而降低了显示面板的整体负载。栅介质层140、第一绝缘层400、电容介质层730和第 二绝缘层800通过半色调掩膜或灰度掩膜工艺一体形成绝缘膜。在半色调掩膜或灰度掩膜工艺中，与绝缘膜图案对应的掩膜图案形成在半色调掩膜版或灰度掩膜版上，进而形成厚度不同的绝缘膜图案。本申请中，通过半色调掩膜或灰度掩膜工艺一体形成厚度不同的栅介质层140和第一绝缘层400，第一，避免了多次沉积绝缘膜导致的工艺复杂度的提高，降低了生产成本，且避免了可能产生的界面缺陷；第二，栅介质层140的厚度可根据驱动晶体管100的性能要求灵活调整，不影响驱动晶体管100的性能，具体的，不影响驱动晶体管100的开态电流，通过进一步优化栅介质层140厚度，还能够进一步提高显示面板的响应速度，以及提高与图像灰度相应的数据线电平的分辨率，从而提高显示面板的分辨率；第三，第一绝缘层400的厚度可根据数据线200与扫描线300之间的寄生电容的要求灵活调整，通过增大第一绝缘层厚度能够减小数据线200与扫描线300之间的寄生电容，降低显示面板的整体负载，从而提高显示面板的性能。
在本申请的一实施例中，如图1和图2所示，电容介质层730的厚度小于第二绝缘层800的厚度。
其中，驱动晶体管100通过漏电极130实现对子像素电极500的充放电，子像素电极500所在的显示面板的第一基板和显示面板的第二基板之间填充有液晶，在子像素电极500与第二基板的共电极之间的电场作用下，液晶的排列方向发生偏转，从而控制该子像素的显示灰度，产生显示图像。
考虑到子像素电极500和共电极之间填充液晶，液晶电容的电场难以维持，在子像素中还包括存储电容700，存储电容700与液晶电容并联设置，以维持电场，保持液晶的偏转，使显示图像稳定。存储电容可形成在子像素电极和不与该子像素连接的扫描线之间，也可以另行设置公共线，使存储电容形成在子像素电极和公共线之间。本实施例中，存储电容700的第一电极710与子像素电极500电连接、第二电极720与公共线600电连接，电容介质层730设于第一电极710和第二电极720之间，形成近似于平行板电容器的结构，随着电容介质层730厚度的减薄，存储电容700的容值增大，从而具有更好的性能。
公共线600可与扫描线300平行设置或近似平行设置，为了避免公共线600与数据线200之间因交叉而导通，在公共线600和数据线200之间设有第 二绝缘层800，第二绝缘层800至少分布在公共线600和数据线200的交叉处，当然，第二绝缘层800的分布范围也可以大于公共线600与数据线200的交叉范围。在公共线600、第二绝缘层800和数据线200相层叠的部分，形成近似于平行板电容器的结构，随着第二绝缘层800厚度的增大，公共线600、第二绝缘层800和数据线200所形成的电容容值减小，从而使得子像素的寄生电容减小，提高了子像素的响应速度，减小了整体负载。
栅介质层140、第一绝缘层400、电容介质层730和第二绝缘层800通过半色调掩膜或灰度掩膜工艺一体形成绝缘膜。在半色调掩膜或灰度掩膜工艺中，与绝缘膜图案对应的掩膜图案形成在半色调掩膜版或灰度掩膜版上，在半色调掩膜版或灰度掩膜版中，根据不同的图案形成透光率不同的部分，或在不同位置形成变化的透光率，从而在光刻过程中形成厚度不同的光刻胶图案，再通过刻蚀等工艺形成厚度不同的绝缘膜图案。通过半色调掩膜或灰度掩膜工艺一体形成厚度不同的栅介质层140、第一绝缘层400、电容介质层730和第二绝缘层800，避免了多次沉积导致工艺步骤的增多，生产成本的提高，并且避免了多次沉积过程中可能导致的界面缺陷，进而避免了界面电荷对子像素的显示性能的影响。并且，电容介质层730的厚度h3小于第二绝缘层800的厚度h4，一方面满足了存储电容700的容值要求，另一方面减小了公共线600与数据线200之间的寄生电容，降低了显示面板的整体负载，从而提高了显示面板的性能。
可选的，第一绝缘层400的厚度h2等于第二绝缘层800的厚度h4，由于第一绝缘层400和第二绝缘层800的主要作用都是绝缘，设置其厚度相等时，可以减少工艺过程中半色调掩膜版或灰度掩膜版的制版成本，进而降低生产成本。而栅介质层140的厚度h1与驱动晶体管100的性能要求相关，电容介质层的厚度h3与存储电容700的容值要求相关，因此，厚度h1、h3可以和厚度h2、h4各不相同。
在本实施例中，如图2所示，子像素还包括钝化膜900，钝化膜900覆盖驱动晶体管100、数据线200、扫描线300和公共线600，以避免空气中的氧气、水蒸气等对子像素的性能造成影响，特别是对子像素中驱动晶体管100以及各导线的性能造成影响。钝化膜900包括通孔，子像素电极500设于钝化膜900上，子像素电极500通过通孔与漏电极130电连接，通过层叠设置， 提高了子像素的开口率，从而降低了所需的背光源功率，使得显示面板的功耗降低。
在本申请中，绝缘膜的材料包括氧化硅、氮化硅、氧化铝或氧化铪中的至少一种。其中，氧化硅可通过热氧化法等工艺直接在硅沟道材料上产生，具有简单可靠的工艺；而氮化硅、氧化铝或氧化铪材料的介电常数相比氧化硅高，从而使得驱动晶体管和存储电容具有更好的电学性能。当然，也可以沉积包括不同材料的多层绝缘膜，如底层沉积介电常数较高的氮化硅、氧化铝或氧化铪，而在上层沉积氧化硅，通过半色调掩膜或灰度掩膜工艺形成仅包括氮化硅、氧化铝或氧化铪的栅介质层和电容介质层，以改善驱动晶体管和存储电容的性能，同时形成包括氮化硅、氧化铝或氧化铪以及氧化硅的第一绝缘层和第二绝缘层，以降低绝缘膜的材料成本，同时提高第一绝缘层和第二绝缘层的绝缘性能。
显示面板具有多种架构方式。可选的，多个子像素呈矩形阵列状排列，至少一子像素形成一像素。通常，一个像素包括分别控制红色、绿色和蓝色三种色光显示的三个子像素，当然，一个像素也可以包括四个子像素，且子像素之间具有多种排列方式。通常情况下，显示面板的数据线沿纵向延伸、横向排列，扫描线沿横向延伸、纵向排列。
在本申请的一实施例中，如图3所示，是一种传统架构的显示面板，同一像素的三个子像素沿横向排列；多条数据线200沿纵向延伸、横向排列；多条扫描线300沿横向延伸、纵向排列；同一像素的子像素连接于同一扫描线300，并分别与一不同的数据线200连接。
在本申请的另一实施例中，如图4所示，是一种半源驱动(half source driving)架构的显示面板，以两个子像素为一组，一组中的两个子像素连接于同一条扫描线300，并分别与一不同的数据线200连接，相邻组中的子像素分别与一不同的扫描线300连接、且相邻组内的相邻子像素共用一条数据线200，相比传统的架构方式，半源驱动架构中，扫描频率是传统架构的两倍。
在本申请的又一实施例中，如图5所示，是一种三栅(triple gate)架构的显示面板，同一像素的三个子像素沿纵向排列；同一像素的子像素连接于同一数据线200，并分别与一不同的扫描线300连接。在这种架构方式中，减少了成本较高的数据线200的数量，降低了生产成本，并且，相比传统架 构的显示面板，扫描频率是传统架构的三倍。但相应的，显示面板的整体负载也大幅增加，因此有必要设置具有不同厚度的绝缘膜，以满足相应的性能需求。
本申请还提出一种显示面板的制备方法，用以制备上述显示面板，如图6所示，该显示面板的制备方法包括以下步骤：
步骤S100：在显示面板的基板上沉积第一导电图案；
其中，第一导电图案包括栅电极150和扫描线300，栅电极150与扫描线300电连接，以通过扫描线300的电平控制驱动晶体管100的打开和关断。
步骤S200：在第一导电图案上通过半色调掩膜或灰度掩膜工艺沉积绝缘膜图案；
其中，绝缘膜图案包括栅介质层140和第一绝缘层400，栅介质层140的厚度小于第一绝缘层400的厚度，一方面保证驱动晶体管100的栅控性能，提高驱动晶体管100的开态电流，以提高相应速度和改善显示灰阶的分辨率；另一方面降低数据线200与扫描线300产生的寄生电容，降低显示面板的整体负载。
步骤S300：在绝缘膜图案上沉积第二导电图案；
其中，第二导电图案包括沟道110、源电极120、漏电极130和数据线200，由于沟道110、源电极120、漏电极130和数据线200的材料可能存在差异，步骤S300可包括多次工艺，以分别形成沟道110、源电极120、漏电极130和数据线200。
在上述各步骤中，每一材料层图案的沉积中，首先通过光刻将与相应的材料层图案对应的掩膜版图案转移为光刻胶图案，再通过牺牲层刻蚀工艺或镀膜剥离等工艺将光刻胶图案转移为相应的材料层图案。
进一步的，第一导电图案还包括第二电极720与公共线600；第二电极720和公共线600在步骤S100中同时沉积；绝缘膜图案还包括电容介质层730和第二绝缘层800，且电容介质层730的厚度小于第二绝缘层800的厚度；电容介质层730和第二绝缘层800在步骤S200中通过半色调掩膜或灰度掩膜工艺一体形成，以减少工艺步骤，降低生产成本。
如图6所示，步骤S300之后，显示面板的制备方法还包括以下步骤：
步骤S400：在第二导电图案上沉积钝化膜900图案；
其中，钝化膜900包括通孔，钝化膜900用以减少空气中的氧气、水蒸气等对驱动晶体管100和各导线的性能的影响，从而提高显示面板的稳定性，延长显示面板的使用寿命。
步骤S500：在钝化膜900图案上沉积第三导电图案。
其中，第三导电图案包括第一电极710与子像素电极500，子像素电极500通过通孔与漏电极130电连接，一方面使得子像素电极500与子像素的其它部分相绝缘，另一方面增大了子像素的开口率，避免电路占用过多的面积，从而降低了所需的背光源的亮度，进而降低了显示面板的功耗。
在本申请中，如图7所示，步骤S200包括：
步骤S210：在第一导电图案上沉积绝缘膜；
绝缘膜的沉积可通过热氧化、溅射、蒸镀、外延等工艺实现，不同材料的绝缘膜对应于不同的沉积工艺。
步骤S220：在绝缘膜上沉积光刻胶；
光刻胶可通过旋涂固化等工艺沉积到绝缘膜上，在光刻胶沉积前后，还可以对界面进行相应的处理，以提高沉积质量。
步骤S230：通过半色调掩膜版或灰度掩膜版对光刻胶曝光；
半色调掩膜版或灰度掩膜版是具有多种透光率的掩膜版，通过半色调掩膜版或灰度掩膜版对光刻胶曝光，光源可以是紫外光源或X射线光源等，将掩膜版图案转移到光刻胶上。由于透光率的差别，在透光率高的部分，被曝光的光刻胶厚度较大，而在透光率低的部分，被曝光的光刻胶厚度较小，甚至基本没有光刻胶被曝光。
步骤S240：对光刻胶显影，以在光刻胶上形成与绝缘膜图案对应的光刻胶图案；
显影后，掩膜版图案转移为光刻胶图案，光刻胶图案与绝缘膜图案相对应。其中，与栅介质层140对应的部分光刻胶图案的厚度小于与第一绝缘层400对应的部分光刻胶图案的厚度。
步骤S250：刻蚀光刻胶和绝缘膜，以形成绝缘膜图案。
光刻胶覆盖于绝缘膜上方，具有一定的抗刻蚀性能，随着刻蚀工艺的进行，光刻胶厚度同步减薄，在部分光刻胶被全部清除的区域，绝缘膜被继续刻蚀，而在部分光刻胶尚有留存的区域，绝缘膜被保留，最终形成厚度不同 的绝缘膜图案，以满足显示面板的性能需求。
具体的，如图8所示，步骤S250包括：
步骤S251：灰化光刻胶(PR ashing)，以清除光刻胶图案中当前厚度最小的部分的光刻胶；
灰化光刻胶也就是刻蚀光刻胶的过程，在上述过程中光刻胶厚度均匀减薄，其中，光刻胶图案最薄部分，即对应于成品中绝缘膜图案最薄的部分，光刻胶首先被完全刻蚀清除。
步骤S252：干法刻蚀所述绝缘膜；
在部分绝缘膜上的光刻胶被刻蚀清除后，采用干法刻蚀的方式刻蚀绝缘膜，以形成与光刻胶图案对应的绝缘膜图案。
返回步骤S251。
在完成上述部分绝缘膜的刻蚀后，返回步骤S251，灰化光刻胶至当前厚度最小的部分的光刻胶被清除，也就是清除光刻胶厚度次小的部分的光刻胶，以待形成厚度次小部分的绝缘膜图案。
在干法刻蚀以形成厚度次小的部分绝缘膜图案的过程中，厚度最小的部分绝缘膜也被同步刻蚀，在本轮刻蚀完成后，将在绝缘膜上形成具有两种不同厚度的对应图案。重复上述步骤，至完成全部的绝缘膜图案。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (19)

  1. 一种显示面板，包括多个子像素设置于所述显示面板的基板上，所述子像素包括：
    驱动晶体管，所述驱动晶体管包括栅介质层；
    存储电容，所述存储电容包括电容介质层；
    第一绝缘层，所述第一绝缘层设于显示面板的数据线与显示面板的扫描线之间；以及
    第二绝缘层，所述第二绝缘层设于所述数据线与显示面板的公共线之间；
    所述栅介质层、所述第一绝缘层、所述电容介质层和所述第二绝缘层通过半色调掩膜或灰度掩膜工艺一体形成不同厚度的绝缘膜，所述栅介质层的厚度小于所述第一绝缘层的厚度。
  2. 如权利要求1所述的显示面板，其中，所述电容介质层的厚度小于所述第二绝缘层的厚度。
  3. 如权利要求2所述的显示面板，其中，所述第一绝缘层的厚度等于所述第二绝缘层的厚度。
  4. 如权利要求1所述的显示面板，其中，所述子像素还包括：
    钝化膜，所述钝化膜覆盖所述驱动晶体管、所述数据线、所述扫描线和所述公共线，所述钝化膜包括通孔，子像素电极设于所述钝化膜上，所述子像素电极通过所述通孔与所述驱动晶体管的漏电极电连接。
  5. 如权利要求1所述的显示面板，其中，所述绝缘膜的材料包括氧化硅、氮化硅、氧化铝或氧化铪中的至少一种。
  6. 如权利要求1所述的显示面板，其中，多个所述子像素呈矩形阵列状排列，至少一所述子像素形成一像素，同一所述像素的所述子像素沿纵向排列；
    多条所述数据线沿纵向延伸、横向排列；
    多条所述扫描线沿横向延伸、纵向排列；
    同一所述像素的所述子像素连接于同一所述数据线，并分别与一不同的所述扫描线连接。
  7. 一种显示面板的制备方法，用以制备如权利要求1所述的显示面板，包括以下步骤：
    在显示面板的基板上沉积第一导电图案，所述第一导电图案包括栅电极和扫描线；
    在所述第一导电图案上通过半色调掩膜或灰度掩膜工艺沉积绝缘膜图案，所述绝缘膜图案包括栅介质层和第一绝缘层，所述栅介质层的厚度小于所述第一绝缘层的厚度；以及
    在所述绝缘膜图案上沉积第二导电图案，所述第二导电图案包括沟道、源电极、漏电极和数据线。
  8. 如权利要求7所述的显示面板的制备方法，其中，所述第一导电图案还包括第二电极与公共线；所述绝缘膜图案还包括电容介质层和第二绝缘层，所述电容介质层的厚度小于所述第二绝缘层的厚度；
    在所述绝缘膜图案上沉积第二导电图案的步骤之后，所述显示面板的制备方法还包括以下步骤：
    在所述第二导电图案上沉积钝化膜图案，所述钝化膜包括通孔；以及
    在所述钝化膜图案上沉积第三导电图案，所述第三导电图案包括第一电极与子像素电极，所述子像素电极通过所述通孔与所述漏电极电连接。
  9. 如权利要求7所述的显示面板的制备方法，其中，在所述第一导电图案上通过半色调掩膜或灰度掩膜工艺沉积绝缘膜图案的步骤包括：
    在所述第一导电图案上沉积绝缘膜；
    在所述绝缘膜上沉积光刻胶；
    通过半色调掩膜版或灰度掩膜版对所述光刻胶曝光；
    对所述光刻胶显影，以在所述光刻胶上形成与所述绝缘膜图案对应的光刻胶图案，其中，与所述栅介质层对应的部分所述光刻胶图案的厚度小于与所述第一绝缘层对应的部分所述光刻胶图案的厚度；以及
    刻蚀所述光刻胶和所述绝缘膜，以形成所述绝缘膜图案。
  10. 如权利要求9所述的显示面板的制备方法，其中，所述刻蚀所述光刻胶和所述绝缘膜的步骤包括：
    灰化光刻胶，以清除所述光刻胶图案中当前厚度最小的部分的光刻胶；
    干法刻蚀所述绝缘膜；以及
    返回所述灰化光刻胶，以清除所述光刻胶图案中当前厚度最小的部分的光刻胶的步骤。
  11. 如权利要求7所述的显示面板的制备方法，其中，所述电容介质层的厚度小于所述第二绝缘层的厚度。
  12. 如权利要求11所述的显示面板的制备方法，其中，所述第一绝缘层的厚度等于所述第二绝缘层的厚度。
  13. 如权利要求9所述的显示面板的制备方法，其中，所述绝缘膜的材料包括氧化硅、氮化硅、氧化铝或氧化铪中的至少一种。
  14. 一种显示面板，包括多个子像素设置于所述显示面板的基板上，所述子像素包括：
    驱动晶体管，所述驱动晶体管包括沟道、源电极、漏电极、栅介质层以及栅电极，所述源电极和所述漏电极分别连接于所述沟道两端，所述栅介质层设于所述沟道、所述源电极、所述漏电极与所述栅电极之间；
    数据线，所述数据线与所述源电极电连接；
    扫描线，所述扫描线与所述栅电极电连接；
    子像素电极，所述子像素电极与所述漏电极电连接；
    公共线，所述公共线与所述扫描线的延伸方向一致，且所述公共线与所述扫描线绝缘；
    存储电容，所述存储电容包括第一电极、第二电极以及电容介质层，所述第一电极与所述子像素电极电连接，所述第二电极与所述公共线电连接，所述电容介质层设于所述第一电极与所述第二电极之间；
    第一绝缘层，所述第一绝缘层设于所述数据线与所述扫描线之间；以及
    第二绝缘层，所述第二绝缘层设于所述数据线与所述公共线之间；
    所述栅介质层、所述第一绝缘层、所述电容介质层和所述第二绝缘层通过半色调掩膜或灰度掩膜工艺一体形成不同厚度的绝缘膜，所述栅介质层的厚度小于所述第一绝缘层的厚度。
  15. 如权利要求14所述的显示面板，其中，所述电容介质层的厚度小于所述第二绝缘层的厚度。
  16. 如权利要求15所述的显示面板，其中，所述第一绝缘层的厚度等于所述第二绝缘层的厚度。
  17. 如权利要求14所述的显示面板，其中，所述子像素还包括：
    钝化膜，所述钝化膜覆盖所述驱动晶体管、所述数据线、所述扫描线和 所述公共线，所述钝化膜包括通孔，所述子像素电极设于所述钝化膜上，所述子像素电极通过所述通孔与所述驱动晶体管的漏电极电连接。
  18. 如权利要求14所述的显示面板，其中，所述绝缘膜的材料包括氧化硅、氮化硅、氧化铝或氧化铪中的至少一种。
  19. 如权利要求14所述的显示面板，其中，多个所述子像素呈矩形阵列状排列，至少一所述子像素形成一像素，同一所述像素的所述子像素沿纵向排列；
    多条所述数据线沿纵向延伸、横向排列；
    多条所述扫描线沿横向延伸、纵向排列；
    同一所述像素的所述子像素连接于同一所述数据线，并分别与一不同的所述扫描线连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727296B2 (en) 2018-05-14 2020-07-28 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Methods of manufacturing driving substrates, driving substrates and display apparatuses

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920800A (zh) 2019-02-28 2019-06-21 武汉华星光电半导体显示技术有限公司 一种显示装置及其制作方法
CN110164373B (zh) * 2019-05-27 2021-01-22 京东方科技集团股份有限公司 一种像素驱动电路及其制备方法、oled显示面板
CN110164878B (zh) * 2019-06-10 2022-05-03 惠科股份有限公司 阵列基板及其制备方法
CN113380182B (zh) * 2021-04-21 2022-05-03 电子科技大学 一种栅控类mos发光led像素驱动电路
CN114755854B (zh) * 2022-04-27 2024-03-22 广州华星光电半导体显示技术有限公司 显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110127531A1 (en) * 2009-11-30 2011-06-02 Dong-Gyu Kim Display device, tft substrate, and method of fabricating the tft substrate
CN102446925A (zh) * 2010-09-30 2012-05-09 京东方科技集团股份有限公司 阵列基板、液晶显示器及阵列基板的制造方法
CN103499907A (zh) * 2013-10-25 2014-01-08 合肥京东方光电科技有限公司 阵列基板、显示装置和阵列基板的制作方法
CN104681420A (zh) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN104900502A (zh) * 2014-03-04 2015-09-09 中芯国际集成电路制造(上海)有限公司 栅介质层的形成方法和mos晶体管的形成方法
CN105094486A (zh) * 2015-08-03 2015-11-25 深圳市华星光电技术有限公司 内嵌式自电容触控显示面板及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101216169B1 (ko) * 2005-06-30 2012-12-28 엘지디스플레이 주식회사 액정 표시 장치용 박막 트랜지스터 소자 및 그의 제조 방법
TWI491048B (zh) * 2008-07-31 2015-07-01 Semiconductor Energy Lab 半導體裝置
CN101995713B (zh) * 2009-08-21 2012-08-01 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN104465516B (zh) * 2014-12-05 2017-08-11 京东方科技集团股份有限公司 阵列基板的制造方法、阵列基板和显示装置
TWI880886B (zh) * 2016-10-07 2025-04-21 日商半導體能源研究所股份有限公司 顯示裝置及電子裝置
CN106711087A (zh) * 2016-12-26 2017-05-24 武汉华星光电技术有限公司 薄膜晶体管的制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110127531A1 (en) * 2009-11-30 2011-06-02 Dong-Gyu Kim Display device, tft substrate, and method of fabricating the tft substrate
CN102446925A (zh) * 2010-09-30 2012-05-09 京东方科技集团股份有限公司 阵列基板、液晶显示器及阵列基板的制造方法
CN103499907A (zh) * 2013-10-25 2014-01-08 合肥京东方光电科技有限公司 阵列基板、显示装置和阵列基板的制作方法
CN104681420A (zh) * 2013-11-26 2015-06-03 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN104900502A (zh) * 2014-03-04 2015-09-09 中芯国际集成电路制造(上海)有限公司 栅介质层的形成方法和mos晶体管的形成方法
CN105094486A (zh) * 2015-08-03 2015-11-25 深圳市华星光电技术有限公司 内嵌式自电容触控显示面板及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727296B2 (en) 2018-05-14 2020-07-28 Kunshan Go-Visionox Opto-Electronics Co., Ltd. Methods of manufacturing driving substrates, driving substrates and display apparatuses

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