WO2019037181A1 - 消除电磁干扰装置及其方法 - Google Patents

消除电磁干扰装置及其方法 Download PDF

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Publication number
WO2019037181A1
WO2019037181A1 PCT/CN2017/102236 CN2017102236W WO2019037181A1 WO 2019037181 A1 WO2019037181 A1 WO 2019037181A1 CN 2017102236 W CN2017102236 W CN 2017102236W WO 2019037181 A1 WO2019037181 A1 WO 2019037181A1
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frequency
control chip
electromagnetic interference
timing control
unit
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French (fr)
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王明良
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US15/580,636 priority Critical patent/US20190068177A1/en
Publication of WO2019037181A1 publication Critical patent/WO2019037181A1/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes

Definitions

  • the present application relates to a method for eliminating electromagnetic interference, and more particularly to an apparatus for eliminating electromagnetic interference and a method thereof.
  • Integrated Circuit is one of the main sources of electromagnetic radiation.
  • the electromagnetic radiation generated by the "inductance” in an integrated circuit may interfere with external devices, and in some applications. It may interfere with the operation of the internal components, especially in the LC tank of the differential mode. If the equivalent inductance values of the positive and negative terminals are mutually asymmetrical, they will be at the junction of the positive and negative terminals. A common mode signal is present, which is present on the metal trace that is electrically connected to the junction and causes electromagnetic radiation.
  • the commonly used method is to add EMI suppression component to the power output terminal, or use RC (resistor and capacitor series) snubber circuit, but EMI suppression component can only weaken part of conducted interference, and can't do anything for radiated interference, RC snubber circuit for low power circuit Can have a certain effect, but generally not effective for high power circuits.
  • EMI suppression component can only weaken part of conducted interference, and can't do anything for radiated interference
  • RC snubber circuit for low power circuit Can have a certain effect, but generally not effective for high power circuits.
  • an object of the present application is to provide an apparatus for eliminating electromagnetic interference and a method thereof, which can generate a plurality of different switching frequencies to drive a power chip by using a signal frequency at a system output end, and reduce the frequency by dispersing the switching frequency.
  • the effect of radiation interference is to provide an apparatus for eliminating electromagnetic interference and a method thereof, which can generate a plurality of different switching frequencies to drive a power chip by using a signal frequency at a system output end, and reduce the frequency by dispersing the switching frequency.
  • An apparatus for eliminating electromagnetic interference includes: a timing control chip; a phase-locked loop module electrically connected to the timing control chip, comprising: a phase detecting unit for detecting a clock a frequency generated by the period to generate a frequency difference; a charge pump unit for generating a regulated voltage; a voltage controlled oscillator unit for controlling the oscillation frequency when the regulated voltage is input; and one point A frequency unit for generating an input clock frequency to generate a new output clock frequency.
  • Another object of the present application is an apparatus for eliminating electromagnetic interference, comprising: a timing control chip; a phase-locked loop module electrically connected to the timing control chip, comprising: a phase detecting unit for detecting one by a frequency generated by the clock cycle to generate a frequency difference; a charge pump unit for generating a regulated voltage; a voltage controlled oscillator unit for controlling the oscillation frequency when the regulated voltage is input; a frequency divider unit for generating an input clock frequency at an input clock frequency; further comprising at least one set of said phase locked loop modules; further comprising different power supplies and said locks required by at least four circuits Phase loop The module is electrically connected.
  • a further object of the present application is a method for eliminating electromagnetic interference, comprising: receiving a display data through a timing control chip, and outputting a data signal and a clock cycle signal after processing; and transmitting through a phase locked loop
  • the circuit module is electrically connected to the timing control chip, and includes: a phase detecting unit configured to detect a frequency generated by a clock cycle to generate a frequency difference; and a charge pump unit When the frequency difference is input, generating an adjustment voltage; transmitting a voltage control oscillator unit for controlling the oscillation frequency when the adjustment voltage is input; and using a frequency divider unit to An input clock frequency produces a new output clock frequency.
  • the timing control chip will receive a display data from a front end system end.
  • the timing control chip outputs a data signal and a clock cycle signal after processing the display data.
  • At least one set of the phase locked loop modules is further included.
  • a power control chip is further electrically connected to the voltage controlled oscillator unit and the timing control chip, respectively, for controlling power to the voltage controlled oscillator unit and the Timing control chip.
  • the method further includes at least one set of the phase locked loop modules.
  • the method further includes a power control chip electrically connected to the voltage controlled oscillator unit and the timing control chip, respectively, for controlling power to the voltage controlled oscillator. Unit and the timing control chip.
  • the application adopts the signal frequency of the output end of the system to generate a plurality of different switching frequencies to drive the power chip, and achieves the effect of reducing the radiation interference by dispersing the switching frequency, thereby improving the serious problem of electromagnetic interference radiation of the power circuit.
  • FIG. 1a is a schematic diagram of an exemplary power chip control architecture.
  • FIG. 1b is a schematic diagram of another exemplary power chip control architecture.
  • FIG. 2 is a block diagram of an apparatus for eliminating electromagnetic interference according to an embodiment of the present application.
  • FIG. 3 is a block diagram of a phase locked loop module according to an embodiment of the present application.
  • phase locked loop module is a flow chart of a phase locked loop module according to an embodiment of the present application.
  • the method of the present application is performed using an electromagnetic interference canceling device.
  • the devices and/or methods may be varied and do not need to be associated with one another as fully described below, and such variations are within the scope of the present embodiments.
  • the processing methods of the present application may be implemented in an electromagnetic interference canceling device, such as by operating a driver chip.
  • the methods of the present application are not required to be performed in the exact order as illustrated, unless otherwise stated; and a plurality of similar blocks can be performed in parallel rather than in order; therefore, The elements of the applied method are referred to herein as "blocks" rather than “steps.” It should also be understood that the method can also be implemented in a variant that eliminates electromagnetic interference devices. It will be further appreciated that the method of the present application can be implemented in a processing system. However, the method can also be implemented in a similar system that has similar components to the system but is arranged in different configurations.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • FIG. 1a is a schematic diagram of an exemplary power chip control architecture
  • FIG. 1b is a schematic diagram of another exemplary power chip control architecture.
  • an integrated power chip 100 includes multiple power supplies of 3.3V, 15.6V, 33V, -6V, etc., and the multiple power supplies share the same input clock cycle (CLK) (FIG. 1b)
  • CLK input clock cycle
  • Fs The CLK frequency is Fs), which causes the radiant energy of the multiple power sources to accumulate at the frequency of the input clock cycle CLK, causing the EMI radiation to exceed the standard.
  • an electromagnetic interference canceling apparatus 200 includes: a timing control chip 205; and a phase locked loop module 300 (for example, at least 4 sets of locks as shown in FIG.
  • the phase loop module includes: a -6V module 210, The 15.6V module 220, the 3.3V module 230, and the 33V module 240) are electrically connected to the timing control chip 205, and include: a phase detecting unit 310 for detecting a frequency generated by one clock cycle to generate a a frequency difference difference; a charge pump unit 320 for generating a regulated voltage; a voltage controlled oscillator unit 330 for controlling the oscillation frequency when the regulated voltage is input; and a frequency divider unit 340 for An input clock frequency is input to generate a new output clock frequency.
  • the timing control chip 205 will receive a display data from a front end system end 202.
  • the timing control chip 205 outputs a data signal and a clock cycle signal after processing the display data.
  • At least one set of the phase-locked loop modules 210, 220, 230, 240 is further included.
  • a power control chip (not shown) is further connected to the voltage control oscillator unit 330 and the timing control chip 205 for controlling The power is supplied to the voltage controlled oscillator unit 330 and the timing control chip 205.
  • an electromagnetic interference canceling apparatus 200 includes: a timing control chip 205; and a phase locked loop module 300 (for example, at least 4 sets of phase locks as shown in FIG. 2
  • the loop module includes: a -6V module 210, a 15.6V module 220, a 3.3V module 230, and a 33V module 240), and is electrically connected to the timing control chip 205, and includes: a phase detecting unit 310 for detecting a frequency difference generated by the clock cycle to generate a frequency difference; a charge pump unit 320 for generating a regulated voltage; a voltage controlled oscillator unit 330 for controlling the oscillation frequency when the regulated voltage is input; And a frequency divider unit 340 for generating an input clock frequency to generate a new output clock frequency; further comprising at least one of the phase locked loop modules 210, 220, 230, 240;
  • the different power supplies required for the circuit are -6V, 15.6V, 3.3V, 33V and clock circuit
  • a different frequency division ratio may be set in one frequency divider unit 340, for example, 3.3V is set to 1/N, then 15.6V. It can be set to 1/(N+10).
  • phase-locked loop modules are required corresponding to four different power sources -6V, 15.6V, 3.3V, and 33V.
  • a method for eliminating electromagnetic interference includes: receiving a display data through a timing control chip 205, and outputting a data after processing.
  • the method includes: a phase detecting unit 310 for detecting a frequency generated by a clock cycle to generate a frequency difference; and a charge pump unit 320 for inputting the frequency difference Generating a regulated voltage; transmitting a voltage controlled oscillator unit 330 for controlling the oscillation frequency when the regulated voltage is input; and generating a input clock frequency by a frequency divider unit 340 A new output clock frequency.
  • the method further includes at least one set of the phase locked loop modules 210, 220, 230, 240.
  • the method further includes a power control chip (not shown) electrically connected to the voltage controlled oscillator unit 330 and the timing control chip 205, respectively.
  • a power control chip (not shown) electrically connected to the voltage controlled oscillator unit 330 and the timing control chip 205, respectively.
  • the method further includes a power control chip (not shown) electrically connected to the voltage controlled oscillator unit 330 and the timing control chip 205, respectively.
  • a power control chip electrically connected to the voltage controlled oscillator unit 330 and the timing control chip 205, respectively.
  • step S410 a timing control chip is used to receive a display data, and after processing, a data signal and a clock cycle signal are output.
  • step S420 the timing control chip is electrically connected through a phase locked loop module.
  • a phase detecting unit is used to detect a frequency generated by one clock cycle to generate a frequency difference.
  • step S440 a charge pump unit is passed through to generate a regulated voltage when the frequency difference is input.
  • step S450 a voltage controlled oscillator unit is used to control the oscillation frequency when the regulated voltage is input.
  • step S460 a frequency divider unit is used to generate a new output clock frequency by inputting a clock frequency.
  • the application adopts the signal frequency of the output end of the system to generate a plurality of different switching frequencies to drive the power chip, and achieves the effect of reducing the radiation interference by dispersing the switching frequency, thereby improving the serious problem of electromagnetic interference radiation of the power circuit.

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种消除电磁干扰装置（200）及其方法，包括一时序控制芯片（205）；一锁相环路模块（210，220，230，240，300），与时序控制芯片电性连接。锁相环路模块包括一相位检测单元（310），用以侦测由一时钟周期所产生的频率，产生一频率差值；一电荷泵单元（320），用以产生一调节电压；一电压控制振荡器单元（330），用以当调节电压输入时，来控制振荡频率；以及一分频器单元（340），用以根据一输入时钟频率，产生一新的输出时钟频率。

Description

消除电磁干扰装置及其方法 技术领域
本申请涉及一种消除电磁干扰方法，特别是涉及一种消除电磁干扰装置及其方法。
背景技术
电子产品于运作时会产生电磁辐射，可能会干扰其它装置的正常运作甚至影响人体健康，因此多数国家均针对电子产品的电磁辐射立下规范，以防止电磁干扰(Electromagnetic Interference，EMI)带来危害。
电子产品的组件之一「集成电路(Integrated Circuit，IC)」是电磁辐射的主要来源之一，其中集成电路中的「电感」所产生的电磁辐射除可能干扰外部装置，在某些应用上亦可能干扰内部组件的运作，特别是在差动模式的电感电容共振腔(LC tank)中，若是正负端的电感部分的等效感值互不对称时，便会从正负端电感的交界处出现共模讯号，所述共模讯号会存在于与所述交界处电气连接的金属走线之上，并造成电磁辐射。
目前常用的方式是电源输出端加EMI抑制组件，或使用RC(电阻和电容串联)的缓冲电路，但是EMI抑制组件只能减弱一部分传导干扰，针对辐射干扰则无能为力，RC缓冲电路对小功率电路可以起到一定效果，但对于大功率电路一般无效。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种消除电磁干扰装置及其方法，藉由采用系统输出端的信号频率，产生多个不同的开关频率来驱动电源芯片，通过分散开关频率达到降低辐射干扰的效果。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种消除电磁干扰装置，包括：一时序控制芯片；一锁相环路模块，与所述时序控制芯片电性连接，包括：一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值；一电荷泵单元，用以产生一调节电压；一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率；以及一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率。
本申请的另一目的一种消除电磁干扰装置，包括：一时序控制芯片；一锁相环路模块，与所述时序控制芯片电性连接，包括：一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值；一电荷泵单元，用以产生一调节电压；一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率；以及一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率；其中更包括至少一组所述锁相环路模块；更包括至少四种电路所需的不同电源与所述锁相环路 模块电性连接。
本申请的再一目的一种消除电磁干扰的方法，包括：透过一时序控制芯片，用以接收一显示数据，经过处理后将输出一数据信号及一时钟周期信号；透过一锁相环路模块，与所述时序控制芯片电性连接，包括：藉由一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值；经过一电荷泵单元，用以当所述频率差值输入时，产生一调节电压；透过一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率；以及藉由一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，所述时序控制芯片将由一前端系统端接收一显示数据。
在本申请的一实施例中，所述时序控制芯片将所述显示数据处理后，将输出一数据信号及一时钟周期信号。
在本申请的一实施例中，所述分频器单元其产生一新的输出时钟频率的公式为新的输出时钟频率＝1/N乘上输入时钟频率，其中N为整数。
在本申请的一实施例中，更包括至少一组所述锁相环路模块。
在本申请的一实施例中，更包括一电源控制芯片，分别与所述电压控制振荡器单元及所述时序控制芯片电性连接，用以控制电源给所述电压控制振荡器单元及所述时序控制芯片。
在本申请的一实施例中，所述方法，更包括至少一组所述锁相环路模块。
在本申请的一实施例中，所述方法，更包括一电源控制芯片，分别与所述电压控制振荡器单元及所述时序控制芯片电性连接，用以控制电源给所述电压控制振荡器单元及所述时序控制芯片。
本申请采用系统输出端的信号频率，产生多个不同的开关频率来驱动电源芯片，通过分散开关频率达到降低辐射干扰的效果，因而改善电源电路电磁干扰辐射严重的问题。
附图说明
图1a是范例性的电源芯片控制架构示意图。
图1b是另一范例性的电源芯片控制架构示意图。
图2是本申请一实施例的消除电磁干扰装置方块图。
图3是本申请一实施例的锁相环路模块方块图。
图4是本申请一实施例的锁相环路模块流程图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申 请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
在本申请的实施例中，为了协助解释本申请的方法，将假定用一消除电磁干扰装置来执行本申请的方法。然而，应该理解的是，装置和/或方法可以变化，并不需要完全按照下述描述的彼此关联工作，这些变化都在目前实施例的范围内。可以理解的是，在一些实施例中，本申请的处理方法可通过一消除电磁干扰装置中被实现，例如通过运行驱动芯片。应当强调的是，除非另有说明，本申请的方法不需要按照如图所示的确切顺序被执行；并且类似的多个流程(blocks)可以并行地被执行，而不是按顺序；因此，本申请的方法的元素在文中称为"流程(blocks)"而不是"步骤"。还应当理解的是，方法也可以在消除电磁干扰装置的变型上被实现。可以进一步理解，本申请的方法能在处理系统中实现。然而，方法还可以在与系统有相似部件、但设置在不同配置中的相似系统中被实现。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定申请目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种消除电磁干扰装置及其方法，其具体实施方式、结构、特征及其功效，详细说明如后。
图1a为范例性的电源芯片控制架构示意图及图1b为另一范例性的电源芯片控制架构示意图。请参照图1a及图1b，一种集成电源芯片100，包括3.3V，15.6V，33V，-6V等多路电源，所述多路电源都共享同一个输入时钟周期(CLK)(图1b所示CLK频率为Fs)，这样就会造成在输入时钟周期CLK的频点上多路电源的辐射能量聚集，造成EMI辐射超标。
图2为本申请一实施例的消除电磁干扰装置方块图及图3为本申请一实施例的锁相环路模块方块图。请参照图2及图3，本申请一实施例中，一种消除电磁干扰装置200，包括：一时序控制芯片205；一锁相环路模块300(举例：如图2所示至少4组锁相环路模块包括：-6V模块210、 15.6V模块220、3.3V模块230、33V模块240)，与所述时序控制芯片205电性连接，包括：一相位检测单元310，用以侦测由一时钟周期所产生的频率，而产生一频率差值；一电荷泵单元320，用以产生一调节电压；一电压控制振荡器单元330，用以当所述调节电压输入时，来控制振荡频率；以及一分频器单元340，用以将一输入时钟频率，产生一新的输出时钟频率。
请参照图2及图3，在一实施例中，所述时序控制芯片205将由一前端系统端202接收一显示数据。
请参照图2及图3，在一实施例中，所述时序控制芯片205将所述显示数据处理后，将输出一数据信号及一时钟周期信号。
请参照图2及图3，在一实施例中，所述分频器单元340其产生一新的输出时钟频率的公式为新的输出时钟频率(f)＝1/N乘上输入时钟频率(Fs)，其中N为整数。
请参照图2及图3，在一实施例中，更包括至少一组所述锁相环路模块210、220、230、240。
请参照图2及图3，在一实施例中，更包括一电源控制芯片(图未示)，分别与所述电压控制振荡器单元330及所述时序控制芯片205电性连接，用以控制电源给所述电压控制振荡器单元330及所述时序控制芯片205。
请参照图2及图3，在一实施例中，一种消除电磁干扰装置200，包括：一时序控制芯片205；一锁相环路模块300(举例：如图2所示至少4组锁相环路模块包括：-6V模块210、15.6V模块220、3.3V模块230、33V模块240)，与所述时序控制芯片205电性连接，包括：一相位检测单元310，用以侦测由一时钟周期所产生的频率，而产生一频率差值；一电荷泵单元320，用以产生一调节电压；一电压控制振荡器单元330，用以当所述调节电压输入时，来控制振荡频率；以及一分频器单元340，用以将一输入时钟频率，产生一新的输出时钟频率；其中更包括至少一组所述锁相环路模块210、220、230、240；更包括至少四种电路所需的不同电源-6V、15.6V、3.3V、33V及与其电源(-6V、15.6V、3.3V、33V)所对应的时钟电路，与所述锁相环路模块210、220、230、240电性连接。
请参照图2及图3，在一实施例中，对应4路不同电源，只需要在一分频器单元340设置不同的分频比例即可，比如3.3V设置为1/N，那么15.6V就可以设置为1/(N+10)。
请参照图2及图3，在一实施例中，对应4路不同电源-6V、15.6V、3.3V、33V，需设置4个锁相环路模块。
图4是本申请一实施例的锁相环路模块流程图。请参照图2、图3及图4，本申请一实施例中，一种消除电磁干扰的方法，包括：透过一时序控制芯片205，用以接收一显示数据，经过处理后将输出一数据信号及一时钟周期信号；透过一锁相环路模块300，与所述时序控制芯片205电 性连接，包括：藉由一相位检测单元310，用以侦测由一时钟周期所产生的频率，而产生一频率差值；经过一电荷泵单元320，用以当所述频率差值输入时，产生一调节电压；透过一电压控制振荡器单元330，用以当所述调节电压输入时，来控制振荡频率；以及藉由一分频器单元340，用以将一输入时钟频率，产生一新的输出时钟频率。
请参照图2及图3，在一实施例中，所述方法，更包括至少一组所述锁相环路模块210、220、230、240。
请参照图2及图3，在一实施例中，所述方法，更包括一电源控制芯片(图未示)，分别与所述电压控制振荡器单元330及所述时序控制芯片205电性连接，用以控制电源给所述电压控制振荡器单元330及所述时序控制芯片205。
请参照图4，在流程S410中，透过一时序控制芯片，用以接收一显示数据，经过处理后将输出一数据信号及一时钟周期信号。
请参照图4，在流程S420中，透过一锁相环路模块，与所述时序控制芯片电性连接。
请参照图4，在流程S430中，藉由一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值。
请参照图4，在流程S440中，经过一电荷泵单元，用以当所述频率差值输入时，产生一调节电压。
请参照图4，在流程S450中，透过一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率。
请参照图4，在流程S460中，藉由一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率。
本申请采用系统输出端的信号频率，产生多个不同的开关频率来驱动电源芯片，通过分散开关频率达到降低辐射干扰的效果，因而改善电源电路电磁干扰辐射严重的问题。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的较具体实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以较具体实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (16)

  1. 一种消除电磁干扰装置，包括：
    一时序控制芯片；
    一锁相环路模块，与所述时序控制芯片电性连接，包括:
    一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值；
    一电荷泵单元，用以产生一调节电压；
    一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率；以及
    一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率。
  2. 如权利要求1所述的消除电磁干扰装置，其中，所述时序控制芯片将由一前端系统端接收一显示数据。
  3. 如权利要求2所述的消除电磁干扰装置，其中，所述时序控制芯片将所述显示数据处理后，将输出一数据信号及一时钟周期信号。
  4. 如权利要求1所述的消除电磁干扰装置，其中，所述分频器单元其产生一新的输出时钟频率的公式为新的输出时钟频率＝1/N乘上输入时钟频率，其中N为整数。
  5. 如权利要求1所述的消除电磁干扰装置，更包括至少一组所述锁相环路模块。
  6. 如权利要求1所述的消除电磁干扰装置，更包括至少四种电路所需的不同电源与所述锁相环路模块电性连接。
  7. 如权利要求1所述的消除电磁干扰装置，更包括一电源控制芯片，分别与所述电压控制振荡器单元及所述时序控制芯片电性连接。
  8. 如权利要求7所述的消除电磁干扰装置，其中，所述电源控制芯片用以控制电源给所述电压控制振荡器单元及所述时序控制芯片。
  9. 一种消除电磁干扰装置，包括：
    一时序控制芯片；
    一锁相环路模块，与所述时序控制芯片电性连接，包括：
    一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值；
    一电荷泵单元，用以产生一调节电压；
    一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率；以及
    一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率；其中更包括至少一组所述锁相环路模块；更包括至少四种电路所需的不同电源与所述锁相环路模块电性连接。
  10. 一种消除电磁干扰的方法，包括：
    透过一时序控制芯片，用以接收一显示数据，经过处理后将输出一数据信号及一时钟周期信号；
    透过一锁相环路模块，与所述时序控制芯片电性连接，包括：
    藉由一相位检测单元，用以侦测由一时钟周期所产生的频率，而产生一频率差值；
    经过一电荷泵单元，用以当所述频率差值输入时，产生一调节电压；
    透过一电压控制振荡器单元，用以当所述调节电压输入时，来控制振荡频率；以及
    藉由一分频器单元，用以将一输入时钟频率，产生一新的输出时钟频率。
  11. 如权利要求10所述的消除电磁干扰的方法，其中，所述时序控制芯片将由一前端系统端接收所述显示数据。
  12. 如权利要求10所述的消除电磁干扰的方法，其中，所述分频器单元其产生一新的输出时钟频率的公式为新的输出时钟频率＝1/N乘上输入时钟频率，其中N为整数。
  13. 如权利要求10所述的消除电磁干扰的方法，更包括至少一组所述锁相环路模块。
  14. 如权利要求10所述的消除电磁干扰的方法，更包括至少四种电路所需的不同电源与所述锁相环路模块电性连接。
  15. 如权利要求10所述的消除电磁干扰的方法，更包括一电源控制芯片，分别与所述电压控制振荡器单元及所述时序控制芯片电性连接。
  16. 如权利要求15所述的消除电磁干扰的方法，其中，所述电源控制芯片用以控制电源给所述电压控制振荡器单元及所述时序控制芯片。
PCT/CN2017/102236 2017-08-25 2017-09-19 消除电磁干扰装置及其方法 Ceased WO2019037181A1 (zh)

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