WO2019033548A1 - 一种goa驱动电路及液晶显示装置 - Google Patents

一种goa驱动电路及液晶显示装置 Download PDF

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Publication number
WO2019033548A1
WO2019033548A1 PCT/CN2017/107542 CN2017107542W WO2019033548A1 WO 2019033548 A1 WO2019033548 A1 WO 2019033548A1 CN 2017107542 W CN2017107542 W CN 2017107542W WO 2019033548 A1 WO2019033548 A1 WO 2019033548A1
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Prior art keywords
thin film
film transistor
electrically connected
node
unit
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French (fr)
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石龙强
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/739,784 priority Critical patent/US10446102B2/en
Publication of WO2019033548A1 publication Critical patent/WO2019033548A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

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  • the present invention relates to the field of liquid crystal display technology, and in particular to a GOA driving circuit and a liquid crystal display device.
  • the liquid crystal display device has advantages of high display quality, low price, and convenient portability, and has become a display device for mobile communication devices, PCs, TVs, and the like.
  • the liquid crystal display device driving technology tends to adopt GOA technology.
  • the GOA technology can simplify the manufacturing process of the flat display panel, eliminating the bonding process in the horizontal scanning line direction, which can increase the productivity, reduce the product cost, and can improve the display panel.
  • the integration makes it more suitable for making narrow border or borderless display products, satisfying the visual pursuit of modern people.
  • FIG. 1 is a circuit diagram of a conventional N-th stage GOA unit.
  • the N-th stage GOA unit includes a pull-up control unit 110 and a pull-up unit 120.
  • the pull-up unit 120 is mainly responsible for outputting the clock signal CK(n) to the N-th horizontal scanning line G(n) of the display region, including the third transistor T3.
  • the pull-up control unit 110 is responsible for controlling the turn-on time of the pull-up unit 120, including the first transistor T1, the downlink signal ST(n-1) of the previous stage or the start signal STV is input to the gate and source of the first transistor T1.
  • the drain of the first transistor T1 is connected to the first node Q(n).
  • the pull-down unit 130 is responsible for pulling the horizontal scanning signal on the Nth horizontal scanning line G(n) to a low level, that is, turning off the horizontal scanning signal, including the transistors T4 and T5, and the downlink signal ST(n+1) of the latter stage.
  • the pull-down maintaining unit 140 is responsible for the level N horizontal scanning
  • the horizontal scan signal on line G(n) and the first node Q(n) are maintained in a closed state (i.e., a negative potential).
  • the bootstrap capacitor unit 160 is responsible for the secondary rise of the potential of the first node Q(n), which facilitates the output of the pull up unit 120.
  • the downlink unit 150 is configured to output the downlink transmission signal ST(n) of the present stage.
  • VSS stands for DC low voltage.
  • FIG. 2 is a waveform of each node or each output of the present invention.
  • the second node K(n) is at a high level for most of each period of the GOA driving circuit, thus resulting in a sixth film.
  • the transistor T6 and the seventh thin film transistor T7 are subjected to forward biasing stress (PBTS) for a long time, which causes the threshold voltage of the sixth thin film transistor T6 and the seventh thin film transistor T7 to be positively shifted in the positive direction, and the sixth film is used after a long time operation.
  • PBTS forward biasing stress
  • the threshold voltages of the transistor T6 and the seventh thin film transistor T7 are too high, and the sixth thin film transistor T6 and the seventh thin film transistor T7 are insufficiently opened, resulting in the first node Q(n) and the Nth horizontal scanning line G(n).
  • the upper horizontal scan signal is abnormal, causing the GOA drive unit to fail.
  • a technical problem to be solved by the embodiments of the present invention is to provide a GOA driving circuit and a liquid crystal display device.
  • the positive offset of the threshold voltage of the thin film transistor can be improved to prevent the GOA driving unit from failing.
  • the first aspect of the present invention provides a GOA driving circuit.
  • One cycle of the GOA driving circuit includes a first time and a second time, and the GOA driving circuit includes a plurality of cascaded GOA units.
  • the Nth stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down maintaining unit, a downlink unit, and a bootstrap a capacitor unit; the pull-up unit, the pull-down unit, the pull-down maintaining unit, and the bootstrap capacitor unit are respectively electrically connected to the first node and the Nth horizontal scanning line, and the pull-up control unit and the downlink unit and the first node Electrical connection, where N is a positive integer; wherein
  • the pull-down maintaining unit includes a sixth thin film transistor and a seventh thin film transistor, wherein a source of the sixth thin film transistor is electrically connected to the first node, and a drain thereof is connected to the first low level, and the gate and the second node thereof Electrically connected, the source of the seven thin film transistor is electrically connected to the Nth horizontal scanning line, the drain thereof is connected to the first low level, and the gate thereof is electrically connected to the second node for most of the first time.
  • the threshold voltages of the sixth thin film transistor and the seventh thin film transistor are positively biased;
  • the Nth stage GOA unit further includes a negative bias unit for pairing the sixth film at a second time
  • the threshold voltage of the transistor and the seventh thin film transistor is negatively biased.
  • the second time is a blanking time.
  • the negative bias unit includes a twelfth thin film transistor, a thirteenth thin film transistor, a fourteenth thin film transistor, a fifteenth thin film transistor, a sixteenth thin film transistor, and a seventeenth thin film transistor, wherein the tenth
  • the source and the gate of the second thin film transistor are electrically connected to the second high level, the drain thereof is electrically connected to the third node, and the sources of the thirteenth thin film transistor and the fourteenth thin film transistor are electrically connected to the third node
  • the gate of the thirteenth thin film transistor is electrically connected to the first clock signal, the drain thereof is electrically connected to the first low level, the gate of the fourteenth thin film transistor is electrically connected to the second clock signal, and the drain thereof is electrically connected to the first a low level
  • the source of the fifteenth thin film transistor is electrically connected to the second node
  • the gate thereof is electrically connected to the third node
  • the drain thereof is respectively connected to the source of the sixteenth thin film transistor and the seventeenth thin film transistor
  • the potential of the second high level ranges from 30V to 35V; and the potential of the second low level ranges from -10V to -30V.
  • the pull-down maintaining unit further includes an eighth thin film transistor, a ninth thin film transistor, a tenth thin film transistor, and an eleventh thin film transistor, wherein the gate and the source of the eighth thin film transistor are electrically connected to the first high level
  • the drain is electrically connected to the gate of the ninth thin film transistor and the source of the eleventh thin film transistor, the source of the ninth thin film transistor is electrically connected to the high level, and the drain thereof is electrically connected to the second node.
  • the source of the ten thin film transistor is electrically connected to the second node, the drain thereof is connected to the first low level, the gate thereof is electrically connected to the first node, and the drain of the eleventh thin film transistor is connected to the first low level. Its gate is electrically connected to the first node.
  • the pull-up unit includes a third thin film transistor, the source of the third thin film transistor is connected to the first clock signal, the gate thereof is electrically connected to the first node, and the drain thereof is connected to the Nth horizontal scan line. connection.
  • the downlink unit includes a second thin film transistor, and the source of the second thin film transistor is connected
  • the first clock signal is input, the gate thereof is electrically connected to the first node, and the drain thereof is used for outputting the Nth stage downlink signal.
  • the pull-down unit includes a fourth thin film transistor and a fifth thin film transistor, the source of the fourth thin film transistor is electrically connected to the first node, and the drain thereof is connected to the first low level, and the fifth thin film transistor is The source is electrically connected to the Nth horizontal scanning line, the drain thereof is connected to the first low level, and the gate of the fourth thin film transistor and the gate of the fifth thin film transistor are used to be connected to the N+1th stage. Signal.
  • the pull-up control unit includes a first thin film transistor, and the gate and the source of the first thin film transistor receive the N-1th stage down signal or the start signal, and the drain thereof is electrically connected to the first node.
  • a second aspect of the present invention provides a liquid crystal display device including the above GOA driving circuit.
  • the negative bias unit is configured to negatively bias a threshold voltage of the sixth thin film transistor and the seventh thin film transistor at a second time, thereby causing the sixth thin film transistor,
  • the threshold voltage of the seven thin film transistors is negatively shifted in the second time, so that the positive bias of the threshold voltage of the sixth thin film transistor and the seventh thin film transistor at the first time can be cancelled, thereby making the sixth thin film transistor,
  • the threshold voltage of the seventh thin film transistor is hardly shifted, so that the GOA unit can be prevented from failing.
  • 1 is a circuit diagram of a prior art Nth stage GOA unit
  • FIG. 2 is a schematic diagram of a waveform of the prior art
  • FIG. 3 is a circuit diagram of an Nth stage GOA unit according to an embodiment of the present invention.
  • FIG. 4 is a waveform diagram of an embodiment of the present invention.
  • An embodiment of the present invention provides a GOA driving circuit, where the GOA driving circuit includes a plurality of cascaded GOA units, for example, including M GOA units, and the second level GOA unit is electrically connected to the first level GOA unit, and the third level GOA
  • the unit is electrically connected to the second stage GOA unit, ..., the Mth stage GOA unit is electrically connected to the M-1th stage GOA unit, and each GOA unit outputs a gate driving signal to the horizontal scanning line G corresponding to the display area, for example, the first The stage GOA unit outputs a gate driving signal to the first level horizontal scanning line G(1), the second stage GOA unit outputs a gate driving signal to the second level horizontal scanning line G(2), and the third stage GOA unit output gate
  • the driving signal is supplied to the third-level horizontal scanning line G(3), ..., and the M-th stage GOA unit outputs a gate driving signal to the M-th horizontal scanning line G(m).
  • the GOA driving circuit sequentially outputs gate driving signals to the first horizontal scanning line G(1), the second horizontal scanning line G(2), the third horizontal scanning line G(3), ..., the mth horizontal scanning line G ( m), after a while, the GOA driving circuit sequentially outputs the gate driving signal to the first horizontal scanning line G(1), the second horizontal scanning line G(2), and the third horizontal scanning line G(3).
  • the second time is the blanking time of the GOA driving circuit, that is, the second time is between the time after the output of the gate driving signal of the Mth stage GOA unit to the Mth horizontal scanning line G(m) to the beginning of the next cycle.
  • Time interval, the second time includes a synchronization leading edge time, a synchronization time, and a synchronization trailing edge time, and the first clock signal and the second clock at the blanking time
  • the signals are all low.
  • the first time is a period other than the second time, that is, the first time is that the first GOA unit starts outputting the gate driving signal to the output grating of the first-level horizontal scanning line G1 to the M-th order GOA unit.
  • the GO stage unit of the Nth stage includes a pull-up control unit 210, a pull-up unit 220, a pull-down unit 230, a pull-down maintaining unit 240, a downlink unit 250, and a bootstrap capacitor unit. 260, where N is a positive integer and N is less than or equal to M.
  • the pull-up unit 220, the pull-down unit 230, the pull-down maintaining unit 240, and the bootstrap capacitor unit 260 are respectively electrically connected to the first node Q(n) and the N-th horizontal scanning line G(n), and the pull-up control Unit 210 and downlink unit 250 are electrically coupled to first node Q(n).
  • the pull-down maintaining unit 240 includes a sixth thin film transistor T6 and a seventh thin film transistor T7.
  • the source of the sixth thin film transistor T6 is electrically connected to the first node Q(n), and the drain terminal thereof is connected.
  • the first low level Vss1 is a low voltage DC power source, the potential is -7V
  • the gate thereof is electrically connected to the second node K(n)
  • the source of the seventh thin film transistor T7 Electrically connected to the Nth horizontal scanning line G(n)
  • the drain thereof is connected to the first low level Vss1
  • the gate thereof is electrically connected to the second node K(n), which is described most of the first time
  • the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 are forward biased.
  • most of the first time refers to the first time of 70% of the first time -99.9%, such as 70% of the first time, 75% of the first time, 80% of the first time, 85% The first time, 90% of the first time, 95% of the first time, 98% of the first time, etc., 99.99% of the first time.
  • the negative bias unit 270 is configured to negatively bias the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 at a second time.
  • the negative bias unit 270 is The second time, the second low level Vss2 is applied to the second node K(n), the second low level Vss2 is a low voltage DC power source, and the potential of the second low level Vss2 is higher than the first low level Vss1 The potential is low, and the potential of the second low level Vss2 ranges from -10V to -30V, for example, -10V, -15V, -10V, -20V, -25V, -30V, etc., so that the second node K(n)
  • the voltage at the second time is a second low level Vss2, and the second low level Vss2 negatively biases the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7, thereby making the sixth The threshold voltages of the thin film transistor T6 and the seventh thin film transistor T
  • the negative bias unit 270 is configured to negatively bias the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 at a second time, thereby making the sixth
  • the threshold voltages of the thin film transistor T6 and the seventh thin film transistor T7 are negatively shifted in the second time, so that the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 for most of the first time can be cancelled.
  • the positive biasing causes the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 to be hardly shifted, thereby preventing the GOA unit from failing.
  • the negative bias unit 270 includes a twelfth thin film transistor T12, a thirteenth thin film transistor T13, a fourteenth thin film transistor T14, a fifteenth thin film transistor T15, a sixteenth thin film transistor T16, and a tenth. a thin film transistor T17, wherein a source and a gate of the twelfth thin film transistor T12 are electrically connected to a second high level DCHH.
  • the second high level DCHH is a high voltage direct current power source.
  • the potential range is 30V-35V, for example, 30V, 31V, 32V, 33V, 34V, 35V, etc.
  • the drain of the twelfth thin film transistor T12 is electrically connected to the third node S(n)
  • the thirteenth thin film transistor The source of the T13 and the fourteenth thin film transistor T14 is electrically connected to the third node S(n).
  • the gate of the thirteenth thin film transistor T13 is electrically connected to the first clock signal CK, and the drain thereof is electrically connected to the first low level.
  • the gate of the fourteenth thin film transistor T14 is electrically connected to the second clock signal XCK, the drain thereof is electrically connected to the first low level Vss1, and the source of the fifteenth thin film transistor T15 is connected to the second node K ( n) electrical connection, the gate is electrically connected to the third node S(n), and the drain thereof is respectively The source of the six thin film transistor T16 and the drain of the seventeenth thin film transistor T17 are electrically connected.
  • the gate of the sixteenth thin film transistor T16 is electrically connected to the third node S(n), and the drain thereof is electrically connected to the second low.
  • the level Vss2, the gate of the seventeenth thin film transistor T17 is electrically connected to the second node K(n), the source thereof is electrically connected to the first high level DCH, and the first high level DCH is a high voltage DC power supply.
  • the potential of the first high level DCH is less than the potential of the second high level DCHH, and the potential of the first high level DCH is 28V; wherein the first clock signal CK and the second The clock signal XCK has the same frequency, and the phase is opposite in time except for the blanking time in each period, that is, the phase is opposite at the first time, and the blanking time is at a low level.
  • the first clock signal CK and the second clock signal XCK are opposite in phase, that is, one is a high level, and the other is a low level.
  • the thirteenth thin film transistor T13 and the tenth The four thin film transistors T14 are turned on and the other is turned off.
  • the potential of the third node S(n) is the first low level Vss1, and the fifteenth thin film transistor T15 and the sixteenth thin film transistor T16 are turned off due to the The two nodes K(n) are mostly high level, so that the seventeenth thin film transistor T17 Most of the time is on; when at the second time, that is, at the blanking time, the first clock signal CK and the second clock signal XCK are both low, and thus the thirteenth thin film transistor T13 and the tenth The four thin film transistors T14 are all turned off, the twelfth thin film transistor T12 is turned on, and the voltage at the third node S(n) is the second high level DCHH, so that the fifteenth thin film transistor T15 and the sixteenth thin film transistor T16 are turned on.
  • a low potential of the second low level Vss2 is applied to the second node K(n), and the potential of the second low level Vss2 is low, so that the sixth thin film transistor T6 and the seventh thin film transistor T7 are greatly affected.
  • the negative bias voltage (NBTS) a large negative bias voltage, causes the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 to be negatively shifted. In this way, the forward biasing of the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 caused by the forward bias stress for most of the first time can be cancelled. In combination, the threshold voltages of the sixth thin film transistor T6 and the seventh thin film transistor T7 are hardly shifted, thereby improving the resistance of the circuit.
  • the pull-down maintaining unit 240 further includes an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, an eleventh thin film transistor T11, and a gate of the eighth thin film transistor T8.
  • the source is electrically connected to the first high level DCH, and the drain thereof is electrically connected to the gate of the ninth thin film transistor T9 and the source of the eleventh thin film transistor T11, respectively, and the source of the ninth thin film transistor T9 is the first high
  • the level DCH is electrically connected, the drain thereof is electrically connected to the second node K(n), the source of the tenth thin film transistor T10 is electrically connected to the second node K(n), and the drain thereof is connected to the first low level Vss1
  • the gate is electrically connected to the first node Q(n), the drain of the eleventh thin film transistor T11 is connected to the first low level Vss1, and the gate thereof is electrically connected to the first node Q(n).
  • the pull-up unit 220 includes a third thin film transistor T3.
  • the source of the third thin film transistor T3 is connected to the first clock signal CK, and the gate thereof is electrically connected to the first node Q(n).
  • the drain thereof is electrically connected to the Nth horizontal scanning line G(n).
  • the downlink unit 250 includes a second thin film transistor T2.
  • the source of the second thin film transistor T2 is connected to the first clock signal CK, and the gate thereof is electrically connected to the first node Q(n).
  • the drain thereof is used to output the Nth stage down signal ST(n).
  • the pull-down unit 230 includes a fourth thin film transistor T4 and a fifth thin film transistor T5.
  • the source of the fourth thin film transistor T4 is electrically connected to the first node Q(n), and the drain thereof is connected.
  • a low level Vss1 the source of the fifth thin film transistor T5 is electrically connected to the Nth horizontal scanning line G(n), the drain thereof is connected to the first low level Vss1, and the gate of the fourth thin film transistor T4 is Pole and the fifth The gate of the thin film transistor T5 is used to connect the N+1th down signal ST(n+1).
  • the pull-up control unit 210 includes a first thin film transistor T1, and the gate and source of the first thin film transistor T1 receive the N-1th-level downlink signal ST(n-1) or The start signal STV has its drain electrically connected to the first node Q(n).
  • the bootstrap capacitor unit 260 includes a capacitor Cb, one end of the capacitor Cb is electrically connected to the first node Q(n), and the other end is electrically connected to the Nth horizontal scan line G(n).
  • an embodiment of the present invention further provides a liquid crystal display device including the above GOA driving circuit.
  • the present invention has the following advantages:
  • the negative bias unit is configured to negatively bias a threshold voltage of the sixth thin film transistor and the seventh thin film transistor at a second time, thereby causing the sixth thin film transistor,
  • the threshold voltage of the seven thin film transistors is negatively shifted in the second time, so that the positive bias of the threshold voltage of the sixth thin film transistor and the seventh thin film transistor at the first time can be cancelled, thereby making the sixth thin film transistor,
  • the threshold voltage of the seventh thin film transistor is hardly shifted, so that the GOA unit can be prevented from failing.

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Abstract

一种GOA驱动电路，GOA驱动电路的一个周期包括第一时间和第二时间，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，第N级GOA单元包括上拉单元（220）、上拉控制单元（210）、下拉单元（230）、下拉维持单元（240）、下传单元（250）以及自举电容单元（260）；其中，第N级GOA单元还包括负偏单元（270），其用于在第二时间对第六薄膜晶体管（T6）、第七薄膜晶体管（T7）的阈值电压进行负偏。还公开了一种包括GOA驱动电路的液晶显示装置。

Description

一种GOA驱动电路及液晶显示装置
本发明要求2017年8月16日递交的发明名称为“一种GOA驱动电路及液晶显示装置”的申请号CN 201710702610.X的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示技术领域，特别是涉及一种GOA驱动电路以及液晶显示装置。
背景技术
液晶显示装置以其显示品质高、价格低廉、携带方便等优点，成为移动通讯设备、PC、TV等的显示装置。目前液晶显示装置驱动技术逐渐趋向于采用GOA技术，GOA技术能简化平板显示面板的制作工序，省去水平扫描线方向的接合(bonding)工艺，可提升产能、降低产品成本，同时可以提升显示面板的集成度使之更适合制作窄边框或无边框显示产品，满足现代人们的视觉追求。
GOA技术，即Gate Driver on Array技术，也就是利用现有薄膜晶体管液晶显示器Array制程将Gate行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式。现有的GOA驱动电路包括多个级联的GOA单元，图1是现有的第N级GOA单元的电路图，参照图1，第N级的GOA单元包括上拉控制单元110、上拉单元120、下拉单元130、下拉维持单元140、下传单元150和自举电容单元160。
上拉单元120主要负责将时钟信号CK(n)输出给显示区域第N级水平扫描线G(n)，包括第三晶体管T3。上拉控制单元110负责控制上拉单元120的打开时间，包括第一晶体管T1，前一级的下传信号ST(n-1)或者起始信号STV输入到第一晶体管T1的栅极和源极，第一晶体管T1的漏极连接到第一节点Q(n)。下拉单元130负责将第N级水平扫描线G(n)上的水平扫描信号拉低为低电位，即关闭水平扫描信号，包括晶体管T4和T5，后一级的下传信号ST(n+1)输入到晶体管T4和T5的栅极。下拉维持单元140则负责将第N级水平扫描 线G(n)上的水平扫描信号和第一节点Q(n)维持在关闭状态(即负电位)。自举电容单元160则负责所述第一节点Q(n)电位的二次抬升，这样有利于上拉单元120的输出。下传单元150用于输出本级下传信号ST(n)。VSS表示直流低电压。
图2是本发明各个节点或者各个输出端的波形，从图2可以看出，第二节点K(n)在GOA驱动电路每个周期内的大部分时间都是高电平，这样导致第六薄膜晶体管T6、第七薄膜晶体管T7长期受到正向偏压的应力(PBTS)，导致第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压正向偏移严重，长时间操作以后会因为第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压太高，而导致第六薄膜晶体管T6、第七薄膜晶体管T7打开不充分，导致第一节点Q(n)、第N级水平扫描线G(n)上的水平扫描信号异常，导致GOA驱动单元失效。
发明内容
本发明实施例所要解决的技术问题在于，提供一种GOA驱动电路及液晶显示装置。可改善薄膜晶体管阈值电压的正向偏移，防止GOA驱动单元失效。
为了解决上述技术问题，本发明第一方面实施例提供了一种GOA驱动电路，该GOA驱动电路的一个周期包括第一时间和第二时间，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，该第N级GOA单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元、下传单元以及自举电容单元；所述上拉单元、下拉单元、下拉维持单元及自举电容单元均分别与第一节点以及第N级水平扫描线电连接，所述上拉控制单元以及下传单元与第一节点电连接，其中N为正整数；其中，
所述下拉维持单元包括第六薄膜晶体管、第七薄膜晶体管，所述第六薄膜晶体管的源极与第一节点电连接，其漏极接入第一低电平，其栅极与第二节点电连接，所述七薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接入第一低电平，其栅极与第二节点电连接，在第一时间的大部分时间所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行正偏；
该第N级GOA单元还包括负偏单元，其用于在第二时间对所述第六薄膜 晶体管、第七薄膜晶体管的阈值电压进行负偏。
其中，所述第二时间为消隐时间。
其中，所述负偏单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管和第十七薄膜晶体管，其中，所述第十二薄膜晶体管的源极和栅极电连接第二高电平，其漏极电连接第三节点，所述第十三薄膜晶体管和第十四薄膜晶体管的源极电连接第三节点，所述第十三薄膜晶体管的栅极电连接第一时钟信号，其漏极电连接第一低电平，所述第十四薄膜晶体管的栅极电连接第二时钟信号，其漏极电连接第一低电平，所述第十五薄膜晶体管的源极与第二节点电连接，其栅极与第三节点电连接，其漏极分别与第十六薄膜晶体管的源极、第十七薄膜晶体管的漏极电连接，所述第十六薄膜晶体管的栅极与第三节点电连接，其漏极电连接第二低电平，所述第十七薄膜晶体管的栅极与第二节点电连接，其源极电连接第一高电平，其中，所述第一时钟信号和所述第二时钟信号频率相同，在每个周期除消隐时间以外的时间相位相反，在消隐时间均为低电平，所述第二高电平高于第一高电平，所述第二低电平低于第一低电平。
其中，所述第二高电平的电位范围为30V-35V；所述第二低电平的电位范围为-10V～-30V。
其中，所述下拉维持单元还包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管，所述第八薄膜晶体管的栅极与源极与第一高电平电连接，其漏极分别与第九薄膜晶体管的栅极和第十一薄膜晶体管的源极电连接，第九薄膜晶体管的源极与高电平电连接，其漏极与第二节点电连接，第十薄膜晶体管的源极与第二节点电连接，其漏极接入第一低电平，其栅极与第一节点电连接，第十一薄膜晶体管的漏极接入第一低电平，其栅极与第一节点电连接。
其中，所述上拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极与第N级水平扫描线电连接。
其中，所述下传单元包括第二薄膜晶体管，所述第二薄膜晶体管的源极接 入第一时钟信号，其栅极与第一节点电连接，其漏极用于输出第N级下传信号。
其中，所述下拉单元包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管的源极与第一节点电连接，其漏极接第一低电平，所述第五薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接第一低电平，所述第四薄膜晶体管的栅极和所述第五薄膜晶体管的栅极用于接第N+1级下传信号。
其中，所述上拉控制单元包括第一薄膜晶体管，所述第一薄膜晶体管的栅极和源极接收第N-1级下传信号或者起始信号，其漏极与第一节点电连接。
本发明第二方面实施例提供了一种液晶显示装置，包括上述的GOA驱动电路。
实施本发明实施例，具有如下有益效果：
由于所述GOA单元包括负偏单元，所述负偏单元用于在第二时间对所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行负偏，从而使所述第六薄膜晶体管、第七薄膜晶体管的阈值电压在第二时间向负向偏移，从而可以抵消所述第六薄膜晶体管、第七薄膜晶体管在第一时间的阈值电压的正偏，从而使所述第六薄膜晶体管、第七薄膜晶体管的阈值电压几乎不进行偏移，从而可以防止GOA单元失效。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术第N级GOA单元的电路图；
图2是现有技术的波形示意图；
图3是本发明一实施例第N级GOA单元的电路图；
图4是本发明一实施例的波形示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
本发明实施例提供一种GOA驱动电路，所述GOA驱动电路包括多个级联的GOA单元，例如包括M个GOA单元，第二级GOA单元与第一级GOA单元电连接，第三级GOA单元与第二级GOA单元电连接，…，第M级GOA单元与第M-1级GOA单元电连接，每个GOA单元输出栅极驱动信号给显示区域对应的水平扫描线G，例如第一级GOA单元输出栅极驱动信号给第一级水平扫描线G(1)，第二级GOA单元输出栅极驱动信号给第二级水平扫描线G(2)，第三级GOA单元输出栅极驱动信号给第三级水平扫描线G(3)，…，第M级GOA单元输出栅极驱动信号给第M级水平扫描线G(m)。GOA驱动电路依序输出栅极驱动信号给第一水平扫描线G(1)、第二水平扫描线G(2)、第三水平扫描线G(3)、…、第m水平扫描线G(m)，其后过一段时间，GOA驱动电路再次依序输出栅极驱动信号给第一水平扫描线G(1)、第二水平扫描线G(2)、第三水平扫描线G(3)、…、第m水平扫描线G(m)，也即GOA驱动电路按周期输出栅极驱动信号，所述GOA驱动电路的一个周期包括第一时间和第二时间，在本实施例中，所述第二时间为GOA驱动电路的消隐时间，也即第二时间为第M级GOA单元输出栅极驱动信号给第M级水平扫描线G(m)之后的时间到下一个周期开始之间的时间间隔，该第二时间包括同步前沿时间、同步时间和同步后沿时间，在消隐时间所述第一时钟信号和所述第二时钟 信号均为低电平。该第一时间为一个周期除第二时间之外的时间，也即该第一时间为第一GOA单元开始输出栅极驱动信号给第一级水平扫描线G1到第M级GOA单元输出栅极驱动信号给第M级水平扫描线G(m)完成之间的时间间隔。其中m为正整数。
请参见图3和图4，在本实施例中，第N级的GOA单元包括上拉控制单元210、上拉单元220、下拉单元230、下拉维持单元240、下传单元250、自举电容单元260，其中N为正整数，N小于或等于M。所述上拉单元220、下拉单元230、下拉维持单元240及自举电容单元260均分别与第一节点Q(n)以及第N级水平扫描线G(n)电连接，所述上拉控制单元210以及下传单元250与第一节点Q(n)电连接。
在本实施例中，所述下拉维持单元240包括第六薄膜晶体管T6、第七薄膜晶体管T7，所述第六薄膜晶体管T6的源极与第一节点Q(n)电连接，其漏极接入第一低电平Vss1，所述第一低电平Vss1为低压直流电源，电位为-7V，其栅极与第二节点K(n)电连接，所述第七薄膜晶体管T7的源极与第N级水平扫描线G(n)电连接，其漏极接入第一低电平Vss1，其栅极与第二节点K(n)电连接，在第一时间的大部分时间所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压进行正偏。在这里，第一时间的大部分时间是指70％的第一时间-99.99％的第一时间，例如70％的第一时间、75％的第一时间、80％的第一时间、85％的第一时间、90％的第一时间、95％的第一时间、98％的第一时间等、99.99％的第一时间。
所述负偏单元270用于在第二时间对所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压进行负偏，具体说来，在本实施例中，所述负偏单元270在第二时间施加第二低电平Vss2给第二节点K(n)，所述第二低电平Vss2为低压直流电源，所述第二低电平Vss2的电位比第一低电平Vss1的电位低，所述第二低电平Vss2的电位范围为-10V～-30V，例如为-10V、-15V、-10V、-20V、-25V、-30V等，从而第二节点K(n)处的电压在第二时间为第二低电平Vss2，所述第二低电平Vss2对所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压进行负偏，从而使所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压向负向偏移，请参见图4所述的波形图。
由于所述GOA单元包括负偏单元270，所述负偏单元270用于在第二时间对所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压进行负偏，从而使所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压在第二时间向负向偏移，从而可以抵消所述第六薄膜晶体管T6、第七薄膜晶体管T7在第一时间内大部分时间的阈值电压的正偏，从而使所述第六薄膜晶体管T6、第七薄膜晶体管T7的阈值电压几乎不进行偏移，从而可以防止GOA单元失效。
在本实施例中，所述负偏单元270包括第十二薄膜晶体管T12、第十三薄膜晶体管T13、第十四薄膜晶体管T14、第十五薄膜晶体管T15、第十六薄膜晶体管T16和第十七薄膜晶体管T17，其中，所述第十二薄膜晶体管T12的源极和栅极电连接第二高电平DCHH，在本实施例中，所述第二高电平DCHH为高压直流电源，其电位的范围为30V-35V，例如为30V、31V、32V、33V、34V、35V等，所述第十二薄膜晶体管T12漏极电连接第三节点S(n)，所述第十三薄膜晶体管T13和第十四薄膜晶体管T14的源极电连接第三节点S(n)，所述第十三薄膜晶体管T13的栅极电连接第一时钟信号CK，其漏极电连接第一低电平Vss1，所述第十四薄膜晶体管T14的栅极电连接第二时钟信号XCK，其漏极电连接第一低电平Vss1，所述第十五薄膜晶体管T15的源极与第二节点K(n)电连接，其栅极与第三节点S(n)电连接，其漏极分别与第十六薄膜晶体管T16的源极、第十七薄膜晶体管T17的漏极电连接，所述第十六薄膜晶体管T16的栅极与第三节点S(n)电连接，其漏极电连接第二低电平Vss2，所述第十七薄膜晶体管T17的栅极与第二节点K(n)电连接，其源极电连接第一高电平DCH，所述第一高电平DCH为高压直流电源，所述第一高电平DCH的电位小于所述第二高电平DCHH的电位，所述第一高电平DCH的电位为28V；其中，所述第一时钟信号CK和所述第二时钟信号XCK频率相同，在每个周期除消隐时间以外的时间相位相反，也即在第一时间相位相反，在消隐时间均为低电平。从而，当在第一时间时，第一时钟信号CK和第二时钟信号XCK相位相反，也即一个是高电平，另一个是低电平，此时，第十三薄膜晶体管T13和第十四薄膜晶体管T14一个导通，另一个截止，此时第三节点S(n)的电位为第一低电平Vss1，此时第十五薄膜晶体管T15和第十六薄膜晶体管T16截止，由于第二节点K(n)大部分时间是高电平，从而第十七薄膜晶体管T17 大部分时间导通；当在第二时间时，也即在消隐时间时，此时第一时钟信号CK和第二时钟信号XCK均为低电平，从而第十三薄膜晶体管T13和第十四薄膜晶体管T14均截止，第十二薄膜晶体管T12导通，第三节点S(n)处的电压为第二高电平DCHH，从而第十五薄膜晶体管T15和第十六薄膜晶体管T16导通，从而会对第二节点K(n)施加一个第二低电平Vss2的低电位，而第二低电平Vss2电位很低，这样第六薄膜晶体管T6和第七薄膜晶体管T7会受到很大负向偏压的应力(NBTS)，很大的负向偏压会使得第六薄膜晶体管T6和第七薄膜晶体管T7的阈值电压负向偏移。这样一来，可以抵消第一时间中绝大多数时间正向偏压应力导致第六薄膜晶体管T6和第七薄膜晶体管T7的阈值电压的正向偏移。综合起来，第六薄膜晶体管T6和第七薄膜晶体管T7的阈值电压几乎不进行偏移，从而提高电路的耐性。
在本实施例中，所述下拉维持单元240还包括第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11，所述第八薄膜晶体管T8的栅极与源极与第一高电平DCH电连接，其漏极分别与第九薄膜晶体管T9的栅极和第十一薄膜晶体管T11的源极电连接，第九薄膜晶体管T9的源极与第一高电平DCH电连接，其漏极与第二节点K(n)电连接，第十薄膜晶体管T10的源极与第二节点K(n)电连接，其漏极接入第一低电平Vss1，其栅极与第一节点Q(n)电连接，第十一薄膜晶体管T11的漏极接入第一低电平Vss1，其栅极与第一节点Q(n)电连接。
在本实施例中，所述上拉单元220包括第三薄膜晶体管T3，所述第三薄膜晶体管T3的源极接入第一时钟信号CK，其栅极与第一节点Q(n)电连接，其漏极与第N级水平扫描线G(n)电连接。
在本实施例中，所述下传单元250包括第二薄膜晶体管T2，所述第二薄膜晶体管T2的源极接入第一时钟信号CK，其栅极与第一节点Q(n)电连接，其漏极用于输出第N级下传信号ST(n)。
在本实施例中，所述下拉单元230包括第四薄膜晶体管T4和第五薄膜晶体管T5，所述第四薄膜晶体管T4的源极与第一节点Q(n)电连接，其漏极接第一低电平Vss1，所述第五薄膜晶体管T5的源极与第N级水平扫描线G(n)电连接，其漏极接第一低电平Vss1，所述第四薄膜晶体管T4的栅极和所述第五 薄膜晶体管T5的栅极用于接第N+1级下传信号ST(n+1)。
在本实施例中，所述上拉控制单元210包括第一薄膜晶体管T1，所述第一薄膜晶体管T1的栅极和源极接收第N-1级下传信号ST(n-1)或者起始信号STV，其漏极与第一节点Q(n)电连接。
在本实施例中，所述自举电容单元260包括电容Cb，所述电容Cb的一端与第一节点Q(n)电连接，另一端与第N级水平扫描线G(n)电连接
另外，本发明实施例还提供一种液晶显示装置，其包括上述的GOA驱动电路。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
通过上述实施例的描述，本发明具有以下优点：
由于所述GOA单元包括负偏单元，所述负偏单元用于在第二时间对所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行负偏，从而使所述第六薄膜晶体管、第七薄膜晶体管的阈值电压在第二时间向负向偏移，从而可以抵消所述第六薄膜晶体管、第七薄膜晶体管在第一时间的阈值电压的正偏，从而使所述第六薄膜晶体管、第七薄膜晶体管的阈值电压几乎不进行偏移，从而可以防止GOA单元失效。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (18)

  1. 一种GOA驱动电路，其中，该GOA驱动电路的一个周期包括第一时间和第二时间，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，该第N级GOA单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元、下传单元以及自举电容单元；所述上拉单元、下拉单元、下拉维持单元及自举电容单元均分别与第一节点以及第N级水平扫描线电连接，所述上拉控制单元以及下传单元与第一节点电连接，其中N为正整数；其中，
    所述下拉维持单元包括第六薄膜晶体管、第七薄膜晶体管，所述第六薄膜晶体管的源极与第一节点电连接，其漏极接入第一低电平，其栅极与第二节点电连接，所述七薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接入第一低电平，其栅极与第二节点电连接，在第一时间的大部分时间所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行正偏；
    该第N级GOA单元还包括负偏单元，其用于在第二时间对所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行负偏。
  2. 如权利要求1所述的GOA驱动电路，其中，所述第二时间为消隐时间。
  3. 如权利要求2所述的GOA驱动电路，其中，所述负偏单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管和第十七薄膜晶体管，其中，所述第十二薄膜晶体管的源极和栅极电连接第二高电平，其漏极电连接第三节点，所述第十三薄膜晶体管和第十四薄膜晶体管的源极电连接第三节点，所述第十三薄膜晶体管的栅极电连接第一时钟信号，其漏极电连接第一低电平，所述第十四薄膜晶体管的栅极电连接第二时钟信号，其漏极电连接第一低电平，所述第十五薄膜晶体管的源极与第二节点电连接，其栅极与第三节点电连接，其漏极分别与第十六薄膜晶体管的源极、第十七薄膜晶体管的漏极电连接，所述第十六薄膜晶体管的栅极与 第三节点电连接，其漏极电连接第二低电平，所述第十七薄膜晶体管的栅极与第二节点电连接，其源极电连接第一高电平，其中，所述第一时钟信号和所述第二时钟信号频率相同，在每个周期除消隐时间以外的时间相位相反，在消隐时间均为低电平，所述第二高电平高于第一高电平，所述第二低电平低于第一低电平。
  4. 如权利要求3所述的GOA驱动电路，其中，所述第二高电平的电位范围为30V-35V；所述第二低电平的电位范围为-10V～-30V。
  5. 如权利要求1所述的GOA驱动电路，其中，所述下拉维持单元还包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管，所述第八薄膜晶体管的栅极与源极与第一高电平电连接，其漏极分别与第九薄膜晶体管的栅极和第十一薄膜晶体管的源极电连接，第九薄膜晶体管的源极与高电平电连接，其漏极与第二节点电连接，第十薄膜晶体管的源极与第二节点电连接，其漏极接入第一低电平，其栅极与第一节点电连接，第十一薄膜晶体管的漏极接入第一低电平，其栅极与第一节点电连接。
  6. 如权利要求1所述的GOA驱动电路，其中，所述上拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极与第N级水平扫描线电连接。
  7. 如权利要求1所述的GOA驱动电路，其中，所述下传单元包括第二薄膜晶体管，所述第二薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极用于输出第N级下传信号。
  8. 如权利要求1所述的GOA驱动电路，其中，所述下拉单元包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管的源极与第一节点电连接，其漏极接第一低电平，所述第五薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接第一低电平，所述第四薄膜晶体管的栅极和所述第五薄膜晶 体管的栅极用于接第N+1级下传信号。
  9. 如权利要求1所述的GOA驱动电路，其中，所述上拉控制单元包括第一薄膜晶体管，所述第一薄膜晶体管的栅极和源极接收第N-1级下传信号或者起始信号，其漏极与第一节点电连接。
  10. 一种液晶显示装置，其中，包括一种GOA驱动电路，该GOA驱动电路的一个周期包括第一时间和第二时间，该GOA驱动电路包括多个级联的GOA单元，按照第N级GOA单元输出栅极驱动信号给显示区域第N级水平扫描线，该第N级GOA单元包括上拉单元、上拉控制单元、下拉单元、下拉维持单元、下传单元以及自举电容单元；所述上拉单元、下拉单元、下拉维持单元及自举电容单元均分别与第一节点以及第N级水平扫描线电连接，所述上拉控制单元以及下传单元与第一节点电连接，其中N为正整数；其中，
    所述下拉维持单元包括第六薄膜晶体管、第七薄膜晶体管，所述第六薄膜晶体管的源极与第一节点电连接，其漏极接入第一低电平，其栅极与第二节点电连接，所述七薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接入第一低电平，其栅极与第二节点电连接，在第一时间的大部分时间所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行正偏；
    该第N级GOA单元还包括负偏单元，其用于在第二时间对所述第六薄膜晶体管、第七薄膜晶体管的阈值电压进行负偏。
  11. 如权利要求10所述的液晶显示装置，其中，所述第二时间为消隐时间。
  12. 如权利要求11所述的液晶显示装置，其中，所述负偏单元包括第十二薄膜晶体管、第十三薄膜晶体管、第十四薄膜晶体管、第十五薄膜晶体管、第十六薄膜晶体管和第十七薄膜晶体管，其中，所述第十二薄膜晶体管的源极和栅极电连接第二高电平，其漏极电连接第三节点，所述第十三薄膜晶体管和第十四薄膜晶体管的源极电连接第三节点，所述第十三薄膜晶体管的栅极电连 接第一时钟信号，其漏极电连接第一低电平，所述第十四薄膜晶体管的栅极电连接第二时钟信号，其漏极电连接第一低电平，所述第十五薄膜晶体管的源极与第二节点电连接，其栅极与第三节点电连接，其漏极分别与第十六薄膜晶体管的源极、第十七薄膜晶体管的漏极电连接，所述第十六薄膜晶体管的栅极与第三节点电连接，其漏极电连接第二低电平，所述第十七薄膜晶体管的栅极与第二节点电连接，其源极电连接第一高电平，其中，所述第一时钟信号和所述第二时钟信号频率相同，在每个周期除消隐时间以外的时间相位相反，在消隐时间均为低电平，所述第二高电平高于第一高电平，所述第二低电平低于第一低电平。
  13. 如权利要求12所述的液晶显示装置，其中，所述第二高电平的电位范围为30V-35V；所述第二低电平的电位范围为-10V～-30V。
  14. 如权利要求10所述的液晶显示装置，其中，所述下拉维持单元还包括第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管，所述第八薄膜晶体管的栅极与源极与第一高电平电连接，其漏极分别与第九薄膜晶体管的栅极和第十一薄膜晶体管的源极电连接，第九薄膜晶体管的源极与高电平电连接，其漏极与第二节点电连接，第十薄膜晶体管的源极与第二节点电连接，其漏极接入第一低电平，其栅极与第一节点电连接，第十一薄膜晶体管的漏极接入第一低电平，其栅极与第一节点电连接。
  15. 如权利要求10所述的液晶显示装置，其中，所述上拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极与第N级水平扫描线电连接。
  16. 如权利要求10所述的液晶显示装置，其中，所述下传单元包括第二薄膜晶体管，所述第二薄膜晶体管的源极接入第一时钟信号，其栅极与第一节点电连接，其漏极用于输出第N级下传信号。
  17. 如权利要求10所述的液晶显示装置，其中，所述下拉单元包括第四薄膜晶体管和第五薄膜晶体管，所述第四薄膜晶体管的源极与第一节点电连接，其漏极接第一低电平，所述第五薄膜晶体管的源极与第N级水平扫描线电连接，其漏极接第一低电平，所述第四薄膜晶体管的栅极和所述第五薄膜晶体管的栅极用于接第N+1级下传信号。
  18. 如权利要求10所述的液晶显示装置，其中，所述上拉控制单元包括第一薄膜晶体管，所述第一薄膜晶体管的栅极和源极接收第N-1级下传信号或者起始信号，其漏极与第一节点电连接。
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