WO2019033534A1 - 一种液晶显示面板及装置 - Google Patents

一种液晶显示面板及装置 Download PDF

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Publication number
WO2019033534A1
WO2019033534A1 PCT/CN2017/106646 CN2017106646W WO2019033534A1 WO 2019033534 A1 WO2019033534 A1 WO 2019033534A1 CN 2017106646 W CN2017106646 W CN 2017106646W WO 2019033534 A1 WO2019033534 A1 WO 2019033534A1
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Prior art keywords
pixels
column
pixel
thin film
film transistor
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Ceased
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PCT/CN2017/106646
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English (en)
French (fr)
Inventor
郝思坤
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/577,351 priority Critical patent/US10591792B2/en
Publication of WO2019033534A1 publication Critical patent/WO2019033534A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel and device.
  • Liquid crystal displays are currently the most widely used flat panel display and are used in a variety of electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens.
  • PDAs personal digital assistants
  • LCDs liquid crystal display
  • computer screens computer screens or laptop screens.
  • Liquid crystal displays which are commonly used at present, are usually composed of upper and lower substrates and a liquid crystal layer, and the substrate is composed of glass, electrodes, and the like.
  • a vertical electric field mode display such as TN (Twist) can be formed. Nematic) mode, VA (Vertical Alignment) mode, and MVA (Multi-domain Vertical) developed to solve narrow viewing angles Alignment).
  • IPS In-plane switching
  • FFS Frringe
  • the conventional liquid crystal display panel includes a plurality of scan lines G0-G7, a plurality of data lines D1-D3, and a plurality of pixels, and each row of pixels corresponds to two scan lines. That is, the number of scan lines is twice the horizontal resolution, and each data line drives the left and right columns of pixels, that is, the number of data lines is twice the vertical resolution.
  • Data1 represents the waveform of the data signal input by the data line D1
  • Data2 represents the waveform of the data signal input by the data line D2
  • Gate1 represents the waveform of the scanning signal input by the first scanning line G1.
  • Gate2 represents the waveform of the scan signal input by the second scan line G2;
  • Pixel11 represents the actual voltage waveform of the pixel 101 in FIG. 1
  • Pixel12 represents the actual voltage waveform of the pixel 102 in FIG. 1
  • Pixel21 represents the actual voltage of the pixel 103 in FIG. Waveform
  • Pixel22 represents the actual voltage waveform of pixel 104 in FIG. 1;
  • the charging rate is low, and the pixel 102 is located before the polarity of the data signal is reversed, so the charging rate is high. It can be seen that the charging rates of two adjacent pixels are largely different, so that flicker and afterimage are easily generated.
  • An object of the present invention is to provide a liquid crystal display panel and device capable of improving display performance.
  • the present invention provides a liquid crystal display panel including: a plurality of data lines, a plurality of scan lines, m common lines, and a plurality of pixels, wherein the plurality of pixels form N rows of pixels and M columns of pixels.
  • Each row of pixels is correspondingly provided with two scan lines, and each of the two columns of pixels is correspondingly provided with one data line;
  • each common line corresponds to at least one column of pixels, and the common line is used for inputting a common voltage;
  • the pixel includes a first thin film transistor, and a gate of the first thin film transistor located in the nth row and 2k+1th column pixel is connected to a second scan line of the n-1th row of pixels, where the nth row is 2k+ a source of the first thin film transistor of one column of pixels is connected to a corresponding common line, and a drain of the first thin film transistor of the pixel of the nth row and the second k+1 column is connected to the pixel of the nth row and the second k+1 column;
  • a gate of the first thin film transistor located in the nth row and 2kth column of pixels is connected to a first scan line of the nth row of pixels, and a source of the first thin film transistor located in the nth row and 2kth column of pixels is corresponding to a common a line connection, the drain of the first thin film transistor located in the nth row and the 2kth column pixel is connected to the nth row and the 2kth column pixel; 0 ⁇ n ⁇ N, N ⁇ 2, 0 ⁇ k ⁇ (M-1) /2, M ⁇ m ⁇ 2;
  • the pixel further includes a second thin film transistor, and a gate of the second thin film transistor located in the nth row and the 2k+1th column pixel is connected to a first scan line of the nth row of pixels, where the nth row is 2k+1
  • the source of the second thin film transistor of the column pixel is connected to the corresponding data line, and the drain of the second thin film transistor located in the nth row and the 2k+1th column pixel is connected to the nth row and the 2k+1th column pixel;
  • a gate of the second thin film transistor located in the nth row and the 2kth row of pixels is connected to a second scan line of the nth row of pixels, and a source and a corresponding data of the second thin film transistor located in the nth row and the 2kth column of pixels a line connection, the drain of the second thin film transistor located in the nth row and the 2kth column pixel is connected to the nth row and the 2kth column pixel;
  • the pixel of the first column corresponds to the first common line
  • the pixel of the Mth column corresponds to the mth common line
  • the pixels of the second column to the M-1 column correspond to one common line.
  • the voltages of the two pixels located on the same side of the adjacent two data lines in the same row are opposite in polarity.
  • the first thin film transistor is configured to input the common voltage to the pixel before the pixel inputs a data signal.
  • two adjacent common lines are located on both sides of adjacent two columns of pixels.
  • the voltage of the pixel before the input of the data voltage is equal to the common voltage.
  • the present invention provides a liquid crystal display panel including: a plurality of data lines, a plurality of scan lines, m common lines, and a plurality of pixels, wherein the plurality of pixels form N rows of pixels and M columns of pixels, and each row of pixels corresponds to a setting Two scanning lines, one data line corresponding to each two columns of pixels; each common line corresponding to at least one column of pixels, the common line is used for inputting a common voltage;
  • the pixel includes a first thin film transistor, and a gate of the first thin film transistor located in the nth row and 2k+1th column pixel is connected to a second scan line of the n-1th row of pixels, where the nth row is 2k+ a source of the first thin film transistor of one column of pixels is connected to a corresponding common line, and a drain of the first thin film transistor of the pixel of the nth row and the second k+1 column is connected to the pixel of the nth row and the second k+1 column;
  • a gate of the first thin film transistor located in the nth row and 2kth column of pixels is connected to a first scan line of the nth row of pixels, and a source of the first thin film transistor located in the nth row and 2kth column of pixels is corresponding to a common a line connection, the drain of the first thin film transistor located in the nth row and the 2kth column pixel is connected to the nth row and the 2kth column pixel; 0 ⁇ n ⁇ N, N ⁇ 2, 0 ⁇ k ⁇ (M-1) /2, M ⁇ m ⁇ 2.
  • the first column of pixels corresponds to the first common line
  • the Mth column of pixels corresponds to the mth common line
  • the second column to the M-1 column of pixels, each of the two columns of pixels corresponds to a common line.
  • the pixel further includes a second thin film transistor, and a gate of the second thin film transistor located in the nth row and the 2k+1th column pixel is connected to the first scan line of the nth row of pixels.
  • the source of the second thin film transistor in the second row of the 2k+1th column pixel is connected to the corresponding data line, and the drain and the nth row of the second thin film transistor located in the nth row and 2k+1th column of pixels 2k+1 column pixel connection;
  • a gate of the second thin film transistor located in the nth row and the 2kth row of pixels is connected to a second scan line of the nth row of pixels, and a source and a corresponding data of the second thin film transistor located in the nth row and the 2kth column of pixels
  • the drain of the second thin film transistor located in the nth row and the 2kth column of pixels is connected to the nth row and the 2kth column of pixels.
  • the voltages of the two pixels located on the same side of the adjacent two data lines in the same row are opposite in polarity.
  • the first thin film transistor is configured to input the common voltage to the pixel before the pixel inputs a data signal.
  • two adjacent common lines are located on both sides of adjacent two columns of pixels.
  • the voltage of the pixel before the input of the data voltage is equal to the common voltage.
  • the invention also provides a liquid crystal display device comprising:
  • a liquid crystal display panel comprising:
  • each common line corresponds to at least one column of pixels, and the common line is used for inputting a common voltage
  • the pixel includes a first thin film transistor, and a gate of the first thin film transistor located in the nth row and 2k+1th column pixel is connected to a second scan line of the n-1th row of pixels, where the nth row is 2k+ a source of the first thin film transistor of one column of pixels is connected to a corresponding common line, and a drain of the first thin film transistor of the pixel of the nth row and the second k+1 column is connected to the pixel of the nth row and the second k+1 column;
  • a gate of the first thin film transistor located in the nth row and 2kth column of pixels is connected to a first scan line of the nth row of pixels, and a source of the first thin film transistor located in the nth row and 2kth column of pixels is corresponding to a common a line connection, the drain of the first thin film transistor located in the nth row and the 2kth column pixel is connected to the nth row and the 2kth column pixel; 0 ⁇ n ⁇ N, N ⁇ 2, 0 ⁇ k ⁇ (M-1) /2, M ⁇ m ⁇ 2.
  • the first column of pixels corresponds to the first common line
  • the Mth column of pixels corresponds to the mth common line
  • the second column to the M-1 column of pixels, each of the two columns of pixels corresponds to a common line line.
  • the pixel further includes a second thin film transistor, and the gate of the second thin film transistor located in the nth row and the 2k+1th column pixel is connected to the first scan line of the nth row of pixels.
  • the source of the second thin film transistor in the second row of the 2k+1th column pixel is connected to the corresponding data line, and the drain and the nth row of the second thin film transistor located in the nth row and 2k+1th column of pixels 2k+1 column pixel connection;
  • a gate of the second thin film transistor located in the nth row and the 2kth row of pixels is connected to a second scan line of the nth row of pixels, and a source and a corresponding data of the second thin film transistor located in the nth row and the 2kth column of pixels
  • the drain of the second thin film transistor located in the nth row and the 2kth column of pixels is connected to the nth row and the 2kth column of pixels.
  • the polarities of the voltages of the two pixels located on the same side of the adjacent two data lines in the same row are opposite.
  • the first thin film transistor is configured to input the common voltage to the pixel before the pixel inputs a data signal.
  • two adjacent common lines are located on both sides of adjacent two columns of pixels.
  • the voltage of the pixel before the input of the data voltage is equal to the common voltage.
  • the liquid crystal display panel and device of the present invention since the voltages of the adjacent two pixels before and after the inversion are charged to the common electrode in advance, the difference in the charging rates of the adjacent two pixels is reduced, and the occurrence of flicker and afterimage is avoided. The display effect of the liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a conventional liquid crystal display panel
  • FIG. 2 is a waveform diagram of a driving signal corresponding to FIG. 1;
  • FIG. 3 is a schematic structural view of a liquid crystal display panel of the present invention.
  • FIG. 4 is a waveform diagram of a driving signal corresponding to FIG. 3;
  • FIG. 5 is a schematic structural view of a single pixel in FIG. 3.
  • FIG. 5 is a schematic structural view of a single pixel in FIG. 3.
  • FIG. 3 is a schematic structural diagram of a liquid crystal display panel according to the present invention.
  • the liquid crystal display panel of the present embodiment includes a plurality of scanning lines G0-G7, a plurality of data lines D1-D3, m common lines com, and a plurality of pixels.
  • the plurality of pixels form N rows of pixels and M columns of pixels, the pixels including red pixels 201, green pixels 202, and blue pixels 203.
  • the colors of the adjacent two columns of pixels are different, that is, the pixels in the same column have the same color, and the colors of the adjacent two pixels in the same row are different.
  • the first column of pixels is R
  • the second column of pixels is G
  • the third column of pixels is B.
  • Two scanning lines are correspondingly arranged for each row of pixels, for example, two scanning lines G1 and G2 are correspondingly arranged in the first row of pixels.
  • a data line is set corresponding to every two columns of pixels.
  • the first column of pixels corresponds to the first common line
  • the Mth column of pixels corresponds to the mth common line, that is, the last column of pixels corresponds to the last common line
  • the second column of pixels to the M-1th column of pixels, every two columns of pixels
  • Corresponding to a common line for example, the first column of pixels is connected to the first common line, the second column of pixels and the third column of pixels are connected to the second common line, for example, the fourth column pixel and the fifth column pixel are connected to the third common line
  • the sixth column of pixels is connected to the fourth common line.
  • the two adjacent common lines are located on opposite sides of the adjacent two columns of pixels.
  • the first common line and the second common line are respectively located on the left and right sides of the pixels of the first column and the second column.
  • Each common line com is used to input the voltage of the common electrode, that is, the common voltage.
  • Each of the pixels includes a first thin film transistor T1 and a second thin film transistor T2, and a gate of the first thin film transistor T1 located in the nth row and 2k+1th column of pixels is connected to a second scan line of the n-1th row of pixels.
  • the source of the first thin film transistor T1 located in the nth row 2k+1 column (odd column) pixel is connected to a corresponding common line, and the drain of the first thin film transistor T1 located in the nth row 2k+1th column pixel
  • the pole is connected to the nth row 2k+1 column pixel.
  • the gate of the first thin film transistor T1 of the pixel in the first row and the first column is connected to the scanning line G0
  • the source of the first thin film transistor T1 is connected to the first common line
  • the drain thereof and the first row are 1 column of pixel connections.
  • the gate of the first thin film transistor T1 located in the nth row and the 2kth column (even column) is connected to the first scan line of the nth row of pixels, and the source of the first thin film transistor T1 located in the nth row and 2kth column of pixels
  • the pole is connected to the corresponding common line, and the drain of the first thin film transistor T1 located in the pixel of the nth row and the second column is connected to the pixel of the nth row and the second column.
  • the gate of the first thin film transistor T1 of the pixel in the first row and the second column is connected to the scanning line G1, and the source of the first thin film transistor T1 is connected to the second common line, and the drain thereof and the first row are 2 columns of pixel connections, where 0 ⁇ n ⁇ N, N ⁇ 2, 0 ⁇ k ⁇ (M-1)/2; M ⁇ m ⁇ 2.
  • the gate of the second thin film transistor T2 located in the 2k+1th column of the nth row is connected to the first scan line of the nth row of pixels, and the source of the second thin film transistor T2 located in the nth row and 2k+1th column of pixels
  • the pole is connected to the corresponding data line
  • the drain of the second thin film transistor T2 located in the nth row 2k+1th column pixel is connected to the nth row and 2k+1th column pixel.
  • the gate of the second thin film transistor T2 of the pixel in the first row and the first column is connected to the scanning line G1
  • the source of the second thin film transistor T2 is connected to the data line D1
  • the drain thereof and the first row and the first column Pixel connection is
  • the gate of the second thin film transistor T2 located in the pixel of the nth row and the second column is connected to the second scan line of the pixel of the nth row, and the source and corresponding data of the second thin film transistor T2 of the pixel of the nth row and the second column of the column are connected.
  • the drain is connected to the drain of the second thin film transistor T2 located in the nth row and the 2kth column pixel, and is connected to the nth row and the 2kth column of pixels.
  • the gate of the second thin film transistor T2 of the pixel in the first row and the second column is connected to the scanning line G2
  • the source of the second thin film transistor T2 is connected to the data line D1
  • the drain thereof and the first row and the second column Pixel connection is connected to the scanning line G2
  • the first thin film transistor T1 is configured to input a common voltage to the pixel to precharge the pixel before the pixel inputs a data signal, and the common line is used to input a common voltage, that is, a common electrode Voltage.
  • the voltages of the two pixels located on the same side of the adjacent two data lines in the same row are opposite in polarity.
  • the polarity of the voltage of the pixel 201 on the left side of the data line D1 and the pixel 203 on the left side of the data line D2 are opposite.
  • the polarity of the voltage of the pixel 202 on the right side of the data line D1 and the pixel 204 on the right side of the data line D2 are opposite.
  • FIG. 4 please refer to FIG. 4.
  • the voltages of the two pixels located on both sides of the same data line in the same row have the same polarity.
  • the polarity of the pixel 201 on the left side of the data line D1 and the pixel 202 on the right side in the first row are both negative.
  • the voltage of each pixel before the input data voltage is equal to the common voltage, please refer to FIG. 4 for details.
  • Data1 represents the waveform of the data signal input by the data line D1;
  • Data2 represents the waveform of the data signal input by the data line D2;
  • Gate1 represents the waveform of the scanning signal input by the scanning line G0, and Gate1 represents The waveform of the scan signal input by the scan line G1;
  • Gate2 represents the waveform of the scan signal input by the scan line G2;
  • P1 represents the actual voltage waveform of the pixel 201 in FIG. 3
  • P2 represents the actual voltage waveform of the pixel 202 in FIG. 3;
  • P3 represents FIG.
  • the actual voltage waveform of the middle pixel 203, P4 represents the actual voltage waveform of the pixel 204 in FIG. 3;
  • V0 represents the voltage of the common electrode, that is, the voltage of the common electrode on the array substrate side.
  • the voltage of the scan signal of the scan line G1 is at a low level, and the voltage of the scan signal of the scan line G0 is at a high level.
  • the first thin film transistor T1 of the pixel 201 is closed, and the pixel 201 is input to the common electrode.
  • the voltage V0 that is, the pixel 201 is precharged.
  • the voltage of the scan signal of the scan line G1 is at a high level.
  • the second thin film transistor T2 of the pixel 201 is closed, and the pixel 201 inputs the data voltage of the data line D1, due to the voltage of the data signal Data1 during this period.
  • the voltage of P1 changes to the voltage of Data1, that is, the voltage decreases. after that, P1 maintains the current voltage.
  • the voltage of the scan signal of the scan line G1 is at a low level, and the voltage of the scan signal of the scan line G2 is at a low level.
  • the first thin film transistor T1 and the second thin film transistor T2 of the pixel 202 are both off.
  • the voltage of P2 is the initial level.
  • the voltage of the scan signal of the scanning line G1 is at a high level.
  • the first thin film transistor T1 of the pixel 202 is closed, and the pixel 202 is input with the voltage V0 of the common electrode, and the voltage of this P2 changes to V0.
  • the voltage of the scan signal of the scan line G1 is at a low level, at which time the first thin film transistor T1 of the pixel is turned off, and the voltage of the scan signal of the scan line G2 is at a high level, at this time, the pixel The second thin film transistor T2 of 202 is closed, and the pixel 202 inputs the data voltage of the data line D1. Since the data voltage of the input data line D1 is at a low level at this time, the voltage of P2 is the voltage of Data1, that is, the voltage drops again. After that, P2 maintains the current voltage.
  • the voltage of the scan signal of the scan line G1 is at a low level, and the voltage of the scan signal of the scan line G0 is at a high level.
  • the first thin film transistor T1 of the pixel 203 is closed, and the pixel 203 is input to the common electrode.
  • the voltage V0 that is, the pixel is precharged.
  • the voltage of the scan signal of the scan line G1 is at a high level, at which time the second thin film transistor T2 of the pixel 203 is closed, and the pixel 203 is input to the data voltage of the data line D2, due to the voltage of the data signal Data2 during this period.
  • the voltage of P3 changes to the voltage of Data2, that is, it changes to high level. After that, P3 maintains the current voltage.
  • the voltage of the scan signal of the scan line G1 is at a low level, and the voltage of the scan signal of the scan line G2 is at a low level.
  • the first thin film transistor T1 and the second thin film transistor T2 of the pixel 204 are both off.
  • the voltage of P4 is the initial level.
  • the voltage of the scan signal of the scan line G1 is at a high level.
  • the first thin film transistor T1 of the pixel 204 is closed, and the pixel 204 inputs the voltage V0 of the common electrode, that is, the voltage of the P4 changes to the common electrode. Voltage V0.
  • the voltage of the scan signal of the scan line G1 is at a low level, at which time the first thin film transistor T1 of the pixel is turned off, and the voltage of the scan signal of the scan line G2 is at a high level, at this time, the pixel
  • the second thin film transistor T2 of 204 is closed, 204 inputs the data voltage of the data line D2. Since the data voltage of the input data line D2 is at a high level at this time, the voltage of P4 changes to the voltage of Data2, that is, rises again. P4 then maintains the current voltage.
  • the pixels in the first row and the first column are located after the polarity is reversed, and the pixels in the first row and the second column are located before the polarity inversion, but the two pixels are precharged to the potential of the common electrode, thereby reducing The difference in charging rate between the two pixels avoids flicker and afterimage of the liquid crystal display panel.
  • each pixel has a data line 11 in the vertical direction, a scanning line 12 in the horizontal direction, a common line 13 in the vertical direction, or a common line in the horizontal direction.
  • each pixel has two thin film transistors T1 and T2, T1 is used to precharge the first pixel and charge the adjacent two pixels before charging the first one of the adjacent two pixels When the first pixel is charged, the second pixel is precharged to precharge each pixel to the potential of the common electrode; T2 is used to charge each pixel, that is, to input to the pixel electrode 15 of each pixel.
  • the data voltage is such that it displays the grayscale value of the actual picture.
  • the embodiment of the invention further provides a liquid crystal display device comprising a backlight module and the above liquid crystal display panel.
  • the liquid crystal display panel and device of the present invention since the voltages of the adjacent two pixels before and after the inversion are charged to the common electrode in advance, the difference in the charging rates of the adjacent two pixels is reduced, and the occurrence of flicker and afterimage is avoided. The display effect of the liquid crystal display panel.

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Abstract

一种液晶显示面板及装置，面板包括：位于第n行第2k+1列像素的第一薄膜晶体管(T1)的栅极与第n-1行像素的第二扫描线连接，位于第n行第2k+1列像素的第一薄膜晶体管(T1)的源极与对应的公共线连接，位于第n行第2k+1列像素的第一薄膜晶体管(T1)的漏极与第n行第2k+1列像素连接。

Description

一种液晶显示面板及装置 技术领域
本发明涉及显示器技术领域，特别是涉及一种液晶显示面板及装置。
 背景技术
液晶显示器是目前使用最广泛的一种平板显示器，被应用在各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕中。
目前普遍采用的液晶显示器，通常由上下衬底和液晶层组成，衬底由玻璃和电极等组成。当上下衬底都设置电极时，可以形成纵向电场模式的显示器，如TN（Twist Nematic）模式、VA（Vertical Alignment）模式以及为了解决视角过窄开发的MVA（Multi-domain Vertical Alignment）。当仅在一侧的衬底上设置电极时，形成横向电场模式的显示器，如IPS（In-plane switching）模式和FFS（Fringe Field Switching）模式等。
如图1所示，现有的液晶显示面板包括多条扫描线G0-G7、多条数据线D1-D3以及多个像素，每行像素对应两条扫描线， 也即扫描线的数量为水平解析度的2倍，每一条数据线驱动左右两列像素，也即数据线的数量为垂直解析度的2倍。如图2所示，在具体驱动过程中，Data1表示数据线D1输入的数据信号的波形；Data2表示数据线D2输入的数据信号的波形；Gate1表示第一条扫描线G1输入的扫描信号的波形；Gate2表示第二条扫描线G2输入的扫描信号的波形；Pixel11表示图1中像素101的实际电压波形，Pixel12表示图1中像素102的实际电压波形；Pixel21表示图1中像素103的实际电压波形，Pixel22表示图1中像素104的实际电压波形；
由于像素101位于数据信号极性反转后，因此充电率低，像素102位于数据信号极性反转前，因此充电率高。可见相邻两个像素的充电率差别较大，因而容易产生闪烁和残像现象。
因此，有必要提供一种液晶显示面板及装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶显示面板及装置，能够提高显示效果。
 技术解决方案
为解决上述技术问题，本发明提供一种液晶显示面板，其包括：多条数据线、多条扫描线、m条公共线以及多个像素，所述多个像素形成N行像素和M列像素，每行像素对应设置两条扫描线，每两列像素对应设置一条数据线；每条公共线对应至少一列像素，所述公共线用于输入公共电压；
所述像素包括第一薄膜晶体管，位于第n行第2k+1列像素的第一薄膜晶体管的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的漏极与第n行第2k+1列像素连接；
位于第n行第2k列像素的第一薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k列像素的第一薄膜晶体管的漏极与第n行第2k列像素连接；0＜n＜N，N≥2，0≤k≤（M-1）/2，M≥m≥2；
所述像素还包括第二薄膜晶体管，位于第n行第2k+1列像素的第二薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的漏极与第n行第2k+1列像素连接；
位于第n行第2k列像素的第二薄膜晶体管的栅极与第n行像素的第二扫描线连接，所述位于第n行第2k列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k列像素的第二薄膜晶体管的漏极与第n行第2k列像素连接；
其中第1列像素对应第1条公共线对应，第M列像素对应第m条公共线；第2列至M-1列像素中，每两列像素对应一条公共线。
在本发明的液晶显示面板中，同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。
在本发明的液晶显示面板中，所述第一薄膜晶体管用于在所述像素输入数据信号前，向所述像素输入所述公共电压。
在本发明的液晶显示面板中，相邻两条公共线位于相邻两列像素的两侧。
在本发明的液晶显示面板中，所述像素在输入数据电压之前的电压等于所述公共电压。
本发明提供一种液晶显示面板，其包括：多条数据线、多条扫描线、m条公共线以及多个像素，所述多个像素形成N行像素和M列像素，每行像素对应设置两条扫描线，每两列像素对应设置一条数据线；每条公共线对应至少一列像素，所述公共线用于输入公共电压；
所述像素包括第一薄膜晶体管，位于第n行第2k+1列像素的第一薄膜晶体管的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的漏极与第n行第2k+1列像素连接；
位于第n行第2k列像素的第一薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k列像素的第一薄膜晶体管的漏极与第n行第2k列像素连接；0＜n＜N，N≥2，0≤k≤（M-1）/2，M≥m≥2。
在本发明的液晶显示面板中，第1列像素对应第1条公共线对应，第M列像素对应第m条公共线；第2列至M-1列像素中，每两列像素对应一条公共线。
在本发明的液晶显示面板中，所述像素还包括第二薄膜晶体管，位于第n行第2k+1列像素的第二薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的漏极与第n行第2k+1列像素连接；
位于第n行第2k列像素的第二薄膜晶体管的栅极与第n行像素的第二扫描线连接，所述位于第n行第2k列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k列像素的第二薄膜晶体管的漏极与第n行第2k列像素连接。
在本发明的液晶显示面板中，同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。
在本发明的液晶显示面板中，所述第一薄膜晶体管用于在所述像素输入数据信号前，向所述像素输入所述公共电压。
在本发明的液晶显示面板中，相邻两条公共线位于相邻两列像素的两侧。
在本发明的液晶显示面板中，所述像素在输入数据电压之前的电压等于所述公共电压。
本发明还提供一种液晶显示装置，其包括：
背光模块；以及
液晶显示面板，其包括：
多条数据线、多条扫描线、m条公共线以及多个像素，所述多个像素形成N行像素和M列像素，每行像素对应设置两条扫描线，每两列像素对应设置一条数据线；每条公共线对应至少一列像素，所述公共线用于输入公共电压；
所述像素包括第一薄膜晶体管，位于第n行第2k+1列像素的第一薄膜晶体管的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的漏极与第n行第2k+1列像素连接；
位于第n行第2k列像素的第一薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k列像素的第一薄膜晶体管的漏极与第n行第2k列像素连接；0＜n＜N，N≥2，0≤k≤（M-1）/2，M≥m≥2。
在本发明的液晶显示装置中，第1列像素对应第1条公共线对应，第M列像素对应第m条公共线；第2列至M-1列像素中，每两列像素对应一条公共线。
在本发明的液晶显示装置中，所述像素还包括第二薄膜晶体管，位于第n行第2k+1列像素的第二薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的漏极与第n行第2k+1列像素连接；
位于第n行第2k列像素的第二薄膜晶体管的栅极与第n行像素的第二扫描线连接，所述位于第n行第2k列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k列像素的第二薄膜晶体管的漏极与第n行第2k列像素连接。
在本发明的液晶显示装置中，同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。
在本发明的液晶显示装置中，所述第一薄膜晶体管用于在所述像素输入数据信号前，向所述像素输入所述公共电压。
在本发明的液晶显示装置中，相邻两条公共线位于相邻两列像素的两侧。
在本发明的液晶显示装置中，所述像素在输入数据电压之前的电压等于所述公共电压。
 有益效果
本发明的液晶显示面板及装置，由于预先将反转前后的相邻两个像素都充到公共电极的电压，从而缩小了相邻两个像素充电率的差异，避免产生闪烁和残像现象，提高了液晶显示面板的显示效果。
附图说明
图1为现有液晶显示面板的结构示意图；
图2为图1对应的驱动信号的波形图；
图3为本发明液晶显示面板的结构示意图；
图4为图3对应的驱动信号的波形图；
图5为图3中单个像素的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图3-5，图3为本发明液晶显示面板的结构示意图。
如图3所示，本实施例的液晶显示面板包括：多条扫描线G0-G7、多条数据线D1-D3、m条公共线com以及多个像素。多个像素形成N行像素和M列像素，所述像素包括红色像素201、绿色像素202以及蓝色像素203。其中相邻两列像素的颜色不同，也即位于同一列的像素的颜色相同，位于同一行中相邻两个像素的颜色不同。比如第一列像素为R，第二列像素为G，第三列像素为B。
每行像素对应设置两条扫描线，比如第一行像素对应设置两条扫描线G1、G2。每两列像素对应设置一条数据线。第1列像素对应第1条公共线，第M列像素对应第m条公共线，也即最后一列像素对应最后一条公共线，第2列像素至第M-1列像素中，每两列像素对应一条公共线；比如第1列像素连接第1条公共线，第2列像素和第3列像素连接第2条公共线，比如第4列像素和第5列像素连接第3条公共线，第6列像素连接第4条公共线。其中相邻两条公共线位于相邻两列像素的两侧。比如，第1条公共线和第2条公共线分别位于第一列和第二列像素的左右两侧。每条公共线com用于输入公共电极的电压，也即公共电压。
每个像素包括第一薄膜晶体管T1和第二薄膜晶体管T2，位于第n行第2k+1列像素的第一薄膜晶体管T1的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列（奇数列）像素的第一薄膜晶体管T1的源极与对应的公共线连接，该位于第n行第2k+1列像素的第一薄膜晶体管T1的漏极与该第n行第2k+1列像素连接。比如第1行第1列的像素的第一薄膜晶体管T1的栅极与扫描线G0连接，该第一薄膜晶体管T1的源极与第1条公共线连接，其漏极与该第1行第1列的像素连接。
位于第n行第2k列（偶数列）像素的第一薄膜晶体管T1的栅极与第n行像素的第一扫描线连接，该位于第n行第2k列像素的第一薄膜晶体管T1的源极与对应的公共线连接，该位于第n行第2k列像素的第一薄膜晶体管T1的漏极与第n行第2k列像素连接。比如第1行第2列的像素的第一薄膜晶体管T1的栅极与扫描线G1连接，该第一薄膜晶体管T1的源极与第2条公共线连接，其漏极与该第1行第2列的像素连接，其中0＜n＜N，N≥2，0≤k≤（M-1）/2；M≥m≥2。
位于第n行第2k+1列像素的第二薄膜晶体管T2的栅极与第n行像素的第一扫描线连接，该位于第n行第2k+1列像素的第二薄膜晶体管T2的源极与对应的数据线连接，该位于第n行第2k+1列像素的第二薄膜晶体管T2的漏极与第n行第2k+1列像素连接。比如第1行第1列的像素的第二薄膜晶体管T2的栅极与扫描线G1连接，该第二薄膜晶体管T2的源极与数据线D1连接，其漏极与该第1行第1列的像素连接。
位于第n行第2k列像素的第二薄膜晶体管T2的栅极与第n行像素的第二扫描线连接，位于第n行第2k列像素的第二薄膜晶体管T2的源极与对应的数据线连接，位于第n行第2k列像素的第二薄膜晶体管T2的漏极与该第n行第2k列像素连接。比如第1行第2列的像素的第二薄膜晶体管T2的栅极与扫描线G2连接，该第二薄膜晶体管T2的源极与数据线D1连接，其漏极与该第1行第2列的像素连接。
所述第一薄膜晶体管T1，用于在所述像素输入数据信号前，向所述像素输入公共电压，以对所述像素进行预充电，所述公共线用于输入公共电压，也即公共电极的电压。
优选地，同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。比如数据线D1左侧的像素201和数据线D2左侧的像素203的电压的极性相反。比如数据线D1右侧的像素202和数据线D2右侧的像素204的电压的极性相反，具体请参照图4。
优选地，同一行中位于同一数据线两侧的两个像素的电压的极性相同。比如图3中，第一行中数据线D1左侧的像素201和右侧的像素202的极性都为负。
优选地，每个像素在输入数据电压之前的电压等于公共电压，具体请参照图4。
如图4所示，在具体驱动过程中，Data1表示数据线D1输入的数据信号的波形；Data2表示数据线D2输入的数据信号的波形；Gate1表示扫描线G0输入的扫描信号的波形，Gate1表示扫描线G1输入的扫描信号的波形；Gate2表示扫描线G2输入的扫描信号的波形；P1表示图3中像素201的实际电压波形，P2表示图3中像素202的实际电压波形；P3表示图3中像素203的实际电压波形，P4表示图3中像素204的实际电压波形；V0表示公共电极的电压，也即阵列基板侧公共电极的电压。
在t1-t2时段，扫描线G1的扫描信号的电压为低电平，扫描线G0的扫描信号的电压为高电平，此时像素201的第一薄膜晶体管T1闭合，像素201输入公共电极的电压V0，也即对该像素201进行预充电。在t2-t3时段，扫描线G1的扫描信号的电压为高电平，此时该像素201的第二薄膜晶体管T2闭合，像素201输入数据线D1的数据电压，由于此时段数据信号Data1的电压为低电平，P1的电压变化至Data1的电压，也即电压降低。之后， P1维持当前的电压。
在t1-t2时段，扫描线G1的扫描信号的电压为低电平，扫描线G2的扫描信号的电压为低电平，此时像素202的第一薄膜晶体管T1和第二薄膜晶体管T2都断开，P2的电压为初始电平。在t2-t3时段，扫描线G1的扫描信号的电压为高电平，此时像素202的第一薄膜晶体管T1闭合，像素202输入公共电极的电压V0，此P2的电压变化至V0。在t3-t4时段，扫描线G1的扫描信号的电压为低电平，此时该像素的第一薄膜晶体管T1断开，且扫描线G2的扫描信号的电压为高电平，此时该像素202的第二薄膜晶体管T2闭合，像素202输入数据线D1的数据电压，由于此时输入数据线D1的数据电压为低电平，因此P2的电压为Data1的电压，也即电压再次下降。之后，P2维持当前的电压。
在t1-t2时段，扫描线G1的扫描信号的电压为低电平，扫描线G0的扫描信号的电压为高电平，此时像素203的第一薄膜晶体管T1闭合，像素203输入公共电极的电压V0，也即对该像素进行预充电。在t2-t3时段，扫描线G1的扫描信号的电压为高电平，此时该像素203的第二薄膜晶体管T2闭合，像素203输入数据线D2的数据电压，由于此时段数据信号Data2的电压为高电平，P3的电压变化至Data2的电压，也即变化至高电平。之后，P3维持当前电压。
在t1-t2时段，扫描线G1的扫描信号的电压为低电平，扫描线G2的扫描信号的电压为低电平，此时像素204的第一薄膜晶体管T1和第二薄膜晶体管T2都断开，P4的电压为初始电平。
在t2-t3时段，扫描线G1的扫描信号的电压为高电平，此时像素204的第一薄膜晶体管T1闭合，像素204输入公共电极的电压V0，也即P4的电压变化至公共电极的电压V0。在t3-t4时段，扫描线G1的扫描信号的电压为低电平，此时该像素的第一薄膜晶体管T1断开，且扫描线G2的扫描信号的电压为高电平，此时该像素204的第二薄膜晶体管T2闭合，204输入数据线D2的数据电压，由于此时输入数据线D2的数据电压为高电平，因此P4的电压变化至Data2的电压，也即再次上升。之后P4维持当前电压。
由此看出，第一行第1列像素位于极性反转后，第一行第2列像素位于极性反转前，但是这两个像素都是预先充电到公共电极的电位，从而缩小了两个像素充电率的差异，避免液晶显示面板出现闪烁和残像现象。
图5是本发明的液晶显示器中单个像素的结构，如图5所示，每个像素都具有垂直方向的数据线11、水平方向的扫描线12、垂直方向公共线13或水平方向的公共线14，每个像素有两个薄膜晶体管T1和T2，T1用于在对相邻两个像素中的第一个像素充电前，对第一个像素进行预充电以及在对相邻两个像素中的第一个像素充电时，对第二个像素进行预充电，使每个像素预充电到公共电极的电位；T2用于对每个像素进行充电，也即向每个像素的像素电极15输入数据电压，使其显示实际画面的灰阶值。
本发明实施例还提供一种液晶显示装置，其包括背光模块及上述的液晶显示面板。
本发明的液晶显示面板及装置，由于预先将反转前后的相邻两个像素都充到公共电极的电压，从而缩小了相邻两个像素充电率的差异，避免产生闪烁和残像现象，提高了液晶显示面板的显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种液晶显示面板，其包括：多条数据线、多条扫描线、m条公共线以及多个像素，所述多个像素形成N行像素和M列像素，每行像素对应设置两条扫描线，每两列像素对应设置一条数据线；每条公共线对应至少一列像素，所述公共线用于输入公共电压；
    所述像素包括第一薄膜晶体管，位于第n行第2k+1列像素的第一薄膜晶体管的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的漏极与第n行第2k+1列像素连接；
    位于第n行第2k列像素的第一薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k列像素的第一薄膜晶体管的漏极与第n行第2k列像素连接；0＜n＜N，N≥2，0≤k≤（M-1）/2，M≥m≥2；
    所述像素还包括第二薄膜晶体管，位于第n行第2k+1列像素的第二薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的漏极与第n行第2k+1列像素连接；
    位于第n行第2k列像素的第二薄膜晶体管的栅极与第n行像素的第二扫描线连接，所述位于第n行第2k列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k列像素的第二薄膜晶体管的漏极与第n行第2k列像素连接；
    其中第1列像素对应第1条公共线对应，第M列像素对应第m条公共线；第2列至M-1列像素中，每两列像素对应一条公共线。
  2. 根据权利要求1所述的液晶显示面板，其中同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。
  3. 根据权利要求1所述的液晶显示面板，其中
    所述第一薄膜晶体管用于在所述像素输入数据信号前，向所述像素输入所述公共电压。
  4. 根据权利要求1所述的液晶显示面板，其中相邻两条公共线位于相邻两列像素的两侧。
  5. 根据权利要求1所述的液晶显示面板，其中所述像素在输入数据电压之前的电压等于所述公共电压。
  6. 一种液晶显示面板，其包括：多条数据线、多条扫描线、m条公共线以及多个像素，所述多个像素形成N行像素和M列像素，每行像素对应设置两条扫描线，每两列像素对应设置一条数据线；每条公共线对应至少一列像素，所述公共线用于输入公共电压；
    所述像素包括第一薄膜晶体管，位于第n行第2k+1列像素的第一薄膜晶体管的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的漏极与第n行第2k+1列像素连接；
    位于第n行第2k列像素的第一薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k列像素的第一薄膜晶体管的漏极与第n行第2k列像素连接；0＜n＜N，N≥2，0≤k≤（M-1）/2，M≥m≥2。
  7. 根据权利要求6所述的液晶显示面板，其中第1列像素对应第1条公共线对应，第M列像素对应第m条公共线；第2列至M-1列像素中，每两列像素对应一条公共线。
  8. 根据权利要求6所述的液晶显示面板，其中
    所述像素还包括第二薄膜晶体管，位于第n行第2k+1列像素的第二薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的漏极与第n行第2k+1列像素连接；
    位于第n行第2k列像素的第二薄膜晶体管的栅极与第n行像素的第二扫描线连接，所述位于第n行第2k列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k列像素的第二薄膜晶体管的漏极与第n行第2k列像素连接。
  9. 根据权利要求6所述的液晶显示面板，其中同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。
  10. 根据权利要求6所述的液晶显示面板，其中
    所述第一薄膜晶体管用于在所述像素输入数据信号前，向所述像素输入所述公共电压。
  11. 根据权利要求6所述的液晶显示面板，其中相邻两条公共线位于相邻两列像素的两侧。
  12. 根据权利要求6所述的液晶显示面板，其中所述像素在输入数据电压之前的电压等于所述公共电压。
  13. 一种液晶显示装置，其包括：
    背光模块；以及
    液晶显示面板，其包括：
    多条数据线、多条扫描线、m条公共线以及多个像素，所述多个像素形成N行像素和M列像素，每行像素对应设置两条扫描线，每两列像素对应设置一条数据线；每条公共线对应至少一列像素，所述公共线用于输入公共电压；
    所述像素包括第一薄膜晶体管，位于第n行第2k+1列像素的第一薄膜晶体管的栅极与第n-1行像素的第二扫描线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k+1列像素的第一薄膜晶体管的漏极与第n行第2k+1列像素连接；
    位于第n行第2k列像素的第一薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k列像素的第一薄膜晶体管的源极与对应的公共线连接，所述位于第n行第2k列像素的第一薄膜晶体管的漏极与第n行第2k列像素连接；0＜n＜N，N≥2，0≤k≤（M-1）/2，M≥m≥2。
  14. 根据权利要求13所述的液晶显示装置，其中
    第1列像素对应第1条公共线对应，第M列像素对应第m条公共线；第2列至M-1列像素中，每两列像素对应一条公共线。
  15. 根据权利要求13所述的液晶显示装置，其中
    所述像素还包括第二薄膜晶体管，位于第n行第2k+1列像素的第二薄膜晶体管的栅极与第n行像素的第一扫描线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k+1列像素的第二薄膜晶体管的漏极与第n行第2k+1列像素连接；
    位于第n行第2k列像素的第二薄膜晶体管的栅极与第n行像素的第二扫描线连接，所述位于第n行第2k列像素的第二薄膜晶体管的源极与对应的数据线连接，所述位于第n行第2k列像素的第二薄膜晶体管的漏极与第n行第2k列像素连接。
  16. 根据权利要求13所述的液晶显示装置，其中
    同一行中位于相邻两条数据线的同一侧的两个像素的电压的极性相反。
  17. 根据权利要求13所述的液晶显示装置，其中
    所述第一薄膜晶体管用于在所述像素输入数据信号前，向所述像素输入所述公共电压。
  18. 根据权利要求13所述的液晶显示装置，其中相邻两条公共线位于相邻两列像素的两侧。
  19. 根据权利要求13所述的液晶显示装置，其中所述像素在输入数据电压之前的电压等于所述公共电压。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108646480B (zh) * 2018-04-02 2020-12-29 深圳市华星光电半导体显示技术有限公司 一种垂直取向型液晶显示器
CN108957882A (zh) * 2018-07-16 2018-12-07 惠科股份有限公司 一种显示面板及显示装置
KR102571661B1 (ko) * 2018-11-09 2023-08-28 엘지디스플레이 주식회사 표시패널 및 표시장치
KR20240042305A (ko) * 2022-09-23 2024-04-02 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070229419A1 (en) * 2006-03-31 2007-10-04 Ju-Young Lee In plane switching mode liquid crystal display device
KR20130067923A (ko) * 2011-12-14 2013-06-25 엘지디스플레이 주식회사 액정표시장치
CN104730780A (zh) * 2013-12-20 2015-06-24 乐金显示有限公司 液晶显示设备
CN104914640A (zh) * 2015-06-26 2015-09-16 合肥鑫晟光电科技有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN105047166A (zh) * 2015-08-28 2015-11-11 深圳市华星光电技术有限公司 液晶显示面板驱动方法及液晶显示装置
CN105717721A (zh) * 2016-04-13 2016-06-29 深圳市华星光电技术有限公司 阵列基板及液晶显示面板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101354406B1 (ko) * 2008-05-23 2014-01-22 엘지디스플레이 주식회사 액정표시장치
US9007284B2 (en) * 2009-07-30 2015-04-14 Sharp Kabushiki Kaisha Liquid crystal display element, liquid crystal display device, and display method employed in liquid crystal display element
CN202003648U (zh) * 2011-01-28 2011-10-05 深圳华映显示科技有限公司 一种具有预充功能的像素结构
KR102091434B1 (ko) * 2013-07-29 2020-03-23 삼성디스플레이 주식회사 표시 장치
CN104678668A (zh) * 2015-02-09 2015-06-03 深超光电（深圳）有限公司 薄膜晶体管阵列基板及液晶显示面板
CN106959563B (zh) * 2017-05-26 2020-08-18 上海天马微电子有限公司 一种阵列基板及其驱动方法、显示面板、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070229419A1 (en) * 2006-03-31 2007-10-04 Ju-Young Lee In plane switching mode liquid crystal display device
KR20130067923A (ko) * 2011-12-14 2013-06-25 엘지디스플레이 주식회사 액정표시장치
CN104730780A (zh) * 2013-12-20 2015-06-24 乐金显示有限公司 液晶显示设备
CN104914640A (zh) * 2015-06-26 2015-09-16 合肥鑫晟光电科技有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN105047166A (zh) * 2015-08-28 2015-11-11 深圳市华星光电技术有限公司 液晶显示面板驱动方法及液晶显示装置
CN105717721A (zh) * 2016-04-13 2016-06-29 深圳市华星光电技术有限公司 阵列基板及液晶显示面板

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