WO2019033512A1 - 用于oled显示设备的像素驱动电路、oled显示设备 - Google Patents

用于oled显示设备的像素驱动电路、oled显示设备 Download PDF

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Publication number
WO2019033512A1
WO2019033512A1 PCT/CN2017/103563 CN2017103563W WO2019033512A1 WO 2019033512 A1 WO2019033512 A1 WO 2019033512A1 CN 2017103563 W CN2017103563 W CN 2017103563W WO 2019033512 A1 WO2019033512 A1 WO 2019033512A1
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Prior art keywords
signal
threshold voltage
scan signal
thin film
film transistor
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English (en)
French (fr)
Inventor
蔡玉莹
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US15/750,852 priority Critical patent/US10593260B1/en
Publication of WO2019033512A1 publication Critical patent/WO2019033512A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present invention belongs to the field of display technologies, and in particular, to a pixel driving circuit and an OLED display device for an OLED display device.
  • OLED display devices have become very popular emerging flat display devices at home and abroad, because OLED display devices have self-luminous, wide viewing angle, short reaction time, high luminous efficiency, Wide color gamut, low operating voltage, thin thickness, large size and flexible display device, and simple process, and it has the potential for low cost.
  • a thin film transistor In an OLED display device, a thin film transistor (TFT) is generally used in conjunction with a capacitance storage signal to control the brightness gray scale performance of the OLED.
  • TFT thin film transistor
  • each pixel needs to be composed of at least two TFTs and one storage capacitor, that is, 2T1C mode.
  • 1 is a circuit diagram of a pixel driving circuit of a conventional OLED display device.
  • a pixel driving circuit of a conventional OLED display device includes two thin film transistors (TFTs) and a capacitor, specifically, a switching TFT T1, a driving TFT T2, and a storage capacitor Cst.
  • a pixel driving circuit for an OLED display device comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a capacitor, and An organic light emitting diode; a gate of the first thin film transistor is electrically connected to the first node, and a source thereof is electrically connected to the second node; a gate of the second thin film transistor is connected to the second scan signal, and The drain is electrically connected to the first node; the gate of the third thin film transistor is connected to the third scan signal, and the drain thereof is electrically connected to the drain of the first thin film transistor, and the source thereof is electrically Connected to the positive pole of the DC power supply; the gate of the fourth thin film transistor is connected to the first scan signal, and the drain thereof is electrically connected to the second node; one end of the capacitor is electrically connected to the first node, and The other end is electrically connected to the second node; the anode
  • the pixel driving circuit performs a reset operation and a threshold voltage sensing operation.
  • the first scan signal, the second scan signal, and the third scan signal are both high, and the source of the fourth thin film transistor is connected to Said initialization signal.
  • the first scan signal, the second scan signal, and the third scan signal are both high, and the source of the fourth thin film transistor Accessing the threshold voltage detector.
  • the pixel driving circuit performs a reset operation, a threshold voltage detecting operation, a threshold voltage compensation operation, and a driving lighting operation.
  • the first scan signal and the second scan signal are at a high potential
  • the third scan signal is at a low potential
  • the second data signal is The sum of the low potential reference signal and the threshold voltage signal.
  • the first scan signal is low
  • the second scan signal and the third scan signal are high
  • the second data signal is The sum of the low potential reference signal and the threshold voltage signal.
  • the first scan signal and the third scan signal are at a low potential
  • the second scan signal is at a high potential
  • the second data signal is The sum of the high potential display data signal and the threshold voltage signal.
  • the first scan signal and the second scan signal are at a low potential
  • the third scan signal is at a high potential
  • the second data signal is at a low potential
  • an OLED display device comprising the above pixel driving circuit.
  • the OLED display device of the present invention detects the threshold voltage of the driving thin film transistor when the power is turned off or on, and compensates the detected threshold voltage to the driving current of the organic light emitting diode during normal operation display, thereby The influence of the threshold voltage of the driving thin film transistor on the driving current of the organic light emitting diode is eliminated, thereby improving the quality of the display image of the OLED display device.
  • FIG. 1 is a circuit diagram of a pixel driving circuit of a conventional OLED display device
  • FIG. 2 is a block diagram of an organic light emitting diode display device in accordance with an embodiment of the present invention
  • FIG. 3 is a circuit diagram of a pixel driving circuit of an organic light emitting diode display device according to an embodiment of the present invention
  • FIG. 4 is a timing diagram of various stages of operation of a pixel driving circuit when turned off or turned on according to an embodiment of the present invention
  • 5A and 5B are diagrams showing a working process of a pixel driving circuit when turned off or turned on according to an embodiment of the present invention
  • FIG. 6 is a timing diagram of various stages of operation of a pixel driving circuit in a normal operation display according to an embodiment of the present invention
  • FIG. 7A through 7D are diagrams showing the operation of a pixel driving circuit in a normal operation display according to an embodiment of the present invention.
  • FIG. 2 is a block diagram of an organic light emitting diode display device in accordance with an embodiment of the present invention.
  • an organic light emitting diode display device includes a display panel 100, a scan driver 200, and a data driver 300. It should be noted that the OLED display device according to the present invention may further include other suitable devices, such as a timing controller that controls the scan driver 200 and the data driver 300, and a power supply voltage that supplies the power positive voltage and the negative voltage of the power supply. Generator, etc.
  • the display panel 100 includes a plurality of pixels PX arranged in an array, N scanning lines G 1 to G N , and M data lines D 1 to D M .
  • the scan driver 200 is connected to the scan lines G 1 to G N, and drives the scan lines G 1 to G N.
  • the data driver 300 is connected to the data lines D 1 to D M and drives the data lines D 1 to D M .
  • the scan driver 200 is capable of supplying one or more scan signals to each pixel PX, which will be described later.
  • the data driver 300 is capable of providing a data signal to each pixel PX, which will also be described later.
  • Each pixel PX includes a pixel driving circuit.
  • the pixel driving circuit i.e., the pixel structure of the pixel PX
  • the pixel driving circuit will be described in detail below.
  • FIG. 3 is an equivalent circuit diagram of a pixel structure of an organic light emitting diode display device in accordance with an embodiment of the present invention.
  • each pixel PX of an organic light emitting diode display device has a 4T1C pixel structure including an organic light emitting diode OLED, a first thin film transistor T1, and a second thin film transistor T2.
  • the third thin film transistor T3, the fourth thin film transistor T4, and the capacitor C are the first thin film transistor T1, and the second thin film transistor T2.
  • the gate of the first thin film transistor T1 is electrically connected to the first node a, and the source thereof is electrically connected to the second node b.
  • the gate of the second thin film transistor T2 is connected to the second scan signal Scan2, and the drain thereof is electrically connected to the first node a.
  • the gate of the third thin film transistor T3 is connected to the third scan signal Scan3, and the drain thereof is electrically connected to the drain of the first thin film transistor T1, and the source thereof is electrically connected to the DC power supply positive terminal Vdd.
  • the gate of the fourth thin film transistor T4 is connected to the first scan signal Scan1, and the drain thereof is electrically connected to the second node b.
  • One end of the capacitor C is electrically connected to the first node a, and the other end thereof is electrically connected to the second node b.
  • the anode of the OLED is electrically connected to the second node b, and the cathode thereof is electrically connected to the DC power source negative Vss.
  • the first thin film transistor T1 is a driving thin film transistor.
  • the source of the second thin film transistor T2 is connected to the first data signal DATA1, and the source of the fourth thin film transistor T4 is initialized.
  • the signal INI or the threshold voltage detector 400 is used to detect the threshold voltage Vth of the first thin film transistor T1 and generate a threshold voltage signal, and the specific operation will be described below.
  • the source of the second thin film transistor T2 is connected by the threshold voltage signal and the original data.
  • the signal is combined to form a second data signal DATA2, and the source of the fourth thin film transistor T4 is coupled to the initialization signal INI.
  • the initialization signal INI and the first data signal DATA1 have a constant low potential, and the original data signal has a single pulse high potential.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous silicon thin film transistors.
  • the first scan signal Scan1, the second scan signal Scan2, the third scan signal Scan2, the initialization signal INI, the first data signal DATA1, and the original data signal are each generated by an external timing controller (not shown).
  • the pixel driving circuit according to the embodiment of the present invention employing the 4T1C pixel structure performs a reset operation (ie, a reset phase) and a threshold voltage sensing operation (ie, a threshold voltage sensing phase) when turned off or on.
  • 4 is a timing diagram of various stages of operation of the pixel driving circuit at the time of shutdown or power-on according to an embodiment of the present invention
  • FIGS. 5A and 5B are diagrams showing the operation of the pixel driving circuit at the time of shutdown or power-on according to an embodiment of the present invention. Figure.
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are at a high potential
  • the first data signal DATA1 is at a low potential VA
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are both at a high potential, and the first data signal DATA1 is at a low potential VA, and the fourth thin film transistor
  • the source of T4 is connected to the threshold voltage detector 400; at this time, the third thin film transistor T3, the second thin film transistor T2, and the fourth thin film transistor T4 are both turned on, the first node a
  • the voltage Va VA
  • the threshold voltage detector 400 obtains the threshold voltage Vth via its internal calculation, for example, by subtracting the voltage detected by the voltage VA. Thereafter, the threshold voltage detector 400 feeds back the resulting threshold voltage Vth and feeds it back to the original data signal to superimpose the original data signal to form a second data signal DATA2, as will be described below.
  • the pixel driving circuit according to the embodiment of the present invention employing the 4T1C pixel structure performs a reset operation (ie, a reset phase), a threshold voltage detecting operation (ie, a threshold voltage component measuring phase), a threshold value at the time of normal operation display.
  • the voltage compensation operation ie, the threshold voltage compensation phase
  • the driving illumination operation ie, driving the illumination phase. 6 is a timing diagram of each stage of operation of a pixel driving circuit in a normal operation display according to an embodiment of the present invention; FIGS.
  • FIGS. 7A to 7D are diagrams showing a working process of a pixel driving circuit in a normal operation display according to an embodiment of the present invention.
  • the cross symbol (x) on the thin film transistor indicates that the thin film transistor is in an off state.
  • the first scan signal Scan1 and the second scan signal Scan2 are at a high potential
  • the third scan signal Scan3 is at a low potential
  • the second data signal DATA2 is a low potential reference signal Vref and a threshold voltage.
  • the sum of the signals Vth, the source of the fourth thin film transistor T4 is connected to the initialization signal INI; at this time, the third thin film transistor T3 is turned off, the second thin film transistor T2 and the fourth thin film transistor T4 are turned on, and the initialization signal INI has a constant low potential.
  • the second data signal DATA2 is written into the first node a through the third thin film transistor T3 (ie, the gate of the first thin film transistor T1) Therefore, the gate and the source of the first thin film transistor T1 are initialized to clear the residual data; the first thin film transistor T1 is turned off, and the organic light emitting diode OLED does not emit light.
  • Vg represents the gate potential of the first thin film transistor T1
  • Va represents the potential of the first node a
  • Vs represents the source potential of the first thin film transistor T1
  • Vb represents the potential of the second node b
  • Vini Indicates a constant low potential of the initialization signal INI.
  • the first scan signal Scan1 is at a low potential
  • the second scan signal Scan2 and the third scan signal Scan3 are at a high potential
  • the second data signal DATA2 is at a low potential reference signal Vref and The sum of the threshold voltage signals Vth; at this time, the second thin film transistor T2 and the third thin film transistor T3 are turned on, the fourth thin film transistor T4 is turned off, and the first node a, that is, the gate of the first thin film transistor T1 is written with the second data signal.
  • the reference potential of the DATA2 is the sum of the low potential Vref and the threshold voltage Vth
  • the second node b that is, the source potential of the first thin film transistor T1 is converted to Vref.
  • the first scan signal Scan1 and the third scan signal Scan3 are at a low potential
  • the second scan signal Scan2 is at a high potential
  • the second data signal DATA2 is at a high potential display data signal Vdata.
  • the third thin film transistor T3 and the fourth thin film transistor T4 are turned off, the second thin film transistor T2 is turned on, and the second data signal DATA2 passes through the second thin film transistor T2 to the first node a
  • the gate of a thin film transistor T1 and the capacitor C are written to the sum of the display data signal high potential Vdata and the threshold voltage Vth, and the second node b, that is, the source potential of the first thin film transistor T1 is converted to Vref+ ⁇ V, and ⁇ V is a display data signal.
  • the influence of the high potential Vdata on the source potential of the first thin film transistor T1, that is, the potential of the second node b, is independent of the threshold voltage Vth of the first thin film transistor.
  • the first scan signal Scan1 and the second scan signal Scan2 are at a low potential
  • the third scan signal Scan3 is at a high potential
  • the second data signal DATA2 is a low potential reference signal Vref and a threshold.
  • the sum of the voltage signals Vth; at this time, the second to fourth thin film transistors T2 to T4 are both turned off. Due to the storage function of the capacitor C, the first node a, that is, the gate potential of the first thin film transistor T1 and the second node b are The voltage difference Vgs between the source potentials of the first thin film transistor T1 remains unchanged.
  • the current I flowing through the organic light emitting diode OLED is expressed as:
  • K represents the intrinsic conduction factor of the first thin film transistor T1, which is determined by the characteristics of the first thin film transistor T1 itself.
  • the current I flowing through the organic light emitting diode OLED is independent of the threshold voltage Vth of the first thin film transistor T1, which can eliminate the display failure caused by the shift of the threshold voltage Vth of the first thin film transistor T1. .

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Abstract

一种用于OLED显示设备的像素驱动电路以及具有该像素驱动电路的OLED显示设备。像素驱动电路采用4T1C的像素结构，以在OLED显示设备在关机或者开机时检测到驱动薄膜晶体管（T1）的阈值电压（Vth），并在正常工作显示时将检测到的阈值电压（Vth）补偿到有机发光二极管（OLED）的驱动电流中，从而消除驱动薄膜晶体管（T1）的阈值电压（Vth）对有机发光二极管（OLED）的驱动电流的影响，进而提高OLED显示设备显示画面的质量。

Description

用于OLED显示设备的像素驱动电路、OLED显示设备 技术领域
本发明属于显示技术领域，具体地讲，涉及一种用于OLED显示设备的像素驱动电路、OLED显示设备。
背景技术
近年来，有机发光二极管(Organic Light-Emitting Diode，OLED)显示设备成为国内外非常热门的新兴平面显示设备产品，这是因为OLED显示设备具有自发光、广视角、短反应时间、高发光效率、广色域、低工作电压、薄厚度、可制作大尺寸与可挠曲的显示设备及制程简单等特性，而且它还具有低成本的潜力。
在OLED显示设备中，通常利用薄膜晶体管(TFT)搭配电容存储信号来控制OLED的亮度灰阶表现。为了达到定电流驱动的目的，每个像素至少需要两个TFT和一个储存电容来构成，即2T1C模式。图1是现有的OLED显示设备的像素驱动电路的电路图。参照图1，现有的OLED显示设备的像素驱动电路包括两个薄膜晶体管(TFT)和一个电容器，具体地，包括一个开关TFT T1、一个驱动TFT T2和一个存储电容器Cst。OLED的驱动电流由驱动TFT T2控制，其电流大小为：IOLED＝k(Vgs-Vth)2，其中，k为驱动TFT T2的本征导电因子，由驱动TFT T2本身特性决定，Vth为驱动TFT T2的阈值电压，Vgs为驱动TFT T2的栅极和源极之间的电压。由于长时间的操作，驱动TFT T2的阈值电压Vth会发生漂移，因此会导致OLED的驱动电流变化，从而使得OLED显示设备出现显示不良，进而影响显示画面的质量。
发明内容
为了解决上述现有技术的问题，本发明的目的在于提供一种能够消除驱动薄膜晶体管的阈值电压对有机发光二极管的驱动电流的影响的用于OLED显示设备的像素驱动电路及OLED显示设备。
根据本发明的一方面，提供了一种用于OLED显示设备的像素驱动电路，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容器及有机发光二极管；所述第一薄膜晶体管的栅极电性连接于第一节点，且其源极电性连接于第二节点；所述第二薄膜晶体管的栅极接入第二扫描信号，且其漏极电性连接于第一节点；所述第三薄膜晶体管的栅极接入第三扫描信号，且其漏极电性连接于所述第一薄膜晶体管的漏极，且其源极电性连接于直流电源正极；所述第四薄膜晶体管的栅极接入第一扫描信号，且其漏极电性连接于第二节点；所述电容器的一端电性连接于第一节点，且其另一端电性连接于第二节点；所述有机发光二极管的阳极电性连接于第二节点，且其阴极电性连接于直流电源负极；当所述OLED显示设备关机或者开机时，所述第二薄膜晶体管的源极接入第一数据信号，所述第四薄膜晶体管的源极接入初始化信号或者阈值电压探测器，所述阈值电压探测器用于探测所述第一薄膜晶体管的阈值电压，并生成阈值电压信号；当所述OLED显示设备正常工作显示时，所述第二薄膜晶体管的源极接入由所述阈值电压信号和原始数据信号组合形成的第二数据信号，所述第四薄膜晶体管的源极接入初始化信号；其中，所述初始化信号和所述第一数据信号具有恒定低电位，所述原始数据信号具有单脉冲高电位。
进一步地，当所述OLED显示设备关机或者开机时，所述像素驱动电路执行复位操作和阈值电压感测操作。
进一步地，当所述像素电路执行复位操作时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为高电位，所述第四薄膜晶体管的源极接入所述初始化信号。
进一步地，当所述像素电路执行阈值电压感测操作时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为高电位，所述第四薄膜晶体管的源极接入所述阈值电压探测器。
进一步地，当所述OLED显示设备正常工作显示时，所述像素驱动电路执行复位操作、阈值电压检测操作、阈值电压补偿操作及驱动发光操作。
进一步地，当所述像素驱动电路执行复位操作时，所述第一扫描信号和所述第二扫描信号为高电位，所述第三扫描信号为低电位，所述第二数据信号为 低电位的参考信号与所述阈值电压信号之和。
进一步地，当所述像素驱动电路执行阈值电压检测操作时，所述第一扫描信号为低电位，所述第二扫描信号和所述第三扫描信号为高电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和。
进一步地，当所述像素驱动电路执行阈值电压补偿操作时，所述第一扫描信号和所述第三扫描信号为低电位，所述第二扫描信号为高电位，所述第二数据信号为高电位的显示数据信号与所述阈值电压信号之和。
进一步地，当所述像素驱动电路执行驱动发光操作，所述第一扫描信号和所述第二扫描信号为低电位，所述第三扫描信号为高电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和。
根据本发明的另一方面，还提供了一种OLED显示设备，其包括上述的像素驱动电路。
本发明的有益效果：本发明的OLED显示设备在关机或者开机时检测到驱动薄膜晶体管的阈值电压，并在正常工作显示时将该检测到的阈值电压补偿到有机发光二极管的驱动电流中，从而消除驱动薄膜晶体管的阈值电压对有机发光二极管的驱动电流的影响，进而提高OLED显示设备显示画面的质量。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是现有的OLED显示设备的像素驱动电路的电路图；
图2是根据本发明的实施例的有机发光二极管显示设备的架构图；
图3是根据本发明的实施例的有机发光二极管显示设备的像素驱动电路的电路图；
图4是根据本发明的实施例的像素驱动电路在关机或开机时的各工作阶段的时序图；
图5A和图5B是根据本发明的实施例的像素驱动电路在关机或开机时的工作过程图；
图6是根据本发明的实施例的像素驱动电路在正常工作显示时的各工作阶段的时序图；
图7A至图7D是根据本发明的实施例的像素驱动电路在正常工作显示时的工作过程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
图2是根据本发明的实施例的有机发光二极管显示设备的架构图。
参照图2，根据本发明的实施例的有机发光二极管显示设备包括：显示面板100、扫描驱动器200和数据驱动器300。需要说明的是，根据本发明的是实力的有机发光二极管显示设备还可以包括其他合适的器件，诸如控制扫描驱动器200和数据驱动器300的时序控制器以及提供电源正极电压和电源负极电压的电源电压产生器等。
具体地，显示面板100包括：阵列排布的多个像素PX、N条扫描线G1至GN、M条数据线D1至DM。扫描驱动器200连接到扫描线G1至GN，并驱动扫描线G1至GN。数据驱动器300连接到数据线D1至DM，并驱动数据线D1至DM。
扫描驱动器200能够向每个像素PX提供一个或者多个扫描信号，之后将会描述。数据驱动器300能够向每个像素PX提供数据信号，之后也将会描述。
每个像素PX包括像素驱动电路。以下将对根据本发明的实施例的像素驱动电路(即像素PX的像素结构)进行详细描述。
图3是根据本发明的实施例的有机发光二极管显示设备的像素结构的等效电路图。
参照图3，根据本发明的实施例的有机发光二极管显示设备的每个像素PX都具有4T1C像素结构，所述4T1C像素结构包括有机发光二极管OLED、第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、和电容器C。
第一薄膜晶体管T1的栅极电性连接于第一节点a，且其源极电性连接于第二节点b。
第二薄膜晶体管T2的栅极接入第二扫描信号Scan2，且其漏极电性连接于第一节点a。
第三薄膜晶体管T3的栅极接入第三扫描信号Scan3，且其漏极电性连接于第一薄膜晶体管T1的漏极，且其源极电性连接于直流电源正极Vdd。
第四薄膜晶体管T4的栅极接入第一扫描信号Scan1，且其漏极电性连接于第二节点b。
电容器C的一端电性连接于第一节点a，且其另一端电性连接于第二节点b。
有机发光二极管OLED的阳极电性连接于第二节点b，且其阴极电性连接于直流电源负极Vss。
其中，第一薄膜晶体管T1为驱动薄膜晶体管。
当有机发光二极管显示设备关机或者开机(或者关机后或开机后的预定时间内)时，第二薄膜晶体管T2的源极接入第一数据信号DATA1，第四薄膜晶体管T4的源极接入初始化信号INI或者阈值电压探测器400，该阈值电压探测器400用于探测第一薄膜晶体管T1的阈值电压Vth，并生成阈值电压信号，具体地的工作过程将在下面描述。
当有机发光二极管显示设备正常工作显示(即开机后(或者开机后的预定时间之后)到关机前的时间内)时，第二薄膜晶体管T2的源极接入由所述阈值电压信号和原始数据信号组合形成的第二数据信号DATA2，第四薄膜晶体管T4的源极接入初始化信号INI。
在本实施例中，初始化信号INI和第一数据信号DATA1具有恒定低电位，所述原始数据信号具有单脉冲高电位。
具体地，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3及第四薄膜晶体管T4均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管。
第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan2、初始化信号INI、第一数据信号DATA1及所述原始数据信号均通过外部时序控制器(未示出)产生。
以下将对根据本发明的实施例的像素驱动电路在关机或者开机时的工作原理进行详细描述。在本实施例中，采用了4T1C像素结构的根据本发明的实施例的像素驱动电路在关机或者开机时执行复位操作(即复位阶段)和阈值电压感测操作(即阈值电压感测阶段)。图4是根据本发明的实施例的像素驱动电路在关机或开机时的各工作阶段的时序图；图5A和图5B是根据本发明的实施例的像素驱动电路在关机或开机时的工作过程图。
在复位阶段，参照图4和图5A，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3为高电位，第一数据信号DATA1为低电位VA，第四薄膜晶体管T4的源极接入初始化信号INI，第一初始化信号INI为低电位Vini；此时，第三薄膜晶体管T3、第二薄膜晶体管T2和第四薄膜晶体管T4均导通，第一节点a的电压Va＝VA，第二节点b的电压Vb＝Vini，使Vini＝VA，从而完成初始化。
在阈值电压感测阶段，参照图4和图5B，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3均为高电位，第一数据信号DATA1为低电位VA，第四薄膜晶体管T4的源极接入阈值电压探测器400；此时，第三薄膜晶体管T3、第二薄膜晶体管T2和第四薄膜晶体管T4均导通，第一节点a的 电压Va＝VA，第二节点b的电压Vb＝VA-Vth，从而阈值电压探测器400探测到的电压为VA-Vth，其中Vth为第一薄膜晶体管T1的阈值电压。进一步地，阈值电压探测器400经由其内部的计算，例如利用电压VA减去其探测到的电压，从而得到阈值电压Vth。之后，阈值电压探测器400将其得到的阈值电压Vth进行反馈，并反馈给原始数据信号，以与所述原始数据信号叠加而形成第二数据信号DATA2，具体将在下面描述。
以下将对根据本发明的实施例的像素驱动电路在正常工作显示时的工作原理进行详细描述。在本实施例中，采用了4T1C像素结构的根据本发明的实施例的像素驱动电路在正常工作显示时执行复位操作(即复位阶段)、阈值电压检测操作(即阈值电压件测阶段)、阈值电压补偿操作(即阈值电压补偿阶段)及驱动发光操作(即驱动发光阶段)。图6是根据本发明的实施例的像素驱动电路在正常工作显示时的各工作阶段的时序图；图7A至图7D是根据本发明的实施例的像素驱动电路在正常工作显示时的工作过程图。在图7A至图7D中，薄膜晶体管上的叉符号(×)表示该薄膜晶体管处于截止状态。
在复位阶段，参照图6和图7A，第一扫描信号Scan1和第二扫描信号Scan2为高电位，第三扫描信号Scan3为低电位，第二数据信号DATA2为低电位的参考信号Vref与阈值电压信号Vth之和，第四薄膜晶体管T4的源极接入初始化信号INI；此时，第三薄膜晶体管T3截止，第二薄膜晶体管T2与第四薄膜晶体管T4导通，初始化信号INI的恒定低电位经第四薄膜晶体管T4写入第二节点b(即第一薄膜晶体管T1的源极)，第二数据信号DATA2经第三薄膜晶体管T3写入第一节点a(即第一薄膜晶体管T1的栅极)，从而对第一薄膜晶体管T1的栅极与源极进行初始化处理，清空残留的数据；第一薄膜晶体管T1截止，有机发光二极管OLED不发光。
在该复位阶段中：
Vg＝Va＝Vref+Vth
Vs＝Vb＝Vini
其中，Vg表示第一薄膜晶体管T1的栅极电位，Va表示第一节点a的电位，Vs表示第一薄膜晶体管T1的源极电位，Vb表示第二节点b的电位，Vini 表示初始化信号INI的恒定低电位。
在阈值电压检测阶段，参照图6和图7B，第一扫描信号Scan1为低电位，第二扫描信号Scan2和第三扫描信号Scan3为高电位，第二数据信号DATA2为低电位的参考信号Vref与阈值电压信号Vth之和；此时，第二薄膜晶体管T2和第三薄膜晶体管T3导通，第四薄膜晶体管T4截止，第一节点a即第一薄膜晶体管T1的栅极写入第二数据信号DATA2的参考低电位Vref和阈值电压Vth之和，第二节点b即第一薄膜晶体管T1的源极电位转变为Vref。
在该阈值电压检测阶段中：
Vg＝Va＝Vref+Vth
Vs＝Vb＝Vref
在阈值电压补偿阶段，参照图6和图7C，第一扫描信号Scan1和第三扫描信号Scan3为低电位，第二扫描信号Scan2为高电位，第二数据信号DATA2为高电位的显示数据信号Vdata与阈值电压信号Vth之和；此时，第三薄膜晶体管T3与第四薄膜晶体管T4截止，第二薄膜晶体管T2导通，第二数据信号DATA2经过第二薄膜晶体管T2向第一节点a即第一薄膜晶体管T1的栅极以及电容器C写入显示数据信号高电位Vdata和阈值电压Vth之和，第二节点b即第一薄膜晶体管T1的源极电位转变为Vref+ΔV，ΔV为显示数据信号高电位Vdata对第一薄膜晶体管T1的源极电位即第二节点b的电位所产生的影响，其与第一薄膜晶体管的阈值电压Vth无关。
在该阈值电压补偿阶段中：
Vg＝Va＝Vdata+Vth
Vs＝Vb＝Vref+ΔV
这样，第一薄膜晶体管T1的栅极电压Vg与源极电压Vs之间的差值Vgs为：
Vgs＝Vg-Vs＝Vdata+Vth-Vref-ΔV
在驱动发光阶段，参照图6和图7D，第一扫描信号Scan1和第二扫描信号Scan2为低电位，第三扫描信号Scan3为高电位，第二数据信号DATA2为低电位的参考信号Vref与阈值电压信号Vth之和；此时，第二薄膜晶体管T2至第四薄膜晶体管T4均截止，由于电容器C的存储作用，第一节点a即第一薄膜晶体管T1的栅极电位与第二节点b即第一薄膜晶体管T1的源极电位之间的压差Vgs保持不变。
进一步地，流经有机发光二极管OLED的电流I表示为：
I＝K(Vgs-Vth)2＝K(Vdata-Vref-ΔV+Vth-Vth)2＝K(Vdata-Vref-ΔV)2，
其中，K表示第一薄膜晶体管T1的本征导电因子，由第一薄膜晶体管T1本身特性决定。
因此，在流经有机发光二极管OLED的电流I的表达式中，电流I与第一薄膜晶体管T1的阈值电压Vth无关，这样可以消除第一薄膜晶体管T1的阈值电压Vth漂移引起的画面显示不良现象。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (12)

  1. 一种用于OLED显示设备的像素驱动电路，其中，所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、电容器及有机发光二极管；
    所述第一薄膜晶体管的栅极电性连接于第一节点，且其源极电性连接于第二节点；
    所述第二薄膜晶体管的栅极接入第二扫描信号，且其漏极电性连接于第一节点；
    所述第三薄膜晶体管的栅极接入第三扫描信号，且其漏极电性连接于所述第一薄膜晶体管的漏极，且其源极电性连接于直流电源正极；
    所述第四薄膜晶体管的栅极接入第一扫描信号，且其漏极电性连接于第二节点；
    所述电容器的一端电性连接于第一节点，且其另一端电性连接于第二节点；
    所述有机发光二极管的阳极电性连接于第二节点，且其阴极电性连接于直流电源负极；
    当所述OLED显示设备关机或者开机时，所述第二薄膜晶体管的源极接入第一数据信号，所述第四薄膜晶体管的源极接入初始化信号或者阈值电压探测器，所述阈值电压探测器用于探测所述第一薄膜晶体管的阈值电压，并生成阈值电压信号；
    当所述OLED显示设备正常工作显示时，所述第二薄膜晶体管的源极接入由所述阈值电压信号和原始数据信号组合形成的第二数据信号，所述第四薄膜晶体管的源极接入初始化信号；
    其中，所述初始化信号和所述第一数据信号具有恒定低电位，所述原始数 据信号具有单脉冲高电位。
  2. 根据权利要求1所述的像素驱动电路，其中，当所述OLED显示设备关机或者开机时，所述像素驱动电路执行复位操作和阈值电压感测操作。
  3. 根据权利要求2所述的像素驱动电路，其中，当所述像素电路执行复位操作时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为高电位，所述第四薄膜晶体管的源极接入所述初始化信号。
  4. 根据权利要求3所述的像素驱动电路，其中，当所述像素电路执行阈值电压感测操作时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为高电位，所述第四薄膜晶体管的源极接入所述阈值电压探测器。
  5. 根据权利要求1所述的像素驱动电路，其中，当所述OLED显示设备正常工作显示时，所述像素驱动电路执行复位操作、阈值电压检测操作、阈值电压补偿操作及驱动发光操作。
  6. 根据权利要求5所述的像素驱动电路，其中，当所述像素驱动电路执行复位操作时，所述第一扫描信号和所述第二扫描信号为高电位，所述第三扫描信号为低电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和。
  7. 根据权利要求6所述的像素驱动电路，其中，当所述像素驱动电路执行阈值电压检测操作时，所述第一扫描信号为低电位，所述第二扫描信号和所述第三扫描信号为高电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和。
  8. 根据权利要求7所述的像素驱动电路，其中，当所述像素驱动电路执行阈值电压补偿操作时，所述第一扫描信号和所述第三扫描信号为低电位，所述第二扫描信号为高电位，所述第二数据信号为高电位的显示数据信号与所述阈值电压信号之和。
  9. 根据权利要求8所述的像素驱动电路，其中，当所述像素驱动电路执行驱动发光操作，所述第一扫描信号和所述第二扫描信号为低电位，所述第三扫描信号为高电位，所述第二数据信号为低电位的参考信号与所述阈值电压信 号之和。
  10. 一种OLED显示设备，其中，包括权利要求1所述的像素驱动电路。
  11. 根据权利要求10所述的OLED显示设备，其中，当所述OLED显示设备关机或者开机时，所述像素驱动电路执行复位操作和阈值电压感测操作；
    当所述像素电路执行复位操作时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为高电位，所述第四薄膜晶体管的源极接入所述初始化信号；
    当所述像素电路执行阈值电压感测操作时，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号均为高电位，所述第四薄膜晶体管的源极接入所述阈值电压探测器。
  12. 根据权利要求10所述的OLED显示设备，其中，当所述OLED显示设备正常工作显示时，所述像素驱动电路执行复位操作、阈值电压检测操作、阈值电压补偿操作及驱动发光操作；
    当所述像素驱动电路执行复位操作时，所述第一扫描信号和所述第二扫描信号为高电位，所述第三扫描信号为低电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和；
    当所述像素驱动电路执行阈值电压检测操作时，所述第一扫描信号为低电位，所述第二扫描信号和所述第三扫描信号为高电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和；
    当所述像素驱动电路执行阈值电压补偿操作时，所述第一扫描信号和所述第三扫描信号为低电位，所述第二扫描信号为高电位，所述第二数据信号为高电位的显示数据信号与所述阈值电压信号之和；
    当所述像素驱动电路执行驱动发光操作，所述第一扫描信号和所述第二扫描信号为低电位，所述第三扫描信号为高电位，所述第二数据信号为低电位的参考信号与所述阈值电压信号之和。
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