WO2019027902A1 - Procédé de recuit par lampe flash permettant de fabriquer du silicium polycristallin - Google Patents

Procédé de recuit par lampe flash permettant de fabriquer du silicium polycristallin Download PDF

Info

Publication number
WO2019027902A1
WO2019027902A1 PCT/US2018/044383 US2018044383W WO2019027902A1 WO 2019027902 A1 WO2019027902 A1 WO 2019027902A1 US 2018044383 W US2018044383 W US 2018044383W WO 2019027902 A1 WO2019027902 A1 WO 2019027902A1
Authority
WO
WIPO (PCT)
Prior art keywords
mesa
super
substrate
silicon
amorphous silicon
Prior art date
Application number
PCT/US2018/044383
Other languages
English (en)
Inventor
Karl D. Hirschman
Robert George MANLEY
Tarun MUDGAL
Original Assignee
Corning Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Corning Incorporated filed Critical Corning Incorporated
Priority to US16/635,056 priority Critical patent/US11158504B2/en
Priority to CN201880050286.0A priority patent/CN111279458B/zh
Publication of WO2019027902A1 publication Critical patent/WO2019027902A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline

Definitions

  • the disclosure relates to a method of making polycrystalline silicon and to silicon products of the method.
  • the disclosure provides a method of making polycrystalline silicon, and an apparatus for making the polycrystalline silicon.
  • the disclosure provides polycrystalline silicon products and devices containing polycrystalline silicon made from the method and the disclosed polycrystalline silicon (p-Si).
  • the disclosure provides a method for flash- lamp annealing, which method provides edge-directed crystallization of amorphous silicon (a-Si) to polycrystalline silicon.
  • a-Si amorphous silicon
  • the disclosure provides polycrystalline silicon and articles thereof having long (e.g., greater than 1 micron) channel devices having aligned grains and having minimal grain boundaries.
  • the minimal grain boundaries avoid mobility degradation.
  • Fig. l shows a schematic of a disclosed super mesa (100) as defined herein.
  • Fig. 2 shows a schematic (200) summary of the disclosed method encompassing starting material substrates that lead to high performance transistors.
  • Fig. 3 is a plan view (300) that shows the disclosed method shown in Fig. 2 of forming high quality, aligned-grain, active regions for flash-lamp annealed polycrystalline silicon thin-film transistors (FLAPS TFTs).
  • FLAPS TFTs flash-lamp annealed polycrystalline silicon thin-film transistors
  • Fig. 4 shows an image of an actual and exemplary flash lamp annealed (FLA) and crystallized mesa (110) having exemplary dimensions of, for example, a width of 100 microns and a length of 200 microns.
  • FLA flash lamp annealed
  • crystallized mesa (110) having exemplary dimensions of, for example, a width of 100 microns and a length of 200 microns.
  • Figs. 5A and 5B show a scanning electron microscope (SEM) image (Fig. 5A) and an Euler crystal orientation map (image in grey scale; color rendering not provided) (Fig. 5B) from Electron Backscatter Diffraction (EBSD) measurements.
  • SEM scanning electron microscope
  • Euler crystal orientation map image in grey scale; color rendering not provided
  • Figs. 6A and 6B show schematic representations of a disclosed FLAPS TFT in plan view (6A) and a cross section view (6B), respectively.
  • Figs. 7A and 7B show a FLAPS device as a partially processed mesa (Fig. 7A image) showing the mesa structure (750) (the remainder of super-mesa having been etched away) with source/drain and channel regions exhibiting a different apparent texture (i.e., color appearance image not provided).
  • 0.1 V and 5 V) scales.
  • Fig. 9 shows a NFET T-M analysis of NMOS TFTs.
  • Fig. 10 shows a PFET T-M analysis of PMOS TFTs.
  • Figs. 11 A and 1 IB are overlay plots of current-voltage characteristics of NMOS and PMOS devices, respectively.
  • strain point refers to a point where stresses within a material relax within several hours. Stresses acquired at temperatures above the strain point, and not relaxed by annealing, remain in the glass indefinitely and may cause failure. Soda lime glass has a low strain point of 514 °C. A moderate strain point would be 665 °C such as Corning, Inc., EXG®. A high strain point glass of 752 °C is, for example, Corning, Inc., Lotus NXT®.
  • Super-mesa refers to an isolated silicon island on a substrate that will eventually be subdivided into transistor active regions.
  • the super mesa is flash lamp crystallized before the active regions are formed.
  • the resulting active regions may be divided into as little as one active region to a plurality (e.g., 10 to several hundred) of active regions depending upon, for example, transistor dimensions (width and length), transistor design rules, and the initial super mesa size.
  • Supersized grain refers to a domain comprised of two or more crystallites.
  • the domains of a super grain are formed when two or more
  • crystallization fronts meet and form a boundary.
  • the crystallites are aligned based on their longest growth vector, for example, the crystallites have an aspect ratio, i.e., a length (1) greater than the width (w) (i.e., l:w > 1).
  • the individual crystallites within the super grain may or may not have the same crystal orientation.
  • Polycrystalline silicon refers to a high purity, polycrystalline form of silicon.
  • FLAPS refers to polycrystalline silicon formed by flash-lamp annealing (FLA).
  • Mobility and like terms refer to the field effect channel mobility of electrons.
  • “Include,” “includes,” or like terms means encompassing but not limited to, that is, inclusive and not exclusive.
  • the term "about” also encompasses amounts that differ due to aging of a composition or formulation with a particular initial concentration or mixture, and amounts that differ due to mixing or processing a composition or formulation with a particular initial concentration or mixture.
  • compositions and methods of the disclosure can include any value or any combination of the values, specific values, more specific values, and preferred values described herein, including explicit or implicit intermediate values and ranges.
  • the disclosure provides equipment, process parameters, and thin- film transistors (TFT) design rules for making high performance TFT on glass substrates (i.e., having lower thermal conductivity, and high optical transparency).
  • TFT thin-film transistors
  • particular aspects of the disclosure can include, for example: an edge directed crystallization method from preparing thin films such as silicon, germanium, diamond, and like materials;
  • super-mesa pattern definition preferably exceeds the desired mesa pattern by, for example, 10 microns on border regions (i.e., the mesa pattern is inside of the super-mesa border by a minimum of 10 microns, and within a trapezoid resulting from the merger of crystallization fronts as represented in Fig. 3 (C));
  • mesa pattern definition preferably is oriented such that adjacent grains form boundaries aligned to the direction of the channel length (e.g., the channel width is defined by the mesa pattern definition);
  • the gate pattern definition overlaps the mesa borders in the direction of the channel width to avoid source/drain implant encroachment into the edges of the channel region (e.g., in a self-aligned gate structure) and ensures complete electrostatic control over carriers in the channel (i.e., the channel length in self-aligned gate TFTs is defined by the gate pattern definition); the source/drain pattern definition overlaps the mesa edges (e.g., for non-self-aligned gate TFTs the source/drain pattern definition defines the channel length and overlaps the gate pattern definition); and
  • the present disclosure provides a method of making polycrystalline silicon comprising:
  • amorphous silicon amorphous silicon
  • a suitable substrate such as glass
  • the substrate having a strain point of from 650 °C to 800 °C, for example, Lotus® XT available from Corning, Inc., to produce at least one amorphous silicon super-mesa on the substrate
  • dehydrogenating the at least one amorphous silicon super-mesa on the substrate e.g., by annealing at 450 ⁇ to yield a-Si super-mesa having a hydrogen concentration of less than about 10 mol%)
  • a-Si amorphous silicon
  • patterned substrate i.e., defining a geometry to force, direct, or select grain growth, e.g., using conventional photoresist patterning technology and pre-activation etching methods
  • a capping oxide layer on the amorphous silicon (e.g., comprised of a S1O 2 film having a thickness of from 50 to 150 nm) to form a capped, patterned substrate;
  • amorphous silicon e.g., comprised of a S1O 2 film having a thickness of from 50 to 150 nm
  • the capped, patterned substrate e.g., from 525 to 550 °C below the intrinsic solid phase crystallization temperature of amorphous silicon
  • FLA flash lamp annealing
  • the suitable pulse duration can be, for example, from 150 to 300 microseconds, from 150 to 300 microseconds, from 200 to 275 microseconds, and from 200 to 250 microseconds, including intermediate values and ranges. In embodiments, an especially preferred pulse duration is 250 microseconds.
  • the method can further comprise removing the mesa from the supersized grains, e.g., having aligned grains that are free of metal contamination.
  • removing the mesa can be accomplished by any suitable method of, for example, cutting, etching, ablation, or a combination thereof, and size of the removed mesa are any size suitable for a transistor article.
  • the method can further comprise forming a transistor having a grain direction parallel to the direction of current flow, e.g., from a source to a drain in a MOSFET device.
  • the crystal growth of the polycrystalline silicon is edge initiated.
  • patterning the super-mesa comprises, for example, a masking and etching including photolithography combined with aqueous or plasma etching.
  • the substrate can be selected from, for example, a glass sheet, a roll-to- roll glass, a sheet-to-sheet glass, a glass-ceramic sheet, and combinations thereof.
  • the present disclosure provides a conducting device comprising: at least two silicon grains on a glass substrate;
  • the device having an electron mobility of greater than 300 cm 2 per volt second, a hole mobility of from 100 cm 2 per volt second, and a sub-threshold swing, i.e., a measure of on-off slope; the reciprocal of sub-threshold slope, of less than 150 mV/decade at 25 °C.
  • Prior art devices that have polycrystalline silicon made using, for example, metal induced crystallization methods can have mobilities of from 0 to 200 cm 2 per volt second, and using, for example, eximer laser annealing ( ELA) induced methods can have mobilities of from 120 to 150 cm 2 per volt second.
  • ELA eximer laser annealing
  • a device of the disclosure can have a steep subthreshold slope and can exhibit a faster transition between off (low current) and on (high current) states.
  • the electron mobility can be, for example, of from 350 to 450 cm 2 per volt second and sub-threshold swing can be, for example, of from 60 to 100 mV/decade at 25 °C.
  • a device having a steep sub-threshold slope exhibits a faster transition between off (low current) and on (high current) states.
  • the device can be included in or selected from at least one of, e.g., any thin film semiconductor: a MOSFET (including various gate configurations, e.g., top gate, poly gate, co-planar, staggered, bottom gate co-planar staggered; multigate, etc.), a diode, a capacitor, and combinations thereof.
  • a MOSFET including various gate configurations, e.g., top gate, poly gate, co-planar, staggered, bottom gate co-planar staggered; multigate, etc.
  • the disclosure provides a method of making a device comprising: incorporating at least one device made in accordance with the present disclosure into another device or platform.
  • the presently disclosed method of silicon crystallization and products thereof are advantaged in several aspects, particularly over eximer laser annealing (ELA) processed low- temperature polycrystalline silicon (LTPS), including for example:
  • ELA eximer laser annealing
  • the method of making polycrystalline silicon enables pre-deposition or solid source doping (i.e., it may be possible to eliminate ion implantation);
  • the method of making provides a larger range of film thickness compatibility (e.g., thicker films);
  • PV photovoltaic devices
  • the method of making is self-aligned gate-source/drain compatible
  • the method of making is bottom gate compatible
  • the disclosed polycrystalline silicon crystallization method can be accomplished in ambient atmosphere
  • the disclosed polycrystalline silicon crystallization method uses no toxic gas and does not generate toxic gas or fumes
  • the disclosed apparatus can be combined the with a CVD chamber (i.e., for in situ crystallization of a-Si films);
  • the disclosed method is scalable to commercial production to, for example, substrates greater than about 1870 mm x 2200 mm (e.g. GEN 7).
  • the disclosure provides an improved apparatus, material processing, and semiconductor device fabrication for an advanced low temperature polycrystalline silicon (LTPS), having crystallization temperatures typically less than 800 °C, enabling high performance thin-film transistors on glass substrates.
  • LTPS advanced low temperature polycrystalline silicon
  • FPD flat panel display
  • LAE larger area electronics
  • a-Si amorphous silicon
  • a-Si is simple, uniform and cost effective to integrate, the properties of the film are such that only slow, low current drive and relatively large devices can be realized.
  • CMOS complementary metal oxide insulator semiconductor
  • Metal-oxide based semiconductors have advantages over a-Si, for example, having higher mobilities approaching 15 to 20 cm 2 /Vs.
  • Metal-oxide semiconductor as stated in prior art, can be either amorphous or polycrystalline in nature, and can have high uniformity on large substrates. Most practical metal-oxide semiconductors are unipolar in nature and only support electrons as free carriers. While this leads to lower off-state leakage current levels, metal- oxide semiconductors cannot support CMOS integration. While some p-type metal-oxide semiconductors have been identified, their properties tend to be poor for electronic integration. Even if they did have desirable properties, CMOS integration would require the incorporation of two semiconductor material systems.
  • LTPS LTPS
  • CVD chemical vapor deposition
  • ELA Excimer laser annealing
  • the film goes through a partial melt, typically one third of the silicon film thickness, and re-solidifies in polycrystalline form resulting in a distribution of silicon grain sizes.
  • the grain size distribution, alignment of the grains, and crystal orientation of the grains can all impact the final transistor performance.
  • the ELA process results in random distribution of all these properties and ultimately limits the manufacturability of high performance TFTs and other devices.
  • the disclosure provides a method for making LTPS TFTs on a glass substrate using an alternative approach to the ELA method.
  • the disclosure provides a flash-lamp annealing (FLA) method for making LTPS TFTs, which method uses a series of short but intense bursts of a broad spectrum light source such as from one or more xenon flash lamps.
  • FLA flash-lamp annealing
  • the disclosed method preferably uses only a single burst of the broad spectrum light source.
  • the disclosed FLA method was shown to be capable of crystalizing amorphous silicon and to activate implanted dopants. The process is readily extendable to accommodate arbitrarily large substrates, such as those in flat panel manufacturing.
  • the disclosure provides a method for making polysilicon and thin film transistors incorporating the polysilicon.
  • the crystallization method can be accomplished in a modified commercially available FLA system having, for example, a high temperature substrate chuck for steady-state heating (e.g., a hot plate), and a high temperature ambient control chamber.
  • the disclosure provides process parameter design and provides new TFT design rules (mentioned below), which permit high performing TFTs to be made.
  • the disclosure provides a device comprising: at least one conducting device comprising:
  • the conducting device having an electron mobility of greater than 300 cm 2 per volt second, a hole mobility of from 100 cm 2 per volt second, and a sub-threshold swing of less than 150 mV/decade at 25 °C.
  • One of more xenon flash lamps can be used and the lamps typically have a broader spectral range than a laser (e.g., UV to 1R) having a spectral range, for example, of from 250 to 1000 nm, of from 300 to 800 nm, including intermediate values and ranges, and a peak at about 500 nm.
  • a laser e.g., UV to 1R
  • Flash lamp crystallization may or may not go above the melting point of silicon. In contrast ELA does melt the silicon, typically up to one third of the layer thickness.
  • ELA exposures can scan a high energy beam over the sample surface, where the beam width is relatively large in one direction (e.g., x-direction) and the sample moves in an orthogonal direction (e.g., y-direction). Uniformity issues and high exposure times needed for large samples makes ELA methods impractical and is cost prohibitive for panels at Gen 8 or larger.
  • the grains from FLA can be as small as, for example, 5 nm or larger, e.g., greater than 100 microns.
  • the grain growth direction in FLA can be controlled/aligned. In contrast, grain growth in normal excimer laser annealing (ELA) is random. In sequential laser solidification (SLS), larger aligned grains (e.g., about 5 microns) can be formed using a special pulse and stepping sequence of the substrate, but is not necessary for FLA.
  • Grains for FLA can be smaller or larger than the device feature size. For enhanced transistor device performance, it is preferred that the grains are larger than the transistor channel length and that the grains are aligned.
  • FLA has an advantage over metal-induced crystallization as the polysilicon remains pure and no metal contaminates remain to degrade performance of the material.
  • a 60 nm a-Si:H layer was deposited on 150 mm diameter Corning EAGLE XG® display glass wafers using plasma-enhanced chemical vapor deposition (PECVD). The deposition was performed using SiH 4 and H 2 at 400 °C, 1 Torr pressure and 30 W RF power. Blanket film samples were dehydrogenated at 450 °C for 1 hr in vacuum. A 100 nm S1O 2 capping layer/screening oxide was deposited over the a-Si film using PECVD with TEOS precursor at 380 °C.
  • PECVD plasma-enhanced chemical vapor deposition
  • the FLA system used in this work was a NovaCentrix PulseForge 3300 configured with two xenon lamps, and having a 75 mm x 150 mm exposure window.
  • Electron Backscatter Diffraction confirmed the relationship between the resulting surface morphology and crystal orientation. Multiple data points from each region were collected to determine crystal orientation.
  • Figs. 5A and 5B show an SEM image and a crystal orientation map, respectively, of the same region. While a preferred crystal orientation may not be evident, the correlation between the color map and the SEM image is readily evident.
  • a hotplate chamber was built and integrated into the apparatus, which chamber provides significant improvements in temperature and ambient control, and provides the ability to heat the substrate up to 550°C.
  • the hotplate chamber has its own built-in quartz window, which allows for the removal of the OEM quartz window under the PulseForge lamps to minimize surface reflections.
  • the system is microprocessor controlled with feedback and control parameters to accurately drive embedded resistive heating elements within a stainless steel sample stage.
  • the stage can accommodate up to 150 mm round (wafer format) samples.
  • the chamber has gas inlet and vacuum ports to evacuate atmosphere, and to provide a pressure-controlled inert ambient condition while avoiding thermal loss.
  • the chamber is designed to fit beneath the exposure head of the PulseForge system with a clearance gap of about 2 mm.
  • Bolometer measurements taken inside the chamber showed exposure intensity values that are within 5% of measurements taken directly under the exposure head with the OEM quartz window installed.
  • One modification of the chamber design includes
  • a further modification includes the integration of tungsten- halogen heat lamps (e.g., those implemented in rapid thermal processors) beneath the susceptor to provide steady-state heating rather than using resistive heating elements.
  • tungsten- halogen heat lamps e.g., those implemented in rapid thermal processors
  • Figs. 7A and 7B show a FLAPS in a fabrication process for a 4-probe Van der Pauw test structure (see for example, O. Paul, IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 2, May 2000) and a TFT. The following process flow for non-self-aligned top-gate TFTs was followed for preparing the devices in this discussion.
  • the super-mesa provides sacrificial edge material that extends beyond the mesa, or active device region.
  • the super-mesa was designed to provide a sacrificial border region of 20 microns (e.g., at a minimum), and large enough such that crystallization fronts do not merge to form a boundary in the device mesa active region (see Fig. 3 (C) and 3 (D)).
  • RIE reactive-ion etching
  • a 100 nm S1O 2 capping layer was deposited by PECVD using TEOS as a precursor, at 380 °C with a deposition time of about 12 sec.
  • This capping layer serves several significant functions, which can include providing a thermal buffer to the surface and acting as an anti-reflective layer for the FLA exposure.
  • the capping layer also serves as a screen oxide layer to position the boron and phosphorus implant profiles within the a-Si layer.
  • the FLA exposure served to both crystallize the a-Si and to activate the implanted dopant.
  • the HTAC chamber maintained a temperature of 550 °C with a nitrogen purge at atmospheric pressure.
  • the FLA exposures were done with lamp voltage supplies at 600 V and a time of 200 microseconds, with bolometer measurements showing an integrated energy of about 6 J/cm 2 . These exposure conditions produced the FLAPS observed in Figs. 5A and 5B.
  • the screen or capping oxide was removed in buffered hydrofluoric acid, and the mesa (active transistor region) was patterned.
  • the 1E process described previously was used to remove the sacrificial super-mesa regions.
  • Piranha (sulfuric acid / hydrogen peroxide mixture) and HC1/H 2 0 2 cleaning solutions were then used to remove any contaminants prior to the PECVD gate oxide deposition, using the same process as described for the oxide. This was then followed by a 630 °C, 12 hr furnace anneal in nitrogen ambient which serves several functions, i.e., additional dopant activation, grain growth, defect reduction, and stress relaxation.
  • a 1 micron thick aluminum film was sputter deposited using a 2,000W DC argon plasma.
  • the design of the non-self-aligned transistors included a gate overlap of the source/drain implanted regions of 4 microns for overlay tolerance.
  • the source/drain and gate electrodes were patterned and etched in Transene type-A aluminum etchant. Finally the devices were sintered in a forming gas ambient (5% H 2 in N 2 ) at 450 °C for 30 min.
  • the disclosed FLA-crystallized polysilicon devices provide superior device performance and the results are shown in the graphs in Figs. 8A and 8B. While the devices exhibit certain non-ideal behavior, the results are quite suggestive and clearly demonstrate the potential for the disclosed method, materials, and articles.
  • the following device parameters were obtained using the physical dimensions, and transfer characteristics in Figs. 8A and 8B, and the Terada-Muta (T-M) method to establish the effective channel length.
  • T-M Terada-Muta
  • Table 1 lists the physical parameters of CMOS (i.e., PMOS & NMOS) TFTs, and electrical parameters that characterize the on-state and off-state performance.
  • the analysis is based on selected results.
  • the extracted channel mobility values are consistent with the effective channel lengths ⁇ L ef j) arrived at using the T-M analysis.
  • the electron/hole channel mobility ratio is about 2.7, which is consistent with crystalline silicon.
  • Molten silicon with dopants present also provides an explanation for the large AL from the T-M analysis as a result of the diffusivity of phosphorus and boron in liquid phase silicon. Additional notable aspects include:
  • T-M analysis was performed on two different channel length devices that had similar electrical behavior.
  • the ratio of channel mobility for electrons and holes is consistent with that observed in crystalline silicon devices.
  • a self-aligned top-gate is a practical implementation. If a metal gate is applied, such as molybdenum used for self-aligned TFTs on Coming's SiOG, the presently disclosed FLA process can be accomplished prior to the metal gate and dopant introduction.
  • the dopant activation can be accomplished by, for example, via furnace annealing following the formation of FLAPS. Experiments on FLA crystallization and dopant activation support the feasibility of this approach (see T. Mudgal, supra.).
  • a bottom- gate approach that is also compatible with FLA is the use of a doped polysilicon or a transparent conductive oxide such as 1TO. This can be implemented, for example, using a self-aligned strategy that creates a photoresist implant pattern definition using a through-glass exposure where the gate serves as the mask.
  • HTAC chamber parameters include temperature, gas ambient, pressure (sub-atmosphere or above atmosphere), and sample distance.
  • FLA exposure options include, for example, multiple overlapping high-power exposures, or a combination of high frequency pulses (e.g., 10 to 100 Hz) at low power to establish a steady- state thermal surface condition followed by high intensity pulses for crystallization.
  • process integration there are several process variants that can be created by simply changing the order of process steps (e.g., FLA, ion implantation, furnace annealing) in the disclosed process flow.
  • Dopant pre-deposition can be a replacement of ion
  • Fig.l shows a schematic of a disclosed super mesa (100) including: a substrate (105) such as a glass or like support material; and an isolated silicon island ( 110) on the surface of the support material.
  • the isolated silicon island (110) can include, for example: one or more supersized grains or super grains (115).
  • the super grains (115) can include one or more (such as a plurality of) crystallites (117) of high purity polycrystalline silicon within the boundary or crystallization fronts (119).
  • the super grain (115) can be, for example, an equilateral triangle, a trapezoid, or an isosceles triangle having a base (b) and height (h) dimensions.
  • Within the super grains (115) one or more mesa or transistor active regions (120) can be identified or defined for further processing into a device including the polycrystalline silicon mesa (120) or a portion thereof.
  • Fig. 2 shows a schematic (200) summary of the disclosed method encompassing starting material substrates that lead to high performance transistors.
  • Fig. 2 schematically shows a process for transforming a-Si into high performance flash-lamp annealed
  • FLAPS polycrystalline silicon
  • TFTs thin film transistors
  • A plasma-enhanced chemical vapor deposition (PECVD) of a-Si onto the substrate (105), which is subsequently dehydrogenated (107);
  • PECVD plasma-enhanced chemical vapor deposition
  • C crystallization via flash lamp annealing using a xenon source (210) that produces flash photons (212) to produce polycrystalline silicon (110);
  • D forming a transistor active region (120) definition and alignment of grains; and
  • E fabricating (intermediate steps not shown) a thin-film transistor structure (220)(e.g., a single
  • Fig. 3 is a plan view (300) that shows the disclosed method shown in Fig. 2 of forming high quality, aligned-grain, active regions for FLAPS TFTs, including the above mentioned steps (A) through (E) and enumerated components.
  • Fig. 3 (E) an alternative to the single TFT structure of Fig. 2 (E) shows an inverter structure (220).
  • Fig. 4 shows an image of an actual and exemplary flash lamp annealed (FLA) and crystallized mesa (110) having exemplary dimensions of, for example, a width of 100 microns and a length of 200 microns.
  • FLA flash lamp annealed
  • crystallized mesa (110) having exemplary dimensions of, for example, a width of 100 microns and a length of 200 microns.
  • Figs. 5A and 5B show a scanning electron microscope (SEM) image (Fig. 5A) and an Euler crystal orientation map (image in grey scale; color rendering not provided) (Fig. 5B) from Electron Backscatter Diffraction (EBSD) measurements.
  • the boxed region (510) on the SEM image was used for the EBSD analysis.
  • Each color in the EBSD original represents a different crystal orientation.
  • the FLAPS channel shows different morphology compared to Fig. 4 but the EBSD result confirmed that the crystallization remains edge directed. Analysis indicated a preferential surface crystal orientation of "(1 1 1)".
  • Figs. 6A and 6B show schematic representations of a disclosed FLAPS TFT in plan view (6A) and a cross section view (6B), respectively, and structure (715), (720), (725), and (730), mentioned in Figs. 7A and 7B.
  • Figs. 7A and 7B show a FLAPS device as a partially processed mesa (Fig. 7A image) showing the mesa structure (750) (the remainder of super-mesa having been etched away) with source/drain and channel regions exhibiting a different apparent texture (i.e., color appearance image not provided).
  • the apparent background region where the super-mesa was etched away (710) has a roughened appearance due to the etch process used.
  • the Fig. 7B image shows a completed TFT structure incorporating the FLAPS device of Fig. 7A (750) (encircled) having an aluminum source contact (715), an aluminum drain contact (725), and an aluminum gate (720) that overlaps the implanted regions (730).
  • 0.1V and 5 V) scales.
  • the mask-defined channel length i.e., the distance between source/drain implanted regions
  • L 30 microns
  • W 100 microns.
  • Bias conditions and extracted values of threshold voltage (VT), transconductance (GM), and subthreshold swing (SS) are shown.
  • the T-M analysis worked reasonably well on both NMOS (Fig. 9) and PMOS (Fig. 10) FLAPS TFT devices. However, lower
  • the channel length offset (AL) values were 6.3 microns and 13.4 microns for NMOS and PMOS devices, respectively.
  • the on-state and off-state operational parameters for the exemplary transfer characteristics shown in Fig. 8 A and 8B were extracted once L e g was established, with results listed in Table 1.
  • the width ( W) of the TFTs was taken as the designed value of 100 microns.
  • the oxide capacitance was calculated from the 100 nm deposition thickness.
  • the channel mobility values were calculated from the maximum transconductance at
  • V DS ⁇ 0.1 V.
  • the extracted channel mobility values were 380 cm 2 /V-s and 143 cm 2 /V-s for electrons and holes, respectively.
  • Off-state parameters were minimum subthreshold swing (SS) values below 150 mV/dec, and about 1 pA/micron leakage current at
  • Figs. 8A and 8B show transfer characteristics for NFETs and PFETs fabricated in polycrystalline silicon.
  • Fig. 8A shows the linear operation mode characteristics on a linear scale at drain-source bias of 0.1 V.
  • the threshold voltage is linearly extrapolated from the NMOS characteristic curve (805) to 0.23 V with a transductance of 5.10 microA/V.
  • the threshold voltages are extracted from the PMOS curve (800) and is -2.82 V with a transconductance of 2.66 microA/V.
  • Fig. 8B shows the transfer linear and saturation mode characteristic curves plotted on a logarithmic scale.
  • 0.1 V) PMOS curve (810) and saturation mode (
  • 5V) PMOS curve (81 1) overlap in the subthreshold region (812) and exhibit a subthreshold slope of 140 V/dec.
  • Fig. 9 shows a NFET T-M analysis of NMOS TFTs.
  • Fig. 10 shows a PFET T-M analysis of PMOS TFTs.
  • the reference dimensions for channel length (x-axis) are the mask-defined distance between implanted source/drain regions.
  • Figs. 1 1 A and 1 IB are overlay plots of current-voltage characteristics of NMOS and PMOS devices, respectively, made with the disclosed FLAPS articles and methods, and the plots demonstrate superior device performance, i.e., consistently low variation. While there is noted variation in device operation, the plots demonstrate the potential of the disclosed FLAPS method for improved device performance and manufacturability.
  • the super mesa location was arbitrarily defined or is defined in relation to the edges of the substrate.
  • a photosensitive resist i.e., photoresist
  • the photoresist was coated on a substrate with an amorphous silicon film.
  • the photoresist was exposed in selected regions with UV light using a photomask (e.g., chrome pattern on glass).
  • the exposed photoresist was dissolved in developer solution, uncovering regions of amorphous silicon to be removed.
  • the un-exposed photoresist remained and masked the super-mesa regions.
  • the unprotected amorphous silicon was etched in fluorine ion plasma containing fluorine ions. The etching was completed upon exposure of the substrate.
  • the remaining photoresist over the super-mesa regions was removed using, for example, a ketone - based solvent or oxygen ion plasma.
  • the substrate was cleaned in heated solutions of HCl or NH 4 OH mixed with hydrogen peroxide.
  • a silicon dioxide capping layer was deposited.
  • the super-mesa (108) remained on the substrate as shown in Fig. 3 (B).
  • Example 1 Super-Mesa FLA Exposure and TFT Mesa
  • the super mesa structure of Example 1 then underwent FLA exposure using nominal substrate temperature and flash exposure settings.
  • the mesa pattern definition was applied to the FLAPS super mesa, with the photoresist polygons shown in Fig. 3 (C) protecting the incipient mesa regions (120) from removal during a F " ion plasma etch.
  • the TFT mesa structures (120) appeared as shown in Fig. 3 (D).
  • NMOS and PMOS TFTs were then fabricated in the FLAPS mesa structures.
  • CMOS Characteristics of FLAPS TFTs Current- voltage characteristics of NMOS and PMOS devices were measured on disclosed FLAPS devices. The overlay plots of from about 30 to 40 devices in Figs. 11A and 1 IB show nominal variation in performance. Selected devices shown in Figs. 8A and 8B demonstrate superior results using the disclosed process of FLA crystallization of silicon. Previous work which demonstrated FLA LTPS TFTs on crystallized material without preferential grain alignment provided current- voltage characteristics for PMOS devices only, and only under low drain bias conditions
  • V D s -0.1V
  • Example 4 FLAPS Surface Morphology A device that had been previously verified as operational and having good performance characteristics was deprocessed (i.e., deconstruction or reversing selected manufacturing steps to elucidate structural antecedents and integrity) to establish the associated FLAPS surface morphology. SEM imaging revealed a channel region as shown in Fig. 5A. EBSD mapping shown in Fig. 5B confirmed that the disclosed crystallization process is edge directed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

La présente invention concerne un procédé de fabrication de silicium polycristallin (p-Si), consistant : à déposer du silicium amorphe pour produire un super mesa en silicium amorphe ; à déshydrogéner le silicium amorphe ; à former les motifs sur le super mesa pour produire un substrat à motifs ; à déposer une couche d'oxyde de recouvrement sur le silicium amorphe sur le substrat à motifs ; à chauffer le substrat à motifs recouvert à la température de cristallisation du a-Si ; et à recuire par lampe flash du substrat à motifs avec une lampe au xénon pour produire du p-Si ayant au moins un super mesa, et le super mesa ayant des grains surdimensionnés. La présente invention porte également sur des articles à base de p-Si et sur des dispositifs incorporant les articles, ainsi que sur un appareil permettant de fabriquer les articles à base de p-Si.
PCT/US2018/044383 2017-07-31 2018-07-30 Procédé de recuit par lampe flash permettant de fabriquer du silicium polycristallin WO2019027902A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/635,056 US11158504B2 (en) 2017-07-31 2018-07-30 Flash-lamp annealing method of making polycrystalline silicon
CN201880050286.0A CN111279458B (zh) 2017-07-31 2018-07-30 制造多晶硅的闪光灯退火方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762539042P 2017-07-31 2017-07-31
US62/539,042 2017-07-31

Publications (1)

Publication Number Publication Date
WO2019027902A1 true WO2019027902A1 (fr) 2019-02-07

Family

ID=63254790

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2018/044383 WO2019027902A1 (fr) 2017-07-31 2018-07-30 Procédé de recuit par lampe flash permettant de fabriquer du silicium polycristallin

Country Status (3)

Country Link
US (1) US11158504B2 (fr)
CN (1) CN111279458B (fr)
WO (1) WO2019027902A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060130939A1 (en) * 2002-11-08 2006-06-22 Jin Jang Phase transition method of amorphous material using cap layer
US20130026479A1 (en) * 2011-03-22 2013-01-31 Panasonic Corporation Semiconductor thin-film forming method, semiconductor device, semiconductor device manufacturing method, substrate, and thin-film substrate

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3497198B2 (ja) 1993-02-03 2004-02-16 株式会社半導体エネルギー研究所 半導体装置および薄膜トランジスタの作製方法
US5843225A (en) 1993-02-03 1998-12-01 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
JP4299959B2 (ja) 2000-08-14 2009-07-22 株式会社東芝 半導体装置の製造方法
TWI313059B (fr) 2000-12-08 2009-08-01 Sony Corporatio
US20040224446A1 (en) * 2003-05-07 2004-11-11 Wen-Chang Yeh [structure of thin-film transistor and method and equipment for fabricating the structure]
US20050130422A1 (en) * 2003-12-12 2005-06-16 3M Innovative Properties Company Method for patterning films
JP2009164451A (ja) 2008-01-09 2009-07-23 Dainippon Screen Mfg Co Ltd 熱処理装置
KR101097348B1 (ko) 2010-03-11 2011-12-23 삼성모바일디스플레이주식회사 결정화 장치, 결정화 방법, 박막 트랜지스터 제조 방법 및 유기 발광 표시 장치의 제조 방법
JP6026090B2 (ja) 2011-09-26 2016-11-16 株式会社Ｓｃｒｅｅｎホールディングス 熱処理方法
JP2013084902A (ja) 2011-09-26 2013-05-09 Dainippon Screen Mfg Co Ltd 熱処理方法および熱処理装置
JP5955604B2 (ja) 2012-03-28 2016-07-20 株式会社Ｓｃｒｅｅｎホールディングス 熱処理装置および熱処理方法
CN104681639A (zh) * 2013-12-02 2015-06-03 北京有色金属研究总院 一种基于柔性基底的多晶硅薄膜太阳能电池及其制备方法
CN106784412B (zh) * 2017-03-30 2019-02-26 武汉华星光电技术有限公司 柔性有机发光二极管显示器及其制作方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060130939A1 (en) * 2002-11-08 2006-06-22 Jin Jang Phase transition method of amorphous material using cap layer
US20130026479A1 (en) * 2011-03-22 2013-01-31 Panasonic Corporation Semiconductor thin-film forming method, semiconductor device, semiconductor device manufacturing method, substrate, and thin-film substrate

Non-Patent Citations (15)

* Cited by examiner, † Cited by third party
Title
B. PECZ ET AL., APPLIED SURFACE SCIENCE, vol. 242, 2005, pages 185 - 191
BAOJIE Y. ET AL.: "Pulsed-light Crystallization of Thin Film Silicon, Germanium, and Silicon Germanium Alloy", MRS PROCEEDINGS, vol. 1666, 2014
K. OHDAIRA ET AL., J. APPL. PHYS., vol. 106, 2009, pages 044907
K. OHDAIRA ET AL., JOURNAL OF CRYSTAL GROWTH, vol. 362, 2013, pages 149
K. OHDAIRA ET AL.: "Large-Grain Polycrystalline Silicon Films Formed through Flash-Lamp-Induced Explosive Crystallization", JAP. J. APPL, PHYS., vol. 51, 2012, pages 10NB15, XP001588570, DOI: doi:10.1143/JJAP.51.10NB15
MUDGAL T ET AL: "Crystallization of amorphous silicon and dopant activation using xenon flash-lamp annealing (FLA)", MATERIALS RESEARCH SOCIETY SYMPOSIUM PROCEEDINGS, MATERIALS RESEARCH SOCIETY, US, vol. 1666, 2014, XP009508869, ISSN: 0272-9172, DOI: 10.1557/OPL.2014.722 *
O. PAUL, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, vol. 13, no. 2, May 2000 (2000-05-01)
R.G. MANLEY ET AL.: "Development of Integrated Electronics on Silicon-on-Glass (SiOG) Substrate", ECS TRANSACTIONS, vol. 16, no. 9, 2008, pages 371 - 380
S. SAXENA ET AL., IEEE ELECTRON DEVICE LETTERS
S. SAXENA ET AL., IEEE ELECTRON DEVICE LETTERS, vol. 31, 2010, pages 1242
S. SAXENA ET AL.: "Polycrystalline Silicon Thin-Film Transistor Using Xe Flash-Lamp Annealing", IEEE ELECTRON DEVICE LETTERS, vol. 31, 2010, pages 1242
S. SAXENA ET AL.: "Protrusions of Super Grains Formed by Ultrashort Xe Flash-Lamp Annealing of Amorphous Silicon, and Its Effect on the Performances of Thin-Film Transistors", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 58, no. 8, August 2011 (2011-08-01), XP011336349, DOI: doi:10.1109/TED.2011.2157827
T. MUDGAL ET AL.: "Crystallization of Amorphous Silicon and Dopant Activation using Xenon Flash-Lamp Annealing (FLA", MRS PROCEEDINGS, vol. 1666, 2014
T. MUDGAL ET AL.: "Mater. Res. Soc. Symp. Proc.", vol. 1666, 2014, MATERIALS RESEARCH SOCIETY, article "Crystallization of Amorphous Silicon and Dopant Activation using Xenon Flash-Lamp Annealing (FLA"
T. WATANABE ET AL.: "The formation ofpoly-Si films on flat glass substrates by flash lamp annealing", THIN SOLID FILMS, vol. 595, 2015, pages 235 - 238

Also Published As

Publication number Publication date
CN111279458A (zh) 2020-06-12
CN111279458B (zh) 2023-10-27
US20200251335A1 (en) 2020-08-06
US11158504B2 (en) 2021-10-26

Similar Documents

Publication Publication Date Title
Hirao et al. Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs
US5834071A (en) Method for forming a thin film transistor
US20120268681A1 (en) Semiconductor circuit for electro-optical device and method of manufacturing the same
KR20030060403A (ko) 비정질 실리콘의 결정화 방법
Cboi et al. Thin-film transistors fabricated with poly-Si films crystallized at low temperature by microwave annealing
Nguyen et al. The metal-induced crystallization of poly-Si and the mobility enhancement of thin film transistors fabricated on a glass substrate
Mudgal et al. Communication—CMOS thin-film transistors via Xe flash-lamp crystallization of patterned amorphous Si
Cho et al. High performance fully and partially depleted poly-Si surrounding gate transistors
US11158504B2 (en) Flash-lamp annealing method of making polycrystalline silicon
Hayashi et al. Investigation of silicon grain structure and electrical characteristics of TFTs fabricated using different crystallized silicon films by atmospheric pressure micro-thermal-plasma-jet irradiation
Chowdhury et al. Self-aligned IGZO TFTs with boron implanted source/drain regions
CN104599973A (zh) 低温多晶硅薄膜晶体管的制备方法
Park et al. High temperature crystallized poly-Si on Mo substrates for TFT application
Bayraktaroglu et al. Pulsed laser deposited ZnO for thin film transistor applications
JPH0336767A (ja) 絶縁ゲート型電界効果トランジスタの製造方法
Kim et al. 12.2: Large‐Area Poly‐Si on Glass by UV Scan Heating
Packard et al. Flash Lamp Annealed Polycrystalline Silicon TFT Dependence on Surface Morphology and the Back-Channel Material Interface
Kawachi et al. Characterization of high-performance polycrystalline silicon complementary metal–oxide–semiconductor circuits
Li Investigation on solid-phase crystallization techniques for low temperature polysilicon thin-film transistors
JP2709376B2 (ja) 非単結晶半導体の作製方法
JP2002299629A (ja) ポリシリコン薄膜半導体およびポリシリコン薄膜半導体の製造方法
Packard et al. Flash lamp annealed ltps tfts with ito bottom-gate structures
CN103258855A (zh) 基于固相结晶技术的多晶硅薄膜晶体管及其制造方法
Pangal et al. Hydrogen plasma-enhanced crystallization of amorphous silicon for low-temperature polycrystalline silicon TFT's
Packard et al. Flash-Lamp Annealing for Manufacturing of Reduced Thermal Budget Self-Aligned LTPS TFTs

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18756335

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18756335

Country of ref document: EP

Kind code of ref document: A1