WO2019019277A1 - 低温多晶硅薄膜晶体管及其制作方法、显示设备 - Google Patents

低温多晶硅薄膜晶体管及其制作方法、显示设备 Download PDF

Info

Publication number
WO2019019277A1
WO2019019277A1 PCT/CN2017/100714 CN2017100714W WO2019019277A1 WO 2019019277 A1 WO2019019277 A1 WO 2019019277A1 CN 2017100714 W CN2017100714 W CN 2017100714W WO 2019019277 A1 WO2019019277 A1 WO 2019019277A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
polysilicon
forming
source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/100714
Other languages
English (en)
French (fr)
Inventor
李松杉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/736,150 priority Critical patent/US20190386147A1/en
Publication of WO2019019277A1 publication Critical patent/WO2019019277A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/254—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks

Definitions

  • the invention belongs to the technical field of thin film transistor fabrication, and in particular to a low temperature polysilicon thin film transistor, a manufacturing method thereof and a display device.
  • liquid crystal displays LCDs
  • organic light emitting diodes OLED
  • amorphous silicon thin film transistors are widely used as switching elements of LCD and OLED displays, but a-Si TFT LCDs are required to be thin, lightweight, high-definition, high in brightness, high in reliability, Requirements such as low power consumption are still limited.
  • Lower Temperature Polycrystal Silicon (LTPS) TFTs have significant advantages in meeting the above requirements compared to a-Si TFTs.
  • the leakage current I off of the low temperature polysilicon thin film transistor is increased, thereby affecting the characteristics of the low temperature polysilicon thin film transistor. This in turn affects the display quality of LCD and OLED displays.
  • a low temperature polysilicon thin film transistor comprising: a substrate; a gate disposed on the substrate; a gate insulating layer disposed on the substrate and the gate; a source layer disposed on the gate insulating layer, the polysilicon active layer including a polysilicon body layer And a source contact layer and a drain contact layer respectively disposed at two ends of the polysilicon body layer; an etch barrier layer disposed on the gate insulating layer and the polysilicon active layer, wherein the etch barrier layer has a first a via hole exposing the source contact layer, the second via hole exposing the drain contact layer; a source and a drain disposed on the etch barrier a layer, the source filling the first via to contact the source contact layer, the drain filling the second via to contact the drain contact layer; a passivation layer Provided on the source, the drain, and the etch stop layer.
  • the source contact layer and the drain contact layer are doped with boron ions.
  • the etch stop layer is made of an oxide of silicon and/or a nitride of silicon.
  • a display device comprising the above-described low temperature polysilicon thin film transistor.
  • a method for fabricating a low temperature polysilicon thin film transistor includes the steps of: providing a substrate; forming a gate on the substrate; fabricating on the substrate and the gate Forming a gate insulating layer; forming a polysilicon layer on the gate insulating layer; forming an etch barrier layer on the gate insulating layer and the polysilicon layer; forming a first pass in the etch stop layer a hole and a second via, the first via exposing one end of the polysilicon layer, the second via exposing the other end of the polysilicon layer; forming an exposed end of the polysilicon layer a contact layer, and exposing the other end of the polysilicon layer to form a drain contact layer; forming a source and a drain on the etch stop layer, the source filling the first via hole to Contacting the source contact layer, the drain filling the second via to contact the drain contact layer; fabricating on the source, the drain, and the etch stop layer A passivation layer is formed.
  • the method of “forming a polysilicon layer on the gate insulating layer” includes: forming an amorphous silicon layer on the gate insulating layer; using the ion implantation technology in the amorphous silicon Implanting ions in the layer; recrystallizing the amorphous silicon layer by rapid thermal annealing to form a polysilicon layer and an ion doped polysilicon layer on the polysilicon layer; the doping is performed by dry etching The polysilicon layer of the impurity ions is removed.
  • the method of “forming a first via hole and a second via hole in the etch barrier layer” includes: forming a photoresist layer on the etch barrier layer; and performing the photoresist layer on the photoresist layer Patterning treatment to form a first via and a second pass in a portion of the photoresist layer exposing the etch stop layer a hole; a portion of the exposed etch stop layer is removed to form the first via and the second via in the etch barrier.
  • the method of forming a source contact layer at one end of the exposed polysilicon layer and forming the drain contact layer at the other end of the exposed polysilicon layer in the step includes: using ion implantation technology Implanting ions in one end and the other end of the polysilicon layer; performing rapid thermal annealing activation on one end and the other end of the polysilicon layer implanting ions; and removing the remaining photoresist layer.
  • the etch stop layer is made of an oxide of silicon and/or a nitride of silicon.
  • the ions implanted by the ion implantation technique are boron ions.
  • the invention has the beneficial effects that the invention can prevent direct contact between the source and the drain and the undoped polysilicon layer, thereby reducing the leakage current of the low temperature polysilicon thin film transistor, thereby greatly improving the characteristics of the low temperature polysilicon thin film transistor.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIGS. 2A through 2I are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • 3A-3C are process diagrams of a first via and a second via in an etch stop layer, in accordance with an embodiment of the present invention.
  • FIGS. 4A through 4C are process diagrams of a source contact layer and a drain contact layer, in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • a low temperature polysilicon thin film transistor includes a substrate 100, a gate 200, a gate insulating layer 300, a polysilicon active layer 400, an etch barrier 500, a source 600, a drain 700, and passivation.
  • Layer 800 a low temperature polysilicon thin film transistor
  • the substrate 100 may be, for example, a transparent glass substrate or a resin substrate, but the present invention is not limited thereto.
  • the gate 200 is disposed on the substrate 100.
  • the gate electrode 200 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the gate insulating layer 300 is disposed on the gate 200 and the substrate 100.
  • the gate insulating layer 300 may be, for example, a SiN x /SiO x structure formed on the gate 200 and the substrate 100, but the present invention is not limited thereto.
  • the gate insulating layer 300 may also be a single layer of SiN x . Structure or SiO x structure.
  • the polysilicon active layer 400 is disposed on the gate insulating layer 300.
  • the polysilicon active layer 400 includes a polysilicon body layer 410 and a source contact layer 420 and a drain contact layer 430 respectively located at opposite ends of the polysilicon body layer 410.
  • the source contact layer 420 and the drain contact layer 430 have boron ions implanted by an ion implantation technique, but the present invention is not limited thereto.
  • the etch barrier layer 500 is disposed on the polysilicon active layer 400 and the gate insulating layer 300, and the etch barrier layer 500 has a first via 510 and a second via 520, and the first via 510 exposes the source contact layer 420, The second via 520 exposes the drain contact layer 430.
  • the etching stopper layer 500 is formed of SiN x and/or SiO x , but the present invention is not limited thereto.
  • the source 600 and the drain 700 are disposed on the etch barrier 500, the source 600 fills the first via 510 to be in contact with the source contact layer 420, and the drain 700 fills the second via 520 to Contact layer 430 is in contact.
  • the source 600 and the drain 700 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • the passivation layer 800 is disposed on the source 600, the drain 700, and the etch stop layer 500.
  • the passivation layer 800 is formed of an oxide of silicon such as SiO x , but the present invention is not limited thereto.
  • the low temperature polysilicon thin film transistor according to an embodiment of the present invention can be applied to a display device such as a liquid crystal display device and an OLED display device.
  • the low temperature polysilicon thin film transistor of the embodiment of the present invention can prevent the source 600 and the drain 700 from directly contacting the polysilicon body layer 410, thereby reducing the leakage current of the low temperature polysilicon thin film transistor, thereby greatly improving the characteristics of the low temperature polysilicon thin film transistor.
  • FIGS. 2A through 2I are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 2A, a substrate 100 is provided.
  • the substrate 100 may be, for example, an insulating and transparent glass substrate or a resin substrate, but the invention is not limited thereto.
  • a gate electrode 200 is formed on the substrate 100.
  • the gate electrode 400 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • a gate insulating layer 300 is formed on the substrate 100 and the gate 200.
  • the gate insulating layer 300 may be, for example, a SiN x /SiO x structure formed on the semiconductor body layer 210, but the invention is not limited thereto, for example, the gate insulating layer 300 may also be a single-layer SiN x structure or SiO x structure.
  • Step 4 Referring to FIG. 2D, a polysilicon layer 400A is formed on the gate insulating layer 300.
  • the method of forming the polysilicon layer 400A specifically includes: first, forming an amorphous silicon layer on the gate insulating layer 300 by plasma enhanced chemical vapor deposition (PECVD); An ion implantation (Ion Implant) technique implants ions (such as boron ions, etc.) into the amorphous silicon layer; then, recrystallizes the amorphous silicon layer in a rapid thermal annealing manner, thereby A polysilicon layer 400A and a doped ion polysilicon layer on the polysilicon layer 400A are formed; finally, the ion doped polysilicon layer is removed by dry etching.
  • PECVD plasma enhanced chemical vapor deposition
  • Ion Implant ion Implant
  • Step 5 Referring to FIG. 2E, an etch stop layer 500 is formed on the gate insulating layer 300 and the polysilicon layer 400A.
  • the etching stopper layer 500 is formed of an oxide of silicon such as SiO x and/or a nitride of silicon such as SiN x , but the present invention is not limited thereto.
  • Step 6 referring to FIG. 2F, forming a first via 510 and a second via 520 in the etch barrier 500, the first via 510 exposing one end of the polysilicon layer 400A, and the second via 520 exposing the polysilicon layer 400A The other end.
  • FIGS. 3A-3C are process diagrams of first and second vias in an etch stop layer, in accordance with an embodiment of the present invention.
  • the method of forming the first via 510 and the second via 520 in the etch barrier layer according to the embodiment of the present invention includes: first, referring to FIG. 3A, forming a photoresist layer PR on the etch barrier layer 500; 3B, patterning the photoresist layer PR to form a first via hole PR1 and a second via hole PR2 exposing a portion of the etch barrier layer 500 in the photoresist layer PR; finally, referring to FIG. 3C, the exposed portion will be exposed A portion of the etch barrier layer 500 is removed, thereby forming a first via 510 and a second via 520 in the etch barrier layer 500.
  • Step 7 Referring to FIG. 2G, one end of the exposed polysilicon layer 400A is formed with a source contact layer 420, and the other end of the exposed polysilicon layer 400A is formed with a drain contact layer 430.
  • the portion of the polysilicon layer 400A other than the source contact layer 420 and the drain contact layer 430 is the polysilicon body layer 410 shown in FIG. 1, such that the polysilicon body layer 410, the source contact layer 420, and the drain contact layer. 430 constitutes the polysilicon active layer 400 shown in FIG.
  • a method of forming a source contact layer and a drain contact layer according to an embodiment of the present invention includes: first, referring to FIG. 4A, implanting ions (such as boron ions) in one end and the other end of the polysilicon layer 400A by ion implantation techniques, respectively.
  • FIG. 4B implanting ions (such as boron ions) in one end and the other end of the polysilicon layer 400A by ion implantation techniques, respectively.
  • RTA rapid thermal annealing
  • Step 8 Referring to FIG. 2H, a source 600 and a drain 700 are formed on the etch stop layer 500.
  • the source 600 fills the first via 510 to be in contact with the source contact layer 420, and the drain 700 fills the second via. 520 is in contact with the drain contact layer 430.
  • the source 600 and the drain 700 may be a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure, or may be a single layer molybdenum structure or a single layer aluminum structure, but the invention is not limited thereto.
  • Step 9 Referring to FIG. 2I, a passivation layer 800 is formed on the source 600, the drain 700, and the etch barrier 500.
  • the passivation layer 800 is formed of an oxide of silicon such as SiO x , but the present invention is not limited thereto.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

一种低温多晶硅薄膜晶体管，其包括：基板（100）；栅极（200），设置于基板（100）上；栅极绝缘层（300），设置于基板（100）和栅极（200）上；多晶硅有源层（400），设置于栅极绝缘层（300）上，多晶硅有源层（400）包括源极接触层（420）和漏极接触层（430）；蚀刻阻挡层（500），设置于栅极绝缘层（300）和多晶硅有源层（400）上，蚀刻阻挡层（500）中具有暴露源极接触层（420）的第一过孔（510）和暴露漏极接触层（430）的第二过孔（520）；源极（600）和漏极（700），设置于蚀刻阻挡层（500）上，源极（600）填充第一过孔（510），以与源极接触层（420）接触，漏极（700）填充第二过孔（520），以与漏极接触层（430）接触；钝化层（800），设置于源极（600）、漏极（700）和蚀刻阻挡层（500）上。还提供了一种低温多晶硅薄膜晶体管的制作方法及显示设备。能防止源极（600）和漏极（700）与未掺杂的多晶硅层直接接触，从而减小低温多晶硅薄膜晶体管的漏电流。

Description

低温多晶硅薄膜晶体管及其制作方法、显示设备 技术领域
本发明属于薄膜晶体管制作技术领域，具体地讲，涉及一种低温多晶硅薄膜晶体管及其制作方法、显示设备。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)和有机发光二极管(OLED)显示器因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD和OLED显示器的开关元件而广泛采用的是非晶硅薄膜三极管(a-Si TFT)，但a-Si TFT LCD在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)TFT与a-Si TFT相比，在满足上述要求方面，具有明显优势。
然而在目前的低温多晶硅薄膜晶体管中，由于源极和漏极能够与未掺杂离子的多晶硅层接触，因此会导致低温多晶硅薄膜晶体管漏电流Ioff增大，从而影响低温多晶硅薄膜晶体管的特性，进而会影响LCD和OLED显示器的显示质量。
发明内容
为了解决上述现有技术的问题，本发明的目的在于提供一种能够减小漏电流的低温多晶硅薄膜晶体管及其制作方法、显示设备。
根据本发明的一方面，提供了一种低温多晶硅薄膜晶体管，其包括：基板；栅极，设置于所述基板上；栅极绝缘层，设置于所述基板和所述栅极上；多晶硅有源层，设置于所述栅极绝缘层上，所述多晶硅有源层包括多晶硅本体层以 及分别位于所述多晶硅本体层两端的源极接触层和漏极接触层；蚀刻阻挡层，设置于所述栅极绝缘层和所述多晶硅有源层上，所述蚀刻阻挡层中具有第一过孔和第二过孔，所述第一过孔暴露出所述源极接触层，所述第二过孔暴露出所述漏极接触层；源极和漏极，设置于所述蚀刻阻挡层上，所述源极填充所述第一过孔，以与所述源极接触层接触，所述漏极填充所述第二过孔，以与所述漏极接触层接触；钝化层，设置于所述源极、所述漏极和所述刻蚀阻挡层上。
可选地，所述源极接触层和所述漏极接触层中掺杂有硼离子。
可选地，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
根据本发明的另一方面，还提供了一种显示设备，其包括上述的低温多晶硅薄膜晶体管。
根据本发明的又一方面，又提供了一种低温多晶硅薄膜晶体管的制作方法，其包括步骤：提供一基板；在所述基板上制作形成栅极；在所述基板和所述栅极上制作形成栅极绝缘层；在所述栅极绝缘层上制作形成多晶硅层；在所述栅极绝缘层和所述多晶硅层上制作形成蚀刻阻挡层；在所述蚀刻阻挡层中制作形成第一过孔和第二过孔，所述第一过孔暴露出所述多晶硅层的一端，所述第二过孔暴露出所述多晶硅层的另一端；将暴露出的所述多晶硅层的一端形成源极接触层，并将暴露出的所述多晶硅层的另一端形成漏极接触层；在所述蚀刻阻挡层上制作形成源极和漏极，所述源极填充所述第一过孔，以与所述源极接触层接触，所述漏极填充所述第二过孔，以与所述漏极接触层接触；在所述源极、所述漏极和所述刻蚀阻挡层上制作形成钝化层。
可选地，在步骤“在所述栅极绝缘层上制作形成多晶硅层”的方法包括：在所述栅极绝缘层上制作形成非晶硅层；利用离子植入技术在所述非晶硅层中植入离子；以快速热退火技术使所述非晶硅层再结晶，从而生成多晶硅层以及在所述多晶硅层上的掺杂离子的多晶硅层；利用干刻蚀的方式将所述掺杂离子的多晶硅层去除。
可选地，在步骤“在所述蚀刻阻挡层中制作形成第一过孔和第二过孔”的方法包括：在所述蚀刻阻挡层上制作形成光阻层；对所述光阻层进行图案化处理，以在所述光阻层中形成暴露所述蚀刻阻挡层的部分的第一通孔和第二通 孔；将暴露出的所述蚀刻阻挡层的部分去除，从而在所述蚀刻阻挡层中形成所述第一过孔和所述第二过孔。
可选地，在步骤“将暴露出的所述多晶硅层的一端形成源极接触层，并将暴露出的所述多晶硅层的另一端形成漏极接触层”的方法包括：利用离子植入技术在所述多晶硅层的一端和另一端中分别植入离子；对植入离子的所述多晶硅层的一端和另一端进行快速热退火活化；将剩余的所述光阻层去除。
可选地，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
可选地，所述利用离子植入技术植入的离子为硼离子。
本发明的有益效果：本发明能防止源极和漏极与未掺杂的多晶硅层直接接触，从而减小低温多晶硅薄膜晶体管的漏电流，进而可以大幅度改善低温多晶硅薄膜晶体管的特性。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图；
图2A至图2I是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图；
图3A至图3C是根据本发明的实施例的蚀刻阻挡层中第一过孔和第二过孔的制程图；
图4A至图4C是根据本发明的实施例的源极接触层和漏极接触层的制程图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的 各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基板的元件被称作“在”另一元件“上”时，该元件可以直接在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”另一元件“上”时，不存在中间元件。
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图。
参照图1，根据本发明的实施例的低温多晶硅薄膜晶体管包括基板100、栅极200、栅极绝缘层300、多晶硅有源层400、蚀刻阻挡层500、源极600、漏极700和钝化层800。
具体而言，基板100可例如是透明的玻璃基板或者树脂基板，但本发明并不限制于此。
栅极200设置于基板100上。栅极200可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
栅极绝缘层300设置于栅极200和基板100上。这里，栅极绝缘层300可例如是在栅极200和基板100上形成的SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层300也可以是单层的SiNx结构或SiOx结构。
多晶硅有源层400设置于栅极绝缘层300上。多晶硅有源层400包括多晶硅本体层410以及分别位于多晶硅本体层410两端的源极接触层420和漏极接触层430。在本实施例中，源极接触层420和漏极接触层430中具有被采用离子注入技术注入的硼离子，但本发明并不限制于此。
蚀刻阻挡层500设置于多晶硅有源层400和栅极绝缘层300上，并且蚀刻阻挡层500具有第一过孔510和第二过孔520，第一过孔510暴露出源极接触层420，第二过孔520暴露出漏极接触层430。在本实施例中，蚀刻阻挡层500由SiNx和/或SiOx形成，但本发明并不限制于此。
源极600和漏极700设置于蚀刻阻挡层500上，源极600填充第一过孔510，以与源极接触层420接触，漏极700填充第二过孔520，以与所述漏极接触层430接触。源极600和漏极700可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
钝化层800设置于源极600、漏极700和蚀刻阻挡层500。在本实施例中，钝化层800由硅的氧化物(诸如SiOx)形成，但本发明并不限制于此。
根据本发明的实施例的低温多晶硅薄膜晶体管可应用于显示设备中，诸如液晶显示设备和OLED显示设备中。本发明的实施例的低温多晶硅薄膜晶体管能防止源极600和漏极700与多晶硅本体层410直接接触，从而减小低温多晶硅薄膜晶体管的漏电流，进而可以大幅度改善低温多晶硅薄膜晶体管的特性。
以下对根据本发明的实施例的低温多晶硅薄膜晶体管的制作方法进行详细描述。
图2A至图2I是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图。
根据本发明的实施例的金属氧化物薄膜晶体管的制作方法包括：
步骤一：参照图2A，提供一基板100。基板100可例如为一绝缘且透明的玻璃基板或树脂基板，但本发明并不限制于此。
步骤二：参照图2B，在基板100上制作形成栅极200。栅极400可以是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤三：参照图2C，在基板100和栅极200上制作形成栅极绝缘层300。这里，栅极绝缘层300可例如是在半导体本体层210上形成的SiNx/SiOx结构，但本发明并不限制于此，例如栅极绝缘层300也可以是单层的SiNx结构或SiOx结构。
步骤四：参照图2D，在栅极绝缘层300上制作形成多晶硅层400A。
这里，形成多晶硅层400A的方法具体包括：首先，利用等离子体增强化学气相沉积法(PECVD)在栅极绝缘层300上制作形成非晶硅层；接着，利用 离子植入(Ion Implant)技术在所述非晶硅层中植入离子(诸如硼离子等)；接着，以快速热退火(Rapid Thermal Anneal)的方式使所述非晶硅层再结晶，从而生成多晶硅层400A以及在多晶硅层400A上的掺杂离子的多晶硅层；最后，利用干刻蚀的方式将所述掺杂离子的多晶硅层去除。
步骤五：参照图2E，在栅极绝缘层300和多晶硅层400A上制作形成蚀刻阻挡层500。这里，蚀刻阻挡层500由硅的氧化物(诸如SiOx)和/或硅的氮化物(诸如SiNx)形成，但本发明并不限制于此。
步骤六，参照图2F，在蚀刻阻挡层500中制作形成第一过孔510和第二过孔520，第一过孔510暴露出多晶硅层400A的一端，第二过孔520暴露出多晶硅层400A的另一端。
图3A至图3C是根据本发明的实施例的蚀刻阻挡层中第一过孔和第二过孔的制程图。根据本发明的实施例的蚀刻阻挡层中形成第一过孔510和第二过孔520的方法包括：首先，参照图3A，在蚀刻阻挡层500上制作形成光阻层PR；接着，参照图3B，对光阻层PR进行图案化处理，以在光阻层PR中形成暴露蚀刻阻挡层500的部分的第一通孔PR1和第二通孔PR2；最后，参照图3C，将暴露出的蚀刻阻挡层500的部分去除，从而在蚀刻阻挡层500中形成第一过孔510和第二过孔520。
步骤七：参照图2G，将暴露出的多晶硅层400A的一端形成源极接触层420，并将暴露出的多晶硅层400A的另一端形成漏极接触层430。其中，多晶硅层400A的除源极接触层420和漏极接触层430之外的部分为图1所示的多晶硅本体层410，这样，多晶硅本体层410、源极接触层420和漏极接触层430构成了图1所示的多晶硅有源层400。
图4A至图4C是根据本发明的实施例的源极接触层和漏极接触层的制程图。根据本发明的实施例的源极接触层和漏极接触层的形成方法包括：首先，参照图4A，利用离子植入技术在多晶硅层400A的一端和另一端中分别植入离子(诸如硼离子)；接着，参照图4B，对植入离子的多晶硅层400A的一端和另一端进行快速热退火(RTA)活化；最后，参照图4C，将剩余的光阻层PR刻蚀去除。
步骤八：参照图2H，在蚀刻阻挡层500上制作形成源极600和漏极700，源极600填充第一过孔510，以与源极接触层420接触，漏极700填充第二过孔520，以与漏极接触层430接触。源极600和漏极700可采用钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构，也可以是单层的钼结构或者单层的铝结构，但本发明并不限制于此。
步骤九：参照图2I，在源极600、漏极700和蚀刻阻挡层500上制作形成钝化层800。这里，钝化层800由硅的氧化物(诸如SiOx)形成，但本发明并不限制于此。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管，其中，包括：
    基板；
    栅极，设置于所述基板上；
    栅极绝缘层，设置于所述基板和所述栅极上；
    多晶硅有源层，设置于所述栅极绝缘层上，所述多晶硅有源层包括多晶硅本体层以及分别位于所述多晶硅本体层两端的源极接触层和漏极接触层；
    蚀刻阻挡层，设置于所述栅极绝缘层和所述多晶硅有源层上，所述蚀刻阻挡层中具有第一过孔和第二过孔，所述第一过孔暴露出所述源极接触层，所述第二过孔暴露出所述漏极接触层；
    源极和漏极，设置于所述蚀刻阻挡层上，所述源极填充所述第一过孔，以与所述源极接触层接触，所述漏极填充所述第二过孔，以与所述漏极接触层接触；
    钝化层，设置于所述源极、所述漏极和所述刻蚀阻挡层上。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述源极接触层和所述漏极接触层中掺杂有硼离子。
  3. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
  4. 一种显示设备，其中，包括权利要求1所述的低温多晶硅薄膜晶体管。
  5. 一种低温多晶硅薄膜晶体管的制作方法，其中，包括步骤：
    提供一基板；
    在所述基板上制作形成栅极；
    在所述基板和所述栅极上制作形成栅极绝缘层；
    在所述栅极绝缘层上制作形成多晶硅层；
    在所述栅极绝缘层和所述多晶硅层上制作形成蚀刻阻挡层；
    在所述蚀刻阻挡层中制作形成第一过孔和第二过孔，所述第一过孔暴露出所述多晶硅层的一端，所述第二过孔暴露出所述多晶硅层的另一端；
    将暴露出的所述多晶硅层的一端形成源极接触层，并将暴露出的所述多晶硅层的另一端形成漏极接触层；
    在所述蚀刻阻挡层上制作形成源极和漏极，所述源极填充所述第一过孔，以与所述源极接触层接触，所述漏极填充所述第二过孔，以与所述漏极接触层接触；
    在所述源极、所述漏极和所述刻蚀阻挡层上制作形成钝化层。
  6. 根据权利要求5所述的制作方法，其中，在步骤“在所述栅极绝缘层上制作形成多晶硅层”的方法包括：
    在所述栅极绝缘层上制作形成非晶硅层；
    利用离子植入技术在所述非晶硅层中植入离子；
    以快速热退火技术使所述非晶硅层再结晶，从而生成多晶硅层以及在所述多晶硅层上的掺杂离子的多晶硅层；
    利用干刻蚀的方式将所述掺杂离子的多晶硅层去除。
  7. 根据权利要求5所述的制作方法，其中，在步骤“在所述蚀刻阻挡层中制作形成第一过孔和第二过孔”的方法包括：
    在所述蚀刻阻挡层上制作形成光阻层；
    对所述光阻层进行图案化处理，以在所述光阻层中形成暴露所述蚀刻阻挡层的部分的第一通孔和第二通孔；
    将暴露出的所述蚀刻阻挡层的部分去除，从而在所述蚀刻阻挡层中形成所述第一过孔和所述第二过孔。
  8. 根据权利要求6所述的制作方法，其中，在步骤“在所述蚀刻阻挡层中制作形成第一过孔和第二过孔”的方法包括：
    在所述蚀刻阻挡层上制作形成光阻层；
    对所述光阻层进行图案化处理，以在所述光阻层中形成暴露所述蚀刻阻挡层的部分的第一通孔和第二通孔；
    将暴露出的所述蚀刻阻挡层的部分去除，从而在所述蚀刻阻挡层中形成所述第一过孔和所述第二过孔。
  9. 根据权利要求7所述的制作方法，其中，在步骤“将暴露出的所述多晶硅层的一端形成源极接触层，并将暴露出的所述多晶硅层的另一端形成漏极接触层”的方法包括：
    利用离子植入技术在所述多晶硅层的一端和另一端中分别植入离子；
    对植入离子的所述多晶硅层的一端和另一端进行快速热退火活化；
    将剩余的所述光阻层去除。
  10. 根据权利要求8所述的制作方法，其中，在步骤“将暴露出的所述多晶硅层的一端形成源极接触层，并将暴露出的所述多晶硅层的另一端形成漏极接触层”的方法包括：
    利用离子植入技术在所述多晶硅层的一端和另一端中分别植入离子；
    对植入离子的所述多晶硅层的一端和另一端进行快速热退火活化；
    将剩余的所述光阻层去除。
  11. 根据权利要求5所述的制作方法，其中，所述蚀刻阻挡层由硅的氧化物和/或硅的氮化物制成。
  12. 根据权利要求9所述的制作方法，其中，所述利用离子植入技术植入 的离子为硼离子。
  13. 根据权利要求10所述的制作方法，其中，所述利用离子植入技术植入的离子为硼离子。
PCT/CN2017/100714 2017-07-27 2017-09-06 低温多晶硅薄膜晶体管及其制作方法、显示设备 Ceased WO2019019277A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/736,150 US20190386147A1 (en) 2017-07-27 2017-09-06 Lower temperature polycrystal silicon thin film transistor and manufacturing method thereof, display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710624553.8A CN107393966A (zh) 2017-07-27 2017-07-27 低温多晶硅薄膜晶体管及其制作方法、显示设备
CN201710624553.8 2017-07-27

Publications (1)

Publication Number Publication Date
WO2019019277A1 true WO2019019277A1 (zh) 2019-01-31

Family

ID=60341265

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/100714 Ceased WO2019019277A1 (zh) 2017-07-27 2017-09-06 低温多晶硅薄膜晶体管及其制作方法、显示设备

Country Status (3)

Country Link
US (1) US20190386147A1 (zh)
CN (1) CN107393966A (zh)
WO (1) WO2019019277A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104900532A (zh) * 2015-06-15 2015-09-09 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN106409844A (zh) * 2016-11-29 2017-02-15 深圳市华星光电技术有限公司 底栅型多晶硅tft基板及其制作方法
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6010923A (en) * 1997-03-31 2000-01-04 Sanyo Electric Co., Ltd. Manufacturing method of semiconductor device utilizing annealed semiconductor layer as channel region
JPH11145148A (ja) * 1997-11-06 1999-05-28 Tdk Corp 熱プラズマアニール装置およびアニール方法
JP3318285B2 (ja) * 1999-05-10 2002-08-26 松下電器産業株式会社 薄膜トランジスタの製造方法
JP2005340651A (ja) * 2004-05-28 2005-12-08 Sanyo Electric Co Ltd 半導体装置およびその製造方法
CN102280408A (zh) * 2011-06-28 2011-12-14 深圳市华星光电技术有限公司 薄膜晶体管矩阵基板及显示面板的制造方法
US10121553B2 (en) * 2015-09-30 2018-11-06 Sunrise Memory Corporation Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays
CN105428243B (zh) * 2016-01-11 2017-10-24 京东方科技集团股份有限公司 一种薄膜晶体管及制作方法、阵列基板和显示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104900532A (zh) * 2015-06-15 2015-09-09 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN106409844A (zh) * 2016-11-29 2017-02-15 深圳市华星光电技术有限公司 底栅型多晶硅tft基板及其制作方法
CN106910748A (zh) * 2017-04-10 2017-06-30 深圳市华星光电技术有限公司 一种阵列基板、显示装置及其制作方法

Also Published As

Publication number Publication date
US20190386147A1 (en) 2019-12-19
CN107393966A (zh) 2017-11-24

Similar Documents

Publication Publication Date Title
US10312271B2 (en) Array substrate, manufacturing method thereof and display device
CN105390451B (zh) 低温多晶硅tft基板的制作方法
CN102683354B (zh) 顶栅型n-tft、阵列基板及其制备方法和显示装置
WO2017020358A1 (zh) 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
US9711356B2 (en) Method for manufacturing thin-film transistor by implanting ions into channel region for lowering leakage current
WO2015123903A1 (zh) 一种低温多晶硅薄膜晶体管、阵列基板及其制作方法
CN107170759B (zh) 一种阵列基板及其制作方法、显示装置
WO2017070868A1 (zh) N型tft的制作方法
CN107316874B (zh) 阵列基板及其制作方法、显示装置
WO2016008226A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示设备
WO2017166833A1 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
WO2017028461A1 (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
WO2018000478A1 (zh) 薄膜晶体管的制造方法及阵列基板的制造方法
CN107275390A (zh) 薄膜晶体管及其制作方法、阵列基板及显示装置
CN105390443A (zh) Tft基板的制作方法
US10042211B2 (en) Liquid crystal display panel, array substrate and manufacturing method thereof
KR100729054B1 (ko) 박막 트랜지스터 및 그 제조 방법
CN106952963B (zh) 一种薄膜晶体管及制作方法、阵列基板、显示装置
WO2019071670A1 (zh) N型薄膜晶体管及其制备方法、oled显示面板的制备方法
CN109637932B (zh) 薄膜晶体管及其制备方法
WO2018032579A1 (zh) 一种tft基板的制备方法
US10516058B2 (en) Low temperature polysilicon thin film transistor and preparation method thereof
CN111599879B (zh) Pin感光器件及其制作方法、及显示面板
WO2019184026A1 (zh) Cmos晶体管的制备方法、阵列基板的制备方法
KR100811997B1 (ko) 박막트랜지스터 및 그 제조방법과 이를 포함한평판표시장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17918734

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17918734

Country of ref document: EP

Kind code of ref document: A1