WO2019015667A1 - 功率放大器 - Google Patents

功率放大器 Download PDF

Info

Publication number
WO2019015667A1
WO2019015667A1 PCT/CN2018/096421 CN2018096421W WO2019015667A1 WO 2019015667 A1 WO2019015667 A1 WO 2019015667A1 CN 2018096421 W CN2018096421 W CN 2018096421W WO 2019015667 A1 WO2019015667 A1 WO 2019015667A1
Authority
WO
WIPO (PCT)
Prior art keywords
power amplifier
input
power
frequency
signals
Prior art date
Application number
PCT/CN2018/096421
Other languages
English (en)
French (fr)
Inventor
杜清兆
索海雷
李松
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP18835340.3A priority Critical patent/EP3648345A4/en
Priority to BR112020001104-5A priority patent/BR112020001104A2/pt
Publication of WO2019015667A1 publication Critical patent/WO2019015667A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/246—A series resonance being added in shunt in the input circuit, e.g. base, gate, of an amplifier stage, e.g. as a trap
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/391—Indexing scheme relating to amplifiers the output circuit of an amplifying stage comprising an LC-network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to the field of communications and, more particularly, to power amplifiers in the field of communications.
  • the RF power amplifier module is the most energy-consuming module of the transmitter in wireless communication. Therefore, improving the efficiency of the power amplifier is the key to energy saving.
  • the existing power amplifier can work in a single-band narrowband signal mode, but the power amplifier is more efficient, but in dual-frequency or In the multi-frequency concurrent working mode, the efficiency of the power amplifier is poor, resulting in poor system performance.
  • the present application provides a power amplifier that can improve the efficiency of the power amplifier and help improve system performance.
  • a power amplifier comprising: an input terminal for inputting at least two signals of different frequencies; and a power tube for performing the at least two signals input by the input terminal Power amplification, and generating a first non-linear incremental signal of the at least two signals; a first suppression circuit for suppressing the first non-linear incremental signal; and an output end for outputting the power tube after amplification At least two signals; wherein the input is connected to the output through the power tube, and the power tube is connected to the first suppression circuit.
  • the envelope impedance corresponding to the first nonlinear incremental signal may be reduced, and thus, the power amplifier efficiency of the power amplifier may be improved.
  • the power tube can be connected to the output end by using the first suppression circuit, so that the envelope impedance of the output end is low, and the generation of the first nonlinear increment of the envelope can be suppressed, thereby improving Power amplifier efficiency in dual-frequency or multi-frequency concurrent scenarios.
  • the output impedance of the power tube may not have an output impedance of the first nonlinear incremental signal, thereby improving the power amplifier. Power consumption.
  • the at least two signals of different frequencies may be at least two signals that are dual-frequency or multi-frequency concurrent.
  • the output terminal can output the amplified at least two signals to a duplexer or an antenna or the like.
  • the output terminal can also output the amplified at least two signals to the lower power amplifier.
  • the first suppression circuit in the dual-frequency or multi-frequency operation mode, can suppress the nonlinear incremental signal generated by the power tube in the process of amplifying the dual-frequency or multi-frequency signal, so that the output can be avoided.
  • the non-linear incremental signal generated in the amplified dual-frequency or multi-frequency signal is output to the lower-level power amplifier, which can prevent the lower-level power amplifier from amplifying the nonlinear incremental signal and reduce the power consumption of the amplifier, thereby improving the lower-level power amplifier. Power amplifier efficiency.
  • the first suppression circuit includes a first capacitor and a first inductor, and the first inductor and the first capacitor are used to perform impedance at a frequency of the first nonlinear incremental signal Short circuit processing.
  • the first nonlinear incremental signal exhibits a series resonance at a frequency that is approximately shorted to ground.
  • the first suppression circuit may also be a capacitive and inductive component of a lumped parameter, or may be an equivalent component (eg, a microstrip, a varactor, etc.) having similar functions as the capacitor and the inductor.
  • the first inductor and the first capacitor are connected in series.
  • the resonant frequency of the first inductance and the first capacitance is determined by the frequency of the at least two signals.
  • the resonant frequency of the first inductance and the first capacitance is determined by a difference in frequency of the at least two signals.
  • the frequency of the at least two signals input by the input terminal is fixed, and the capacitance value of the first capacitor and the inductance value of the first inductor are fixed, and the capacitance value of the first capacitor and the inductance value of the first inductor are according to at least two signals.
  • the frequency is determined such that the resonant frequency of the first suppression circuit composed of the first capacitance and the first inductance is fixed; the frequency of the at least two signals input at the input end is not fixed, for example, at least two signals input at the first time
  • the frequency is different from the frequency of the at least two signals input at the second time, and the inductance value of the first inductor and the capacitance value of the first capacitor are adjustable, and the frequency varies according to the frequency of the input signal, thereby making the first
  • the resonant frequency of the suppression circuit is adjustable.
  • the first suppression circuit may include a set of first capacitance and a first inductance; if the first nonlinear incremental signal is M components, then The second suppression circuit includes M sets of the first capacitor and the first inductor; optionally, the capacitance values of the first capacitors of each of the M sets of the first capacitor and the first inductor may be different, and the first of each of the P sets of the first inductors
  • the inductance value of an inductor can be different, and M is an integer greater than or equal to 1.
  • the first suppression circuit includes a set of first inductance and a first capacitance; if the input signal is a signal of three different frequencies, the first suppression The circuit includes three sets of first capacitors and a first inductor. If the input signal is N signals of different frequencies, the first suppression circuit includes The first capacitor and the first inductor are set, and N is an integer greater than or equal to 2.
  • the spectrum generated by the power amplifier mainly includes the following spectral components: the fundamental frequency components F1 and F2, the envelope component F2-F1, and the third order.
  • the first suppression circuit of the embodiment of the present application can suppress the envelope component; optionally, the first suppression circuit of the embodiment of the present application can suppress the envelope component and the third-order intermodulation component. At least one of the second harmonic components.
  • the first suppression circuit may include more than two sets of the first capacitance and the first inductance.
  • the number of groups of the first inductor and the first capacitor included in the first suppression circuit may be determined according to requirements.
  • the first suppression circuit needs to suppress several components, and may include several sets of first capacitors and first inductors.
  • the number of sets of capacitors and first inductance is not limited to the frequency of the input signal.
  • the input terminal is further configured to: input a second non-linear incremental signal generated by the upper power amplifier to the power tube; the power amplifier further includes: a second suppression circuit, configured to suppress A second non-linear incremental signal; wherein the input is coupled to the second suppression circuit.
  • the input end is connected to the power tube through the second suppression circuit, so that the input end input includes a low impedance, and the second nonlinear increment of the envelope can be suppressed, thereby improving Power amplifier efficiency in dual-frequency or multi-frequency concurrent scenarios.
  • the second suppression circuit includes a second capacitor and a second inductor, and the second capacitor and the second inductor are used for impedance at a frequency of the second nonlinear incremental signal Short circuit treatment.
  • the second nonlinear incremental signal exhibits a series resonance at a frequency that is approximately shorted to ground.
  • the second suppression circuit may also be a capacitive and inductive component of a lumped parameter, or an equivalent component (eg, such as a microstrip, a varactor, etc.) that functions similarly to a capacitor and an inductor.
  • an equivalent component eg, such as a microstrip, a varactor, etc.
  • the second capacitor and the second inductor are connected in series.
  • the second suppression circuit may include a set of the second capacitor and the second inductor; and if the second nonlinear incremental signal is the P component, the second suppression The circuit includes a P group second capacitor and a second inductor; optionally, the capacitance values of the second capacitors of each of the P groups of the second capacitor and the second inductor may be different, and the second inductor of each of the P groups of the second inductors The inductance value can be different, and P is an integer greater than or equal to 1.
  • the resonant frequency of the second inductance and the second capacitance is determined by the frequency of the input signal of the superior power amplifier.
  • the resonant frequency of the second inductance and the second capacitance is determined by a difference in frequency of an input signal of the superior power amplifier.
  • the input signal of the upper power amplifier may also be at least two signals of different frequencies.
  • the power amplifier further includes: an input matching circuit for matching a first impedance of the input to a second impedance of the power tube input; and an output matching circuit for using the power a third impedance of the tube output is matched to a fourth impedance of the output; wherein the input is coupled to the power tube through the input matching circuit, and the power tube passes the output matching circuit and the output connection.
  • the power amplifier further includes: an input bias circuit for supplying power to the power tube through the input matching circuit; and an output bias circuit for using the output matching circuit to Power tube power supply.
  • the input bias circuit may be directly connected to the power tube, and the output bias circuit may be directly connected to the power tube.
  • a power amplifier comprising: an input terminal for inputting at least two signals of different frequencies and a second non-linear incremental signal generated by a superior power amplifier; and a second suppression circuit for suppressing said The input end inputs the second non-linear incremental signal; the power tube is configured to perform power amplification on the at least two signals of the different frequencies input by the input terminal to obtain at least two signals after amplification; And outputting the amplified at least two signals; wherein the input suppression circuit is connected to the power tube, and the input of the suppression circuit is connected to the output through the power tube.
  • the input end is connected to the power tube through the second suppression circuit, so that the input end input includes a low impedance, and the second nonlinear increment of the envelope can be suppressed, thereby improving Power amplifier efficiency in dual-frequency or multi-frequency concurrent scenarios.
  • the second suppression circuit includes a second capacitor and a second inductor, the second inductor and the second capacitor being used for impedance at a frequency of the second nonlinear incremental signal Short circuit treatment.
  • the resonant frequency of the second inductance and the second capacitance is determined by the frequency of the input signal of the superior power amplifier.
  • the resonant frequency of the second inductance and the second capacitance is determined by a difference in frequency of an input signal of the superior power amplifier.
  • the second capacitor and the second inductor in the second aspect may refer to the second capacitor and the second inductor in the first aspect.
  • the power amplifier in the first aspect or the implementation of any one of the first aspects may be a Doherty power amplifier or a different phase amplifier.
  • the power amplifier in any of the second aspect or the second aspect may be a Doherty power amplifier or a different phase amplifier.
  • FIG. 1 is a schematic diagram of an application scenario of an embodiment of the present application.
  • FIG. 2 shows a power amplifier provided by an embodiment of the present application.
  • FIG. 3 shows another power amplifier provided by an embodiment of the present application.
  • Fig. 4 is a view showing the effect of the prior art power amplifier.
  • FIG. 5 is a schematic diagram showing the efficiency of a power amplifier provided by an embodiment of the present application.
  • FIG. 6 shows still another power amplifier provided by the embodiment of the present application.
  • FIG. 7 shows still another power amplifier provided by the embodiment of the present application.
  • FIG. 8 shows still another power amplifier provided by the embodiment of the present application.
  • FIG. 9 shows still another power amplifier provided by the embodiment of the present application.
  • FIG. 10 shows still another power amplifier provided by the embodiment of the present application.
  • FIG. 11 shows still another power amplifier provided by the embodiment of the present application.
  • FIG. 12 shows still another power amplifier provided by the embodiment of the present application.
  • the power amplifier provided by the present application can be applied to a radio frequency module of a transmitting end in various communication systems, for example, a global system of mobile communication (GSM) system, a code division multiple access (CDMA) system, Wideband code division multiple access (WCDMA) system, general packet radio service (GPRS), long term evolution (LTE) system, LTE frequency division duplex (frequency division duplex, FDD) system, LTE time division duplex (TDD), universal mobile telecommunication system (UMTS), worldwide interoperability for microwave access (WiMAX) communication system, wireless local area network (wireless Local area network (WLAN) or the future fifth generation (5G).
  • GSM global system of mobile communication
  • CDMA code division multiple access
  • WCDMA Wideband code division multiple access
  • GPRS general packet radio service
  • LTE long term evolution
  • LTE LTE frequency division duplex
  • FDD frequency division duplex
  • TDD LTE time division duplex
  • UMTS universal mobile telecommunication system
  • WiMAX worldwide interoper
  • the power amplifier amplifies the signal into a narrowband signal, for example, a modulated signal at 1840 MHz, or a modulated signal at 2140 MHz, and the power amplifier is more efficient.
  • the power amplifier amplifies the signal into a wideband signal, for example, a modulated signal at 1840 MHz + 2140 MHz. Due to the nonlinear characteristics of the power tube in the dual-frequency or multi-frequency operation mode, the output spectral components of the power amplifier are very rich.
  • the spectrum generated by the power amplifier mainly includes the following spectral components: the fundamental frequency components F1 and F2, the envelope component F2-F1, and the third-order intermodulation component 2*F2- F1 and 2*F1-F2, second harmonic component 2*F1, 2*F2, F1+F2, third harmonic component 3*F1, 3*F2, 2*F1+F2, 2*F2+F1, etc.
  • the fundamental component is a useful signal, and the other components produced by the power amplifier are nonlinear incremental signals. These nonlinear increments are useless signals that interfere with the signals of other devices.
  • the amplifier also amplifies during amplification.
  • the power amplifier provided by the embodiment of the present application can suppress the nonlinear incremental signal during the amplification process, thereby preventing the power amplifier from amplifying the power of the nonlinear incremental signal during the amplification process, thereby improving the power amplifier. Power amplifier efficiency of the power amplifier.
  • the power amplifier in the embodiment of the present application can be applied to a power amplifier architecture such as a Doherty power amplifier architecture, an out-of-phase amplifier, an envelope tracking amplifier, or the like, or is applied to other high-efficiency power amplifier architectures. This is not limited.
  • connection between A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B can pass other devices, which is not limited in this embodiment of the present application.
  • first nonlinear increment, the second nonlinear increment, or the nonlinear increment in the embodiment of the present application may be an envelope component, which may be all or part of an envelope component generated by the amplifier in the process of amplifying the signal. This embodiment of the present application does not limit this.
  • the embodiment of the present application can be applied to a scenario of a multi-stage amplifier, and is of course not limited to a multi-stage amplifier, and may also be a first-order amplifier.
  • the amplifying circuit includes an n-stage amplifier, and n is greater than or An integer equal to 1, the amplifiers in Figure 1 can all operate in dual or multi-frequency operation.
  • the amplifier in the embodiment of the present application may be a first stage amplifier, and a first suppression circuit of the amplifier is connected to an output end of the amplifier, and the first suppression circuit is configured to suppress a nonlinear incremental signal generated in the amplifier.
  • the amplifier in the embodiment of the present application may be a second stage amplifier, and a second suppression circuit of the amplifier is connected to an input end of the amplifier, and the second suppression circuit is configured to suppress nonlinear increase generated by the first stage amplifier.
  • the second stage amplifier includes a first suppression circuit and a second suppression circuit.
  • the first suppression circuit is connected to the output end, so that the envelope impedance of the output end is low, and the generation of the first nonlinear increment of the envelope can be suppressed.
  • the amplifier in the embodiment of the present application may be an nth stage amplifier, and a second suppression circuit of the amplifier is connected to an input end of the amplifier, and the second suppression circuit is configured to suppress a non-negative amplifier.
  • the linear incremental signal so that the nonlinear incremental signal generated by the n-1th stage amplifier can be suppressed before the amplifier amplifies the signal, so that the envelope impedance at the input end is low, so that the amplifier can be prevented from amplifying the nth-
  • the non-linear incremental signal generated by the level 1 amplifier can improve the amplifier's power amplifier efficiency.
  • the amplifier in the embodiment of the present application may be an nth stage amplifier, and a first suppression circuit of the amplifier is connected to an output end of the amplifier, and a first suppression circuit of the amplifier is used to suppress nonlinear increase generated by the amplifier.
  • the output signal, the envelope impedance of the output of the power tube in the nth stage amplifier is very low, so that the power amplifier efficiency of the nth stage amplifier can be improved; for example, the amplifier in the embodiment of the present application can be an nth stage amplifier.
  • a first suppression circuit in the amplifier is coupled to an output of the amplifier
  • a second suppression circuit of the amplifier is coupled to an input of the amplifier
  • a first suppression circuit is configured to suppress nonlinear increase generated by the n-1th stage amplifier
  • the quantity signal can avoid the non-linear incremental signal generated by the nth stage amplifier amplifying the n-1th stage amplifier, and the input impedance of the input end of the nth stage amplifier is very low
  • the second suppression circuit is used for suppressing the nth stage.
  • the nonlinear incremental signal generated by the amplifier can make the envelope impedance of the output of the nth stage amplifier very low, and can significantly suppress the generation of the envelope component. Enhance the efficiency of the power amplifier in dual or multiple frequently made the scene
  • the n-1th stage amplifier in FIG. 1 may be referred to as the upper stage power amplifier of the nth stage amplifier, and the nth stage amplifier may be referred to as the lower stage power amplifier of the n-1th stage amplifier, for example, the first stage amplifier may A higher-level power amplifier called a second-stage amplifier, which can be called a lower-stage power amplifier of the first-stage amplifier.
  • the power amplifier 200 may be any one of the n power amplifiers in FIG. 1, for example, may be the nth stage amplifier in FIG.
  • the power amplifier 200 includes an input terminal 210, a power tube 220, a first suppression circuit 230, and an output terminal 240.
  • the input end 210 is configured to input at least two signals of different frequencies, and the at least two signals may be the same signal or different signals, which is not limited by the embodiment of the present application;
  • a power tube 220 configured to perform power amplification on the at least two signals input by the input terminal 210, and generate a first non-linear incremental signal of the at least two signals
  • the power tube 220 may At least two signals of different frequencies input by the input terminal 210 are amplified to obtain at least two signals that are amplified, and the power tube 220 generates a first nonlinearity of the at least two signals when the at least two signals of the different frequencies are amplified. Incremental signal
  • the first suppression circuit 230 is configured to suppress the first nonlinear incremental signal.
  • the output terminal 240 is configured to output at least two signals amplified by the power tube 220.
  • the input end 210 is connected to the output terminal 240 through the power tube 220, and the power tube 220 is connected to the first suppression circuit 230, such as the connection mode in FIG. 1, or the power tube.
  • the first suppression circuit 230 is connected to the output terminal 240, and the first suppression circuit 230 functions to suppress the first nonlinear incremental signal output by the power tube 230, as long as it is connected after the power tube 230, and outputs Before the terminal 240, the specific connection relationship is not limited in this application.
  • the first suppression circuit 230 can suppress the nonlinear incremental signal generated by the power tube 220 during the amplification of the dual-frequency or multi-frequency signal, when the first suppression circuit 230 suppresses
  • the envelope impedance of the output end is very low, and the first nonlinear incremental signal of the envelope can be significantly suppressed, thereby improving the power amplifier efficiency of the power amplifier in a dual-frequency or multi-frequency concurrent scenario.
  • the output terminal 240 is connected to a duplexer or an antenna or the like.
  • the first suppression circuit 230 can suppress the nonlinear incremental signal generated by the power tube 220 during the amplification of the dual-frequency or multi-frequency signal, thereby avoiding the output.
  • the output of the nonlinear incremental signal generated in the amplified dual-frequency or multi-frequency signal can prevent the next-level network from amplifying the nonlinear incremental signal and reduce the power consumption of the amplifier, thereby improving the power amplifier efficiency of the next-level network.
  • the first suppression circuit 230 includes a first inductor 231 and a first capacitor 232, wherein the first inductor 231 and the first capacitor 232 are used for The impedance at the frequency of the first nonlinear incremental signal is short-circuited.
  • the first inductor 231 and the first capacitor 232 may be connected in series.
  • the first suppression circuit may also be a capacitive and inductive component of a lumped parameter, or an equivalent component (eg, such as a microstrip, a varactor, etc.) that functions similarly to a capacitor and an inductor.
  • an equivalent component eg, such as a microstrip, a varactor, etc.
  • the resonant frequency of the first inductor 231 and the first capacitor 232 is determined by the frequency of the at least two signals, specifically, the first inductor 231 and the first capacitor The resonant frequency of 232 is determined by the difference in frequency of the at least two signals.
  • the resonant frequencies of the first inductor 231 and the first capacitor 232 are fixed.
  • the first The resonant frequency of the inductor 231 and the first capacitor 232 is 300MHz (2140MHz-1840MHz), which can reduce the double-frequency concurrent 300MHz nonlinear signal increment of the power amplifier output, as shown in FIG. 4 and FIG. 5, FIG. 4 and FIG.
  • the abscissa represents the output power
  • the ordinate represents the power amplifier efficiency.
  • FIG. 4 shows the power amplifier efficiency of the lower stage amplifier before the first suppression circuit 230 is increased
  • FIG. 5 shows the power amplifier efficiency of the lower stage amplifier after the first suppression circuit 230 is increased. After the first suppression circuit 230 is increased, the power amplifier efficiency is increased by five percentage points.
  • each set of capacitors and inductors can be a first capacitor 232 and a first inductor 231.
  • the resonant frequencies of the three sets of capacitors and inductors are AB, AC, and BC, respectively.
  • the first inductor 231 and the first capacitor 232 may change according to the frequency of the signal input by the input terminal, that is, the inductance value of the first inductor 231 and the first capacitor 232.
  • the capacitance value is adaptively adjustable so that the resonant frequency is adaptively adjustable with the input signal frequency.
  • the input terminal 210 is further configured to: input a second non-linear incremental signal generated by the upper power amplifier to the power tube 220; the power amplifier 200 further includes: a second suppression circuit 250, And for suppressing the second non-linear incremental signal; wherein the input end 210 is connected to the second suppression circuit 250.
  • the connection mode in FIG. 6 or the input terminal 210 is connected to the power tube 220 through the second suppression circuit 230, and the second suppression circuit 230 functions as the second input power amplifier of the input terminal 210.
  • the nonlinear incremental signal is suppressed, as long as it is connected after the output terminal 2100 and before the power tube 220.
  • the specific connection relationship is not limited in this application.
  • the power amplifier can be a power amplifier other than the first stage power amplifier of FIG.
  • the second suppression circuit 250 includes a second inductor 251 and a second capacitor 252, and the second inductor 251 and the second capacitor 252 are used to The impedance at the frequency of the two nonlinear incremental signals is short-circuited.
  • the connection relationship between the second inductor 251 and the second capacitor 252 may be similar to the connection relationship between the first inductor 231 and the first capacitor 232 in FIG.
  • the resonant frequencies of the second inductance 251 and the second capacitance 252 are determined by the frequency of the input signal of the upper power amplifier.
  • the resonant frequency of the second inductor 251 and the second capacitor 252 is determined by a difference in frequency of an input signal of the upper power amplifier.
  • the signal input by the upper power amplifier is a dual-frequency or multi-frequency concurrent signal
  • the resonant frequency of the second inductor 251 and the second capacitor 252 of the amplifier 200 is concurrently transmitted by the dual-frequency or multi-frequency of the upper power amplifier. The frequency of the signal is determined.
  • the resonant frequency of the second inductor 251 and the second capacitor is fixed.
  • the resonant frequencies of the second inductor 251 and the second capacitor 252 are 300 MHz (2140 MHz - 1840 MHz).
  • the resonant frequencies of the second inductor 251 and the second capacitor 252 may change according to the frequency of the concurrent signal of the upper-stage power amplifier, that is, the first
  • the resonant frequencies of the two inductors 251 and the second capacitor 252 are adaptively adjustable.
  • the power amplifier 200 further includes an input matching circuit 260 for matching the first impedance of the input terminal 210 to the second impedance of the power tube 220 input.
  • An output matching circuit 270 configured to match a third impedance output by the power tube 220 to a fourth impedance of the output terminal 240; wherein the input terminal 210 passes the input matching circuit 260 and the power tube Connected, the power tube 220 is connected to the output terminal 240 through the output matching circuit 270.
  • the second inductor 251 and the second capacitor 252 included in the second suppression power 250 may be connected in series on the input matching circuit 260.
  • the first inductance 231 and the first capacitance 232 included in the first suppression circuit 230 may be connected in series on the output matching circuit 270.
  • the second suppression circuit 250 can be connected to the input matching circuit 260 as shown in FIG. 8.
  • the input terminal 210 can also be connected to the input matching circuit 260 through the second suppression circuit 250.
  • the output matching circuit 270 is connected through the power tube 220.
  • the first suppression circuit 230 can output the connection of the matching circuit 270.
  • the power tube 220 can also be connected to the first suppression circuit 230 through the output matching circuit 270, and the output matching circuit 270 passes the first suppression.
  • Circuit 230 is coupled to the output 240.
  • the power amplifier 200 further includes: an input bias circuit 280 for supplying power to the power tube through the input matching circuit 260; and an output bias circuit 290 for The power tube is powered by the output matching circuit 270.
  • connection relationship between the components of the amplifiers in the foregoing figures in the embodiments of the present application is a schematic example, and does not impose any limitation on the embodiments of the present application.
  • FIG. 10 shows another power amplifier 300 provided by an embodiment of the present application, including:
  • the input terminal 310 is configured to input at least two signals of different frequencies and a second non-linear incremental signal generated by the upper power amplifier;
  • a second suppression circuit 320 configured to inhibit the input end 310 from inputting the second nonlinear incremental signal
  • the power tube 330 is configured to perform power amplification on the at least two signals of the different frequencies input by the input terminal 310 to obtain at least two signals after being amplified;
  • the output end 340 is configured to output the amplified at least two signals
  • the input end 310 is connected to the power tube 320, and the input end 310 is connected to the output end 340 through the power tube 320.
  • the connection mode in FIG. 9 or the input terminal 310 is connected to the power tube 330 through the second suppression circuit 320.
  • the second suppression circuit 320 functions as the upper power amplifier input from the input terminal 310.
  • the two non-linear incremental signals are suppressed.
  • the power tube 330 can be used.
  • the specific connection relationship is not limited in this application.
  • the second suppression circuit 320 can suppress the nonlinear incremental signal generated by the upper-stage power amplifier during the amplification of the dual-frequency or multi-frequency signal, so that the power amplifier 300 can be avoided.
  • the nonlinear incremental signal generated by the upper power amplifier is amplified, so that the envelope impedance of the input terminal is low, thereby reducing the power consumption of the power amplifier 300, thereby improving the power amplifier efficiency of the power amplifier 300.
  • the second suppression circuit 320 includes a second inductor 321 and a second capacitor 322, and the second inductor 321 and the second capacitor 322 are used to The impedance at the frequency of the two nonlinear incremental signals is short-circuited.
  • the resonant frequencies of the second inductance 321 and the second capacitance 322 are determined by the frequency of the input signal of the upper power amplifier.
  • the resonant frequencies of the second inductance 321 and the second capacitance 322 are determined by the difference in frequency of the input signal of the upper power amplifier.
  • the second inductance 321 and the second capacitance 322 included in the second suppression circuit 320 in the power amplifier 300 are similar to the second inductance 251 and the second capacitance 252 included in the second suppression circuit 250 in the power amplifier 200, in order to avoid For details, it will not be described in detail here.
  • the power amplifier 300 may also include an input matching circuit, an output matching circuit, an input bias circuit, an output bias circuit, and the like.
  • an input matching circuit for a specific connection relationship, refer to the connection relationship in the power amplifier 200.
  • an output matching circuit for a specific connection relationship, refer to the connection relationship in the power amplifier 200.
  • the present application is implemented. This example will not be described in detail.
  • FIG. 12 shows a power amplifier 400 in the Doherty power amplifier architecture of the embodiment of the present application, including:
  • the input terminal 401 is configured to input a nonlinear incremental signal output by the upper power amplifier and a dual or multiple frequency concurrent signal that needs to be amplified, or input at least two signals of different frequencies.
  • the power divider 402 is configured to copy the signal input by the input terminal 401 to obtain a first branch signal and a second branch signal, where the first branch signal is a nonlinear incremental signal input to the input terminal 401 and a double that needs to be amplified
  • the frequency or multi-frequency concurrent signal, the second branch signal is a non-linear incremental signal input to the input terminal 401 and a dual-frequency or multi-frequency concurrent signal that needs to be amplified.
  • the input matching circuit 403 is configured to match the impedance of the first branch signal output by the power divider 402 to the impedance of the power tube 406.
  • An input bias circuit 404 is provided for powering the power tube 406.
  • the second suppression circuit 405 inputs the nonlinear incremental signal output by the upper power amplifier and the signal to be amplified when the input terminal 401 is input, and the second suppression circuit 405 is configured to suppress the nonlinearity assigned by the power divider 420 to the first branch.
  • Incremental signal which is a nonlinear incremental signal generated by the upper power amplifier.
  • the power tube 406 is configured to amplify signals of different frequencies of the first branch.
  • the power tube 406 is further configured to amplify a non-linear incremental signal that is not suppressed by the second suppression circuit 405.
  • the output matching circuit 407 is configured to match the impedance of the power tube 406 output to the impedance of the synthesizer 417.
  • Output bias circuit 408 is used to power power tube 406.
  • the first suppression circuit 409 is configured to suppress the nonlinear incremental signal generated by the power tube 406 and the nonlinear incremental signal after the nonlinear incremental signal amplification that is not suppressed by the second suppression circuit 405.
  • the input matching circuit 410 is configured to match the first impedance of the second branch signal output by the power divider 402 to the second impedance of the power tube 413.
  • the input bias circuit 411 is configured to supply power to the power tube 413.
  • the second suppression circuit 412 when the input terminal 401 inputs the nonlinear incremental signal output by the upper power amplifier and the signal to be amplified, the second suppression circuit 412 is configured to suppress the nonlinearity assigned by the power divider 420 to the second branch.
  • Incremental signal which is a nonlinear incremental signal generated by the upper power amplifier.
  • the power tube 413 is configured to amplify signals of different frequencies of the first branch, and is also used to amplify a non-linear incremental signal that is not suppressed by the second suppression circuit 412.
  • An output matching circuit 414 is configured to match the impedance of the power tube 413 output to the impedance of the synthesizer 417.
  • the output bias circuit 415 is configured to supply power to the power tube 413.
  • the first suppression circuit 416 is configured to suppress the nonlinear incremental signal generated by the power transistor 415 and the nonlinear incremental signal after the nonlinear incremental signal amplification that is not suppressed by the second suppression circuit 412.
  • a synthesizer 417 for synthesizing the signals of the first branch and the second branch, optionally also for impedance transformation, for matching the impedance of the output matching circuit 407 and the output matching circuit 414 to the impedance of the output 418.
  • the output terminal 418 is configured to output the amplified signal synthesized by the synthesizer 417.
  • the input terminal 401 may be the aforementioned input terminal 210 or the input terminal 310; the input matching circuit 403 or the input matching circuit 410 may be the aforementioned input matching circuit 260; the input bias circuit 404 or the input bias circuit 411 may be the foregoing Input bias circuit 280; second suppression circuit 405 or second suppression circuit 412 may be the aforementioned second suppression circuit 250 or second suppression circuit 320; power tube 406 or power tube 413 may be the aforementioned power tube 220 or power The tube 330; the output matching circuit 407 or the output matching circuit 414 may be the aforementioned output matching circuit 270; the output bias voltage 408 or the output bias voltage 415 may be the aforementioned output bias voltage 290; the first suppression circuit 409 or the first The suppression circuit 416 can be the aforementioned first suppression circuit 230; the output 418 can be the aforementioned output 240 or output 340.
  • the input terminal 401 is connected to the input matching circuit 403 and the input matching circuit 410 through the power divider 402.
  • Power splitter 402 is coupled to power tube 406 via input matching circuit 403.
  • Input bias voltage 404 is coupled to power transistor 406 via input matching circuit 403.
  • the second suppression circuit 405 is connected to the input matching circuit 403.
  • Power tube 406 is coupled to synthesizer 417 via output matching circuit 407, which passes output matching circuit 408 and power tube 406.
  • the first suppression circuit 409 is connected to the output matching circuit 407.
  • the power divider 402 is coupled to the power transistor 413 via an input matching circuit 410.
  • the input bias voltage 411 is connected to the power transistor 413 through the input matching circuit 410.
  • the second suppression circuit 412 is connected to the input matching circuit 410.
  • the power transistor 413 is coupled to the combiner 417 via an output matching circuit 414 that passes through the output matching circuit 414 and the power transistor 413.
  • the first suppression circuit 416 is coupled to the output
  • the suppression of the nonlinear incremental signal in the embodiment of the present application may be a series resonance at a frequency of the nonlinear incremental signal, and a short circuit to the ground; or the suppression of the nonlinear incremental signal may be performed on the impedance of the nonlinear incremental signal.
  • Short-circuit processing but the embodiment of the present application is not limited thereto, and may be other manners of suppression processing.
  • power amplifier 200, power amplifier 300 or power amplifier 400 may be a discrete device, or may be used as a circuit unit, or may be combined into a high efficiency power amplifier module, such as a Doherty power amplifier or a different phase amplifier.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

一种功率放大器，所述功率放大器包括：输入端（210），用于输入不同频率的至少两个信号；功率管（220），用于将所述输入端（210）输入的所述至少两个信号进行功率放大，并产生所述至少两个信号的第一非线性增量信号；第一抑制电路（230），用于抑制所述第一非线性增量信号；输出端（240），用于输出所述功率管（220）放大后的至少两个信号；其中，所述输入端（210）通过所述功率管（220）与所述输出端（240）连接，所述功率管（220）与所述第一抑制电路（230）连接，可以提高功放效率。

Description

功率放大器
本申请要求于2017年7月21日提交中国专利局、申请号为201710602258.2、申请名称为“功率放大器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信领域，并且更具体地，涉及通信领域中的功率放大器。
背景技术
随着网络系统的发展，通信容量的需求日益增加，电信运营商通过部署多频段无线系统来提升系统容量，无线系统的多频段特性，会使得无线通信设备需要具备多带或宽带射频能力。射频功放模块为无线通信中发射机最耗能的模块，因此，提升功放效率是节能的关键所在，现有的功放器能在单频窄带信号工作模式下功放效率较高，但是在双频或多频并发工作模式下，功放的效率较差，从而导致系统性能较差。
发明内容
本申请提供一种功率放大器，能够提高功放的效率，有助于提高系统性能。
第一方面，提供了一种功率放大器，所述功率放大器包括：输入端，用于输入不同频率的至少两个信号；功率管，用于将所述输入端输入的所述至少两个信号进行功率放大，并产生所述至少两个信号的第一非线性增量信号；第一抑制电路，用于抑制所述第一非线性增量信号；输出端，用于输出所述功率管放大后的至少两个信号；其中，所述输入端通过所述功率管与所述输出端连接，所述功率管与所述第一抑制电路连接。
在本申请实施例中，当第一抑制电路抑制了所述第一非线性增量信号时，可以降低第一非线性增量信号对应的包络阻抗，这样，可以提高功率放大器的功放效率。
可选地，所述功率管可以通过所述第一抑制电路与所述输出端连接，这样使得输出端的包络阻抗很低，能够抑制包络的第一非线性增量的产生，从而提升了双频或多频并发场景下的功放效率。
可选地，当第一抑制电路抑制了所述第一非线性增量信号时，功率管的输出阻抗中就可以没有所述第一非线性增量信号的输出阻抗，从而可以提高功率放大器的功耗。
可选地，不同频率的至少两个信号可以是双频或多频并发的至少两个信号。
可选地，输出端可以将放大后的至少两个信号输出到双工器或天馈等。
可选地，输出端也可以将放大后的至少两个信号输出到下级功率放大器。在本申请实施例中，在双频或多频工作模式下，第一抑制电路可以将功率管在放大双频或多频信号过程中产生的非线性增量信号进行抑制，这样，可以避免输出端将该放大双频或多频信号中产生的非线性增量信号输出到下级功率放大器中，可以避免下级功率放大器放大该非线性增量信号，减少放大器的功耗，从而可以提高下级功率放大器的功放效率。
在某些实现方式中，所述第一抑制电路包括第一电容和第一电感，所述第一电感和所述第一电容用于对所述第一非线性增量信号频率处的阻抗进行短路处理。
可选地，第一非线性增量信号频率处呈现串联谐振，近似对地短路。
可选地，第一抑制电路也可以是集总参数的电容和电感元件，也可以是其他功能与电容和电感类似的等效元件(例如，微带、变容管等)。
可选地，第一电感和第一电容串联连接。
在某些实现方式中，所述第一电感和所述第一电容的谐振频率由所述至少两个信号的频率确定。
在某些实现方式中，所述第一电感和所述第一电容的谐振频率由所述至少两个信号的频率的差值确定。
可选地，输入端输入的至少两个信号的频率固定，则第一电容的电容值和第一电感的电感值固定，第一电容的电容值和第一电感的电感值根据至少两个信号的频率确定，从而第一电容和第一电感组成的第一抑制电路的谐振频率固定；输入端输入的至少两个信号的的频率不固定，例如，在第一次输入的至少两个信号的频率与第二次输入的至少两个信号的频率至少有一个频率不同，则第一电感的电感值和第一电容的电容值可调，随着输入信号的频率不同而不同，从而使得第一抑制电路的谐振频率可调。
可选地，若第一非线性增量信号为一个分量，则第第一抑制电路可以包括一组第一电容和第一电感；若第第一非线性增量信号为M个分量，则第二抑制电路包括M组第一电容和第一电感；可选地，M组第一电容和第一电感中每组的第一电容的电容值可以不同，P组第一电感中每组的第一电感的电感值可以不同，M为大于或等于1的整数。
可选地，若输入的信号为两个不同的频率的信号，则第一抑制电路包括一组第一电感和第一电容；若输入的信号为三个不同的频率的信号，则第一抑制电路包括三组第一电容和第一电感，若输入信号为N个不同频率的信号，则第一抑制电路包括
Figure PCTCN2018096421-appb-000001
组第一电容和第一电感，N为大于或等于2的整数。
可选地，若输入信号为载波频率为F1和F2的双频并发场景下输入的信号，功放产生的频谱主要包含如下频谱分量：基频分量F1和F2,包络分量F2-F1,三阶互调分量2*F2-F1和2*F1-F2，二次谐波分量2*F1、2*F2、F1+F2，三次谐波分量3*F1、3*F2、2*F1+F2、2*F2+F1等，可选地，本申请实施例的第一抑制电路可以抑制包络分量；可选地，本申请实施例的第一抑制电路可以抑制包络分量、三阶互调分量、二次谐波分量中的至少一种。当第一抑制电路抑制两个以上的分量时，第一抑制电路可以包括两组以上的第一电容和第一电感。
可选地，第一抑制电路包括的第一电感和第一电容的组数可以根据需要确定，例如第一抑制电路需要抑制几个分量就可以包括几组第一电容和第一电感，第一电容和第一电感的组数并不局限于输入信号的频率。
在某些实现方式中，所述输入端还用于：向所述功率管输入上级功率放大器产生的第二非线性增量信号；所述功率放大器还包括：第二抑制电路，用于抑制所述第二非线性增量信号；其中，所述输入端与所述第二抑制电路连接。
可选地，所述输入端通过所述第二抑制电路与所述功率管连接，可以使得输入端输入的包括阻抗很低，能够抑制包络的第二非线性增量的产生，从而提升了双频或多频并发场 景下的功放效率。
在某些实现方式中，所述第二抑制电路包括第二电容和第二电感，所述第二电容和所述第二电感用于对所述第二非线性增量信号的频率处的阻抗进行短路处理。
可选地，第二非线性增量信号频率处呈现串联谐振，近似对地短路。
可选地，第二抑制电路也可以是集总参数的电容和电感元件，也可以是其他功能与电容和电感类似的等效元件(例如，比如微带、变容管等等)。
可选地，所述第二电容和所述第二电感串联连接。
可选地，若第二非线性增量信号为一个分量，则第二抑制电路可以包括一组第二电容和第二电感；若第二非线性增量信号为P个分量，则第二抑制电路包括P组第二电容和第二电感；可选地，P组第二电容和第二电感中每组的第二电容的电容值可以不同，P组第二电感中每组的第二电感的电感值可以不同，P为大于或等于1的整数。
在某些实现方式中，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率确定。
在某些实现方式中，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率的差值确定。
可选地，上级功率放大器的输入信号也可以是不同频率的至少两个信号。
在某些实现方式中，所述功率放大器还包括：输入匹配电路，用于将所述输入端的第一阻抗匹配为所述功率管输入的第二阻抗；输出匹配电路，用于将所述功率管输出的第三阻抗匹配为所述输出端的第四阻抗；其中，所述输入端通过所述输入匹配电路与所述功率管连接，所述功率管通过所述输出匹配电路与所述输出端连接。
在某些实现方式中，所述功率放大器还包括：输入偏置电路，用于通过所述输入匹配电路向所述功率管供电；输出偏置电路，用于通过所述输出匹配电路向所述功率管供电。
可选地，所述输入偏置电路可以与所述功率管直接连接，所述输出偏置电路可以与所述功率管直接连接。
第二方面，提供了一种功率放大器，包括：输入端，用于输入不同频率的至少两个信号和上级功率放大器产生的第二非线性增量信号；第二抑制电路，用于抑制所述输入端输入所述第二非线性增量信号；功率管，用于将所述输入端输入的所述不同频率的至少两个信号进行功率放大得到放大后的至少两个信号；输出端，用于输出所述放大后的至少两个信号；其中，所述输入端抑制电路与所述功率管连接，所述抑制电路输入端通过所述功率管与所述输出端连接。
可选地，所述输入端通过所述第二抑制电路与所述功率管连接，可以使得输入端输入的包括阻抗很低，能够抑制包络的第二非线性增量的产生，从而提升了双频或多频并发场景下的功放效率。
在某些实现方式中，所述第二抑制电路包括第二电容和第二电感，所述第二电感和所述第二电容用于对所述第二非线性增量信号的频率处的阻抗进行短路处理。
在某些实现方式中，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率确定。
在某些实现方式中，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率的差值确定。
可选地，第二方面中的第二电容和第二电感可以参照第一方面中的第二电容和第二电感。
第三方面，所述第一方面或所述第一方面中任一种实现方式中的功率放大器都可以是Doherty功率放大器或者异相放大器。可选地，所述第二方面或所述第二方面中任一种实现方式中的功率放大器都可以是Doherty功率放大器或者异相放大器。
附图说明
图1是本申请实施例的应用场景示意图。
图2示出了本申请实施例提供的功率放大器。
图3示出了本申请实施例提供的另一功率放大器。
图4示出了现有技术的功率放大器的效果示意图。
图5示出了本申请实施例提供的功率放大器的效率示意图。
图6示出了本申请实施例提供的又一功率放大器。
图7示出了本申请实施例提供的又一功率放大器。
图8示出了本申请实施例提供的又一功率放大器。
图9示出了本申请实施例提供的又一功率放大器。
图10示出了本申请实施例提供的又一功率放大器。
图11示出了本申请实施例提供的又一功率放大器。
图12示出了本申请实施例提供的又一功率放大器。
具体实施方式
本申请提供的功率放大器可以应用于各种通信系统中的发送端的射频模块，例如：全球移动通讯(global system of mobile communication，GSM)系统、码分多址(code division multiple access，CDMA)系统、宽带码分多址(wideband code division multiple access，WCDMA)系统、通用分组无线业务(general packet radio service，GPRS)、长期演进(long term evolution，LTE)系统、LTE频分双工(frequency division duplex，FDD)系统、LTE时分双工(time division duplex，TDD)、通用移动通信系统(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信系统、无线局域网(wireless local area network，WLAN)或未来第五代无线通信系统(the fifth Generation，5G)等。
现有的功率放大器在单频窄带信号工作模式下，功率放大器放大的信号为窄带信号，例如1840MHz处的调制信号，或者2140MHz处的调制信号，功放的效率较高。现有的功率放大器在双频或多频并发工作模式下，功率放大器放大的信号为宽带信号，例如为1840MHz+2140MHz处的调制信号。由于在双频或多频工作模式下，由于功率管的非线性特性，功放输出频谱分量非常丰富。例如，在载波频率分为F1和F2的双频并发场景下，功放产生的频谱主要包含如下频谱分量：基频分量F1和F2,包络分量F2-F1,三阶互调分量2*F2-F1和2*F1-F2，二次谐波分量2*F1、2*F2、F1+F2，三次谐波分量3*F1、3*F2、2*F1+F2、2*F2+F1等，其中基频分量是有用信号，功率放大器产生的其他分量是非线性增量信号，这些非线性增量是无用的信号，这些分量会干扰其他的设备的信号，放大器在 放大的过程中也会放大非线性增量信号，这样，放大后的非线性增量信号对其他设备的干扰会更大，并且，非线性增量会显著恶化功功率放大器的效率，会导致在双频或多频工作模式下放大器的效率降低。实验证明，其中包络分量对宽带放大器的效率影响尤为重要。例如表1所示的一个功率放大器在单频和双频工作模式下效率对比。功放效率表示输出功率与功耗的比值，应理解，在本申请实施例中，功放效率也可以为输出功率和输入功率之差与功耗的比值，表1中的功放效率为前一种定义。
表1
Figure PCTCN2018096421-appb-000002
针对上述问题，本申请实施例提供的功率放大器，可以在放大的过程中将非线性增量信号进行抑制，可以避免功率放大器在放大的过程中也放大非线性增量信号的功率，从而可以提高功率放大器的功放效率。
应理解，本申请实施例中的功率放大器可以应用在Doherty功放架构、异相(Outphasing)放大器、包络跟踪放大器等功放架构中，或者是应用到其他的高效功放架构中，本申请实施例对此不作限定。
应理解，本申请实施例中的A与B连接，表示A与B可以串联连接或并联连接，或者A与B通过其他的器件，本申请实施例对此不作限定。
应理解，本申请实施例中的第一非线性增量、第二非线性增量或非线性增量可以是包络分量，可以是放大器在放大信号的过程中产生的全部或部分包络分量，本申请实施例对此不作限定。
本申请实施例可以应用到多级放大器的场景中，当然也不限于是多级放大器，也可以是一级放大器，例如，如图1所示，放大电路中包括n级放大器，n为大于或等于1的整数，图1中的放大器都可以工作在双频或多频工作模式下。例如，本申请实施例中的放大器可以是第一级放大器，该放大器中的第一抑制电路与该放大器的输出端连接，该第一抑制电路用于抑制该放大器中产生的非线性增量信号，所述输出端与第一抑制电路连接时，可以使得输入端输入的包络阻抗很低，能够抑制包络的第一非线性增量的产生，从而提升了双频或多频并发场景下的功放效率；或者当该第一级放大器输出的信号输入到第二级放大器中时，第二级放大器就可以避免放大第一级放大器产生的非线性增量信号，从而可以降低第二级放大器的功耗。又例如，本申请实施例中的放大器可以是第二级放大器，该放大器中的第二抑制电路与该放大器的输入端连接，该第二抑制电路用于抑制第一级放大器产生的非线性增量信号，这样，在该放大器放大信号之前，可以抑制第二非线性增量的产生，可以使得输入端输入的包络阻抗很低，从而可以提升双频或多频并发场景下的功放效率；或者该第二级放大器包括第一抑制电路和第二抑制电路，第一抑制电路与输出端连接，使得输出端包络阻抗很低，能够抑制包络的第一非线性增量的产生，可以提高第二级放大器的功放效率和/或提高第三级放大器的功放效率，第二抑制电路与输入端连接，可以抑制第一级放大器产生的包络非线性增量信号，可以使得输入端的输入的包络阻抗很低，可 以提高第二级放大器的功放效率。再例如，本申请实施例中的放大器可以是第n级放大器，该放大器中的第二抑制电路与该放大器的输入端连接，该第二抑制电路用于抑制第n-1级放大器产生的非线性增量信号，这样，在放大器放大信号之前，就可以将第n-1级放大器产生的非线性增量信号进行抑制，使得输入端的包络阻抗很低，从而可以避免该放大器放大第n-1级放大器产生的非线性增量信号，从而可以提高该放大器的功放效率。又例如，本申请实施例中的放大器可以是第n级放大器，该放大器中的第一抑制电路与该放大器的输出端连接，该放大器的第一抑制电路用于抑制该放大器产生的非线性增量信号，该第n级放大器中功率管的输出端输出的包络阻抗很低，从而可以提高第n级放大器的功放效率；又例如，本申请实施例中的放大器可以是第n级放大器，该放大器中的第一抑制电路与该放大器的输出端连接，该放大器中的第二抑制电路与该放大器的输入端连接，第一抑制电路用于抑制第n-1级放大器产生的非线性增量信号，可以避免第n级放大器放大第n-1级放大器产生的非线性增量信号，也可以使得第n级放大器的输入端包络阻抗很低，第二抑制电路用于抑制第n级放大器产生的非线性增量信号，可以使得该第n级放大器的输出端的包络阻抗很低，能够显著抑制包络分量的产生，从而提升了在双频或多频频发场景下的功放效率。
应理解，在图1中第n-1级放大器可以称为第n级放大器的上级功率放大器，第n级放大器可以称为第n-1级放大器的下级功率放大器，例如，第一级放大器可以称为第二级放大器的上级功率放大器，第二级放大器可以称为第一级放大器的下级功率放大器。
下面结合附图描述本申请实施例提供的功率放大器。
图2示出了本申请实施例提供的功率放大器200，例如，该功率放大器200可以是图1中的n个功率放大器中的任意一个功率放大器，例如，可以是图1中的第n级放大器，该功率放大器200包括：输入端210、功率管220，第一抑制电路230和输出端240。
输入端210，用于输入不同频率的至少两个信号，该至少两个信号可以是相同的信号也可以是不同的信号，本申请实施例对此不作限定；
功率管220，用于将所述输入端210输入的所述至少两个信号进行功率放大，并产生所述至少两个信号的第一非线性增量信号，例如，功率管220可以将所述输入端210输入的不同频率的至少两个信号进行放大得到放大后的至少两个信号，功率管220在放大所述不同频率的至少两个信号时会产生该至少两个信号的第一非线性增量信号；
第一抑制电路230，用于抑制所述第一非线性增量信号。
输出端240，用于输出所述功率管220放大后的至少两个信号。
其中，所述输入端210通过所述功率管220与所述输出端240单元连接，所述功率管220与所述第一抑制电路230连接，例如图1中的连接方式，或者所述功率管220通过所述第一抑制电路230与所述输出端240连接，第一抑制电路230的作用是将功率管230输出的第一非线性增量信号进行抑制，只要连接在功率管230之后，输出端240之前即可，本申请对具体的连接关系并不作限定。
因此，在双频或多频工作模式下，第一抑制电路230可以将功率管220在放大双频或多频信号过程中产生的非线性增量信号进行抑制，当第一抑制电路230抑制了所述第一非线性增量信号时，输出端的包络阻抗就很低，能够显著抑制包络的第一非线性增量信号这样可以提高功率放大器在双频或多频并发场景下的功放效率。
可选地，输出端240与双工器或天馈等连接。
可选地，当所述输出端240与下级功率放大器连接时，第一抑制电路230可以将功率管220在放大双频或多频信号过程中产生的非线性增量信号进行抑制，可以避免输出端将该放大双频或多频信号中产生的非线性增量信号输出，可以避免下一级网络放大该非线性增量信号，减少放大器的功耗，从而可以提高下一级网络的功放效率。
作为一个可选实施例，如图3所示，所述第一抑制电路230包括第一电感231和第一电容232，其中，所述第一电感231和所述第一电容232用于对所述第一非线性增量信号频率处的阻抗进行短路处理。例如，第一电感231和第一电容232可以串联连接。
可选地，第一抑制电路也可以是集总参数的电容和电感元件，也可以是其他功能与电容和电感类似的等效元件(例如，比如微带、变容管等等)。
作为一个可选实施例，所述第一电感231和所述第一电容232的谐振频率由所述至少两个信号的频率确定，具体来说，所述第一电感231和所述第一电容232的谐振频率由所述至少两个信号的频率的差值确定。当输入端210输入的信号的频率是固定的，则第一电感231和第一电容232的谐振频率固定，例如，当输入端210输入的两个信号的频率分别是1840MHz和2140MHz时，第一电感231和第一电容232的谐振频率为300MHz(2140MHz-1840MHz)，可以减少双频并发是功放输出的300MHz的非线性信号增量，如图4和图5所示，图4和图5中横坐标表示输出功率，纵坐标表示功放效率，其中，图4表示增加第一抑制电路230之前下级放大器的功放效率，图5表示增加第一抑制电路230之后下级放大器的功放效率，可以看出，在增加第一抑制电路230之后功放效率提高了五个百分点。又例如，当输入端210输入的三个不同频率的三个信号时，假设三个信号的频率从大到小分别是A、B和C，则根据需要可以增加三组电容和电感组合电路，每组电容和电感都可以是第一电容232和第一电感231，三组电容和电感的谐振频率分别为A-B、A-C、B-C。当输入端输入的信号的频率不固定时，第一电感231和第一电容232可以随着输入端输入的信号的频率的变化而变化，即，第一电感231的电感值和第一电容232的电容值的自适应可调，从而达到谐振频率随输入信号频率自适应可调。
作为一个可选实施例，所述输入端210还用于：向所述功率管220输入上级功率放大器产生的第二非线性增量信号；所述功率放大器200还包括：第二抑制电路250，用于抑制所述第二非线性增量信号；其中，所述输入端210与所述第二抑制电路250连接。例如图6中的连接方式，或者所述输入端210通过所述第二抑制电路230与所述功率管220连接，第二抑制电路230的作用是将输入端210输入的上级功率放大器的第二非线性增量信号进行抑制，只要连接在输出端2100之后，功率管220之前即可，本申请对具体的连接关系并不作限定。该功率放大器可以是，图1中的除了第一级功率放大器之外的功率放大器。
作为一个可选实施例，如图7所示，所述第二抑制电路250包括第二电感251和第二电容252，所述第二电感251和所述第二电容252用于对所述第二非线性增量信号的频率处的阻抗进行短路处理。例如，第二电感251和第二电容252的连接关系可以与图4中的第一电感231和第一电容232的连接关系类似。
作为一个可选实施例，所述第二电感251和所述第二电容252的谐振频率由所述上级功率放大器的输入信号的频率确定。可选地，所述第二电感251和所述第二电容252的谐 振频率由所述上级功率放大器的输入信号的频率的差值确定。具体来说，上级功率放大器输入的信号是双频或多频并发信号，则放大器200的所述第二电感251和所述第二电容252的谐振频率由上级功率放大器的双频或多频并发信号的频率确定，若上级功率放大器输入的信号是的频率是固定的，则第二电感251和第二电容的谐振频率固定，例如，当上级功率放大器输入的两个信号的频率分别是1840MHz和2140MHz时，第二电感251和第二电容252的谐振频率为300MHz(2140MHz-1840MHz)。当上级功率放大器输入的双频或多频并发信号的频率不固定时，第二电感251和第二电容252的谐振频率可以随着上级功率放大器的并发信号的频率的变化而变化，即，第二电感251和第二电容252的谐振频率自适应可调。
作为一个可选实施例，如图8所示，所述功率放大器200还包括：输入匹配电路260，用于将所述输入端210的第一阻抗匹配为所述功率管220输入的第二阻抗；输出匹配电路270，用于将所述功率管220输出的第三阻抗匹配为所述输出端240的第四阻抗；其中，所述输入端210通过所述输入匹配电路260与所述功率管连接，所述功率管220通过所述输出匹配电路270与所述输出端240连接，例如，在输入匹配电路260上可以串联第二抑制电250包括的第二电感251和第二电容252，在输出匹配电路270上可以串联第一抑制电路230包括的第一电感231和第一电容232。可选地，如图8所示第二抑制电路250可以与输入匹配电路260连接，当然，输入端210也可以通过第二抑制电路250与所述输入匹配电路260连接，所述输入匹配电路260通过功率管220与所述输出匹配电路270连接。可选地，第一抑制电路230可以输出匹配电路270连接，当然，功率管220也可以通过输出匹配电路270与所述第一抑制电路230连接，所述输出匹配电路270通过所述第一抑制电路230与所述输出端240连接。
作为一个可选实施例，如图9所示，所述功率放大器200还包括：输入偏置电路280，用于通过所述输入匹配电路260向所述功率管供电；输出偏置电路290，用于通过所述输出匹配电路270向所述功率管供电。
应理解，本申请实施例中前述的图的放大器各个部件之间的连接关系为示意性举例，并不对本申请实施例造成任何限制。
图10示出了本申请实施例提供的另一功率放大器300，包括：
输入端310，用于输入不同频率的至少两个信号和上级功率放大器产生的第二非线性增量信号；
第二抑制电路320，用于抑制所述输入端310输入所述第二非线性增量信号；
功率管330，用于将所述输入端310输入的所述不同频率的至少两个信号进行功率放大得到放大后的至少两个信号；
输出端340，用于输出所述放大后的至少两个信号；
其中，所述输入端310与所述功率管320连接，所述输入端310通过所述功率管320与所述输出端340连接。例如图9中的连接方式，或者所述输入端310通过所述第二抑制电路320与所述功率管330连接，第二抑制电路320的作用是将输入端310输入的上级功率放大器产生的第二非线性增量信号进行抑制，只要连接在输入端310之后，功率管330之前即可，本申请对具体的连接关系并不作限定。
因此，在双频或多频工作模式下，第二抑制电路320可以将上级功率放大器在放大双 频或多频信号过程中产生的非线性增量信号进行抑制，这样，可以避免功率放大器300将上级功率放大器产生的非线性增量信号进行放大，从而可以使得输入端输入的包络阻抗很低，从而减少功率放大器300的功耗，从而可以提高功率放大器300的功放效率。
作为一个可选实施例，如图11所示，所述第二抑制电路320包括第二电感321和第二电容322，所述第二电感321和所述第二电容322用于对所述第二非线性增量信号的频率处的阻抗进行短路处理。
作为一个可选实施例，所述第二电感321和所述第二电容322的谐振频率由所述上级功率放大器的输入信号的频率确定。
作为一个可选实施例，所述第二电感321和所述第二电容322的谐振频率由所述上级功率放大器的输入信号的频率的差值确定。
应理解，功率放大器300中的第二抑制电路320包括的第二电感321和第二电容322与功率放大器200中的第二抑制电路250包括的第二电感251和第二电容252类似，为避免赘述，在此不详细说明。
可选地，功率放大器300也可以包括输入匹配电路，输出匹配电路，输入偏置电路和输出偏置电路等，具体的连接关系，参见功率放大器200中的连接关系，为避免赘述，本申请实施例对此不作详细描述。
作为一个例子，图12示出了本申请实施例在Doherty功放架构下的功率放大器400，包括：
输入端401，用于输入上级功率放大器输出的非线性增量信号和需要放大的双频或多频并发信号，或者输入不同频率的至少两个信号。
功分器402，用于将所述输入端401输入的信号进行复制，得到第一分支信号和第二分支信号，第一分支信号为输入端401输入的非线性增量信号和需要放大的双频或多频并发信号，第二分支信号为输入端401输入的非线性增量信号和需要放大的双频或多频并发信号。
输入匹配电路403，用于将功分器402输出的第一分支信号的阻抗匹配为功率管406的阻抗。
输入偏置电路404，用于给功率管406进行供电。
第二抑制电路405，当输入端401输入的是上级功率放大器输出的非线性增量信号和需要放大的信号，该第二抑制电路405用于抑制功分器420分配给第一分支的非线性增量信号，该非线性增量信号属于上级功率放大器产生的非线性增量信号。
功率管406，用于将第一分支的不同频率的信号进行放大，可选地，功率管406还用于放大第二抑制电路405未抑制的非线性增量信号。
输出匹配电路407，用于将所述功率管406输出的阻抗匹配为所述合成器417的阻抗。
输出偏置电路408，用于给功率管406供电。
第一抑制电路409，用于抑制功率管406产生的非线性增量信号以及第二抑制电路405未抑制的非线性增量信号放大之后的非线性增量信号。
输入匹配电路410，用于将功分器402输出的第二分支信号的第一阻抗匹配为功率管413的第二阻抗。
输入偏置电路411，用于给功率管413进行供电。
第二抑制电路412，当输入端401输入的是上级功率放大器输出的非线性增量信号和需要放大的信号，该第二抑制电路412用于抑制功分器420分配给第二分支的非线性增量信号，该非线性增量信号属于上级功率放大器产生的非线性增量信号。
功率管413，用于将第一分支的不同频率的信号进行放大，可选地，还用于放大第二抑制电路412未抑制的非线性增量信号。
输出匹配电路414，用于将所述功率管413输出的阻抗匹配为所述合成器417的阻抗。
输出偏置电路415，用于给功率管413进行供电。
第一抑制电路416，用于抑制功率管415产生的非线性增量信号以及第二抑制电路412未抑制的非线性增量信号放大之后的非线性增量信号。
合成器417，用于合成第一分支和第二分支的信号，可选地，还可以用于阻抗变换，用于将输出匹配电路407和输出匹配电路414的阻抗匹配为输出端418的阻抗。
输出端418，用于输出合成器417合成的放大之后的信号。
其中，输入端401可以是前述的输入端210，或者输入端310；输入匹配电路403或输入匹配电路410可以是前述的输入匹配电路260；输入偏置电路404或输入偏置电路411可以是前述的输入偏置电路280；第二抑制电路405或第二抑制电路412可以是前述的第二抑制电路250或第二抑制电路320；功率管406或功率管413可以是前述的功率管220或功率管330；输出匹配电路407或输出匹配电路414可以是前述的输出匹配电路270；输出偏置电压408或输出偏置电压415可以是前述的输出偏置电压290；第一抑制电路409或第一抑制电路416可以是前述的第一抑制电路230；输出端418可以是前述的输出端240或输出端340。输入端401通过功分器402与输入匹配电路403和输入匹配电路410连接。功分器402通过输入匹配电路403与功率管406连接。输入偏置电压404通过输入匹配电路403与功率管406连接。第二抑制电路405与输入匹配电路403连接。功率管406通过输出匹配电路407与合成器417连接，所述输出偏置电路408通过输出匹配电路408与功率管406。第一抑制电路409与输出匹配电路407连接。功分器402通过输入匹配电路410与功率管413连接。输入偏置电压411通过输入匹配电路410与功率管413连接。第二抑制电路412与输入匹配电路410连接。功率管413通过输出匹配电路414与合成器417连接，所述输出偏置电路415通过输出匹配电路414与功率管413。第一抑制电路416与输出匹配电路414连接。
应理解，本申请实施例中抑制非线性增量信号可以是非线性增量信号的频率处呈现串联谐振，近似对地短路；或者抑制非线性增量信号可以是对非线性增量信号的阻抗进行短路处理，但本申请实施例不限于此，可以是其他方式的抑制处理。
应理解，前述的功率放大器200、功率放大器300或功率放大器400可以为分立器件，也可以作为一个电路单元，也可以组合成一个高效功放模块，例如Doherty功率放大器或者异相放大器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种功率放大器，其特征在于，所述功率放大器包括：
    输入端，用于输入不同频率的至少两个信号；
    功率管，用于将所述输入端输入的所述至少两个信号进行功率放大，并产生所述至少两个信号的第一非线性增量信号；
    第一抑制电路，用于抑制所述第一非线性增量信号；
    输出端，用于输出所述功率管放大后的至少两个信号；
    其中，所述输入端通过所述功率管与所述输出端连接，所述功率管与所述第一抑制电路连接。
  2. 根据权利要求1所述的功率放大器，其特征在于，所述第一抑制电路包括第一电容和第一电感，所述第一电感和所述第一电容用于对所述第一非线性增量信号频率处的阻抗进行短路处理。
  3. 根据权利要求2所述的功率放大器，其特征在于，所述第一电感和所述第一电容的谐振频率由所述至少两个信号的频率确定。
  4. 根据权利要求3所述的功率放大器，其特征在于，所述第一电感和所述第一电容的谐振频率由所述至少两个信号的频率的差值确定。
  5. 根据权利要求1至4中任一项所述的功率放大器，其特征在于，所述输入端还用于：
    向所述功率管输入上级功率放大器产生的第二非线性增量信号；
    所述功率放大器还包括：
    第二抑制电路，用于抑制所述第二非线性增量信号；
    其中，所述输入端与所述第二抑制电路连接。
  6. 根据权利要求5所述的功率放大器，其特征在于，所述第二抑制电路包括第二电容和第二电感，所述第二电容和所述第二电感用于对所述第二非线性增量信号的频率处的阻抗进行短路处理。
  7. 根据权利要求6所述的功率放大器，其特征在于，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率确定。
  8. 根据权利要求7所述的功率放大器，其特征在于，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率的差值确定。
  9. 根据权利要求1至8中任一项所述的功率放大器，其特征在于，所述功率放大器还包括：
    输入匹配电路，用于将所述输入端的第一阻抗匹配为所述功率管输入的第二阻抗；
    输出匹配电路，用于将所述功率管输出的第三阻抗匹配为所述输出端的第四阻抗；
    其中，所述输入端通过所述输入匹配电路与所述功率管连接，所述功率管通过所述输出匹配电路与所述输出端连接。
  10. 根据权利要求9所述的功率放大器，其特征在于，所述功率放大器还包括：
    输入偏置电路，用于通过所述输入匹配电路向所述功率管供电；
    输出偏置电路，用于通过所述输出匹配电路向所述功率管供电。
  11. 一种功率放大器，其特征在于，所述功率放大器包括：
    输入端，用于输入不同频率的至少两个信号和上级功率放大器产生的第二非线性增量信号；
    第二抑制电路，用于抑制所述输入端输入所述第二非线性增量信号；
    功率管，用于将所述输入端输入的所述不同频率的至少两个信号进行功率放大得到放大后的至少两个信号；
    输出端，用于输出所述放大后的至少两个信号；
    其中，所述输入端抑制电路与所述功率管连接，所述抑制电路输入端通过所述功率管与所述输出端连接。
  12. 根据权利要求11所述的功率放大器，其特征在于，所述第二抑制电路包括第二电容和第二电感，所述第二电感和所述第二电容用于对所述第二非线性增量信号的频率处的阻抗进行短路处理。
  13. 根据权利要求12所述的功率放大器，其特征在于，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率确定。
  14. 根据权利要求13所述的功率放大器，其特征在于，所述第二电感和所述第二电容的谐振频率由所述上级功率放大器的输入信号的频率的差值确定。
PCT/CN2018/096421 2017-07-21 2018-07-20 功率放大器 WO2019015667A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP18835340.3A EP3648345A4 (en) 2017-07-21 2018-07-20 POWER AMPLIFIER
BR112020001104-5A BR112020001104A2 (pt) 2017-07-21 2018-07-20 amplificador de energia

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710602258.2 2017-07-21
CN201710602258.2A CN109286380A (zh) 2017-07-21 2017-07-21 功率放大器

Publications (1)

Publication Number Publication Date
WO2019015667A1 true WO2019015667A1 (zh) 2019-01-24

Family

ID=65015796

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/096421 WO2019015667A1 (zh) 2017-07-21 2018-07-20 功率放大器

Country Status (4)

Country Link
EP (1) EP3648345A4 (zh)
CN (1) CN109286380A (zh)
BR (1) BR112020001104A2 (zh)
WO (1) WO2019015667A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118100824A (zh) * 2022-11-16 2024-05-28 中兴通讯股份有限公司 功率放大器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7345534B2 (en) * 2005-05-31 2008-03-18 M/A-Com Eurotec Bv Efficient power amplification system
CN102332886A (zh) * 2011-08-16 2012-01-25 雷良军 多频带功率放大器
CN103181086A (zh) * 2010-11-01 2013-06-26 克里公司 传输电路的匹配网络
CN104753476A (zh) * 2013-12-30 2015-07-01 国民技术股份有限公司 多模多频功率放大器
CN106026949A (zh) * 2015-03-31 2016-10-12 天工方案公司 多频带功率放大器
CN106656076A (zh) * 2016-12-31 2017-05-10 唯捷创芯(天津)电子技术股份有限公司 一种支持多模多频的射频功率放大器、芯片及通信终端

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5767743A (en) * 1995-10-13 1998-06-16 Matsushita Electric Industrial Co., Ltd. Radio frequency power amplifier having a tertiary harmonic wave feedback circuit
DE19823049C2 (de) * 1998-05-22 2000-09-21 Ericsson Telefon Ab L M Leistungsverstärker-Ausgangsschaltung zur Unterdrückung von Oberschwingungen für eine Mobilfunkeinheit mit Doppelbandbetrieb und Verfahren zum Betreiben derselben
US6933780B2 (en) * 2000-02-03 2005-08-23 Matsushita Electric Industrial Co., Ltd. Predistortion circuit and power amplifier
JP2002171138A (ja) * 2000-12-01 2002-06-14 Nec Corp マイクロ波電力増幅器
US9467940B2 (en) * 2011-11-11 2016-10-11 Skyworks Solutions, Inc. Flip-chip linear power amplifier with high power added efficiency
CN103490733B (zh) * 2013-09-26 2016-06-08 华东交通大学 一种频率比1.25至2.85的双频带Doherty功率放大器
US9231550B2 (en) * 2014-06-09 2016-01-05 Mitsubishi Electric Research Laboratories, Inc. Output matching network for wideband power amplifier with harmonic suppression
CN104518742B (zh) * 2014-12-10 2018-02-23 天津大学 一种高效率双频带f类功率放大器
CN105262446A (zh) * 2015-10-23 2016-01-20 锐迪科创微电子（北京）有限公司 一种多级射频功率放大电路
CN105811888A (zh) * 2016-04-20 2016-07-27 广东工业大学 一种射频功率放大器输出匹配电路结构及其设计方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7345534B2 (en) * 2005-05-31 2008-03-18 M/A-Com Eurotec Bv Efficient power amplification system
CN103181086A (zh) * 2010-11-01 2013-06-26 克里公司 传输电路的匹配网络
CN102332886A (zh) * 2011-08-16 2012-01-25 雷良军 多频带功率放大器
CN104753476A (zh) * 2013-12-30 2015-07-01 国民技术股份有限公司 多模多频功率放大器
CN106026949A (zh) * 2015-03-31 2016-10-12 天工方案公司 多频带功率放大器
CN106656076A (zh) * 2016-12-31 2017-05-10 唯捷创芯(天津)电子技术股份有限公司 一种支持多模多频的射频功率放大器、芯片及通信终端

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3648345A4

Also Published As

Publication number Publication date
EP3648345A4 (en) 2020-07-22
EP3648345A1 (en) 2020-05-06
BR112020001104A2 (pt) 2020-07-21
CN109286380A (zh) 2019-01-29

Similar Documents

Publication Publication Date Title
US10116272B2 (en) Variable impedance match and variable harmonic terminations for different modes and frequency bands
CN107547050B (zh) 一种双级双频带高效功率放大器
CN107112953B (zh) 用于放大射频信号的功率放大器
US8988147B2 (en) Multi-way Doherty amplifier
US8554162B2 (en) High efficiency power amplifier
EP1911155B1 (en) Two stage microwave class e power amplifier
KR100832160B1 (ko) 결합된 아웃페이징 전력 증폭기의 출력 임피던스를 매칭시키는 방법과 장치, 통신 디바이스, 무선 통신 디바이스 및 무선 통신 시스템
KR102602394B1 (ko) 멀티 밴드 증폭기 및 듀얼 밴드 증폭기
CN107483025B (zh) 一种基于新型谐波控制网络的f类功率放大器
JP2018085635A (ja) 電力増幅器
US10063190B2 (en) Broadband Doherty power amplifier
JP4867346B2 (ja) 高周波増幅器
JP2009213090A (ja) 電力増幅回路
Piazzon et al. A method for designing broadband Doherty power amplifiers
JP2006203635A (ja) 電力合成器、パワーアンプ、及び高周波通信装置
WO2019015667A1 (zh) 功率放大器
CN108736833A (zh) 一种提高高效双频带e类功率放大器载波频率的补偿电路
CN112020826B (zh) 放大器
CN114221623A (zh) 一种宽带高效率非对称Doherty功率放大器
JP2018074303A (ja) 送受信機および送受信機の制御方法
EP3089370B1 (en) Electronic device with rf transmission line stub and rf shorting switch configuration and related methods
Mariappan et al. Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems
JP2011182312A (ja) 増幅器
CN115088191A (zh) 功率放大电路、高频电路以及通信装置
CN112564647B (zh) 一种功率放大器及功率放大方法、存储介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18835340

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

REG Reference to national code

Ref country code: BR

Ref legal event code: B01A

Ref document number: 112020001104

Country of ref document: BR

ENP Entry into the national phase

Ref document number: 2018835340

Country of ref document: EP

Effective date: 20200131

ENP Entry into the national phase

Ref document number: 112020001104

Country of ref document: BR

Kind code of ref document: A2

Effective date: 20200117