WO2019014966A1 - 多晶硅薄膜的制备方法、薄膜晶体管阵列基板的制备方法 - Google Patents

多晶硅薄膜的制备方法、薄膜晶体管阵列基板的制备方法 Download PDF

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WO2019014966A1
WO2019014966A1 PCT/CN2017/095514 CN2017095514W WO2019014966A1 WO 2019014966 A1 WO2019014966 A1 WO 2019014966A1 CN 2017095514 W CN2017095514 W CN 2017095514W WO 2019014966 A1 WO2019014966 A1 WO 2019014966A1
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layer
preparing
thin film
amorphous silicon
transistor array
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French (fr)
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董磊磊
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Definitions

  • the present invention relates to a manufacturing process of a semiconductor device, and more particularly to a method for preparing a polysilicon film, and to a method for preparing a thin film transistor array substrate.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • Thin Film Transistors (TFTs) are an important part of flat panel display devices and can be formed on glass substrates or plastic substrates, and are commonly used as light-emitting devices and driving devices such as LCDs and OLEDs.
  • Poly-Si films are composed of many small grains with different sizes and different crystal plane orientations.
  • the grain size is generally between tens and hundreds of nanometers, and the large grain size can reach several micrometers.
  • the large-grain polycrystalline silicon film has a high mobility and is close to the mobility of the bulk material, so the polycrystalline silicon film has been widely used in the fabrication of semiconductor devices. For example, in thin film transistors in LCD or OLED products, a polysilicon film is mostly used as an active layer.
  • a method for preparing a polycrystalline silicon film is mainly to prepare an amorphous silicon film, and then crystallizing the amorphous silicon film to obtain a polycrystalline silicon film.
  • Excimer Laser Anneal is a commonly used method.
  • the ELA method mainly irradiates the amorphous silicon film with a certain energy excimer laser, and uses the energy of the laser beam to make the amorphous silicon Converted to polysilicon at high temperatures.
  • the present invention provides a method for preparing a polysilicon film, which improves the polycrystalline silicon film prepared by the ELA method, reduces the surface roughness of the prepared polysilicon film, and improves the quality of the product.
  • a method for preparing a polysilicon film comprising: preparing a first amorphous silicon film by using a semiconductor deposition process; and crystallizing the first amorphous silicon film to form a polysilicon film by using an excimer laser annealing process; applying a semiconductor deposition process Forming a second amorphous silicon film on the first surface of the polysilicon film; applying a dry etching process, etching from the second amorphous silicon film toward the polysilicon film, until the first portion is completely removed Two amorphous silicon films.
  • etching is performed below the first surface.
  • the etching speeds are uniform throughout the entire plane.
  • the dry etching process is a plasma etching process.
  • the first amorphous silicon film is further subjected to heating and dehydrogenation treatment before the excimer laser annealing process.
  • the temperature of the heating dehydrogenation treatment is 350 to 450 °C.
  • the present invention also provides a method for fabricating a thin film transistor array substrate, comprising the steps of: preparing an active layer, comprising: preparing a polysilicon film according to a method for preparing a polysilicon film as described above; applying the photolithography process The polysilicon film is etched to form a patterned active layer.
  • the method specifically includes the steps of: S1, providing a substrate substrate and preparing a patterned active layer on the substrate; S2, preparing a gate insulating layer on the active layer; S3, Forming a patterned gate electrode on the gate insulating layer; S4, forming an interlayer dielectric layer on the gate electrode; S5, etching in the interlayer dielectric layer and the gate insulating layer Forming a first via and a second via exposing the active layer; S6, preparing a patterned source electrode and a drain electrode on the interlayer dielectric layer, the source electrode passing the first pass a hole is connected to the active layer, the drain electrode is connected to the active layer through the second via hole; S7, a planarization layer is formed on the source electrode and the drain electrode; S8, in the Etching in the planarization layer to form a third via hole exposing the source electrode or the drain electrode; S9, forming a patterned pixel electrode on the planarization layer, the pixel electrode passing through the third A via is connected to the source electrode
  • the polysilicon film is first covered with an amorphous silicon film, and then etched by a dry etching process.
  • the amorphous silicon film is completely removed, and the variation bumps on the surface of the polysilicon film are uniformly etched and etched during the process of etching and removing the amorphous silicon film, thereby reducing the surface of the prepared polysilicon film.
  • a polycrystalline silicon film having a uniform roughness and a uniform surface can improve the stability of its electrical properties.
  • FIG. 1a to 1d are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a polycrystalline silicon film according to Embodiment 1 of the present invention
  • FIGS. 2a to 2j are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a thin film transistor array substrate according to a second embodiment of the present invention.
  • This embodiment provides a method for preparing a polysilicon film. Referring to FIG. 1a to FIG. 1d, the method includes the following steps:
  • a substrate 1 is provided, and a first amorphous silicon film 2a is formed on the substrate 1 by applying a semiconductor deposition process.
  • the base substrate 1 may be an optional glass substrate.
  • the semiconductor deposition process may be a chemical vapor deposition process.
  • the first amorphous silicon film 2a is crystallized to form a polysilicon film 2 by an excimer laser annealing (ELA) process.
  • ELA excimer laser annealing
  • a second amorphous silicon film 3 is formed on the first surface 2b of the polysilicon film 2 by applying a semiconductor deposition process.
  • the semiconductor deposition process may be a chemical vapor deposition process, and the second amorphous silicon film 3 completely covers the first surface 2b of the polysilicon film 2 and the variation bump 2c on the first surface 2b.
  • the dry etching process selectively uses a plasma etching process.
  • a plasma etching process it is desirable to control the etching speeds throughout the entire plane to be nearly equal, preferably to be completely equal.
  • step S14 when the dry etching process is performed, etching is performed under the first surface 2b to ensure that the variation bump 2c can be completely etched and removed, thereby obtaining a polysilicon film having a uniform surface. .
  • the first amorphous silicon film 2a is further subjected to a heating dehydrogenation treatment before the ELA process of step S12 is performed, thereby making the finally prepared polycrystalline silicon film 2 have better electrical properties.
  • the temperature of the heating dehydrogenation treatment may be selected to be 350 to 450 °C.
  • This embodiment provides a method for fabricating a thin film transistor array substrate. Referring to FIG. 2a to FIG. 2j, the method includes the following steps:
  • This step may specifically include:
  • a polycrystalline silicon film 2 is obtained by first preparing the polycrystalline silicon film provided in the first embodiment.
  • a buffer layer may be first prepared on the base substrate 10, and then the polysilicon film 2 is prepared to be formed on the buffer layer.
  • the buffer layer may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the polysilicon thin film layer 2 is etched to form a patterned active layer 20 by a photolithography process.
  • a gate insulating layer 30 is formed on the active layer 20.
  • the gate insulating layer 30 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the gate electrode 40 is formed. Specifically, the gate electrode 40 is located directly above the patterned active layer 20.
  • the material of the gate electrode 40 is selected from one or more of, but not limited to, Cr, Mo, Al, Cu, and may be one or more layers stacked.
  • an interlayer dielectric layer 50 is formed on the gate electrode 40.
  • the interlayer dielectric layer 50 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a patterned source electrode 61 and a drain electrode 62 are formed on the interlayer dielectric layer 50 by a photolithography process.
  • the source electrode 61 is connected to the active layer 20 through the first via 51
  • the drain electrode 62 is connected to the active layer 20 through the second via 52.
  • the material of the source electrode 61 and the drain electrode 62 is selected from one or more of Cr, Mo, Al, and Cu, and may be one or more layers.
  • a planarization layer 70 is formed on the source electrode 61 and the drain electrode 62.
  • the planarization layer 70 may be a silicon oxide (SiO x ) layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a photolithography process is used to etch a third via 71 exposing the drain electrode 62 in the planarization layer 70.
  • a patterned pixel electrode 80 is formed on the planarization layer 70 by using a photolithography process, and the pixel electrode 80 is connected to the drain electrode 62 through the third via 71. .
  • the third via 71 may be disposed to correspond to the position of the source electrode 61.
  • the pixel electrode 80 passes through the third via. 71 is connected to the source electrode 61.
  • a photolithography process (patterning process) is employed in a plurality of steps.
  • Each of the photolithography processes includes masking, exposure, development, etching, and stripping processes, respectively, wherein the etching process includes dry etching and wet etching.
  • the lithography process has been a relatively mature process technology in the art and will not be described in detail herein.
  • the polycrystal provided in Example 1 can also be used.
  • the preparation method of the silicon thin film is applied to a preparation process of a bottom gate type thin film transistor array substrate.
  • the method for preparing a polysilicon film is used in the process of preparing a thin film transistor array substrate.
  • the polysilicon film is first covered with an amorphous silicon film.
  • the amorphous silicon film is completely removed by a dry etching process, and the variation bumps on the surface of the polysilicon film are uniformly etched and etched during etching to remove the amorphous silicon film, thereby reducing the prepared polysilicon film.
  • the surface roughness, the flat surface of the polycrystalline silicon film can improve the stability of its electrical properties, and further improve the quality of the final product (such as LCD or OLED).

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Abstract

提供一种多晶硅薄膜的制备方法，其包括：应用半导体沉积工艺制备形成第一非晶硅薄膜（2a）；应用准分子激光退火工艺使第一非晶硅薄膜（2a）晶化形成多晶硅薄膜（2）；应用半导体沉积工艺在多晶硅薄膜（2）的第一表面（2b）上制备形成第二非晶硅薄膜（3）；应用干法刻蚀工艺，从第二非晶硅薄膜（3）朝向多晶硅薄膜（2）的方向，刻蚀直至完全去除第二非晶硅薄膜（3）。还提供了一种薄膜晶体管阵列基板的制备方法，其包括制备有源层（20）的步骤：根据上面多晶硅薄膜的制备方法制备形成一层多晶硅薄膜（2）；应用光刻工艺将多晶硅薄膜（2）刻蚀形成图案化的有源层（20）。

Description

多晶硅薄膜的制备方法、薄膜晶体管阵列基板的制备方法 技术领域
本发明涉及半导体器件的制造工艺,尤其涉及一种多晶硅薄膜的制备方法，还涉及一种薄膜晶体管阵列基板的制备方法。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED。
多晶硅(Poly-Si)薄膜是由许多大小不等和晶面取向不同的小晶粒组成，晶粒尺寸一般在几十到几百纳米之间，大晶粒尺寸可达数微米。大晶粒的多晶硅薄膜有较高的迁移率，接近块状材料的迁移率，因此多晶硅薄膜其已被广泛应用于半导体器件的制作中。例如在LCD或OLED产品中薄膜晶体管，大多采用多晶硅薄膜作为有源层。
目前多晶硅薄膜的制备方法，主要是先制备非晶硅薄膜，然后对非晶硅薄膜进行晶化处理获得多晶硅薄膜。其中，准分子激光退火法(Excimer Laser Anneal，ELA)是常用的一种方法，ELA法主要通过一定能量的准分子激光对非晶硅薄膜进行激光照射，利用激光光束的能量使非晶硅在高温下转变成多晶硅。在采用ELA法将非晶硅在高温下转变成多晶硅的过程中，所获得的多晶硅薄膜的表面上不可避免地会产生变异凸点，这些变异凸点会对后续的制程工艺产生影响，最终对薄膜晶体管的电性能的稳定性产生影响，降低产品的品质。
发明内容
有鉴于此，本发明提供了一种多晶硅薄膜的制备方法，对采用ELA法制备多晶硅薄膜进行改善，降低制备得到的多晶硅薄膜的表面粗糙度，提高产品的品质。
为了实现上述目的，本发明采用了如下的技术方案：
一种多晶硅薄膜的制备方法，其包括：应用半导体沉积工艺制备形成第一非晶硅薄膜；应用准分子激光退火工艺使所述第一非晶硅薄膜晶化形成多晶硅薄膜；应用半导体沉积工艺在所述多晶硅薄膜的第一表面上制备形成第二非晶硅薄膜；应用干法刻蚀工艺，从所述第二非晶硅薄膜朝向所述多晶硅薄膜的方向，刻蚀直至完全去除所述第二非晶硅薄膜。
其中，进行干法刻蚀工艺时，刻蚀至所述第一表面之下。
其中，进行干法刻蚀工艺时，在整个平面内各处的刻蚀速度相等。
其中，所述干法刻蚀工艺为等离子体刻蚀工艺。
其中，在进行准分子激光退火工艺之前，还对所述第一非晶硅薄膜进行加热去氢处理。
其中，加热去氢处理的温度为350～450℃。
本发明还提供了一种薄膜晶体管阵列基板的制备方法，包括制备有源层的步骤，其包括：根据如上所述的多晶硅薄膜的制备方法制备形成一层多晶硅薄膜；应用光刻工艺将所述多晶硅薄膜刻蚀形成图案化的有源层。
其中，该方法具体包括步骤：S1、提供以衬底基板并在所述衬底基板上制备形成图案化的有源层；S2、在所述有源层上制备形成栅极绝缘层；S3、在所述栅极绝缘层上制备形成图案化的栅电极；S4、在所述栅电极上制备形成层间介质层；S5、在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述有源层的第一过孔和第二过孔；S6、在所述层间介质层上制备形成图案化的源电极和漏电极，所述源电极通过所述第一过孔连接到所述有源层，所述漏电极通过所述第二过孔连接到所述有源层；S7、在所述源电极和漏电极上制备形成平坦化层；S8、在所述平坦化层中刻蚀形成暴露出所述源电极或所述漏电极的第三过孔；S9、在所述平坦化层上制备形成图案化的像素电极，所述像素电极通过所述第三过孔连接到所述源电极或所述漏电极。
本发明实施例中提供的多晶硅薄膜的制备方法，在采用ELA法将非晶硅薄膜变成多晶硅薄膜之后，在多晶硅薄膜先覆盖一层非晶硅薄膜，然后再使用干法刻蚀工艺刻蚀全去除非晶硅薄膜，在刻蚀去除非晶硅薄膜过程中同时均匀地刻蚀去除多晶硅薄膜表面上的变异凸点，降低了制备得到的多晶硅薄膜的表面 粗糙度，表面平整均匀的多晶硅薄膜可以提高其电性能的稳定性。
附图说明
图1a～1d是本发明实施例1提供的多晶硅薄膜的制备方法中，各个步骤对应获得的器件结构的示例性图示；
图2a～2j是本发明实施例2提供的薄膜晶体管阵列基板的制备方法中，各个步骤对应获得的器件结构的示例性图示。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
实施例1
本实施例提供了一种多晶硅薄膜的制备方法，参阅图1a至图1d，该方法包括以下步骤：
S11、如图1a所示，提供一衬底基板1，应用半导体沉积工艺在所述衬底基板1上制备形成第一非晶硅薄膜2a。其中，所述衬底基板1可以是选用玻璃基板。所述半导体沉积工艺可以是采用化学气相沉积工艺。
S12、如图1b所示，应用准分子激光退火(ELA)工艺使所述第一非晶硅薄膜2a晶化形成多晶硅薄膜2。在该步骤中，由于ELA工艺本身的影响，所获得的多晶硅薄膜2的第一表面(上表面)2b上不可避免地会产生变异凸点2c。
S13、如图1c所示，应用半导体沉积工艺在所述多晶硅薄膜2的第一表面2b上制备形成第二非晶硅薄膜3。其中，所述半导体沉积工艺可以是采用化学气相沉积工艺，第二非晶硅薄膜3完全覆盖多晶硅薄膜2的第一表面2b以及第一表面2b上的变异凸点2c。
S14、如图1d所示，应用干法刻蚀工艺(ETCH)，从所述第二非晶硅薄膜3 朝向所述多晶硅薄膜2的方向，刻蚀直至完全去除所述第二非晶硅薄膜3。其中，在刻蚀去除所述第二非晶硅薄膜3时，将多晶硅薄膜2的第一表面2b的变异凸点2c也同时刻蚀去除，由此最终获得的多晶硅薄膜2的表面更加平整均匀，提高其电性能的稳定性。
在优选的方案中，步骤S14中，所述干法刻蚀工艺选择使用等离子体刻蚀工艺。在进行干法刻蚀工艺时，应当控制在整个平面内各处的刻蚀速度接近于相等，最好是能控制为完全相等。
在优选的方案中，步骤S14中，进行干法刻蚀工艺时，刻蚀至所述第一表面2b之下，以确保变异凸点2c能够完全刻蚀去除，获得表面平整均匀的多晶硅薄膜2。
在优选的方案中，在进行步骤S12的ELA工艺之前，还对所述第一非晶硅薄膜2a进行加热去氢处理，由此使得最终制备得到的多晶硅薄膜2具有更良好的电性能。具体地，加热去氢处理的温度可以选择为350～450℃。
实施例2
本实施例提供了一种薄膜晶体管阵列基板的制备方法，参阅图2a-图2j，该方法包括步骤：
S21、在衬底基板10上制备形成图案化的有源层20。该步骤可以具体包括：
如图2a所示，首先采用实施例1中提供的多晶硅薄膜的制备方法，在衬底基板10上制备获得多晶硅薄膜2。优选的是，在沉积第一非晶硅薄膜层之前，还可以在衬底基板10上首先制备一缓冲层，然后将多晶硅薄膜2制备形成在缓冲层上。所述缓冲层可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
如图2b所示，应用光刻工艺，将所述多晶硅薄膜层2刻蚀形成图案化的有源层20。
S22、如图2c所示，在所述有源层20上制备形成栅极绝缘层30。具体地，所述栅极绝缘层30可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
S23、如图2d所示，应用光刻工艺，在所述栅极绝缘层30上制备形成图案 化的栅电极40。具体地，所述栅电极40相对位于所述图案化的有源层20的正上方。所述栅电极40的材料选自但不限于Cr、Mo、Al、Cu中的一种或多种，可为一层或多层堆叠。
S24、如图2e所示，在所述栅电极40上制备形成层间介质层50。具体地，所述层间介质层50可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
S25、如图2f所示，应用光刻工艺，在所述层间介质层50和所述栅极绝缘层30中刻蚀形成暴露出所述有源层20的第一过孔51和第二过孔52。
S26、如图2g所示，应用光刻工艺，在所述层间介质层50上制备形成图案化的源电极61和漏电极62。所述源电极61通过所述第一过孔51连接到所述有源层20，所述漏电极62通过所述第二过孔52连接到所述有源层20。其中，所述源电极61和漏电极62的材料选自但不限于Cr、Mo、Al、Cu中的一种或多种，可为一层或多层堆叠。
S27、如图2h所示，在所述源电极61和漏电极62上制备形成平坦化层70。具体地，所述平坦化层70可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。
S28、如图2i所示，应用光刻工艺，在所述平坦化层70中刻蚀形成暴露出所述漏电极62的第三过孔71。
S29、如图2j所示，应用光刻工艺，在所述平坦化层70上制备形成图案化的像素电极80，所述像素电极80通过所述第三过孔71连接到所述漏电极62。
需要说明的是，步骤S28中，所述第三过孔71也可以是设置为对应于所述源电极61的位置，此时，步骤S29中，所述像素电极80通过所述第三过孔71连接到所述源电极61。
以上的工艺过程中，在多个步骤中采用了光刻工艺(构图工艺)。其中，每一次光刻工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。光刻工艺已经是本领域中的比较成熟的工艺技术，在此不再展开详细说明。
另外，本实施例制备得到的薄膜晶体管阵列基板，其中的薄膜晶体管是顶栅型的薄膜晶体管。在另外的一些实施例中，也可以将实施例1中提供的多晶 硅薄膜的制备方法应用于底栅型的薄膜晶体管阵列基板的制备工艺中。
以上实施例中提供的多晶硅薄膜的制备方法，其用于薄膜晶体管阵列基板的制备工艺中，在采用ELA法将非晶硅薄膜变成多晶硅薄膜之后，在多晶硅薄膜先覆盖一层非晶硅薄膜，然后再使用干法刻蚀工艺刻蚀全去除非晶硅薄膜，在刻蚀去除非晶硅薄膜过程中同时均匀地刻蚀去除多晶硅薄膜表面上的变异凸点，降低了制备得到的多晶硅薄膜的表面粗糙度，表面平整均匀的多晶硅薄膜可以提高其电性能的稳定性，进一地也提高了最终产品(例如LCD或OLED)的品质。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (16)

  1. 一种多晶硅薄膜的制备方法，其中，包括：
    应用半导体沉积工艺制备形成第一非晶硅薄膜；
    应用准分子激光退火工艺使所述第一非晶硅薄膜晶化形成多晶硅薄膜；
    应用半导体沉积工艺在所述多晶硅薄膜的第一表面上制备形成第二非晶硅薄膜；
    应用干法刻蚀工艺，从所述第二非晶硅薄膜朝向所述多晶硅薄膜的方向，刻蚀直至完全去除所述第二非晶硅薄膜。
  2. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，进行干法刻蚀工艺时，刻蚀至所述第一表面之下。
  3. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，进行干法刻蚀工艺时，在整个平面内各处的刻蚀速度相等。
  4. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，所述干法刻蚀工艺为等离子体刻蚀工艺。
  5. 根据权利要求1所述的多晶硅薄膜的制备方法，其中，在进行准分子激光退火工艺之前，还对所述第一非晶硅薄膜进行加热去氢处理。
  6. 根据权利要求5所述的多晶硅薄膜的制备方法，其中，加热去氢处理的温度为350～450℃。
  7. 一种薄膜晶体管阵列基板的制备方法，包括制备有源层的步骤，其中，制备有源层的步骤包括：
    应用半导体沉积工艺制备形成第一非晶硅薄膜；
    应用准分子激光退火工艺使所述第一非晶硅薄膜晶化形成多晶硅薄膜；
    应用半导体沉积工艺在所述多晶硅薄膜的第一表面上制备形成第二非晶硅薄膜；
    应用干法刻蚀工艺，从所述第二非晶硅薄膜朝向所述多晶硅薄膜的方向， 刻蚀直至完全去除所述第二非晶硅薄膜；
    应用光刻工艺将所述多晶硅薄膜刻蚀形成图案化的有源层。
  8. 根据权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，进行干法刻蚀工艺时，刻蚀至所述第一表面之下。
  9. 根据权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，进行干法刻蚀工艺时，在整个平面内各处的刻蚀速度相等。
  10. 根据权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，所述干法刻蚀工艺为等离子体刻蚀工艺。
  11. 根据权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，在进行准分子激光退火工艺之前，还对所述第一非晶硅薄膜进行加热去氢处理。
  12. 根据权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，加热去氢处理的温度为350～450℃。
  13. 根据权利要求7所述的薄膜晶体管阵列基板的制备方法，其中，该方法具体包括步骤：
    S1、提供以衬底基板并在所述衬底基板上制备形成图案化的有源层；
    S2、在所述有源层上制备形成栅极绝缘层；
    S3、在所述栅极绝缘层上制备形成图案化的栅电极；
    S4、在所述栅电极上制备形成层间介质层；
    S5、在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述有源层的第一过孔和第二过孔；
    S6、在所述层间介质层上制备形成图案化的源电极和漏电极，所述源电极通过所述第一过孔连接到所述有源层，所述漏电极通过所述第二过孔连接到所述有源层；
    S7、在所述源电极和漏电极上制备形成平坦化层；
    S8、在所述平坦化层中刻蚀形成暴露出所述源电极或所述漏电极的第三过孔；
    S9、在所述平坦化层上制备形成图案化的像素电极，所述像素电极通过所 述第三过孔连接到所述源电极或所述漏电极。
  14. 根据权利要求13所述的薄膜晶体管阵列基板的制备方法，其中，步骤S1中，首先在所述衬底基板上制备缓冲层，然后在所述缓冲层上制备形成所述图案化的有源层。
  15. 根据权利要求13所述的薄膜晶体管阵列基板的制备方法，其中，所述栅极绝缘层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层；所述层间介质层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层。
  16. 根据权利要求13所述的薄膜晶体管阵列基板的制备方法，其中，所述栅电极的材料选自Cr、Mo、Al、Cu中的一种或多种，所述栅电极为一层或多层材料堆叠；所述源电极和所述漏电极的材料选自Cr、Mo、Al、Cu中的一种或多种，所述源电极和所述漏电极为一层或多层材料堆叠。
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