WO2019007331A1 - 完全隔离型的横向扩散金属氧化物半导体结构及制造方法 - Google Patents

完全隔离型的横向扩散金属氧化物半导体结构及制造方法 Download PDF

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WO2019007331A1
WO2019007331A1 PCT/CN2018/094299 CN2018094299W WO2019007331A1 WO 2019007331 A1 WO2019007331 A1 WO 2019007331A1 CN 2018094299 W CN2018094299 W CN 2018094299W WO 2019007331 A1 WO2019007331 A1 WO 2019007331A1
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semiconductor structure
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metal oxide
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王琼
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a fully isolated LDMOS.
  • the structure of the Fully Diffused Metal Oxide Semiconductor (LDMOS) of the Fully Isolated N-type channel allows the drain (Drain) and the isolated end (BN-ISO) compared to the conventional NLDMOS.
  • the voltage bias is different, and under different isolation terminal bias voltages, the stability of the electrical characteristics of the device can be ensured, and the application operation of the power supply integrated circuit is more suitable, and the demand is increasing.
  • fully isolated N-channel laterally diffused metal oxide semiconductors (Fully ISO NLDMOS) are currently in low voltage applications and are difficult to extend to high voltage applications.
  • HVPWell high-voltage P-type well region
  • a fully isolated laterally diffused metal oxide semiconductor structure comprising a substrate of a first doping type, a second doping type buried layer disposed within the first doping type substrate, formed in the first a main structure on the buried layer of the two doping type and an isolation ring disposed around the main structure, the buried layer together with the isolation ring isolates the main structure, and the first doped type has a first layer formed therein An enhancement layer of a doping type that is adjacent to one side of the main structure and integral with a well region within the main structure.
  • the present application also provides a method of fabricating a fully isolated laterally diffused metal oxide semiconductor structure, comprising:
  • a main structure and an isolation ring are formed on the epitaxial layer; the second doping type buried layer and the isolation ring together isolate the main structure.
  • FIG. 1 is a schematic structural view of a conventional fully isolated N-channel LDMOS
  • FIG. 2 is a schematic structural view of a completely isolated LDMOS according to an embodiment
  • Figure 3 is a cross-sectional view showing the structure of an LDMOS of a specific embodiment of Figure 2;
  • Figure 4 is a graph of longitudinal doping concentration along the cross section of Figure 3;
  • FIG. 5a is a schematic diagram of electric field distribution when the isolation terminal (ISO) bias voltage is 0V;
  • Figure 5b is a schematic diagram of electric field distribution when the isolation terminal (ISO) bias voltage is 50V;
  • Figure 6a is a breakdown characteristic of the NLDMOS isolation terminal (ISO);
  • FIG. 7 is a flow chart of a method of manufacturing Fully ISO NLDMOS according to an embodiment.
  • the semiconductor structure includes a first doping type substrate 110, a second doping type buried layer 120 disposed in the first doping type substrate 110, and a second doping type buried layer 120 formed on the second doping type buried layer 120.
  • the second doping type buried layer 120 is separated from the isolation ring 140 by a main structure 130.
  • the second doping type buried layer 120 is formed with a first doping type expansion layer 150.
  • the expansion layer 150 is formed. Adjacent to the side of the main structure 130 and integral with the well region within the main structure 130.
  • the first doping type is opposite to the second doping type.
  • the main structure 130 includes mutually separated channel regions and drift regions formed in the well region, wherein the well regions may be high voltage well regions of the first doping type.
  • a source region is formed in the channel region and is taken as a source
  • a drain region is formed in the drift region and is drawn as a drain
  • the gate structure spans the channel region and the drift region. Isolation is also performed at the necessary locations, such as shallow trench isolation between the electrode lead-out areas.
  • the fully isolated NLDMOS in the conventional technology when a large bias voltage is applied to the isolated terminal of the NLDMOS, the device high-voltage P-type well region (HVPWell) is buried by the bottom N-type buried layer (BN- It is completely depleted, affecting the potential distribution of the drift region (N-drift), causing the electrical characteristics of the device to fluctuate greatly.
  • HVPWell high-voltage P-type well region
  • BN- It N-type buried layer
  • N-drift drift region
  • the concentration of the N-type buried layer (BN) is high; in addition, increasing the P-substrate (P-sub) concentration significantly reduces the bottom P-substrate (P-sub) and N-type
  • the junction breakdown voltage of the buried layer (BN) becomes another constraint for the device to expand to high voltage applications. Therefore, the space for the bottom concentration of the P-type substrate is limited, and the improvement effect is limited.
  • the high voltage application of 40 to 60 V is difficult to achieve.
  • the extension layer 150 having the same doping type as the device well region in the epitaxial layer is formed on the side in contact with the epitaxial layer.
  • the well region in the epitaxial layer for forming the device main structure is longitudinally expanded to increase its depth.
  • the first doping type substrate 110 is a P type substrate
  • the second doping type buried layer 120 is an N type buried layer
  • the first doping The impurity type extension layer 150 is P-type doped.
  • the above doping achieves an N-channel fully isolated type of a laterally diffused metal oxide semiconductor (Fully ISO NLDMOS) device structure.
  • Fully ISO NLDMOS is widely used and requires a large amount of demand, but it is not easy to extend to high voltage fields, such as being easily broken down at a high voltage of 40V to 60V.
  • the depletion layer of the well region can be increased, and the junction breakdown voltage can also be high, and the application of the Fully ISO NLDMOS in the high voltage field can be realized, wherein the well region can be a high voltage P-type well region.
  • the doping impurity of the N-type buried layer 120 is phosphorus (P), and the P-type doping impurity of the expansion layer 150 is boron (B).
  • P phosphorus
  • B boron
  • the N-type buried layer 120 and the P-type impurity-extended layer 150 may be sequentially injected by high energy and then pushed together by a strong furnace tube.
  • HVPWell high-voltage P-type well region
  • P-sub P-substrate
  • N-drift drift region
  • the implantation peak of the dopant in the N-type buried layer 120 should be greater than the implantation peak depth of the dopant in the expansion layer 150; the implantation dose of the N-type impurity in the buried layer 120 is 5e12 to 5e13 cm - 2 ; The implantation energy range of the P-type impurity in the extension layer 150 is 50-200 KeV, and the implantation dose range is 5e12 to 5e13 cm -2 ; the specific implantation conditions should be determined by the longitudinal isolation voltage requirement of the device.
  • Figure 4 is a graph of longitudinal doping concentration along the cross section of Figure 3.
  • the solid point is a conventional doping concentration curve, and the hollow point is the doping concentration curve of the present embodiment.
  • NG represents the doping concentration distribution of the drift region on the longitudinal section;
  • HVPWell represents the doping concentration distribution of the well region;
  • BN_B is the doping concentration distribution of boron (B) in the extension layer 150;
  • BN_P is the N-type buried layer Doping concentration distribution of phosphorus (P) in 120;
  • P-sub represents a doping concentration distribution in a P-type substrate (P-sub).
  • the concentration of the N-type buried layer (BN) 120 may be decreased as compared with the doping concentration, implantation depth, and position of the conventional structure, but the implantation depth is increased and a P-type impurity is additionally implanted therein to form a doping region of the expansion layer 150. .
  • FIG. 5a is a schematic diagram of electric field distribution when the isolation terminal (ISO) bias voltage is 0V
  • FIG. 5b is a schematic diagram of electric field distribution when the isolation terminal (ISO) bias voltage is 50V. It can be seen that the isolation terminal (ISO) voltage is biased by 50V, the high voltage P-type well region (HVPwell) is not completely depleted and is far from the drift region; the surface electric field and potential of the device surface are compared with the isolation terminal (ISO) voltage bias of 0V. The distribution is no different.
  • Figure 6a shows the breakdown characteristic of the NLDMOS isolation terminal (ISO).
  • the vertical through-break voltage (Punch BV) of the bottom N-type buried layer (BN) to the surface drain (Drain) is as high as 75V. That is, the isolation terminal (ISO) can withstand voltages up to 75V.
  • Figure 6b shows the breakdown of the drain of the NLDMOS at different isolated terminal voltages.
  • the method includes the following steps S110-S150.
  • Step S110 providing a first doping type substrate 110.
  • Step S120 forming a second doping type buried layer 120 in the first doping type substrate 110 by implanting a second type of impurity.
  • Step S130 forming the expansion layer 150 by implanting impurities of the first type in the second doping type buried layer 120.
  • Step S140 epitaxially growing an epitaxial layer on the first doping type substrate 110 (not labeled in FIG. 2).
  • Step S150 forming a main structure 130 and an isolation ring 140 on the epitaxial layer; the second doping type buried layer 120 and the isolation ring 140 together isolate the main structure 130.
  • the main structure 130 is an LDMOS structure, and the forming method is not described herein.
  • an NLDMOS device is manufactured by first forming an N-type buried layer (BN) on a P-substrate (P-sub), and then a P-type substrate having an N-type buried layer (BN).
  • An epitaxial layer is epitaxially grown on (P-sub), and then a main structure of the NLDMOS is formed using a fixed process to realize its function. Since the process is fixed (the equipment, raw materials, conditions, etc. are fixed and the process is mature and cannot be easily changed), the main structure formed on the epitaxial layer is usually also fixed, and the device parameters are completely fixed.
  • HVPWell high-voltage P-type well region
  • the epitaxial layer can be formed.
  • the well region for forming the main structure of the device is longitudinally expanded to increase its depth.
  • the well region may be a high-voltage well region of the first doping type.
  • the first doping type substrate 110 is a P-type substrate (P-sub), and the second doping type buried layer 120 is an N-type buried layer ( BN), the first doping type expansion layer 150 is P-type doped.
  • the above doping achieves an N-channel fully isolated type of a laterally diffused metal oxide semiconductor (Fully ISO NLDMOS) device structure.
  • Fully ISO NLDMOS is widely used and has a large demand, but it is not easy to extend to the high voltage field, such as it is difficult to work under the high voltage of 40V ⁇ 60V.
  • the depletion layer of the well region can be increased, and the junction breakdown voltage can also be high, thereby realizing the application of the Fully ISO NLDMOS in the high voltage field.
  • the doping impurity of the N-type buried layer is phosphorus (P), and the P-type doping impurity of the expanded layer 150 is boron (B).
  • the N-type buried layer and the P-type impurity-extended layer 150 may be sequentially formed by high-energy implantation and then pushed together through a strong furnace tube, since the high-voltage P-type well region (HVPWell) extends from the epitaxial layer to the P-type substrate (P- Sub)110, effectively increasing the depletion region of HVPwell; in the application, the HVPwell depletion region is far away from the drift region (N-drift) region of the device surface under different high voltage bias, and the device potential and electric field distribution are not The bottom bias is affected and the electrical characteristics of the device are constant.
  • the implantation depth of the dopant in the N-type buried layer (BN) 120 is greater than the implantation depth of the dopant in the expansion layer 150;
  • the implantation dose range of the N-type impurity in the buried layer 120 is 5e12 to 5e13 cm. -2 ;
  • the implantation energy of the P-type impurity in the extension layer 150 ranges from 50 to 200 KeV, and the implantation dose ranges from 5e12 to 5e13 cm -2 ;
  • the specific implantation conditions are determined by the longitudinal isolation voltage requirement of the device.
  • Figure 4 is a graph of longitudinal doping concentration along the cross section of Figure 3.
  • the solid point is a conventional doping concentration curve, and the hollow point is the doping concentration curve of the present embodiment.
  • NG represents the doping concentration distribution of the drift region on the longitudinal section;
  • HVPWell represents the doping concentration distribution of the well region;
  • BN_B is the doping concentration distribution of boron (B) in the extension layer 150;
  • BN_P is the N-type buried layer Doping concentration distribution of phosphorus (P) in 120;
  • P-sub represents a doping concentration distribution in a P-type substrate (P-sub).
  • the concentration of the N-type buried layer (BN) 120 may be decreased as compared with the doping concentration, implantation depth, and position of the conventional structure, but the implantation depth is increased and a P-type impurity is additionally implanted therein to form a doping region of the expansion layer 150. .
  • FIG. 5a is a schematic diagram of electric field distribution when the isolation terminal (ISO) bias voltage is 0V
  • FIG. 5b is a schematic diagram of electric field distribution when the isolation terminal (ISO) bias voltage is 50V. It can be seen that the isolation terminal (ISO) voltage is biased by 50V, the high voltage P-type well region (HVPwell) is not completely depleted and is far from the drift region; the surface electric field and potential of the device surface are compared with the isolation terminal (ISO) voltage bias of 0V. The distribution is no different.
  • Figure 6a shows the breakdown characteristic of the NLDMOS isolation terminal (ISO).
  • the vertical through-break voltage (Punch BV) of the bottom N-type buried layer (BN) to the surface drain (Drain) is as high as 75V, the isolation terminal (ISO) can withstand up to 75V.

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Abstract

一种完全隔离型的横向扩散金属氧化物半导体结构，包括第一掺杂类型的衬底(110)、置于第一掺杂类型衬底(110)内的第二掺杂类型埋层(120)、形成在第二掺杂类型埋层(120)上的主结构(130)以及设置在主结构(130)周围的隔离环(140)，埋层(120)与隔离环(140)一起将主结构(130)进行隔离，第二掺杂类型埋层(120)内形成有第一掺杂类型的扩展层(150)，扩展层(150)靠近主结构(130)一侧、且与主结构(130)内的阱区形成一体。一种制造方法，用于制造该半导体结构。

Description

完全隔离型的横向扩散金属氧化物半导体结构及制造方法 技术领域
本发明涉及半导体技术领域，特别是涉及一种完全隔离型的LDMOS。
背景技术
完全隔离型(Fully Isolated)N型沟道的横向扩散金属氧化物半导体(Laterally Diffused Metal Oxide Semiconductor，LDMOS)的结构与传统NLDMOS相比，其允许漏极(Drain)和隔离端(BN-ISO)电压偏置存在差异，并且在不同的隔离端偏置电压下，能够保证器件电学特性的稳定性，更贴合电源集成电路的应用操作，需求量日益增长。但是，完全隔离型N型沟道的横向扩散金属氧化物半导体(Fully ISO NLDMOS)目前还徘徊于低压应用领域，很难延伸至高压应用。究其原因主要是，高压领域隔离端电压偏置较大，器件高压P型阱区(HVPWell)被底部N型埋层(BN)完全耗尽，影响漂移区(N-drift)的电势分布，造成器件电学特性波动很大。
发明内容
基于此，有必要提供一种新型的完全隔离型的横向扩散金属氧化物半导体结构。
一种完全隔离型的横向扩散金属氧化物半导体结构，包括第一掺杂类型的衬底、置于所述第一掺杂类型衬底内的第二掺杂类型埋层、形成在所述第二掺杂类型埋层上的主结构以及设置在所述主结构周围的隔离环，所述埋层与隔离环一起将主结构进行隔离，所述第二掺杂类型埋层内形成有第一掺杂类型的扩展层，所述扩展层靠近所述主结构一侧、且与主结构内的阱区形成一体。
本申请还提供了一种完全隔离型的横向扩散金属氧化物半导体结构的制 造方法，包括：
提供第一掺杂类型衬底；
在所述第一掺杂类型衬底内通过注入第二类型杂质的方式形成第二掺杂类型埋层；
在所述第二掺杂类型埋层内通过注入第一类型杂质的方式形成扩展层；
在所述第一掺杂类型衬底上外延生长外延层；
在所述外延层上形成主结构和隔离环；所述第二掺杂类型埋层和隔离环一起将主结构隔离。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为传统的完全隔离型N型沟道的LDMOS的结构示意图；
图2为一实施方式的完全隔离型的LDMOS的结构示意图；
图3为图2的一个具体实施例的LDMOS的结构剖视图；
图4为沿图3剖面的纵向掺杂浓度的曲线图；
图5a为隔离端(ISO)偏置电压为0V时的电场分布示意图；
图5b为隔离端(ISO)偏置电压为50V时的电场分布示意图；
图6a为NLDMOS隔离端(ISO)的击穿特性曲线；
图6b为当隔离端(ISO)电压偏置＝0V或者50V时NLDMOS漏极(Drain)的击穿特性曲线；
图7为一实施例的Fully ISO NLDMOS制造方法流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
图2为一实施方式的完全隔离型的横向扩散金属氧化物半导体结构。该半导体结构包括第一掺杂类型衬底110、置于所述第一掺杂类型衬底110内的第二掺杂类型埋层120、形成在所述第二掺杂类型埋层120上的外延层内的主结构130以及设置在所述主结构130周围的隔离环140。所述第二掺杂类型埋层120与隔离环140一起将主结构130进行隔离，所述第二掺杂类型埋层120内形成有第一掺杂类型的扩展层150，所述扩展层150靠近所述主结构130一侧、且与主结构130内的阱区形成一体。第一掺杂类型与第二掺杂类型导电性质相反。
其中，主结构130包括形成在阱区内的相互分离的沟道区和漂移区，其中，阱区可为第一掺杂类型的高压阱区。沟道区内形成源极区并引出为源极，漂移区内形成漏极区并引出为漏极，栅极结构横跨沟道区和漂移区。在必要的位置还进行隔离，例如在各电极引出区域之间采用浅槽隔离。
如图1所示为传统技术中的完全隔离型的NLDMOS，当在该NLDMOS的隔离端施加较大的偏置电压时，器件高压P型阱区(HVPWell)被底部N型埋层(BN-)完全耗尽，影响漂移区(N-drift)的电势分布，造成器件电学特性波动很大。在传统技术中，为减缓杂质耗尽，通常是在已开发好的高压Fully ISO NLDMOS器件底部加大P型杂质，提高P型衬底(P-sub)浓度。 但是，作为隔离端，N型埋层(BN)的浓度会很高；此外，增加P型衬底(P-sub)浓度，会显著地降低底部P型衬底(P-sub)和N型埋层(BN)的结击穿电压，成为器件向高压应用拓展的另一个制约，所以P型衬底底部浓度的提升空间有限，改善效果也有限，40～60V的高压应用难以实现。
而在本方案中，通过在第二掺杂类型埋层120内掺入第一类型杂质，在与外延层接触的一面形成与外延层内的器件阱区掺杂类型相同的扩展层150，可以将外延层内的用于形成器件主结构的阱区纵向扩张，增加其深度。在隔离端进行正向高压偏置时，该阱区不容易被耗尽，从而不会影响到漂移区，器件的电学特性稳定。使得在整个器件工艺固定的情况下，实现这类完全隔离型的横向扩散金属氧化物半导体器件的高压应用。
在其中一个实施例中，如图3所示，所述第一掺杂类型衬底110为P型衬底，所述第二掺杂类型埋层120为N型埋层，所述第一掺杂类型的扩展层150为P型掺杂。在本实施例中，上述掺杂实现了N沟道完全隔离型的横向扩散金属氧化物半导体(Fully ISO NLDMOS)器件结构。Fully ISO NLDMOS应用广泛，需求量大，但不易延伸到高压领域，如在40V～60V的高压下容易被击穿。通过上述结构，既可以增加阱区的耗尽层，同时结击穿电压也可以很高，实现Fully ISO NLDMOS在高压领域的应用，其中，阱区可为高压P型阱区。
在其中一个实施例中，所述N型埋层120的掺杂杂质为磷(P)，所述扩展层150的P型掺杂杂质为硼(B)。其中，N型埋层120和P型杂质扩展层150可以先后通过高能注入，然后经由强炉管一起推阱形成。由于高压P型阱区(HVPWell)从外延层延伸至P型衬底(P-sub)110，有效增加了HVPwell的耗尽区域；应用中，隔离端在不同高压偏置下，HVPwell耗尽区都远离器件表面的漂移区(N-drift)区域，器件电势、电场分布不受底部偏压影响，进而器件电学特性恒定不变。可以理解，在其他实施例中，可以是其他N型掺杂和P型掺杂。
具体地，所述N型埋层120中掺杂剂的注入峰值应大于所述扩展层150 中掺杂剂的注入峰值深度；埋层120中的N型杂质的注入剂量范围为5e12～5e13cm -2；扩展层150中P型杂质的注入能量范围50～200KeV，注入剂量范围为5e12～5e13cm -2；具体注入条件应由器件纵向隔离电压需求决定。
图4为沿图3剖面的纵向掺杂浓度的曲线图。图中，实心点为传统的掺杂浓度曲线，空心点为本实施例的掺杂浓度曲线。图中，NG代表在该纵向剖面上漂移区的掺杂浓度分布；HVPWell代表阱区的掺杂浓度分布；BN_B为扩展层150中硼(B)的掺杂浓度分布；BN_P为N型埋层120中磷(P)的掺杂浓度分布；P-sub代表P型衬底(P-sub)中的掺杂浓度分布。
与传统结构的掺杂浓度、注入深度、位置相比，N型埋层(BN)120的浓度可以有所下降，但注入深度增加并在其中额外注入P型杂质形成扩展层150的掺杂区域。
上述NLDMOS结构具有良好的高压表现。图5a为隔离端(ISO)偏置电压为0V时的电场分布示意图，图5b为隔离端(ISO)偏置电压为50V时的电场分布示意图。可以看到，隔离端(ISO)电压偏置50V，高压P型阱区(HVPwell)没有完全耗尽，并远离漂移区；与隔离端(ISO)电压偏置0V相比，器件表面电场、电势分布并无不同。
如图6a所示为NLDMOS隔离端(ISO)的击穿特性曲线，由图6a可知，底部N型埋层(BN)到表面漏极(Drain)的纵向穿通击穿电压(Punch BV)高达75V，即隔离端(ISO)所承受的电压可高达75V。如图6b所示为当隔离端(ISO)电压偏置＝0V或者50V时NLDMOS漏极(Drain)的击穿特性曲线，由图6b可知，NLDMOS在不同的隔离端电压下漏极的击穿特性曲线(BV Curve)保持不变，漏极(Drain)所承受的击穿电压均为BV＝65V。
基于同一发明构思，以下提供一种完全隔离型的横向扩散金属氧化物半导体结构的制造方法。如图7所示，并结合图2，该方法包括以下步骤S110～S150。
步骤S110：提供第一掺杂类型衬底110。
步骤S120：在所述第一掺杂类型衬底110内通过注入第二类型杂质的方 式形成第二掺杂类型埋层120。
步骤S130：在所述第二掺杂类型埋层120内通过注入第一类型杂质的方式形成扩展层150。
步骤S140：在所述第一掺杂类型衬底110上外延生长外延层(图2未标)。
步骤S150：在所述外延层上形成主结构130和隔离环140；所述第二掺杂类型埋层120和隔离环140一起将主结构130隔离。其中主结构130为LDMOS结构，形成方法在此不赘述。
传统技术中，NLDMOS器件在制造时，是先在一个P型衬底(P-sub)上通过注入形成N型埋层(BN)，然后在具有N型埋层(BN)的P型衬底(P-sub)上外延生长外延层，然后使用固定的工艺形成NLDMOS的主体结构，以实现其功能。由于工艺固定(所使用的设备、原料、条件等都固定，工艺成熟不能轻易改变)，在外延层上形成的主体结构通常也是固定的，其器件参数也完全固定。最主要的是，外延层内的高压P型阱区(HVPWell)的厚度、浓度等也固定，无法通过其他方式提升高压P型阱区使其不被耗尽。因此这限制了Fully ISO NLDMOS器件延伸至高压应用。
上述方法，通过在第二掺杂类型埋层120内掺入第一类型杂质，在与外延层接触的一面形成与外延层内的器件阱区掺杂类型相同的扩展层150，可以将外延层内的用于形成器件主结构的阱区纵向扩张，增加其深度，在本方案中，阱区可为第一掺杂类型的高压阱区。在隔离端进行正向高压偏置时，该阱区不容易被耗尽，从而不会影响到漂移区，器件的电学特性稳定。使得在整个器件工艺条件固定的情况下，实现这类完全隔离型的横向扩散金属氧化物半导体器件的高压应用。
在其中一个实施例中，如图3所示，所述第一掺杂类型衬底110为P型衬底(P-sub)，所述第二掺杂类型埋层120为N型埋层(BN)，所述第一掺杂类型的扩展层150为P型掺杂。在本实施例中，上述掺杂实现了N沟道完全隔离型的横向扩散金属氧化物半导体(Fully ISO NLDMOS)器件结构。Fully ISO NLDMOS应用广泛，需求量大，但不易延伸到高压领域，如在40V～60V 的高压下难以工作。通过上述结构，既可以增加阱区的耗尽层，同时结击穿电压也可以很高，实现Fully ISO NLDMOS在高压领域的应用。
在其中一个实施例中，所述N型埋层的掺杂杂质为磷(P)，所述扩展层150的P型掺杂杂质为硼(B)。其中，N型埋层和P型杂质扩展层150可以先后通过高能注入，然后经由强炉管一起推阱形成，由于高压P型阱区(HVPWell)从外延层延伸至P型衬底(P-sub)110，有效增加了HVPwell的耗尽区域；应用中，隔离端在不同高压偏置下，HVPwell耗尽区都远离器件表面的漂移区(N-drift)区域，器件电势、电场分布不受底部偏压影响，进而器件电学特性恒定不变。
具体地，所述N型埋层(BN)120中掺杂剂的注入深度大于所述扩展层150中掺杂剂的注入深度；埋层120中的N型杂质的注入剂量范围为5e12～5e13cm -2；扩展层150中P型杂质的注入能量范围50～200KeV，注入剂量范围为5e12～5e13cm -2；具体注入条件应由器件纵向隔离电压需求决定。
图4为沿图3剖面的纵向掺杂浓度的曲线图。图中，实心点为传统的掺杂浓度曲线，空心点为本实施例的掺杂浓度曲线。图中，NG代表在该纵向剖面上漂移区的掺杂浓度分布；HVPWell代表阱区的掺杂浓度分布；BN_B为扩展层150中硼(B)的掺杂浓度分布；BN_P为N型埋层120中磷(P)的掺杂浓度分布；P-sub代表P型衬底(P-sub)中的掺杂浓度分布。
与传统结构的掺杂浓度、注入深度、位置相比，N型埋层(BN)120的浓度可以有所下降，但注入深度增加并在其中额外注入P型杂质形成扩展层150的掺杂区域。
上述NLDMOS结构具有良好的高压表现。图5a为隔离端(ISO)偏置电压为0V时的电场分布示意图，图5b为隔离端(ISO)偏置电压为50V时的电场分布示意图。可以看到，隔离端(ISO)电压偏置50V，高压P型阱区(HVPwell)没有完全耗尽，并远离漂移区；与隔离端(ISO)电压偏置0V相比，器件表面电场、电势分布并无不同。
如图6a所示为NLDMOS隔离端(ISO)的击穿特性曲线，由图6a可知，， 底部N型埋层(BN)到表面漏极(Drain)的纵向穿通击穿电压(Punch BV)高达75V，即隔离端(ISO)所承受的电压可高达75V。如图6b所示为当隔离端(ISO)电压偏置＝0V或者50V时NLDMOS漏极(Drain)的击穿特性曲线，由图6b可知，NLDMOS在不同的隔离端电压下漏极的击穿曲线(BV Curve)保持不变，漏极(Drain)所承受的击穿电压BV＝65V。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种完全隔离型的横向扩散金属氧化物半导体结构，包括：
    第一掺杂类型衬底；
    第二掺杂类型埋层，置于所述第一掺杂类型衬底内；
    主结构，形成在所述第二掺杂类型埋层上；
    以及
    隔离环，设置在所述主结构周围，所述埋层与隔离环一起将主结构进行隔离；
    其中，所述第二掺杂类型埋层内形成有第一掺杂类型的扩展层，所述扩展层靠近所述主结构一侧、且与主结构内的阱区形成一体。
  2. 根据权利要求1所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述第一掺杂类型衬底为P型衬底，所述第二掺杂类型埋层为N型埋层，所述第一掺杂类型的扩展层为P型掺杂。
  3. 根据权利要求2所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述N型埋层的掺杂杂质为磷，所述扩展层的P型掺杂杂质为硼。
  4. 根据权利要求2所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，扩展层的P型杂质的注入能量范围50～200KeV。
  5. 根据权利要求2所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，扩展层的P型杂质的注入剂量范围5e12～5e13cm -2。
  6. 根据权利要求5所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述N型埋层的注入峰值大于扩展层P型杂质注入峰值，N型杂质的注入剂量范围在5e12～5e13cm -2。
  7. 根据权利要求1所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述第一掺杂类型衬底为N型衬底，所述第二掺杂类型埋层为P型埋层，所述第一掺杂类型的扩展层为N型掺杂。
  8. 根据权利要求1所述的完全隔离型的横向扩散金属氧化物半导体结 构，其中，所述主结构包括阱区以及形成在阱区内的相互分离的沟道区和漂移区，所述沟道区内形成有源极区，所述源极区引出有源极，所述漂移区内形成有漏极区，所述漏极区引出有漏极，所述半导体结构还包括栅极结构，所述栅极结构横跨沟道区和漂移区。
  9. 根据权利要求8所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述阱区为第一掺杂类型高压阱区。
  10. 根据权利要求8所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述半导体结构内中的各电极引出区域之间设置有浅槽以对所述各电极进行隔离。
  11. 一种完全隔离型的横向扩散金属氧化物半导体结构的制造方法，包括：
    提供第一掺杂类型衬底；
    在所述第一掺杂类型衬底内通过注入第二类型杂质的方式形成第二掺杂类型埋层；
    在所述第二掺杂类型埋层内通过注入第一类型杂质的方式形成扩展层；
    在所述第一掺杂类型衬底上外延生长外延层；
    在所述外延层上形成主结构和隔离环；所述第二掺杂类型埋层和隔离环一起将主结构隔离。
  12. 根据权利要求11所述的完全隔离型的横向扩散金属氧化物半导体结构的制造方法，其中，所述第一掺杂类型衬底为P型衬底，所述第二掺杂类型埋层为N型埋层，所述第一掺杂类型的扩展层为P型掺杂。
  13. 根据权利要求12所述的完全隔离型的横向扩散金属氧化物半导体结构的制造方法，其中，所述N型埋层的掺杂杂质为磷，所述扩展层的P型掺杂杂质为硼。
  14. 根据权利要求12所述的完全隔离型的横向扩散金属氧化物半导体结构的制造方法，其中，所述N型埋层和P型杂质扩展层为先后通过高能注入杂质，然后经由强炉管一起推阱形成。
  15. 根据权利要求12所述的完全隔离型的横向扩散金属氧化物半导体结构的制造方法，其中，扩展层的P型杂质的注入能量范围50～200KeV。
  16. 根据权利要求15所述的完全隔离型的横向扩散金属氧化物半导体结构的制造方法，其中，扩展层的P型杂质的注入剂量范围为5e12～5e13cm -2。
  17. 根据权利要求16所述的完全隔离型的横向扩散金属氧化物半导体结构的制造方法，其中，所述N型埋层的注入峰值大于扩展层P型杂质注入峰值，N型杂质的注入剂量范围在5e12～5e13cm -2。
  18. 根据权利要求11所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述主结构包括阱区以及形成在阱区内的相互分离的沟道区和漂移区，所述沟道区内形成有源极区，所述源极区引出有源极，所述漂移区内形成有漏极区，所述漏极区引出有漏极，所述半导体结构还包括栅极结构，所述栅极结构横跨沟道区和漂移区。
  19. 根据权利要求18所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述阱区为第一掺杂类型高压阱区。
  20. 根据权利要求18所述的完全隔离型的横向扩散金属氧化物半导体结构，其中，所述半导体结构内中的各电极引出区域之间设置有浅槽以对所述各电极进行隔离。
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