WO2019004074A1

WO2019004074A1 - Liquid crystal display device and driving method therefor

Info

Publication number: WO2019004074A1
Application number: PCT/JP2018/023777
Authority: WO
Inventors: 美鈴根来; 長和藤本
Original assignee: シャープ株式会社
Priority date: 2017-06-30
Filing date: 2018-06-22
Publication date: 2019-01-03

Abstract

[Problem] To disclose a liquid crystal display device capable of preventing a driving circuit from malfunctioning due to noise caused by inversion drive and thereby suppressing defective display resulting from the malfunction. In the liquid crystal display device, a gradation-voltage slope circuit (620) converts gradation voltages VPk, VNk (k = 1 to n) output from a power supply circuit (600) to gradation voltages for DA conversion VsPk, VsNk (k = 1 to n), and a source driver (300) generates data signals (G1 to GN) to be applied to the data signal lines (GL1 to GLN) for a display unit via DA convertor circuit (320) or the like using these gradation voltages for DA conversion VsPk, VsNk (k = 1 to n). Thereby, when the voltage change during the polarity inversion of data signal lines (SLj) is greater than a prescribed amount, the rate of change of the voltage during the polarity inversion decreases, to thus reduce the noise generated in the scanning signal lines (GLi) due to the change in voltage.

Description

Liquid crystal display device and driving method thereof

The present invention relates to a liquid crystal display device having a plurality of pixel formation portions arranged in a matrix and a method of driving the same.

The active matrix liquid crystal display device is arranged in a matrix corresponding to a plurality of data signal lines, a plurality of scanning signal lines intersecting them, a plurality of data signal lines, and the plurality of scanning signal lines. A liquid crystal panel as a display unit including a plurality of pixel formation units is provided, and each pixel formation unit includes a pixel capacitance and a switching element. Here, as a switching element, a thin film transistor (hereinafter, referred to as "TFT") is usually used. The pixel capacitance in each pixel formation portion is formed of a pixel electrode and a common electrode (also referred to as "counter electrode") facing the pixel electrode with the liquid crystal interposed therebetween, and the pixel electrode is used as the switching element. It is connected to the corresponding data signal line through the TFT, and the corresponding scanning signal line is connected to the gate terminal of the TFT.

The plurality of data signal lines are connected to a source driver as a data signal line drive circuit, and the plurality of scan signal lines are connected to a gate driver as a scan signal line drive circuit. The data signal line drive circuit applies a plurality of data signals representing an image to be displayed to the plurality of data signal lines, and the scan signal line drive circuit performs a plurality of scans for sequentially selecting the plurality of scan signal lines. A signal is applied to the plurality of scan signal lines. Thus, a voltage representing each pixel of the image to be displayed is applied to the pixel electrode in the corresponding pixel formation portion, and a voltage corresponding to the difference between the voltage of the pixel electrode and the voltage of the common electrode in each pixel formation portion is liquid crystal Applied to the Further, light is emitted from the backlight as a planar light source on the back of the liquid crystal panel. As a result, the liquid crystal in each pixel formation portion changes the light transmittance according to the applied voltage, and the image represented by the plurality of data signals is displayed on the liquid crystal panel.

Incidentally, in connection with the following disclosure, in Patent Document 1, two scanning lines (scanning signal lines) are assigned to each pixel row consisting of pixels aligned in the horizontal direction, and the two scanning lines are arranged in one horizontal period. A liquid crystal display device configured to write display voltages with one signal line (data signal line) to each pixel of two pixel columns formed of pixels arranged in the vertical direction by continuously selecting scanning lines is used. Have been described. According to such a configuration, although the number of output drivers of signal line data is reduced to half as compared with the normal configuration, a display defect due to the inversion drive of the liquid crystal display may be a problem. That is, in adjacent pixels sandwiching one signal line, the potential of the previously written pixel (previous stage pixel) is modulated at the time of writing by the opposite polarity potential of the later written pixel (following stage pixel), As a result, a difference occurs in the pixel potential between the front-stage pixel and the rear-stage pixel, which may cause a display defect due to the generation of the longitudinal streak unevenness. In order to solve this problem, the invention described in Patent Document 1 relates to the voltage supplied to the signal line when the even-numbered pixel of the display pixel is selected and the signal line when the odd-numbered pixel of the display pixel is selected. It is configured such that the potential of the front stage pixel and the potential of the rear stage pixel become equal by switching the voltage supplied to the circuit and correcting the gradation voltage of the front stage pixel.

Japanese Patent Application Laid-Open No. 10-171412

In a liquid crystal display device, an inversion driving method of driving a liquid crystal panel so that the polarity of a voltage applied to a pixel electrode is inverted at regular intervals with reference to the voltage (common voltage) of a common electrode in order to prevent deterioration of liquid crystal. Is adopted. Several methods are known as this inversion drive method, but line inversion that inverts the polarity of the voltage applied to the liquid crystal every predetermined number of one or more display lines so that the display quality is not deteriorated by the inversion drive. In many cases, a driving method, a dot inversion driving method in which the polarity of the voltage applied to the liquid crystal is inverted for each pixel formation portion, or the like is used. Therefore, the polarity of the data signal applied from the source driver to each data signal line is usually inverted every one horizontal period or every predetermined number of two or more horizontal periods.

In the liquid crystal display device, since such a reverse drive method is adopted, depending on the image to be displayed, noise in the display panel may cause the gate driver to malfunction and cause a display failure. Patent Document 1 discloses a display defect problem based on a pixel potential difference generated due to inversion driving between an immediately preceding pixel and a succeeding pixel interposing a single signal line, and a configuration for solving the problem. Although it is described, the description regarding the malfunction of the gate driver by the noise resulting from the inversion drive, the suppression method of such a malfunction, etc. is not seen.

Therefore, it is desirable to provide a liquid crystal display device that prevents a malfunction of a driving circuit due to noise caused by inversion driving and suppresses a display defect due to the malfunction.

Some embodiments of the present invention may include a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, a matrix along the plurality of data signal lines and the plurality of scan signal lines. A liquid crystal display device having a display portion including a plurality of pixel formation portions arranged in a shape of
A scanning signal line drive circuit for selectively driving the plurality of scanning signal lines;
The plurality of data signals are generated including a plurality of buffers to which the plurality of data signal lines are respectively connected, and a plurality of data signals whose polarity is inverted at predetermined time intervals with reference to a predetermined center voltage. And a data signal line drive circuit applied to the signal line,
In the data signal line drive circuit, when the amount of change of any data signal is larger than a predetermined amount in the polarity inversion of the plurality of data signals, the change speed of any one data signal in the polarity inversion is the plurality The plurality of data signals are generated so as to have a predetermined low change rate smaller than the change rate corresponding to the through rate of the buffer.

Preferred configurations of the above several embodiments are:
A gradation voltage generation circuit that generates a plurality of positive and negative polarity gradation voltages;
Among the plurality of positive and negative polarity gradation voltages, at least one of the plurality of positive and negative polarity gradation voltages is provided inside or outside the data signal line drive circuit, and at least one of the positive and negative polarity gradation voltages is greater than a predetermined value. Immediately before the point of time of polarity inversion of the plurality of data signals, the gradation voltage changes toward the central voltage at a change rate corresponding to the low change rate, and immediately after the point of inversion Gradation voltage conversion that converts the plurality of positive and negative polarity gradation voltages into a plurality of positive and negative polarity DA conversion gradation voltages by replacing the voltage with a waveform that returns to the gradation voltage at speed. Further comprising a circuit and
The data signal line drive circuit is configured such that, for each of the plurality of data signal lines, the polarity of the data signal to be applied to the data signal line out of the plurality of positive and negative polarity gradation voltages for DA conversion is The gradation voltage for positive polarity or negative polarity DA conversion according to the image to be displayed on the display unit is selected to be inverted every predetermined time, and the selected gradation voltage for positive polarity or negative polarity DA conversion is selected. It applies to the said data signal line as a data signal.

According to other embodiments of the present invention, a plurality of data signal lines, a plurality of scan signal lines intersecting the plurality of data signal lines, the plurality of data signal lines and the plurality of scan signal lines are provided. It is a driving method of a liquid crystal display device having a display unit including a plurality of pixel formation units arranged in a matrix.
A scanning signal line driving step of selectively driving the plurality of scanning signal lines;
A data signal line driving step of generating a plurality of data signals whose polarity is inverted at predetermined time intervals with reference to a predetermined center voltage, and applying the plurality of data signals to the plurality of data signal lines via a plurality of buffers; Equipped with
In the data signal line driving step, when the change amount of any data signal is larger than a predetermined amount in polarity inversion of the plurality of data signals, the change speed of any one data signal in the polarity inversion is the plurality The plurality of data signals are generated to have a predetermined low change rate smaller than the change rate corresponding to the through rate of the buffer.

According to the above embodiments of the present invention, when the amount of change in any data signal is larger than a predetermined amount in the polarity inversion of the plurality of data signals in the display unit, the data in the polarity inversion is any one of the data The plurality of data signals are generated such that the change rate of the signal is a predetermined low change rate smaller than the change rate corresponding to the slew rate of the buffer. Thereby, the noise caused by the voltage change of the data signal line due to the polarity inversion of the data signal affecting the scanning signal line through the parasitic capacitance of the pixel formation portion is reduced. Therefore, the malfunction of the scanning signal line due to the noise is prevented, and the display failure due to the malfunction is suppressed.

According to a preferable configuration of the above-described some embodiments of the present invention, at least one positive polarity having a larger absolute value than a predetermined value among a plurality of positive polarity and negative polarity gradation voltage generated by the gradation voltage generation circuit And the negative polarity gradation voltage is changed from the gradation voltage to the central voltage of polarity inversion at a change rate corresponding to the low change speed immediately before the polarity inversion point of the data signal and immediately after the inversion point The plurality of positive polarity and negative polarity gradation voltages are converted into a plurality of positive polarity and negative polarity DA conversion floors by replacing the voltage of the waveform that returns to the gradation voltage at a change rate corresponding to the low change rate. Converted to regulated voltage. A plurality of data signals generated by DA conversion processing based on the plurality of positive polarity and negative polarity DA conversion gradation voltages are applied to the plurality of data signal lines in the display unit. Thereby, when the voltage change of the data signal line due to the polarity inversion of the data signal is large, the change speed of the data signal line in the polarity inversion becomes low. Therefore, the scanning signal line is changed by the voltage change of the data signal line in the polarity inversion. Noise generated in the Therefore, the malfunction of the scanning signal line due to the noise is prevented, and the display failure due to the malfunction is suppressed.

It is a block diagram which shows the structure of the liquid crystal display device which concerns on 1st Embodiment. It is a block diagram for demonstrating the structure of the gradation voltage slope circuit in the said 1st Embodiment. FIG. 7 is a signal waveform diagram for describing the operation of the slope addition circuit included in the gradation voltage slope circuit in the first embodiment. FIG. 5 is a signal waveform diagram showing an operation of the liquid crystal display device according to the first embodiment. It is a block diagram for demonstrating the structure of the gradation voltage slope circuit in the liquid crystal display device which concerns on 2nd Embodiment. It is a signal waveform diagram which shows operation | movement of the liquid crystal display device which concerns on the said 2nd Embodiment. It is a block diagram which shows the structure of the liquid crystal display device which concerns on 3rd Embodiment. It is a block diagram which shows the structure of the liquid crystal display device which concerns on a prior art example. It is a figure which shows the example of a display in the said prior art example with the polarity pattern of applied voltage. It is a signal waveform diagram for demonstrating the problem in the said prior art example.

<0. Basic study>
As described above, in the liquid crystal display device, since the inversion driving method is adopted, depending on the image to be displayed, the noise in the display panel may cause the gate driver to malfunction and cause a display defect. The inventor examined the cause of this problem and the mechanism of occurrence of the malfunction. In the following, the contents and results of this examination will be described before describing each embodiment.

FIG. 8 is a block diagram showing a configuration example (hereinafter referred to as “conventional example”) of a typical active matrix liquid crystal display device. The liquid crystal display device shown in FIG. 8 includes a liquid crystal panel as a display unit 100, a source driver 300 as a data signal line drive circuit, a gate driver 400 as a scanning signal line drive circuit, a display control circuit 200, and a power supply circuit. And 600. Moreover, in order to display an image in the liquid crystal panel as the display part 100, the back light for irradiating light in the back is required, and this liquid crystal display device is equipped also with such a back light (not shown). There is. The back lights and their drive circuits are well known in their own construction and related constructions and will not be described because they are not directly related to the features of the respective embodiments described later.

In the display unit 100, source lines SL1 to SLM as a plurality of (M) data signal lines and gate lines GL1 to GLN as a plurality of (N) scanning signal lines intersecting the plurality of source lines SL1 to SLM. Are provided, and a plurality of (M × N) pixel formation portions 10 arranged in a matrix along the plurality of source lines SL1 to SLM and the plurality of gate lines GL1 to GLN are provided. There is.

Each pixel formation portion 10 corresponds to any one of the plurality of source lines SL1 to SLM and corresponds to one to any of the plurality of gate lines GL1 to GLN. As shown in FIG. 8, in each pixel formation portion 10, switching is performed in which the source terminal as one conduction terminal is connected to the corresponding source line SLj and the gate terminal as the control terminal is connected to the corresponding gate line GLi. A thin film transistor (TFT) 12 as an element and (i = 1 to N, j = 1 to M), a pixel electrode Ep connected to a drain terminal as the other conduction terminal of the TFT 12, and the plurality (M × N) Liquid crystal layer provided in common to the pixel formation portion 10) and the plurality of (M.times.N) pixel formation portions 10 in common, and disposed so as to face the pixel electrode Ep with the liquid crystal layer interposed therebetween. And a common electrode Ec. A liquid crystal as a pixel capacitance Cp for holding a voltage corresponding to pixel data indicating a gradation value of a pixel by the pixel electrode Ep, the common electrode Ec, and the liquid crystal layer sandwiched therebetween in each pixel formation portion 10 A capacity Clc is formed. As shown in FIG. 8, normally, in order to reliably hold the voltage in the liquid crystal capacitance Clc, an auxiliary capacitance electrode is disposed on the substrate on which the TFT 12 is formed in the display unit 100, and the storage capacitance Cs is parallel to the liquid crystal capacitance Clc. Is formed. In this case, a pixel capacitance Cp for holding a voltage corresponding to pixel data is constituted by a liquid crystal capacitance Clc and a storage capacitance Cs.

In the pixel formation portion 10 of the above configuration, as shown in FIG. 8, a parasitic capacitance (hereinafter referred to as “gate-source parasitic capacitance”) Cgs exists between the gate terminal and the source terminal of the TFT 12. A parasitic capacitance also exists between the source line SLj and the gate line GLi, and in the following, this parasitic capacitance is also included in the gate-source parasitic capacitance Cgs. As described later, when the voltage of the data signal Sj applied to the source line SLj changes significantly, the change causes noise in the gate line GLi via the parasitic capacitance Cgs.

The display control circuit 200 is realized, for example, as a single IC (Integrated Circuit) called a control IC. The display control circuit 200 receives an input signal Din including image data representing an image to be displayed and timing control information from the outside of the liquid crystal display device, and based on the input signal Din, the digital image signal DA and the data side control signal SCT. And the scan side control signal GCT. The digital image signal DA and the data side control signal SCT are input to the source driver 300, and the scan side control signal GCT is input to the gate driver 400. Data-side control signal SCT includes data-side start pulse signal SSP, data-side clock signal SCK, latch strobe signal LS, and polarity control signal Cpn, and scan-side control signal GCT includes scan-side start pulse signal GSP and the scan side. Clock signal GCK is included.

As shown in FIG. 8, the source driver 300 includes a data signal conversion circuit 310, a DA conversion circuit 320, and an output buffer circuit 330. Among the data-side control signals SCT from the display control circuit 200, the data-side start pulse signal SSP, the data-side clock signal SCK, and the latch strobe signal LS are input to the data signal conversion circuit 310. Data signal conversion circuit 310 includes a shift register and a sampling latch circuit operated by data side clock signal SCK, etc., and start pulses included in data side start pulse signal SSP are sequentially selected by the shift register according to data side clock signal SCK. Transfer, sequentially sampling the digital image signal DS according to the transfer, and sequentially holding the digital image signal DS one line at a time by the pulse (latch pulse) of the latch strobe signal LS generated each time one line is sampled And output as internal image signals D1 to DN. The DA conversion circuit 320 converts the internal image signals D1 to DN, which are image signals for one line, into analog image signals A1 to A based on positive and negative gradation voltages VPk and VNk (k = 1 to n) described later. Convert to AN. The output buffer circuit 330 includes a plurality of buffers respectively connected to the source lines SL1 to SLn, and data in which the analog image signals A1 to AN are inverted in polarity every predetermined time via the plurality of buffers. It outputs as the signals S1 to SN. The plurality of buffers function as voltage followers. The data signals S1 to SN output from the output buffer circuit 330 are respectively applied to the source lines SL1 to SLN as driving image signals.

The gate driver 400 includes a shift register operated by the scanning clock signal GCK from the display control circuit 200. In this shift register, the start pulse included in the scanning start pulse signal GSP from the display control circuit 200 is scanned The data is sequentially transferred according to the side clock signal GCK. The gate driver 400 generates scanning signals G1 to GN sequentially becoming active (high level) according to the transfer, and applies these scanning signals G1 to GN to the gate lines GL1 to GL1N in the display unit 100, respectively. Thus, the gate lines GL1 to GLN are sequentially selected in each frame period.

The power supply circuit 600 is a power supply voltage required for each part of the present liquid crystal display device, that is, a logic power supply voltage VpwL supplied to digital circuits included in the source driver 300 and the gate driver 400, and an analog circuit included in the source driver 300. Data-side drive voltage VpwS supplied to the scan side, scan-side drive voltage VpwG supplied to the analog circuit included in the gate driver 400, and positive and negative polarity gradation voltages supplied to the DA conversion circuit 320 included in the source driver 300. VPk and VNk (k = 1 to n) and a common voltage Vcom are generated. The common voltage Vcom is supplied to the common electrode Ec and the auxiliary electrode Es in the display unit 100. Instead, a voltage for the auxiliary electrode different from the common voltage Vcom is generated and supplied to the auxiliary electrode Es. It is also good. In the following, it is assumed that the absolute values of the positive polarity and negative polarity gradation voltages VPk and VNk are larger as the subscript k is smaller. Therefore, in the case of the normally black system, the positive polarity and negative polarity gradation voltages VP1 and VN1 correspond to the maximum luminance gradation (white display).

A planar light source (not shown) is provided as a backlight on the rear surface of the liquid crystal panel as the display unit 100, and light is emitted from the backlight to the rear surface of the liquid crystal panel. Although the liquid crystal panel in the present embodiment is a transmissive type, when the liquid crystal panel is a reflective type, it is not necessary to provide a backlight unit.

As described above, in the liquid crystal panel as the display unit 100, the data signals S1 to SM generated based on the external input signal Din are applied to the source lines SL1 to SLM under the control of the display control circuit 200, In synchronization with this, scanning signals G1 to GN generated based on an external input signal Din (timing control information included therein) are applied to the gate lines GL1 to GLN, respectively. By driving display unit 100 (source lines SL1 to SLM and gate lines GL1 to GLN) in this manner, the pixel capacitance Cp of pixel formation unit 10 corresponding to the voltage indicating each pixel data of the image to be displayed. And the voltage held in each pixel capacitance Cp is rewritten every one frame period. Thereby, the liquid crystal panel as the display unit 100 changes the light transmittance by applying a voltage according to the image signal DA to the liquid crystal layer, and displays the image represented by the image signal DA.

In the liquid crystal display device shown in FIG. 8, the source driver 300 and the gate driver 400 that constitute the drive circuit of the display unit 100 are components separate from the display unit 100, but instead of this, At least a part of the source driver 300 and the gate driver 400 may be formed integrally with the pixel circuit (simultaneously in the same process) on the substrate of the liquid crystal panel as the display portion 100 using the TFT. This point is the same in each embodiment described later.

In the liquid crystal display device according to the conventional example as described above, it is assumed that a normally black liquid crystal panel is used as the display unit 100, and the 2H dot inversion driving method is adopted, as shown in FIG. A case will be considered in which an image in which small areas and black small areas are alternately arranged (hereinafter referred to as "evaluation image") is displayed. Here, in the “2H dot inversion driving method”, the voltage applied to the liquid crystal in the same frame is inverted every one pixel formation portion in the extending direction of the gate line GLj, and two pixels are formed in the extending direction of the source line SLi. Invert drive method to invert every part. In FIG. 9, each small rectangle indicates a pixel, and “(+)” added below “black” or “white” in the small rectangle is a positive electrode for the liquid crystal portion corresponding to the pixel indicated by the small rectangle. Negative voltage is applied to the liquid crystal portion corresponding to the pixel indicated by the small rectangle when “(−)” is attached under black or “white”. It is shown that a voltage is applied, and the polarity of the voltage here is based on the voltage of the common electrode Ec, that is, the common voltage Vcom.

FIG. 10 is an internal view for generating the polarity control signal Cpn, the data signal S1 of the first column, and the scanning signal G2 of the second row by the gate driver 400 when displaying the evaluation image shown in FIG. It is a signal waveform diagram which shows control signal Gct2 (For example, the signal corresponded to the start pulse signal GSP or clock signal GCK etc. by the side of scanning), and the scanning signals G2 and G3. Here, “row” refers to a series of pixels or pixel forming portions 10 in the extending direction of the gate line GLi, and “column” refers to a series of pixels or pixel forming portions 10 in the extending direction of the source line SLj. I say something.

In the above-described conventional example, a normally black liquid crystal panel is used as the display unit 100. Therefore, when the voltage applied to the liquid crystal (absolute value) is minimum, black is displayed (minimum luminance display) and application to the liquid crystal is performed. When the voltage (absolute value) is maximum, white display (maximum luminance display) is performed. Therefore, when the polarity of the data signal Sj indicating white display is inverted, the voltage change of the source line SLj to which the data signal Sj is applied becomes maximum. That is, as can be seen from FIG. 10, when the evaluation image of FIG. 9 is displayed in the above-described conventional example, for example, the fourth horizontal period from the third horizontal period to the fourth horizontal period, which is the third row scanning period. At the switching time ta to the horizontal period, changes in the data signals S1, S3,... In the odd columns, ie, voltage changes in the source lines SL1, SL3,. Is generically referred to as "Sod", and the source lines in odd columns are generically referred to as "SLod". A large voltage change of the source line SLod in polarity inversion at this time ta affects the voltage of each gate line GLi (i = 1 to N) through the gate-source parasitic capacitance Cgs in each pixel formation portion 10 in the odd column This may be transmitted to the gate driver 400 as noise to cause the gate driver 400 to malfunction. As shown in FIG. 10, for example, noise is generated in the internal control signal Gct2 for generating the scanning signal G2 in the second row, and this noise causes a pulse not originally present (circled by a dotted circle in FIG. 10). A pulse may appear in the scanning signal G2 etc. in the second row. Further, when the evaluation image of FIG. 9 is displayed, the data of the even-numbered columns is switched from the first horizontal period which is the scanning period of the first row to the second horizontal period which is the scanning period of the second row. The voltage change of the signals S2, S4,..., That is, the voltage change of the even source lines SL2, SL4,. The large voltage change of the source lines SL2, SL4, ... at this time also affects the voltage of each gate line GLi (i = 1 to N) through the gate-source parasitic capacitance Cgs in each pixel formation portion 10 in the even-numbered column This is transmitted to the gate driver 400 as noise.

When the gate driver 400 malfunctions due to the noise as described above, the scanning signal Gi becomes active (at the high level in the conventional example and each embodiment described later) at an incorrect timing, and a display defect occurs.

<1. First embodiment>
As can be seen from the above basic study, the cause of the malfunction of the gate driver 400 that causes a display defect is the voltage of the data signal Sj, for example, from the negative polarity gradation voltage VN1 corresponding to the maximum gradation (white display). As the voltage of the source line SLj sharply and largely changes as when changing to the positive polarity gradation voltage VP1 corresponding to the key adjustment (white display) (see the change of the data signal Sod at the time ta shown in FIG. 10) Noise is generated in the gate line GLi via the capacitance Cgs. Therefore, in order to prevent the generation of such noise, an inversion time point (hereinafter referred to as “maximum change inversion time point”) at which the voltage change amount (absolute value) before and after the polarity inversion time point of data signal Sj becomes maximum. In the example shown in FIG. 10, it is conceivable to moderate the voltage change of the data signal Sj immediately before and immediately after (corresponding to the time point ta) (reduce the change speed of the data signal Sj). This corresponds to adding a slope to the waveform of the data signal Sj immediately before and after the maximum change inversion point.

Based on such a concept, in the first embodiment, in order to reduce the change speed immediately before and after the maximum change inversion time point of the data signal Sj, the gray scale voltages VPk, VNk (k = Among 1 to n), positive and negative gradation voltages having the maximum absolute value (in the above-mentioned conventional example, positive and negative gradation voltages corresponding to white display) VX1 (X = P, N) are data signals A waveform that changes from the gradation voltage VX1 to the common voltage Vcom as the center voltage of the data signal Sj immediately before each time when the polarity of Sj is reversed and returns to the gradation voltage VX1 immediately after the time Voltage VsX1 (see FIG. 3 described later). As the central voltage here, a central voltage of the range in which the data signal Sj changes may be used instead of the common voltage Vcom. The details of the liquid crystal display device according to the first embodiment will be described below.

<1.1 Configuration and operation>
FIG. 1 is a block diagram showing the configuration of the liquid crystal display device according to the present embodiment. The liquid crystal display device according to this embodiment is a normally black type active matrix liquid crystal display device as in the conventional example shown in FIG. 8, and includes a liquid crystal panel as the display unit 100 and a data signal line drive circuit. A source driver 300, a gate driver 400 as a scanning signal line drive circuit, a display control circuit 200, and a power supply circuit 600 are provided. In addition to this, in the liquid crystal display device according to the present embodiment, the positive polarity and the negative polarity gradation voltage having the maximum absolute value (hereinafter referred to as “positive polarity and negative polarity maximum gradation voltage” or simply “maximum gradation voltage”) A gradation voltage slope circuit 620 which performs the above conversion processing on VP1 and VN1 is provided. The configuration other than the gradation voltage slope circuit 620 in this embodiment is the same as that of the conventional example shown in FIG. 8, and therefore, the same or corresponding parts will be denoted by the same reference symbols and detailed description thereof will be omitted (FIG. And Figure 8). The following description will focus on the configuration and operation associated with the grayscale voltage slope circuit 620.

As shown in FIG. 1, among the power supply voltages output from the power supply circuit 600, the logic power supply voltage VpwL is supplied to the digital circuit in the source driver 300 and the gate driver 400 and the data side drive voltage VpwS is The scan side drive voltage VpwG is supplied to the analog circuit in the source driver 300 and is supplied to the analog circuit in the gate driver 400. However, in the present embodiment, the gradation voltages VPk and VNk (k = 1 to n) output from the power supply circuit 600 are not directly input to the DA conversion circuit 320 in the source driver 300, and are shown in FIG. As described above, the D / A conversion circuit 320 is input as the D / A conversion gradation voltages VsPk and VsNk (k = 1 to n) through the gradation voltage slope circuit 620 as the gradation voltage conversion circuit.

FIG. 2 is a block diagram showing the configuration of the gradation voltage slope circuit 620 in the present embodiment. The gradation voltage slope circuit 620 includes a slope addition circuit 622 that converts the gradation voltages VPk and VNk (1 ≦ k ≦ n) into gradation slope voltages VsPk and VsNk described later. In this embodiment, among the gradation voltages VPk and VNk (k = 1 to n) from the power supply circuit 600, a maximum gradation voltage (a positive polarity and a negative polarity gradation voltage having a maximum absolute value) is added to the slope addition circuit 622. ) VP1 and VN1 are input, and a polarity control signal Cpn from the display control circuit 200 is input. The polarity control signal Cpn is a signal indicating the polarity of each data signal Sj, and the output buffer circuit 330 in the source driver 300 outputs the positive polarity data signal Sj when the polarity control signal Cpn is, for example, high level (H level). It outputs a negative data signal Sj when it is at low level (L level). Here, the polarity of the data signal Sj is a voltage polarity based on the common voltage Vcom, and corresponds to the polarity of the voltage applied to the liquid crystal in the display unit 100 based on the data signal Sj.

FIG. 3 is a signal waveform diagram for explaining the operation of the slope addition circuit 622. The slope addition circuit 622 immediately before the polarity inversion time point (time tr1, tr2, tr3 shown in FIG. 3) of the input gradation voltages VPk, VNk (1 ≦ k ≦ n) based on the polarity control signal Cpn. It is a circuit for converting into a voltage with a sloped waveform (hereinafter referred to as “gradation slope voltage”) immediately after that. However, as shown in FIG. 2 and FIG. 3, the slope addition circuit 622 in this embodiment converts only the maximum gray scale voltages VP1 and VN1 into the gray scale slope voltage and outputs them as the maximum DA conversion gray scale voltages VsP1 and VsN1. . As shown in FIG. 3, the positive polarity maximum DA conversion gradation voltage VsP1 is generated from the positive polarity maximum gradation voltage VP1 immediately before the polarity inversion time point trk (k = 1, 2, 3) of each data signal Sj. The voltage decreases toward the common voltage Vcom at a predetermined change rate, and increases at a predetermined change rate immediately after the inversion time point trk to return to the positive polarity maximum gradation voltage VP1. In addition, the negative polarity maximum DA conversion gradation voltage VsN1 increases at a predetermined rate of change from the negative maximum gradation voltage VN1 toward the common voltage Vcom immediately before the inversion time trk of the polarity of each data signal Sj. Immediately after the inversion time point trk, the waveform decreases at a predetermined change rate and returns to the negative maximum gradation voltage VN1. Each change speed here corresponds to the change speed immediately before and after the maximum change inversion point of data signal Sj, and is set to a value sufficiently smaller than the change speed at the maximum change inversion of data signal Sj in the conventional example. Be done. That is, each change rate is set to a value smaller than at least the change rate corresponding to the slew rate of the plurality of buffers described in output buffer circuit 330, and more specifically, the source line at the polarity reversal at the maximum change reversal point. An appropriate value of each change rate is determined based on computer simulation, experiments, etc. so that the noise generated in the gate line GLi due to the voltage change of SLj is sufficiently reduced. Here, the “slew rate” corresponds to the amount of change (absolute value) per unit time of the corresponding output voltage (the voltage of the data signal) when a stepped voltage is input to output buffer circuit 330. .

Of the gray scale voltages VPk and VNk (k = 1 to n) output from the power supply circuit 600, the gray scale voltages VPk and VNk (k = 2 to n) other than the maximum gray scale voltages VP1 and VN1 are gray scale voltage slopes. The signal is input to the circuit 620 but is output from the gray scale voltage slope circuit 620 as the gray scale voltages for DA conversion VsPk, VsNk (k = 2 to n) without being converted into the gray scale slope voltage.

The gradation voltages for DA conversion VsPk and VsNk (k = 1 to n) outputted from the gradation voltage slope circuit 620 as described above are inputted to the DA conversion circuit 320 in the source driver 300. In the source driver 300 according to the present embodiment, the DA conversion circuit 320 converts the internal image signals D1 to DN, which are digital image signals sequentially output from the data signal conversion circuit 310, line by line, into positive and negative polarities. The analog image signals A1 to AN are converted based on the gray scale voltages VPk and VNk (k = 1 to n). More specifically, when the DA conversion circuit 320 is to output the positive polarity data signal Sj based on the polarity control signal Cpn, n positive polarity DA conversions are performed according to the digital value indicated by the corresponding internal image signal Dj. One DA conversion gradation voltage VsPa is selected from the gradation voltages VsPk (k = 1 to n) and output as the analog image signal Aj, and the data signal Sj of negative polarity should be output based on the polarity control signal Cpn. In this case, one DA conversion grayscale voltage VsNa is selected from n negative polarity DA conversion grayscale voltages VsNk (k = 1 to n) in accordance with the digital value indicated by the corresponding internal image signal Dj. It outputs as an analog image signal Aj.

Based on the polarity control signal Cpn, the output buffer circuit 330 outputs each such analog image signal Aj as a data signal Sj via a voltage follower as a positive polarity buffer, if it is positive polarity, When the signal has a negative polarity, it is output as a data signal Sj via a voltage follower as a negative polarity buffer. These data signals S1 to SM are applied to source lines SL1 to SLM in the display unit 100, respectively. Note that, instead of the positive and negative polarity buffers, a bipolar buffer may be used which functions as a voltage follower regardless of whether the analog image signal Aj is positive or negative.

On the other hand, the gate driver 400 generates scanning signals G1 to GN similar to the above-described conventional example based on timing control information included in an external input signal Din and applies them to the gate lines GL1 to GLN in the display unit 100. Also in the present embodiment, by driving the display unit 100 (the source lines SL1 to SLM and the gate lines GL1 to GLN) in this manner, the pixel formation corresponding to the voltage indicating each pixel data of the image to be displayed is formed. The voltage applied to and held by the pixel capacitance Cp of the unit 10 and the voltage held by each pixel capacitance Cp is rewritten every one frame period. Thereby, the liquid crystal panel as the display unit 100 changes the transmittance of light from a backlight (not shown) by applying a voltage according to the image signal DA to the liquid crystal layer, thereby representing the image signal DA. Display an image.

<1.2 Action and effect>
As understood from the above, the voltage waveform of each source line SLj in the display unit 100 corresponds to the waveform of the DA conversion gradation voltage VsPa or VsNa corresponding to the data signal Sj applied thereto. Hereinafter, the operation and effects of the present embodiment will be described on the premise of this.

FIG. 4 is a signal waveform diagram showing the operation of the liquid crystal display device according to the present embodiment. As described above, in the present embodiment, the DA conversion gradation voltages VsPk and VsNk (k = 1 to n) used to generate the data signal Sj (j = 1 to M) in the source driver 300. As shown in FIG. 4, the maximum DA conversion gradation voltages VsP1 and VsN1 corresponding to white display are generated as waveforms to which a slope is added at the time of polarity inversion of each data signal Sj. On the other hand, the other DA conversion gradation voltages VsPk and VsNk (k = 2 to n) including the DA conversion gradation voltages VsPn and VsNn which have the smallest absolute value corresponding to black display are fixed voltages to which no inclination is applied. is there.

In the present embodiment, when the evaluation image shown in FIG. 9 is displayed, the voltage of the data signal Sod of the odd-numbered column such as the data signal S1 (voltage of the source line SLod of the odd-numbered column) is as shown in FIG. In the first to sixth display periods (first to sixth horizontal periods), VsPn, VsNn, VsN1, VsP1, VsPn, and VsNn, respectively. In this case, the voltage change of the odd-numbered source line SLod becomes maximum immediately before and after the polarity inversion time point tr2 when switching from the third horizontal period to the fourth horizontal period. Since changes in the voltages of the odd-numbered source lines SLod immediately before and after the maximum change inversion point correspond to the waveforms of the maximum DA conversion gradation voltages VsP1 and VsN1 (within the ellipse of the dotted line shown in FIG. 4). (Refer to the above), the rate of change of the voltage is at least smaller than the rate of change corresponding to the slew rate of each buffer in the output buffer circuit 330, and the change of the voltage of the source line SLj at the reversal of polarity at the maximum change reversal point Small enough compared to the speed (see Figures 4 and 10). Therefore, noise caused by the voltage change of the odd-numbered source line SLod at the maximum change inversion time tr2 affecting the gate line GLj through the gate-source parasitic capacitance Cgs in the pixel formation portion 10 is higher than that in the prior art. Therefore, the occurrence of a malfunction in the gate driver 400 due to the noise is suppressed (see the waveform of the internal control signal Gct2 shown in FIG. 4).

As described above, according to the present embodiment, by reducing the rate of change of the voltage of the source line SLj at the polarity inversion at the maximum change inversion point, the noise generated in the gate line GLi is reduced. It is possible to suppress display defects caused by the malfunction of

<2. Second embodiment>
In the first embodiment, a slope is added to the DA conversion gradation voltages VsPk and VsNk used in the source driver 300 in order to reduce the rate of change of the voltage of the source line SLj in polarity inversion at the maximum change inversion time point. Although the gradation voltages VPk and VNk (k = 1 to n) output from the power supply circuit 600 are added (refer to FIGS. 1 and 4), the gradient is added at the maximum gradation voltage (absolute value Is the maximum positive polarity and negative polarity gradation voltage) VP1 and VN1 only (see FIG. 2 and FIG. 3). However, all gradation voltages VPk and VNk (k = 1 to n) output from the power supply circuit 600 or absolute values of these gradation voltages VPk and VNk (k = 1 to n) are predetermined reference values. The gradation voltages VsPk, VsNk for DA conversion may be generated by adding a slope to the gradation voltages VPk, VNk (k = 1 to k1, 1 <k1 <n) larger than the above. For example, the gradation voltages VsPk, VsNk for DA conversion are generated by adding a slope to the gradation voltage VP2, VN2 having the second largest absolute value in addition to the gradation voltage VP1, VN1 having the largest absolute value. It is also good. Hereinafter, a liquid crystal display device having such a configuration will be described as a second embodiment.

The configuration of the liquid crystal display device according to this embodiment is the same as that of the first embodiment except for the configuration of the gradation voltage slope circuit 620 (see FIG. 1). Therefore, in the configuration in the present embodiment, the same or corresponding parts as in the configuration in the first embodiment are given the same reference numerals, and the detailed description is omitted. The following description will focus on the configuration and operation associated with the grayscale voltage slope circuit 620.

FIG. 5 is a block diagram showing the configuration of the gradation voltage slope circuit 620 in the present embodiment. The polarity control signal Cpn is input to the slope addition circuit 622 included in the gradation voltage slope circuit 620, and the absolute value of the gradation voltages VPk and VNk (k = 1 to n) from the power supply circuit 600 is In addition to the maximum positive polarity and negative polarity gradation voltage (maximum gradation voltage) VP1 and VN1, positive and negative polarity gradation voltage (hereinafter referred to as "quasi-maximum gradation voltage") VP2 having the second largest absolute value , VN2 are also input. The polarity control signal Cpn is a signal having the same function as the polarity control signal Cpn in the first embodiment.

FIG. 6 is a signal waveform diagram showing the operation of the liquid crystal display device according to the present embodiment. As shown in FIGS. 5 and 6, the slope addition circuit 622 in the present embodiment is based on the polarity control signal Cpn and, like the first embodiment, is the maximum floor immediately before and after the polarity inversion time point of the data signal Sj. In addition to the generation of the gradation throat voltage of the waveform in which the tuning voltages VP1 and VN1 are inclined as the maximum DA conversion gradation voltages VsP1 and VsN1, the quasi-maximum floor immediately before and after the polarity inversion time point of the data signal Sj. The gradation throat voltages of the waveforms in which the tuning voltages VP2 and VN2 are inclined are generated as the quasi-maximum DA conversion gradation voltages VsP2 and VsN2. The grayscale voltage VsP2 for positive polarity quasi-maximum D / A conversion decreases at a predetermined rate of change from the quasi-maximum gradation voltage VP2 to the common voltage Vcom immediately before the time of reversal of the polarity of each data signal Sj. Immediately after this, the waveform rises at a predetermined change rate and returns to the quasi-maximum gradation voltage VP2. In addition, the grayscale voltage VsN2 for negative maximum quasi-maximum DA conversion rises at a predetermined rate of change from the quasi-maximum grayscale voltage VN2 to the common voltage Vcom immediately before the time of inversion of the polarity of each data signal Sj. Immediately after the inversion time point, the waveform decreases at a predetermined change rate and returns to the quasi-maximum gradation voltage VN2. Each change rate here is also set to a value sufficiently smaller than the change rate at the time of the inversion of the data signal Sj in the conventional example. That is, each change rate is set to a value smaller than at least a change rate corresponding to the slew rate of the plurality of buffers described in output buffer circuit 330, and more specifically, source line SLj at the polarity inversion at the time of inversion. The appropriate value of each change rate is determined based on computer simulation, experiments, etc. so that the noise generated in the gate line GLi is sufficiently reduced by the voltage change of.

Among the gradation voltages VPk and VNk (k = 1 to n) outputted from the power supply circuit 600, the gradation voltages VPk and VNk other than the maximum gradation voltages VP1 and VN1 and the quasi-maximum gradation voltages VP2 and VN2 To n) are input to the gray scale voltage slope circuit 620, but are not converted into the gray scale slope voltage, and the gray scale voltage slope is directly used as the gray scale voltages VsPk, VsNk (k = 3 to n) for DA conversion. It is output from the circuit 620.

The gradation voltages for D / A conversion VsPk, VsNk (k = 1 to n) outputted from the gradation voltage slope circuit 620 as described above are inputted to the D / A conversion circuit 320 in the source driver 300, and these D / A conversion circuits Similar to the first embodiment, data signals S1 to SM are generated in the source driver 300 using the gradation voltages VsPk and VsNk (k = 1 to n).

These data signals S1 to SM are applied to source lines SL1 to SLM in the display unit 100, respectively. When the data signal Sj to be applied has a positive polarity, the voltage waveform of the source line SLj (j = 1 to M) has a positive polarity gradation for DA conversion according to the digital value indicated by the corresponding internal image signal Dj. This corresponds to one DA conversion gradation voltage VsPa selected from the voltages VsPk (k = 1 to n), and when the data signal Sj to be applied is negative, the corresponding internal image signal Dj indicates This corresponds to one DA conversion gradation voltage VsNa selected from the negative polarity gradation conversion voltage VsNk (k = 1 to n) according to the digital value.

In the present embodiment as described above, an image obtained by correcting the evaluation image shown in FIG. 9 to have the second highest luminance gradation on the fifth and sixth lines (referred to as “corrected evaluation image” Consider the case of displaying). In this case, the voltage (voltage of the source line SLod of the odd-numbered column) of the data signal Sod of the odd-numbered column such as the data signal S1 is the display period of the first to sixth rows (first In the period from the sixth horizontal period) to VsPn, VsNn, VsN1, VsP1, VsP2, and VsN2, respectively. In this case, the voltage change of the odd-numbered source line SLod becomes maximum immediately before and after the polarity inversion time tr2 when switching from the third horizontal period to the fourth horizontal period, and the fifth horizontal period switches to the sixth horizontal period The voltage change of the odd-numbered source line SLod becomes the second largest immediately before and after the time polarity inversion time point tr3. Here, the voltage changes of the odd-numbered source lines SLod immediately before and after the polarity inversion time point tr2 correspond to the waveforms of the maximum DA conversion gradation voltages VsP1 and VsN1, and immediately before and immediately after the polarity inversion time point tr3. The voltage change of the odd-numbered source line SLod corresponds to the waveform of the gradation voltages VsP2 and VsN2 for quasi-maximum D / A conversion (refer to two ovals shown by dotted lines in FIG. 4). Therefore, the rate of change of the voltage of the odd-numbered source line SLod immediately before and after these polarity inversion time points tr2 and tr3 is higher than that of the data signal Sj at the polarity inversion time of the polarity inversion time points tr2 and tr3 in the conventional example. Is sufficiently small, at least less than the rate of change corresponding to the slew rate of each buffer in the output buffer circuit 330. Therefore, not only the noise caused by the voltage change of the odd-numbered source line SLod in the polarity inversion of the maximum change inversion time tr2 affecting the gate line GLj through the gate-source parasitic capacitance Cgs, but also the inversion time tr3. Noise caused by the second largest voltage change of the odd-numbered source line SLod in the polarity inversion of the gate line GLj via the gate-source parasitic capacitance Cgs is also significantly reduced compared to the prior art (Refer to the waveform of the internal control signal Gct2 shown in FIG. 6). As a result, compared to the first embodiment, the occurrence of a malfunction in the gate driver 400 due to the noise caused by the inversion drive can be more reliably suppressed.

As described above, according to the present embodiment, in addition to the change speed of the voltage of the source line SLj in the polarity inversion where the voltage change is maximum, the change speed of the voltage of the source line SLj in the second largest polarity change also decreases. By doing this, the noise generated in the gate line GLi is further reduced, so that display defects caused by a malfunction in the gate driver 400 due to the noise caused by the inversion driving can be suppressed more reliably.

<3. Third embodiment>
In the first and second embodiments, the gradation voltages VPk and VNk (k = 1 to n) output from the power supply circuit 600 are converted to the gradation voltages VsPk and VsNk (k = 1 to n) for DA conversion. The gradation voltage slope circuit 620 is provided as a component separate from the source driver 300 and the like, but the configuration in which the gradation voltage slope circuit 620 is included in the source driver 300, for example, an IC (for realizing the source driver 300) The configuration may be built in an integrated circuit. Hereinafter, a liquid crystal display device having such a configuration will be described as a third embodiment.

FIG. 7 is a block diagram showing the configuration of the liquid crystal display device according to the present embodiment. The liquid crystal display device according to the present embodiment includes the gray scale voltage slope circuit 620 in the source driver 300, and in this respect, the first and the third embodiments have the gray scale voltage slope circuit 620 provided outside the source driver 300. This differs from the liquid crystal display (FIG. 1) according to the second embodiment. The other configuration in this embodiment is the same as that of the first or second embodiment. Therefore, in the configuration in the present embodiment, the same or corresponding parts as those in the configuration in the first and second embodiments are given the same reference numerals, and detailed description will be omitted. The configuration of the gradation voltage slope circuit 620 included in the source driver 300 in this embodiment may be any configuration of the gradation voltage slope circuit 620 in the first and second embodiments (FIG. 2). , See Figure 5).

According to the present embodiment, as in the first and second embodiments, when the amount of change in voltage in polarity inversion of the source line SLj is larger than a predetermined amount, the rate of change in the voltage is reduced. As a result, noise generated in the gate line GLi is reduced, so that display defects caused by a malfunction in the gate driver 400 due to noise caused by inversion driving can be suppressed.

<4. Modified example>
The present invention is not limited to the above first to third embodiments, and various modifications can be made without departing from the spirit of the present invention. The first to third embodiments and the modifications described later can be implemented in any combination without departing from the spirit of the present invention and causing no contradiction.

The first to third embodiments have been described by taking a normally black liquid crystal display device as an example, but the present invention can also be applied to a normally white liquid crystal display device. That is, even in the normally white liquid crystal display device, when the voltage change in the polarity inversion of the voltage of the source line is larger than a predetermined amount, the change in the voltage is reduced so that the noise generated in the gate line due to the voltage change is reduced. By providing the configuration for reducing the speed, the same effects as those of the first to third embodiments can be obtained.

In the first to third embodiments, the 2H dot inversion drive method is adopted, but another dot inversion drive method or a line inversion drive method is adopted. Also, the application of the present invention is possible.

In the first to third embodiments, when the amount of change in voltage in polarity inversion of the source line is larger than a predetermined amount, the gradation voltage VPk, VNk (k The gradation addition circuit 622 adds an inclination to the gradation voltages VPk and VNk (k = 1 to k1, 1 ≦ k1 ≦ n) whose absolute value is larger than a predetermined value among Slope voltages VsPk and VsNk are generated (FIGS. 2 to 6). However, the configuration for reducing the rate of change in voltage when the amount of change in voltage in polarity inversion of the source line is larger than a predetermined amount is not limited to this. For example, instead of or in addition to this, in output buffer circuit 330 in source driver 300, when the change in data signal Sj is larger than a predetermined amount, the noise generated in the gate line due to the change is reduced. A configuration may be provided to adjust the slew rate of the buffer that outputs the signal Sj.

<5. Other>
The present application is an application for claiming priority based on Japanese Patent Application No. 2017-128875 entitled "Liquid Crystal Display Device and Method of Driving the Same" filed on June 30, 2017, the contents of which is incorporated herein by reference. Is included in the present application by reference.

10 ... pixel formation portion 12 ... thin film transistor (switching element)
100 ... Display (Liquid crystal panel)
200 ... display control circuit 300 ... source driver (data signal line drive circuit)
320 ... DA conversion circuit 330 ... Output buffer circuit (multiple buffers)
400 ... gate driver (scan signal line drive circuit)
600 ... power supply circuit 620 ... gradation voltage slope circuit (gradation voltage conversion circuit)
622 ... Slope added circuit GLi ... Gate line (scanning signal line) (i = 1 to N)
SLj ... Source line (data signal line) (j = 1 to M)
Cgs: Gate-source parasitic capacitance Cpn: Polarity control signal VPk: Positive polarity gradation signal (k = 1 to n)
VNk ... Negative tone signal (k = 1 to n)
VsPk ... gradation signal for positive polarity DA conversion (k = 1 to n)
VsNk ... gradation signal for negative polarity DA conversion (k = 1 to n)
Vcom ... common voltage (center voltage)

Claims

A plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of pixel formation portions arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines A liquid crystal display device having a display portion including
A scanning signal line drive circuit for selectively driving the plurality of scanning signal lines;
The plurality of data signals are generated including a plurality of buffers to which the plurality of data signal lines are respectively connected, and a plurality of data signals whose polarity is inverted at predetermined time intervals with reference to a predetermined center voltage. And a data signal line drive circuit applied to the signal line,
In the data signal line drive circuit, when the amount of change of any data signal is larger than a predetermined amount in the polarity inversion of the plurality of data signals, the change speed of any one data signal in the polarity inversion is the plurality The liquid crystal display device, wherein the plurality of data signals are generated so as to have a predetermined low change rate smaller than a change rate corresponding to a through rate of the buffer.
A gradation voltage generation circuit that generates a plurality of positive and negative polarity gradation voltages;
Among the plurality of positive and negative polarity gradation voltages, at least one of the plurality of positive and negative polarity gradation voltages is provided inside or outside the data signal line drive circuit, and at least one of the positive and negative polarity gradation voltages is greater than a predetermined value. Immediately before the point of time of polarity inversion of the plurality of data signals, the gradation voltage changes toward the central voltage at a change rate corresponding to the low change rate, and immediately after the point of inversion Gradation voltage conversion that converts the plurality of positive and negative polarity gradation voltages into a plurality of positive and negative polarity DA conversion gradation voltages by replacing the voltage with a waveform that returns to the gradation voltage at speed. Further comprising a circuit and
The data signal line drive circuit is configured such that, for each of the plurality of data signal lines, the polarity of the data signal to be applied to the data signal line out of the plurality of positive and negative polarity gradation voltages for DA conversion is The gradation voltage for positive polarity or negative polarity DA conversion according to the image to be displayed on the display unit is selected to be inverted every predetermined time, and the selected gradation voltage for positive polarity or negative polarity DA conversion is selected. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is applied as a data signal to the data signal line.
The gradation voltage conversion circuit is configured to select one of the plurality of positive and negative gradation voltages that has the largest absolute value, the positive and negative gradation voltages, at the time when the polarity of the plurality of data signals is inverted. A waveform that immediately changes from the gradation voltage to the central voltage at a change rate corresponding to the low change rate, and immediately returns to the gradation voltage at a change rate corresponding to the low change rate immediately after the inversion time point 3. The liquid crystal display device according to claim 2, wherein the plurality of positive polarity and negative polarity gradation voltages are converted into the plurality of positive polarity and negative polarity DA conversion gradation voltages by replacing with the voltage of.
The gradation voltage conversion circuit is configured to generate a plurality of positive polarity and negative polarity gradation voltages having an absolute value larger than the predetermined value among the plurality of positive polarity and negative polarity gradation voltages generated by the gradation voltage generation circuit. Each of the plurality of data signals is changed toward the central voltage at a change rate corresponding to the low change rate immediately before the point of time when the polarity of the plurality of data signals is reversed; By replacing the plurality of positive and negative polarity gradation voltages generated by the gradation voltage generation circuit with the plurality of positive and negative polarity voltages by replacing the voltage of the waveform that returns to the gradation voltage at a change speed corresponding to The liquid crystal display device according to claim 2, wherein the liquid crystal display device is converted into a gradation voltage for negative polarity DA conversion.
The gradation voltage conversion circuit changes each of the plurality of positive polarity and negative polarity gradation voltages at a rate corresponding to the low change rate from the gradation voltage immediately before the point of time when the polarity of the plurality of data signals is inverted. By replacing the voltage of such a waveform that changes toward the central voltage and returns to the gradation voltage at a change rate corresponding to the low change rate immediately after the inversion time point. The liquid crystal display device according to claim 2, wherein the tuning voltage is converted into the plurality of gradation voltages for positive and negative polarity DA conversion.
A plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of pixel formation portions arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines A liquid crystal display device having a display portion including
A scanning signal line drive circuit for selectively driving the plurality of scanning signal lines;
The plurality of data signals are generated including a plurality of buffers to which the plurality of data signal lines are respectively connected, and a plurality of data signals whose polarity is inverted at predetermined time intervals with reference to a predetermined center voltage. And a data signal line drive circuit applied to the signal line,
In the data signal line drive circuit, when the amount of change in any data signal is larger than a predetermined amount in the polarity inversion of the plurality of data signals, the rate of change in any one of the data signals in the polarity inversion is The liquid crystal display device, wherein the plurality of data signals are generated such that a change amount in the polarity inversion is smaller than a change rate of the data signal whose amount is smaller than the predetermined amount.
A gradation voltage generation circuit that generates a plurality of positive and negative polarity gradation voltages;
Among the plurality of positive and negative polarity gradation voltages, at least one of the plurality of positive and negative polarity gradation voltages is provided inside or outside the data signal line drive circuit, and at least one of the positive and negative polarity gradation voltages is greater than a predetermined value. Immediately before the point of time of polarity inversion of the plurality of data signals, the gradation voltage changes toward the central voltage at a change rate corresponding to the low change rate, and immediately after the point of inversion Gradation voltage conversion that converts the plurality of positive and negative polarity gradation voltages into a plurality of positive and negative polarity DA conversion gradation voltages by replacing the voltage with a waveform that returns to the gradation voltage at speed. Further comprising a circuit and
The data signal line drive circuit is configured such that, for each of the plurality of data signal lines, the polarity of the data signal to be applied to the data signal line out of the plurality of positive and negative polarity gradation voltages for DA conversion is The gradation voltage for positive polarity or negative polarity DA conversion according to the image to be displayed on the display unit is selected to be inverted every predetermined time, and the selected gradation voltage for positive polarity or negative polarity DA conversion is selected. 7. The liquid crystal display device according to claim 6, wherein the liquid crystal display device is applied as the data signal to the data signal line.
A plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of pixel formation portions arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines And a driving method of a liquid crystal display device having a display portion including
A scanning signal line driving step of selectively driving the plurality of scanning signal lines;
A data signal line driving step of generating a plurality of data signals whose polarity is inverted at predetermined time intervals with reference to a predetermined center voltage, and applying the plurality of data signals to the plurality of data signal lines via a plurality of buffers; Equipped with
In the data signal line driving step, when the change amount of any data signal is larger than a predetermined amount in polarity inversion of the plurality of data signals, the change speed of any one data signal in the polarity inversion is the plurality The plurality of data signals are generated to have a predetermined low change rate smaller than the change rate corresponding to the through rate of the buffer.
A gradation voltage generation step of generating a plurality of positive polarity and negative polarity gradation voltages;
Each of at least one positive polarity and negative polarity gradation voltage of which the absolute value is larger than a predetermined value among the plurality of positive polarity and negative polarity gradation voltages is immediately before the point of time when the polarity of the plurality of data signals is reversed. The voltage changes from a gray scale voltage toward the central voltage at a change rate corresponding to the low change rate, and returns to the gray scale voltage immediately after the inversion time point and returns to the gray scale voltage at a change rate corresponding to the low change rate. And a gradation voltage conversion step of converting the plurality of positive and negative polarity gradation voltages into a plurality of positive and negative polarity DA conversion gradation voltages by replacement.
The data signal line driving step
In each of the plurality of data signal lines, the polarity of the data signal to be applied to the data signal line is inverted at predetermined time intervals among the plurality of positive polarity and negative polarity DA conversion gradation voltages. A voltage selection step of selecting a positive polarity or negative polarity DA conversion gradation voltage according to an image to be displayed on the display unit;
Applying a positive polarity or negative polarity DA conversion gradation voltage selected in the gradation voltage selection step for each of the plurality of data signal lines as a data signal to the data signal line. The driving method according to 8.
A plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, a plurality of pixel formation portions arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines And a driving method of a liquid crystal display device having a display portion including
A scanning signal line driving step of selectively driving the plurality of scanning signal lines;
A data signal line driving step of generating a plurality of data signals whose polarity is inverted at predetermined time intervals with reference to a predetermined center voltage, and applying the plurality of data signals to the plurality of data signal lines via a plurality of buffers; Equipped with
In the data signal line driving step, when the change amount of any data signal is larger than a predetermined amount in the polarity inversion of the plurality of data signals, the change speed of the data signal in the polarity inversion is The driving method, wherein the plurality of data signals are generated such that the amount of change in the polarity inversion is smaller than the rate of change of the data signal whose amount is less than the predetermined amount.
A gradation voltage generation step of generating a plurality of positive polarity and negative polarity gradation voltages;
Each of at least one positive polarity and negative polarity gradation voltage of which the absolute value is larger than a predetermined value among the plurality of positive polarity and negative polarity gradation voltages is immediately before the point of time when the polarity of the plurality of data signals is reversed. The voltage changes from a gray scale voltage toward the central voltage at a change rate corresponding to the low change rate, and returns to the gray scale voltage immediately after the inversion time point and returns to the gray scale voltage at a change rate corresponding to the low change rate. And a gradation voltage conversion step of converting the plurality of positive and negative polarity gradation voltages into a plurality of positive and negative polarity DA conversion gradation voltages by replacement.
The data signal line driving step
In each of the plurality of data signal lines, the polarity of the data signal to be applied to the data signal line is inverted at predetermined time intervals among the plurality of positive polarity and negative polarity DA conversion gradation voltages. A voltage selection step of selecting a positive polarity or negative polarity DA conversion gradation voltage according to an image to be displayed on the display unit;
Applying a positive polarity or negative polarity DA conversion gradation voltage selected in the gradation voltage selection step for each of the plurality of data signal lines as a data signal to the data signal line. The driving method according to 10.