JP2009216852A - Electrooptical device and method for driving electrooptical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrooptical device and a method for driving the electrooptical device capable of suppressing the occurrence of display irregularity near a boundary of a block when using a block sequential driving system with comparatively simple constitution. <P>SOLUTION: In the electrooptical device performing the block sequential driving system in which signal lines are sequentially driven in block units of every several lines, gamma setting of a red system (R), a green system (G) and a blue system (B), and gamma setting for correction of the red system (R) and the blue system (B) are stored, and gradation display voltage is supplied, in accordance with data obtained by correcting a gradation level of input display data by the gamma setting for correction, to a pixel corresponding to the end signal line closest to the block selected next, that is, the signal line belonging to the block selected previously out of a pair of blocks adjacent to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device that supplies display data to pixels in units of blocks and a driving method of the electro-optical device.

  In an active matrix display device, a desired display is performed on each display region arranged in a matrix using a plurality of scanning signal lines and a plurality of data signal lines. In such a display device, in order to sequentially select a plurality of scanning signal lines, and to sequentially supply video signals to the respective pixels corresponding to the selected scanning signal lines via the data signal lines, Shift register circuit technology is used.

  The shift register has a shift register circuit element such as a flip-flop having a number of stages corresponding to the number of scanning signal lines and data signal lines. However, the operating frequency of the shift register circuit element such as the flip-flop has a limit. Then, it is about several MHz. For this reason, in the case of a large number of data signal lines, a block sequential drive method is adopted in which the data signal lines are divided into a plurality of blocks and driven for each block.

However, in such a block sequential driving method, display unevenness may occur near the boundary between blocks.
One of the causes of this display unevenness is that the signal line on the boundary line is subjected to the potential fluctuation due to the parasitic capacitance between the adjacent signal lines, and an error occurs in the written data. It is done.

  Therefore, in a set of blocks having signal lines adjacent to each other, a block whose data signal application end time is earlier is BL1, a later block is BL2, and belongs to the blocks BL1 and BL2, respectively. When the lines are SL1 and SL2, respectively, there is a data transmission method in which SL2 is conducted as a pre-execution continuity prior to the end of application of the data signal as a normal continuity to BL1 in that row within one horizontal scanning period. It is known (see, for example, Patent Document 1).

  Further, by predicting the voltage change of the signal line SL2 belonging to the block BL2, correcting the image signal corresponding to the signal line SL1 adjacent to SL2 based on the prediction result, and supplying the signal to the SL1, the SL2 There is known a driving method of an electro-optical device that cancels out the noise component by correcting the image signal even when noise generated by a voltage change is mixed into the SL1 through a coupling capacitor (see, for example, Patent Document 2). . Here, the voltage change of SL2 is predicted based on the image signal corresponding to SL2 and the precharge voltage.

Further, a semiconductor device is known in which a data signal is supplied again to the signal line SL1 adjacent to the signal line SL2 at the same timing as SL2, thereby preventing a voltage change due to the coupling capacitance between SL1 and SL2 (for example, And Patent Document 3).
Japanese Patent Laid-Open No. 2001-255852 JP 2001-343923 A JP 2003-330403 A

However, in the electro-optical device described in each of the above patent documents, it is necessary to control the operation inside the panel in a complicated manner.
Therefore, the present invention provides an electro-optical device and a driving method of the electro-optical device that can suppress the occurrence of display unevenness near the block boundary when the block sequential driving method is used with a relatively simple configuration. It is an issue.

  In order to solve the above problem, an electro-optical device according to a first aspect of the present invention is provided corresponding to a plurality of scanning lines, a plurality of signal lines, and an intersection of the plurality of scanning lines and the plurality of signal lines. A plurality of pixels, a scanning line driving circuit for supplying a selection voltage to the scanning line in a predetermined order, and the signal line in one horizontal scanning period in which the selection voltage is supplied to the scanning line. A signal line driving circuit that supplies gradation display voltages corresponding to input display data to the pixels corresponding to the signal lines in units of blocks each of which is grouped into a plurality of lines. The signal line driving circuit includes a gamma setting corresponding to each display color of the pixel and a signal line belonging to a previously selected block among a set of blocks adjacent to each other, and the next selected block Tail signal line approaching A storage circuit that stores a correction gamma setting according to the display color of the corresponding pixel, a voltage selection circuit that selects a gradation display voltage according to the input display data and the gamma setting stored in the storage circuit, And the voltage selection circuit selects, as the gradation display voltage supplied to the pixel corresponding to the tail signal line, a voltage corresponding to the input display data of the tail signal line and the correction gamma setting. It is characterized by.

As a result, when the block sequential driving method is adopted, the signal line closest to the block driven later among the two adjacent blocks is set as the signal line to be corrected, and the input of the signal line to be corrected is input. Since gradation correction can be performed on the data, occurrence of display unevenness near the block boundary can be suppressed.
In addition, since the color correction gamma setting corresponding to the signal line to be corrected is newly provided, gradation correction can be performed on the input data of the signal line to be corrected without performing complicated calculation. At this time, tone correction is possible even if the pixel corresponding to the signal line to be corrected has a color filter of any color component.

According to a second aspect, in the first aspect, the voltage selection circuit corrects a gradation level of the input display data based on a gamma setting stored in the storage circuit, and the correction circuit. And a selection circuit that selects the gradation display voltage corresponding to the input display data corrected in step (1).
Thereby, the gradation level of the input display data is corrected using each gamma setting stored in the register or the like, so that gradation correction corresponding to the gamma setting of each color can be performed. In this way, improvement in image quality can be realized with a relatively simple circuit configuration.

  Further, according to a third invention, in the first or second invention, the signal line driving circuit has a bidirectional shift register capable of switching a voltage supply order to each signal line in forward and reverse directions, and the memory The circuit includes a gamma setting according to a display color of a pixel corresponding to the tail signal line when the voltage supply order is a forward direction and a voltage supply order when the voltage supply order is a reverse direction as the correction gamma setting. A gamma setting corresponding to the display color of the pixel corresponding to the tail signal line is stored.

As a result, even if the signal line to be corrected is changed by switching the block sequential driving direction, that is, the direction in which the block is selected, between the forward direction and the reverse direction, the signal line to be corrected is appropriately changed. Grayscale correction can be performed on input data, and display unevenness near the block boundary can be reliably suppressed.
According to a fourth aspect, in the first to third aspects, the pixel includes a color filter, and the color filter includes at least one of a red color, a green color, and a blue color. It is a feature.
Thereby, an appropriate color display can be performed.

  Further, in the driving method of the electro-optical device according to the fifth aspect of the invention, the selection voltage is supplied to the scanning lines in a predetermined order, and the signal is supplied during one horizontal scanning period in which the selection voltage is supplied to the scanning lines. A method of driving an electro-optical device that supplies gradation display voltages corresponding to input display data to pixels corresponding to each signal line in a block unit in which a plurality of lines are grouped. Gamma setting corresponding to each pixel and a signal line belonging to a block selected first among a set of blocks adjacent to each other and corresponding to a tail signal line approaching the next selected block The correction gamma setting according to the display color is stored, and the gradation display voltage according to the input display data of the tail signal line and the correction gamma setting is selected for the pixel corresponding to the tail signal line. Special to do It is set to.

  Accordingly, it is possible to provide a driving method for the electro-optical device that can suppress display unevenness near the block boundary in the block sequential driving method with a relatively simple configuration.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 10 as an electro-optical device according to this embodiment.
As shown in FIG. 1, the liquid crystal display device 10 has a display area 14, and a control circuit 20, a scanning line driving circuit 16, and a signal line driving circuit 30 are arranged around the display area 14. Yes.

Among these, the display area 14 is an area where a plurality of pixels are arranged. In this embodiment, 480 scanning lines extend in the row (X) direction, and 2400 signal lines are arranged in the column (Y). It is assumed that the pixels are arranged in correspondence with the intersections of the scanning lines of 480 rows and the signal lines of 2400 columns.
The liquid crystal display device 10 of this embodiment uses another glass on which a color filter or the like is formed by using a semiconductor element such as a thin transistor (TFT) formed on a glass substrate 12 by low-temperature polysilicon technology. Liquid crystal molecules are sandwiched between the substrate and the substrate. As a result, color display is possible.

The color filter has a colored region in which a primary color is applied corresponding to each pixel. The color filter in the present embodiment has three colored regions of R (red), G (green), and B (blue), and the three color pixels are arranged in the row direction in the order of RGB. It is assumed that the pixel arrangement is a stripe type in which pixels of the same color are arranged in the direction.
In the liquid crystal display device 10 of the present embodiment, the pixels are arranged in a matrix in the display region 14 in a matrix of 480 rows × 2400 columns (3 × 800 = 2400 including three colors of RGB). Although the case where so-called full color WVGA is employed will be described, the present invention is not intended to be limited to this arrangement.

The scanning line driving circuit 16 and the signal line driving circuit 30 can be formed using the above-described low-temperature polysilicon technology as the SOG (System On Glass) technology. A chip IC mounted using COG (Chip On Glass) technology can be used.
The control unit 20 outputs a video signal (digital RGB display data) 21 and a control signal 24 to the scanning line driving circuit 16 and the signal line driving circuit 30. The control unit 20 may be one of the components of the liquid crystal display device 10 or may be configured as another external device.

  The scanning line driving circuit 16 is a circuit that incorporates a shift register having a function of inputting an appropriate input signal, synchronizing the change of the clock signal, and outputting a signal similar to the input signal by sequentially shifting the time. For example, in the case of a 480-stage shift register, 480 signals similar to the input signal are sequentially output for each change of the clock signal. By using the signal that is sequentially shifted and output as the scanning line selection signal 26 of the display area 14, 480 scanning lines can be sequentially selected in synchronization with the change of the clock signal.

The signal line driver circuit 30 also includes a shift register. However, since the number of signal lines is as large as 2400 here, it takes time to scan if a 2400-stage shift register is used. Therefore, 2400 signal lines are divided into n = 100 blocks every m = 24, and a 100-stage shift register is used.
The signal line driving circuit 30 receives the video signal 21 supplied from the control unit 20, divides the video signal of one horizontal scanning period corresponding to 2400 signal lines into 100, and collects the block unit for each block. It has a function of supplying each signal line as data 28. That is, the signal line drive circuit 30 is controlled in accordance with the operation of the shift register of n = 100 stages and the operation of the selection switch group of n = 100 groups under the control of the control signal 24 from the control unit 20. By sequentially supplying the unit data 28 to every m = 24 signal lines, video signals are respectively supplied to n × m = 2400 signal lines.

  FIG. 2 is a diagram illustrating a configuration of the signal line driving circuit 30. The signal line driving circuit 30 includes a driver unit 32, a shift register 38, and a selection switch group 40. The driver unit 32 may be configured as a driver IC of another chip without being a component of the signal line driving circuit 30. For example, the shift register 38 and the selection switch group 40 can be formed on a glass substrate by SOG technology, and the driver unit 32 can be mounted on the glass substrate by COG technology as a separate chip.

  The driver unit 32 is a line that stores the video signal processing circuit 34 that processes the video signal 21 supplied from the control unit 20 of FIG. 1 and the video signal data 22 processed by the video signal processing circuit 34 in units of one horizontal scanning period. The memory 35 and a part of the video signal data stored in the line memory 35 and a block memory 36 for storing the video signal data extracted in units of blocks are configured.

In the case of 256 gray scale display, the video signal processing circuit 34 receives digital RGB display data of 8 bits for each RGB as the video signal 21, and performs signal processing such as gradation correction described later on the video signal 21, The video signal data for one horizontal scanning period supplied to each signal line is transferred to the line memory 35.
Since the video signal data in one horizontal scanning period is divided and supplied to n × m = 2400 signal lines, the video signal data corresponding to each signal line is referred to as signal line-by-line data. Is a memory that stores n × m = 2400 data for each signal line side by side. Further, the block memory 36 stores m = 24 signal line data for each block.

  In order to extract and store the data for each signal line for an arbitrary block from the 2400 signal line data in the line memory 35, it is based on a control signal command from the control unit 20. For example, in order to distinguish 100 blocks, if numbers are assigned from B1 to B100, the control unit 20 sequentially designates the block numbers from B1 to B100 to the signal line drive circuit 30, whereby the designated blocks are designated. The 24 signal line data corresponding to the numbers are sequentially extracted from the line memory 35 and transferred to the block memory 36.

The transferred data is temporarily stored in the block memory 36 and then supplied to the selection switch group 40 as 24 data 42 (VD1 to VD24).
Therefore, when the control unit 20 sequentially designates the block numbers from B1 to B100, the selection switch group 40 is sequentially supplied with the data 42 grouped for each block from the blocks B1 to B100, and the control unit 20 assigns the block numbers from B100. When data is sequentially specified up to B1, the selection switch group 40 is sequentially supplied with data 42 collected from the blocks B100 to B1 for each block.

  As described above, the shift register 38 has a function of inputting an appropriate input signal, synchronizing the change of the clock signal, and outputting the same signal as the input signal by sequentially shifting the time. It is composed of stages. Thus, 100 signals similar to the input signal are sequentially output every time the clock signal changes. In FIG. 2, this sequentially output signal is shown as a sequential shift signal 44 (SR). Then, by using the sequential shift signal 44 as a selection signal for each of the 100 blocks B1 to B100, the 100 blocks B1 to B100 are sequentially selected in synchronization with the change of the clock signal. Can do.

  The shift register 38 employs a system in which a plurality of data flip-flops and the like are connected in series, are driven by a clock signal, and data is sequentially transferred from the previous stage to the subsequent stage. The shift register 38 of this embodiment is configured so that the shift pulse transfer direction (block sequential drive direction) is controlled by a transfer direction control signal (not shown), and here, every one horizontal scanning period. It is assumed that the transfer direction of the shift pulse is switched.

Therefore, when the xth scanning line is selected, the blocks are selected in the order of B1, B2,... B100 (forward direction), and when the x + 1th scanning line is selected, the blocks are B100, B99, ..., B1 is selected in the order (reverse direction).
Note that the order of the data 42 for each block output from the block memory 36 is reversed between the case where the xth scanning line is selected and the case where the x + 1th scanning line is selected. That is, the control unit 20 switches the order in which the block numbers are designated for the line memory 35 every horizontal scanning period.

  The selection switch group 40 is a group of 100 selection switches provided corresponding to 100 blocks, and each selection switch group 40 includes a plurality of selection switches 50. The number of selection switches 50 constituting each group is the same as the number of data per signal line in the block memory 36 in the corresponding block. That is, the selection switch group 40 corresponding to each block includes 24 selection switches 50, and the total number of selection switches constituting the 100 selection switch groups 40 is 2400.

  The selection switch group 40 supplies the data 42 sequentially supplied from the block memory 36 to the signal lines corresponding to the blocks sequentially selected by the sequential shift signal 44 from the shift register 38 as data 28 in units of blocks. To do. In FIG. 2, numerals 1 to 2400 are given to the output of the selection switch group 40 to indicate that they correspond to 2400 signal lines in the display area.

FIG. 3 is a partially enlarged view showing the configuration of the selection switch group 40 and the display area 14.
As shown in FIG. 3, the sequential shift signal 44 is supplied as SR1 to SR100 to 100 sets of signal lines corresponding to each block. Further, the output of the selection switch group 40 is supplied to the signal lines D1 to D2400 in the display area 14 for each block B1 to B100.

The sequential shift signal 44 corresponds to the output of each stage of the shift register 38 and is supplied to 100 sets of signal lines as described above. Each signal line is connected to a selection switch 50, and the same sequential shift signal is supplied to one set of signal lines. Therefore, each selection switch 50 connected to one set of signal lines is simultaneously turned on and off. Will do.
The selection switch 50 is a transmission gate type switch in which a p-channel transistor and an n-channel transistor are combined. In order to turn on and off the p-channel transistor and the n-channel transistor at the same time, an inverter that inverts a shift signal is used for each selection switch. 50. Each selection switch 50 has one end connected to one of signal lines to which data 42 (VD1 to VD24) is supplied, and the other end connected to one of signal lines D1 to D2400 in the display area 14.

For example, the selection switch 50 surrounded by a broken-line circle in FIG. 3 is sequentially turned on and off by the shift signal SR1, and one end is connected to the data VD3 and the other end is connected to the signal line D3. Therefore, when the selection switch 50 is turned on by the sequential shift signal SR1, the data VD3 is supplied to the signal line D3.
In the display area 14, 2400 signal lines D1 to D2400 and 480 scanning lines G1 to G480 are arranged orthogonally, and a pixel is arranged corresponding to each intersection of the signal lines and the scanning lines. .

  Each pixel includes an n-channel thin transistor (hereinafter referred to as TFT) 56 that functions as a switching element, and a pixel electrode 58. Further, between each signal line and the pixel electrode, there are capacitors 60 and 62 due to inter-wiring capacitance.

  Next, the operation of the block sequential drive method will be described. In this one horizontal scanning period, the block sequential driving direction, that is, the direction in which the block is selected is changed from the left side to the right side in FIG. 3, and B1, B2,.

First, the first block B1 operates as follows. In the display area 14, the block B1 includes signal lines D1 to D24 as one block.
When the block B1 is designated by the control signal 24 from the control unit 20, the data for each signal line corresponding to the block B1 is extracted from the line memory 35 and transferred to the block memory 36, and these are transferred to the selection switch group 40. Supplied as VD1 to VD24.

Further, when the sequential shift signal SR1 for selecting the block B1 is output from the shift register 38 by the control signal 24 from the control unit 20, the 24 selection switches 50 connected to the signal lines D1 to D24 are simultaneously transmitted. Turn on. As a result, the data VD1 is supplied to the signal line D1, the data VD2 is supplied to the signal line D2, and similarly, the data VD24 is supplied to the signal line D24.
In this way, the data for each signal line corresponding to each of the 24 signal lines D1 to D24 belonging to the block B1 is supplied.

  Next, the sequential shift signal SR2 corresponding to the block B2 is output. Before that, the signal line data corresponding to the block B2 is extracted from the line memory 35 and stored in the block memory 36. These are transferred and supplied to the selection switch group 40 as VD1 to VD24.

The selection switch group corresponding to the block B2 has the same configuration as that of the selection switch group corresponding to the block B1. Although not shown in FIG. 3, each of the 24 selection switches 50 includes signal lines in the display area 14. D25 to D48 are connected.
Therefore, when the sequential shift signal SR1 for the block B1 is turned off and the next sequential shift signal SR2 is turned on, the data VD1 for the block B2 is transferred to the signal line D25, the data VD2 is transferred to the signal line D26, and so on. VD24 is supplied to the signal line D48.

  In this way, the corresponding data for each signal line is supplied to the 24 signal lines D25 to D48 belonging to the block B2. By repeating this operation until the sequential shift signal SR100 corresponding to the block B100 is output, the data for each signal line is supplied to the 2400 signal lines D1 to D2400 corresponding to the row selected by the scanning line driving circuit 16. Thus, data writing for one row is completed.

FIG. 4 is a block diagram showing the configuration of the video signal processing circuit 34.
Here, the gradation correction of each color is performed by correcting the gradation level of the input display data (video signal 21) according to the gamma setting of each color.
The video signal processing circuit 34 includes an input latch circuit 34a, a gamma setting register 34b, an image processing circuit 34c, a data latch circuit 34d, a level shifter circuit 34e, a DA conversion circuit 34f, an output buffer circuit 34g, A regulated voltage generation circuit 34h.

The gamma setting register 34b corresponds to the storage circuit, the image processing circuit 34c corresponds to the correction circuit, and the DA conversion circuit 34f corresponds to the selection circuit.
The RGB RGB 8-bit digital RGB display data DR, DG, DB as the video signal 21 supplied from the control unit 20 is latched internally in a time division manner in the input latch circuit 34a. The input display data is processed by the image processing circuit 34c on the basis of the register value of the gamma setting register 34b, passes through the data latch circuit 34d and the level shifter circuit 34e, and is supplied from the gradation voltage generating circuit 34h. Based on the regulated voltages V0 to V255, DA conversion is performed by the DA conversion circuit 34f.

The DA conversion circuit 34f selects an analog voltage (gradation display potential) corresponding to the display data level-converted by the level shifter circuit 34e from the reference gradation voltages V0 to V255 supplied from the gradation voltage generation circuit 34h. The analog voltage representing the gradation display is transferred to the above-described line memory 35 via the output buffer circuit 34g.
Here, the gamma setting register 34b has register values corresponding to the three RGB gamma settings (for R, G, and B) and correction gamma settings (for R correction (R ') and B correction (B'). ) Is remembered.

  In the image processing circuit 34c, when the block sequential driving direction is the forward direction, the gradation level of the R input display data is corrected based on the R gamma setting, and the G input display data is corrected. Corrects the gradation level based on the G gamma setting, and corrects the B input display data corresponding to the tail signal lines (D24, D48,..., D2376) of each block excluding the block B100 with B correction. The gradation level is corrected based on the gamma setting for B, and the gradation level is corrected based on the B gamma setting for other B input display data.

  Further, in the image processing circuit 34c, when the block sequential driving direction is the reverse direction, the R input display data corresponding to the tail signal lines (D2377, D2353,..., D25) of each block excluding the block B1, The gradation level is corrected based on the R correction gamma setting, and the gradation input level of the other R input display data is corrected based on the R gamma setting. Corrects the gradation level based on the G gamma setting, and corrects the gradation level of B input display data based on the B gamma setting.

By the way, when the block sequential driving method in which the signal line is driven for each block is adopted, display unevenness may occur in the vicinity of the block boundary. This will be described below.
As described with reference to FIG. 3, a plurality of signal lines D1 to D2400 and a plurality of scanning lines G1 to G480 are arranged orthogonally in the display area 14 and correspond to each intersection of the signal lines and the scanning lines. Thus, the switching element 56 and the pixel electrode 58 are disposed. Capacitances 60 and 62 exist between each signal line and the pixel electrode.

With such a configuration, when the potential of a certain signal line changes, the potential of another signal line changes via the capacitors 60 and 62. In particular, since a signal line to which no potential is supplied from the outside is in a floating state, it is easily affected by potential changes in other signal lines.
For example, if the shift signal SR2 is sequentially output when the block sequential drive direction is the forward direction, the signal lines D25 to D48 belonging to the block B2 have corresponding signals. Since the gradation display potential corresponding to the line-by-line data is supplied, it is hardly affected by other signal lines.

On the other hand, when the sequential shift signal SR2 is output, the output of the sequential shift signal SR1 is already completed, and the gradation display potential is not supplied from the signal lines D1 to D24 belonging to the block B1. The signal lines D1 to D24 are in a floating state, and are easily affected by the potentials of the signal lines D25 to D48 belonging to the block B2.
The pixels corresponding to the signal lines D1 to D24 belonging to the block B1 are charged by the gradation display potential supplied by SR1 and hold the potential necessary for image display. However, the influence of the potentials of the signal lines D25 to D48. If there is, the potential for displaying the image fluctuates and the display state changes. In this way, when the data for each signal line is written in the block B2, the data for each signal line already written in the adjacent block B1 may fluctuate and display unevenness may occur.

  The effect of this capacitive coupling becomes weaker as the potential is moved away from the signal line. For this reason, display unevenness is most likely to occur between adjacent signal lines adjacent to a block in which data is written. When SR2 is output, the influence of the head signal line D25 of the block B2 is most easily received by the tail signal line D24 of the block B1, and the display unevenness is most likely to occur between the signal lines D24 and D25. The signal line D25 has less influence on the signal line D23 than the signal line D24, and the signal line D22 has less influence.

Therefore, first, display unevenness between adjacent signal lines in an adjacent block is suppressed.
For this purpose, among the signal lines of the block to which the data for each signal line is supplied, the signal line adjacent to the block and next to the block to which the data for each signal line is supplied next, that is, sequentially in the forward direction. When the shift signal SR1 is output, the signal line D24 of the block B1 and the signal line D2377 of the block B100 when the shift signal S100 is sequentially output in the reverse direction take into account the above-described influence of capacitive coupling. It is preferable to supply the data for each signal line.

  Therefore, in the present embodiment, the gradation level of the input display data of B corresponding to the last signal line of each block excluding the block B100 in the forward direction based on the B correction gamma setting in the image processing circuit 34c. Is corrected to a gradation level that takes the above influence into consideration, and in the reverse direction, the gradation of the input display data of R corresponding to the last signal line of each block excluding the block B1 is determined based on the R correction gamma setting. The level is corrected to a gradation level in consideration of the above influence.

FIG. 5 is a table showing an example of the optimum gradation correction value for each gradation. A circle (◯) indicates that display unevenness near the block boundary cannot be visually observed, and a cross (×) indicates the display unevenness. Is visible.
As shown in FIG. 5, it can be seen that, by correcting the input display data by adding 3 to 4 gradations in each gradation, display unevenness in the vicinity of the block boundary cannot be visually observed in each gradation. However, as indicated by double circles (◎) and thick broken lines in the figure, the optimum gradation correction value for each gradation is different. In this example, at a low gradation level (for example, 31 gradations) and a high gradation level (for example, 223 gradations), the optimum gradation correction value is 2 to 3 gradations, but an intermediate gradation level (for example, 127 gradation), the optimum gradation correction value is about 4 gradations.

  This is because, as shown in FIG. 6, the slope of the VT curve indicating the characteristic of the luminance (T) with respect to the voltage (V) is steep near the intermediate gradation. In the intermediate gradation, the luminance changes greatly even with a slight voltage change. For this reason, in the vicinity of the intermediate gradation (for example, 127 gradation), it is necessary to set the gradation correction value relatively large compared to other gradation levels and to greatly perform gradation correction of the input display data.

FIG. 7 is a diagram showing normal B gamma setting and B correction gamma setting.
The B correction gamma setting indicated by the broken line is added with an optimum gradation correction value for each gradation in FIG. 5 with respect to the B gamma setting indicated by the solid line. Therefore, the output of the N gradation input display data processed by the image processing circuit 34c using the B correction gamma setting is (N + N ′) where N ′ is the optimum gradation correction value for N gradation. This is a value equivalent to the output when the grayscale input display data is processed using the B gamma setting.

Although not shown in the drawing, the R correction gamma setting is similar to the B correction gamma setting shown in FIG. 7 except that an optimum gradation correction value for each gradation is added to the normal R gamma setting. It has become.
In this way, the gradation correction of the input display data corresponding to the last signal line (the signal line that is most susceptible to capacitive coupling) of each block excluding the block B100 (or block B1) is performed.

FIG. 8 is a diagram for explaining data supplied to each signal line in a general block sequential driving method in which gradation correction is not performed as in the present embodiment.
This general block sequential drive system has three gamma settings corresponding to RGB as gamma settings. Regardless of whether the pixel corresponds to the end signal line of the block, a gradation display potential corresponding to the R gamma setting (setting A) is supplied to the R pixel, and the G gamma is supplied to the G pixel. A gradation display potential corresponding to the setting (setting B) is supplied, and a gradation display potential corresponding to the B gamma setting (setting C) is supplied to the B pixel.

On the other hand, in the present embodiment, as shown in FIG. 9, there are five gamma settings: R gamma setting, G gamma setting, B gamma setting, R correction gamma setting, and B correction gamma setting. Has a gamma setting.
When the block sequential driving direction is the forward direction, as shown in FIG. 9A, a gradation display potential corresponding to the R gamma setting (setting A) is supplied to the R pixel, and the G pixel Is supplied with a gradation display potential corresponding to the G gamma setting (setting B). As for the B pixel, in the case of the pixel corresponding to the end signal line of each block excluding the block B100, a gradation display potential corresponding to the B correction gamma setting (setting D) is supplied, and the other B pixels. A gradation display potential corresponding to the B gamma setting (setting C) is supplied to the pixel.

That is, when the shift signal SR1 is sequentially turned on, the gradation display potential corresponding to the data for each signal line is supplied to the signal lines D1 to D24 belonging to the block B1, but at this time, the signal line D24 is supplied with B A gradation display potential corresponding to the data for each signal line subjected to gradation correction using the correction gamma setting is supplied.
After that, when the sequential shift signal SR1 is turned off and the sequential shift signal SR2 is turned on, the gradation display potential corresponding to the data for each signal line is supplied to the signal lines D25 to D48 belonging to the block B2.

At this time, the signal lines D1 to D24 belonging to the block B1 are in a floating state, and when the potential of the signal lines D25 to D48 belonging to the block B2 is supplied, the potential of the signal line D24 adjacent to the block B2 is changed to a signal. It fluctuates under the influence of the potential fluctuation of the line D25.
However, since the signal line D24 is supplied with a gradation display potential corresponding to the data for each signal line subjected to gradation correction using the B correction gamma setting as described above, the potential supply of the signal line D25 is performed. Even if it is affected, it appears to be unaffected on the display.

  On the other hand, when the block sequential driving direction is the reverse direction, as shown in FIG. 9B, for the R pixel, in the case of the pixel corresponding to the end signal line of each block except the block B1, the R correction gamma is used. The gradation display potential according to the setting (setting D) is supplied, and the gradation display potential according to the R gamma setting (setting A) is supplied to the other R pixels. A gradation display potential corresponding to the G gamma setting (setting B) is supplied to the G pixel, and a gradation display potential corresponding to the B gamma setting (setting C) is supplied to the B pixel.

That is, when the shift signal SR100 is sequentially turned on, the gradation display potential corresponding to the data for each signal line is supplied to the signal lines D2377 to D2400 belonging to the block B100. At this time, the signal line D2377 is supplied with R A gradation display potential corresponding to the data for each signal line subjected to gradation correction using the correction gamma setting is supplied.
Thereafter, when the sequential shift signal SR100 is turned off and the sequential shift signal SR99 is turned on, the gradation display potential corresponding to the data for each signal line is supplied to the signal lines D2353 to D2376 belonging to the block B99.

At this time, the signal lines D2377 to D2400 belonging to the block B100 are in a floating state. When the potential of the signal lines D2353 to D2376 belonging to the block B99 is supplied, the potential of the signal line D2377 adjacent to the block B99 is changed to a signal. It fluctuates under the influence of the potential fluctuation of the line D2376.
However, since the signal line D2377 is supplied with a gradation display potential corresponding to the data for each signal line subjected to gradation correction using the R correction gamma setting as described above, the potential of the signal line D2376 is supplied. Even if it is affected, it appears to be unaffected on the display.

  As described above, in this embodiment, when the block sequential driving method is adopted, among the signal lines belonging to the block being driven, the signal line that is adjacent to the block and is closest to the next driven block. Is the signal line to be corrected, and the gradation level of the input display data is corrected for the signal line to be corrected, so that it is possible to suppress the occurrence of display unevenness near the block boundary due to the influence of capacitive coupling.

In addition, a new color correction gamma setting corresponding to the signal line to be corrected is provided, and for the signal line to be corrected, the gradation level of the input display data is corrected using the correction gamma setting. Thus, the occurrence of display unevenness near the block boundary can be suppressed without performing complicated calculations.
Furthermore, by providing a bidirectional shift register in the signal line drive circuit, the block sequential drive direction can be made bidirectional, and R correction gamma setting and B gamma setting are provided as correction gamma settings. The gradation correction of the signal line to be corrected can be performed regardless of the block sequential driving direction.

  In the above embodiment, the pixel arrangement in which the color corresponding to the signal line to be corrected is B (blue) in the forward direction and the color corresponding to the signal line to be corrected is R (red) in the reverse direction. For example, when the color corresponding to the signal line to be corrected is G (green), a G correction gamma setting is provided instead of the R correction gamma setting or the B correction gamma setting. The input display data of the signal line to be corrected can be subjected to gradation correction using the G correction gamma setting.

  Further, in the above-described embodiment, the case of a stripe type pixel arrangement in which pixels of the same color are arranged in the column direction has been described, but the present invention is also applied to a mosaic type (diagonal type), a delta type (triangle type), and the like. Can be applied. In this case, if the correction gamma settings corresponding to the three primary colors (RGB) are stored as the correction gamma settings, the color of the color filter of the pixel of the tail signal line to be corrected is whatever. Further, gradation correction that cancels the influence of capacitive coupling can be performed.

Furthermore, in the above embodiment, the case where the block sequential driving direction is switched every horizontal scanning period has been described, but the block sequential driving direction can be switched every arbitrary horizontal scanning period.
Furthermore, although the case where the RGB color filters are used has been described in the above embodiment, four color filters such as RGBC (cyan) and RGBW (white) can also be used.

  In the above embodiment, the case where the present invention is applied to an electro-optical device using liquid crystal has been described. However, the present invention can also be applied to an electro-optical device using an electro-optical material other than liquid crystal. For example, electrophoresis using a display panel using an OLED element such as an organic EL or a light emitting polymer as an electro-optical material, or a microcapsule containing a colored liquid and white particles dispersed in the liquid as the electro-optical material The present invention can be applied to various electro-optical devices such as a display panel and a twist ball display panel using a twist ball painted in different colors for each region having different polarities as an electro-optical material.

It is a block diagram which shows the structure of the liquid crystal display device in this embodiment. It is a figure which shows the structure of a signal line drive circuit. It is a figure which expands and partially shows the structure of a selection switch group, and the structure of a display area. It is a block diagram which shows the structure of the video signal processing circuit in this embodiment. It is a figure which shows the optimal gradation correction value in each gradation. It is a VT curve. It is a figure which shows normal B gamma setting and B correction gamma setting. It is a figure explaining the data supplied to each signal line in a general block sequential drive system. It is a figure explaining the data supplied to each signal line in the block sequential drive system of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device, 12 ... Glass substrate, 14 ... Display area, 16 ... Scanning line drive circuit, 20 ... Control part, 21 ... Video signal, 24 ... Control signal, 30 ... Signal line drive circuit, 32 ... Driver part, 34 ... Video signal processing circuit, 34a ... Input latch circuit, 34b ... Gamma setting register, 34c ... Image processing circuit, 34d ... Data latch circuit, 34e ... Level shifter circuit, 34f ... DA conversion circuit, 34g ... Output buffer circuit, 34h ... Gradation voltage generation circuit, 35 ... line memory, 36 ... block memory, 38 ... shift register, 40 ... selection switch group, 50 ... selection switch, 56 ... TFT, 58 ... pixel electrode, 60, 62 ... capacitance

Claims (5)

A plurality of scanning lines, a plurality of signal lines, a plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of signal lines, and a selection voltage in a predetermined order with respect to the scanning lines And a pixel corresponding to each signal line in a block unit in which a plurality of the signal lines are collected in one horizontal scanning period in which the selection voltage is supplied to the scanning line. A signal line driving circuit for supplying a gradation display voltage corresponding to each input display data, and an electro-optical device,
The signal line driving circuit includes:
A gamma setting corresponding to each of the display colors of the pixels, and a signal line belonging to a previously selected block of a set of blocks adjacent to each other, and being close to the next selected block A storage circuit for storing a correction gamma setting corresponding to the display color of the pixel corresponding to the signal line;
A voltage selection circuit that selects a gradation display voltage according to the input display data and the gamma setting stored in the storage circuit;
The voltage selection circuit selects, as the gradation display voltage supplied to the pixel corresponding to the tail signal line, a voltage corresponding to the input display data of the tail signal line and the correction gamma setting. Electro-optic device.   The voltage selection circuit corrects a gradation level of the input display data based on a gamma setting stored in the storage circuit, and the gradation display voltage corresponding to the input display data corrected by the correction circuit. The electro-optical device according to claim 1, further comprising: a selection circuit that selects The signal line drive circuit has a bidirectional shift register capable of switching the voltage supply order to the signal lines in both forward and reverse directions,
In the memory circuit, as the gamma setting for correction, the gamma setting according to the display color of the pixel corresponding to the tail signal line when the voltage supply order is forward and the voltage supply order are reverse. The electro-optical device according to claim 1, wherein a gamma setting corresponding to a display color of a pixel corresponding to the tail signal line is stored. A color filter for the pixel;
The electro-optical device according to claim 1, wherein the color filter includes at least one of a red color, a green color, and a blue color. Each signal line is supplied in units of blocks in which a plurality of signal lines are collected in one horizontal scanning period in which a selection voltage is supplied to the scanning lines in a predetermined order and the selection voltage is supplied to the scanning lines. A method of driving an electro-optical device that supplies gradation display voltages corresponding to input display data to pixels corresponding to
A gamma setting corresponding to each of the display colors of the pixels, and a signal line belonging to a previously selected block of a set of blocks adjacent to each other, and being close to the next selected block A correction gamma setting corresponding to the display color of the pixel corresponding to the signal line, and
A driving method of an electro-optical device, wherein the gradation display voltage corresponding to the input display data of the tail signal line and the correction gamma setting is selected for the pixel corresponding to the tail signal line.

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