WO2019000981A1 - 计算机设备、读取时间的方法和写入时间的方法 - Google Patents

计算机设备、读取时间的方法和写入时间的方法 Download PDF

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Publication number
WO2019000981A1
WO2019000981A1 PCT/CN2018/076893 CN2018076893W WO2019000981A1 WO 2019000981 A1 WO2019000981 A1 WO 2019000981A1 CN 2018076893 W CN2018076893 W CN 2018076893W WO 2019000981 A1 WO2019000981 A1 WO 2019000981A1
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Prior art keywords
time
pld
rtc
real
component
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PCT/CN2018/076893
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English (en)
French (fr)
Inventor
王江
周昔平
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华为技术有限公司
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Publication of WO2019000981A1 publication Critical patent/WO2019000981A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • Embodiments of the present invention relate to the field of computers, and in particular, to a computer device, a method of reading time, and a method of writing time.
  • a real-time clock refers to an electronic device that can output time.
  • the electronic device can be an integrated circuit or a clock chip.
  • the computer device is deployed with an RTC that provides accurate real-time time for the computer device; the computer device uses the real-time time of the RTC output as a time reference to perform the task.
  • the computer device is an Advanced RISC Machine (ARM) server
  • the architecture of the ARM server accessing the RTC is shown in FIG.
  • the ARM processor accesses the RTC
  • the ARM processor requests a complex programmable logic device (CPLD) to connect the switch 101 so that the ARM processor can access the RTC through the I 2 C bus connected by the switch 101, for example from RTC reads real time.
  • the BMC Baseboard Management Controller
  • the BMC requests the CPLD to connect the switch 102 so that the BMC can access the RTC through the I 2 C bus that the switch 102 is connected to.
  • the RTC cannot be accessed by both the ARM processor and the BMC. It is necessary to control the switch (101, 102) to determine whether the ARM processor or the BMC accesses the RTC.
  • the present application provides a computer device, a method of reading time, and a method of writing time to provide access to a real-time clock (RTC) through a programmable logic device (PLD). ) Real time.
  • RTC real-time clock
  • PLD programmable logic device
  • the application provides a computer device including an RTC and a PLD.
  • the PLD is connected to the RTC.
  • the PLD obtains real time from the RTC and stores the real time. In this way, components in the computer device that need to use the real time can obtain the real time from the PLD.
  • the PLD has a first storage unit.
  • the PLD stores the real time acquired from the RTC in the first storage unit.
  • the component of the computer device that needs to use the real-time time can access the first storage unit of the PLD, and acquire the real-time time from the first storage unit.
  • the computer device further includes at least one component.
  • Each of the at least one component is coupled to the PLD.
  • Each of the at least one component can obtain the real time time stored by the PLD. All of the at least one component acquires real time from the PLD relatively independently, such that any of the at least one component can acquire the real time from the PLD at any time.
  • the plurality of components respectively obtain the real-time time from the PLD, since each of the plurality of components independently acquires the real-time time from the PLD, the plurality of components acquire the real-time time from the PLD without interfering with each other, The plurality of components can simultaneously acquire the real time from the PLD.
  • the at least one component is connected to the PLD via a bus.
  • the at least one component can acquire the real time from the PLD based on the bus protocol of the bus.
  • the at least one component is connected to the PLD via a local bus.
  • the at least one component can acquire the real time from the PLD based on the bus protocol of the local bus.
  • the RTC and the PLD are connected by a bus.
  • the PLD can acquire the real time from the RTC based on the bus protocol of the bus.
  • the PLD is connected to the RTC by connecting an internal integrated circuit I 2 C bus.
  • the PLD can acquire the real time from the RTC based on the bus protocol of the I 2 C bus.
  • the at least one component comprises a processor or a baseboard management controller BMC.
  • the processor reads the real-time time from the PLD without being disturbed by other components to read the real-time time, and the processor can obtain the PLD from any real-time time that needs to be used.
  • the real time is read to effectively ensure that the processor performs an action based on the real time.
  • the BMC reads the real-time time from the PLD without being interfered by other components to read the real-time time, and the BMC can use any real-time time when it is needed.
  • the PLD reads the real time, thereby effectively ensuring that the BMC manages the computer device based on the real time.
  • the present application provides a method of reading time applied to a computer device provided by any of the possible aspects of the first aspect or the first aspect.
  • the PLD since the PLD is connected to the RTC, the PLD directly acquires real time from the RTC and stores the real time.
  • the component of the subsequent computer device that needs to use the real time can obtain the real time from the first storage unit of the PLD instead of reading the real time directly from the RTC.
  • each component of at least one component can acquire real-time time from the PLD at any time, and the PLD is respectively directed to the at least one component in the process of acquiring real-time time Each component outputs this real time.
  • at least one component can acquire real-time time from the PLD in parallel, and can even acquire the real-time time from the PLD at the same time.
  • the present application provides a method of updating time, applied to a computer device provided by any of the possible aspects of the first aspect or the first aspect.
  • the PLD acquires another time from at least one component; the PLD writes the other time to the RTC, and the RTC updates the real time in real time on the basis of the other time.
  • the other time can be written to the RTC through the PLD. Subsequently, the RTC updates the real-time time in real time from this other time.
  • the application provides a PLC.
  • the PLC comprises a functional module of a method of performing a read time provided by any of the possible aspects of the second aspect or the second aspect, and/or the PLC comprises a method of performing an update time provided by any of the possible aspects of the third aspect or the third aspect Functional module.
  • the application does not limit the division of the function modules in the PLC, and the function modules may be correspondingly divided according to the process steps of the method, or the function modules may be divided according to specific implementation requirements.
  • a computer readable storage medium is provided, the instructions being stored in a computer readable storage medium.
  • the PLD in the computer device executes the instruction, the PLD performs the method of reading time provided by various possible designs of the second aspect or the second aspect, or the PLD performs various aspects of the third aspect or the third aspect described above. It is possible to design a method of providing updated time.
  • a computer program product comprising instructions stored in a computer readable storage medium.
  • the PLD in the computer device executes the instruction, the PLD performs the method of reading time provided by various possible designs of the second aspect or the second aspect, or the PLD performs various aspects of the third aspect or the third aspect described above. It is possible to design a method of providing updated time.
  • Figure 1 is a schematic diagram of a system architecture of an ARM server
  • FIG. 2 is a schematic structural diagram of a system of a computer device according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart of a read time according to an embodiment of the present disclosure
  • FIG. 4 is a schematic flowchart of a read time according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of an update time according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a logical structure of a PLD according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a logical structure of a PLD according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a system of a computer device according to an embodiment of the present invention.
  • the embodiment of the present invention provides a computer device; the computer device may be a server, such as an Advanced RISC Machine (ARM) server; the computer device may also be other computing capable devices.
  • ARM Advanced RISC Machine
  • the computer device includes a real-time clock (RTC) and a programmable logic device (PLD).
  • RTC real-time clock
  • PLD programmable logic device
  • the RTC is connected to the PLD.
  • the PLD can obtain real time from the RTC.
  • the RTC is connected to the PLD through a bus.
  • the bus may be an Inter-Integrated Circuit (I 2 C) bus.
  • I 2 C Inter-Integrated Circuit
  • the bus may also be implemented between the RTC and the PLD.
  • the bus of data may be any type of data.
  • the PLD has at least one memory unit.
  • the at least one memory unit includes a first memory unit that stores real time in the first memory unit.
  • the real-time time is stored in the first storage unit according to the following storage format, where the storage format is year, month, day, week, hour, minute, and second.
  • the first storage unit may be a register, or may be another medium having storage capability.
  • the first storage unit includes seven registers that store the year, month, day, day of the week, hour, minute, and second of the real time.
  • the PLD is connected to the RTC, and the PLD acquires real time from the RTC and stores the real time. In this way, the component of the computer device that needs to use the real time can obtain the real time from the first storage unit of the PLD.
  • a computer device is deployed with a complex programmable logic device (CPLD) that enables various components of the computer device to trigger the component to start or stop working.
  • CPLD complex programmable logic device
  • the PLD shown in FIG. 2 replaces the CPLD of the computer device provided by the conventional technology, and replaces the role played by the CPLD in the computer device (for example, enabling each component in the computer device)
  • the device is started or stopped by the triggering component; this can avoid the need to simultaneously deploy the CPLD with the conventional function and the device waste caused by the PLD provided by the embodiment of the present invention in the computer device.
  • the PLD of the computer device provided by the conventional technology is used to implement the PLD shown in FIG.
  • the computer device includes n components, n being a positive integer greater than or equal to one.
  • n components are respectively connected to the PLD.
  • Figure 2 illustrates three components (component 1, component 2, component n), which is connected to port out1 of the PLD, component 2 is connected to port out2 of the PLD, and component n is connected to port outn of the PLD.
  • n components are respectively connected to the PLD through a bus, and the bus may be a local bus, and the bus may be another bus capable of transmitting data between the component and the PLD.
  • the n components can respectively acquire the real time from the PLD.
  • component 1 is a processor in a computer device that can access a first storage unit of the PLD through port out1 and read the real-time time stored by the first storage unit.
  • component 2 is a Baseboard Management Controller (BMC) in the computer device, and the BMC can access the first storage unit of the PLD through the port out2, and read the real-time time stored by the first storage unit.
  • BMC Baseboard Management Controller
  • the plurality of components acquire the real-time from the PLD.
  • the real-time time does not interfere with each other. Therefore, the plurality of components can simultaneously acquire the real-time time from the PLD.
  • each of the plurality of components can acquire the real-time time from the PLD at any time.
  • the embodiment of the present invention eliminates the switch, saves cost, and saves the action of the CPLD control switch and improves multiple components. Get the efficiency of this real time.
  • the embodiment of the present invention does not limit the specific implementation manner in which the component obtains the real-time time from the PLD.
  • the following provides an example to provide two implementation manners.
  • the component 1 and the component 2 correspond to a processor and a BMC in the computer device, and the processor and the BMC can respectively read the first storage unit of the PLD to implement the real-time acquisition.
  • component n requests the real-time time from the PLD, and the PLD acquires the real-time time from the first storage unit and sends the acquired real-time time to the component n.
  • n components include a processor or BMC in a computer device.
  • the processor can read the real-time time stored in the first storage unit of the PLD, perform an action based on the real-time time, for example, assigning a task and scheduling a task based on the real-time time, for example, performing data interaction with other components based on the real-time time.
  • the processor reads the real-time time from the PLD without being interfered by other components to read the real-time time, and the processor can read the real-time time from the PLD when any real-time time is needed, thereby effectively ensuring The processor performs an action based on the real time.
  • the BMC can read the real time stored in the first storage unit of the PLD and manage the computer device based on the real time. Compared with the traditional technology, the BMC reads the real-time time from the PLD without being interfered by other components to read the real-time time. The BMC can read the real-time time from the PLD when any real-time time is needed, thereby effectively ensuring that the BMC is based on This real time manages computer equipment.
  • FIG. 3 illustrates the flow of the method of reading the time, the method including step S301 and step S302.
  • Step S301 the PLD acquires real time from the RTC.
  • the PLD is connected to the RTC, and the PLD obtains the real time from the RTC through the connection.
  • the specific manner for obtaining the real-time time of the PLD from the RTC is not limited in the embodiment of the present invention. Two implementation manners are specifically provided below.
  • the RTC generates a real time and outputs the real time to the PLD.
  • the RTC has a second storage unit (for example, a register), and the second storage unit is configured to store the real-time time.
  • the implementation manner of the second storage unit is implemented in the embodiment of the present invention.
  • the implementation of the storage unit may be a similar implementation, and details are not described herein again.
  • the RTC updates the real-time time stored in the second storage unit of the RTC in real time, for example, real-time increasing the real-time time stored in the second storage unit according to a time step (for example, 1 second); the PLD is real-time or periodically from the RTC.
  • the real time is read in the second storage unit.
  • step S302 the PLD stores the real time.
  • the PLD has a first storage unit, and the PLD stores the real time acquired from the RTC in the first storage unit.
  • the PLD is connected to the RTC, and the PLD can acquire and store the real-time time of the RTC by performing step S301 and step S302 in the method for reading the time, and the real-time time is needed in the subsequent computer equipment.
  • the component can obtain the real time from the first storage unit of the PLD instead of reading the real time directly from the RTC.
  • the method for reading time may further include step S303.
  • Step S303 the component acquires real time from the PLD.
  • the specific manner for obtaining the real-time time of the component from the PLD is not limited in the embodiment of the present invention. Two implementation manners are specifically provided below.
  • the component directly accesses the first storage unit of the PLD, and reads a real-time time from the first storage unit. During the reading process, the PLD stores the real-time time stored by the first storage unit to the component. Output.
  • the component requests the latest real-time time from the PLD, and the PLD outputs the real-time time stored by the first storage unit to the component.
  • the component is connected to the PLD, and the component can acquire real-time time from the PLD at any time.
  • the computer device includes a plurality of components that are respectively connected to the PLD, the plurality of components can acquire real-time time from the PLD at any time, and each of the plurality of components is independently from the The PLD obtains the real-time time, and the multiple components acquire the real-time time from the PLD without interference; therefore, the multiple components can not only obtain the real-time time from the PLD at any time, but also acquire the real-time from the PLD at the same time. time.
  • the first storage unit of the PLD includes n storage modules, and each storage module may be a register, or may be another storage capable medium.
  • the storage modules in the n storage modules are in one-to-one correspondence with the components in the n components. Each component can access the corresponding storage module.
  • the PLD acquires real-time time from the RTC, and updates the real-time time acquired each time to each of the n storage modules.
  • Each of the n components accesses a corresponding one of the n storage modules and acquires real time from the corresponding storage module.
  • the n components can independently acquire the real-time time from the PLD, and the plurality of components acquire the real-time time from the PLD without interfering with each other.
  • FIG. 5 illustrates a flow of the method of updating the time, the method including step S501, step S502, and step S503.
  • step S501 the component writes another time to the PLD.
  • the at least one memory unit of the PLD includes a third memory unit.
  • the implementation manner of the third storage unit in the embodiment of the present invention and the implementation manner of the first storage unit in the embodiment of the present invention may be similar implementation manners, and details are not described herein again.
  • the component can access the third storage unit of the PLD and write the other time to the third storage unit; such that the PLD acquires the other time from the component.
  • the component is specifically a processor in the computer device.
  • the processor can update the real-time time through the other time, and the other components of the computer device other than the processor are prevented from illegally changing the real-time time.
  • an operating system (OS) running on a processor or a basic input/output system (BIOS) can access a third storage unit of the PLD, and write the same in the third storage unit. Another time.
  • OS operating system
  • BIOS basic input/output system
  • the processor authorizes the component a component can write to the third storage unit for another time, that is, the plurality of components cannot simultaneously write the other time to the third storage unit, so that the other time can be guaranteed at each time only one.
  • the third storage unit is the same storage unit as the first storage unit. Relative to the need to configure two storage units (the third storage unit and the first storage unit) in the PLD, configuring one storage unit can save storage resources; in addition, updating the first one in real time using the other time written by the component The real time in the storage unit can improve the real-time performance of the processor using the other time in the first storage unit to perform the action.
  • the third storage unit is a different storage unit from the first storage unit.
  • the processor can continue to perform the action using the real time of the first storage unit, ensuring uninterrupted execution of the action.
  • the PLD requests the component for another time, the component sends the other time to the PLD; such that the PLD obtains the other time from the component.
  • the third storage unit of the PLD includes n storage modules, and each storage module may be a register, or may be another storage capable medium.
  • the storage modules in the n storage modules of the third storage unit are in one-to-one correspondence with the components in the n components. Each component can access the corresponding storage module.
  • each of the n components can write the other time to a corresponding one of the n memory modules. Subsequently, the PLD can write the other time in the storage module to the RTC.
  • step S502 the PLD writes the other time to the RTC.
  • the RTC has a second storage unit.
  • the PLD can access the second storage unit of the RTC and write the other time to the second storage unit.
  • Step S503 the RTC updates the real time according to the other time.
  • the RTC continues to update the real-time time stored in the second storage unit on the basis of the other time.
  • the unupdated real-time time stored in the second storage unit is “2017, June, 22, Thursday, 15 o'clock, 20 minutes, 20 seconds”, and the other time is “2017, June” , 23rd, Friday, 15th, 20th, 20th", after the PLD writes the other time to the second storage unit, the real time stored in the second storage unit is "2017, June, 23" Day, Friday, 15 o'clock, 20 minutes, 20 seconds"; subsequently, the RTC updates the real-time time stored in the second storage unit in real time, for example, updating the real-time time stored in the second storage unit every one second, The real time stored in the second storage unit is updated to "2017, June, 23, Friday, 15 o'clock, 20 minutes, 21 seconds" after 1 second, and the second storage unit is passed after 1 minute The real-time time stored in the store is updated to "2017, June, 23, Friday, 15 o'clock, 21 minutes, 20 seconds".
  • the RTC uses the another time to update the real-time time in the second storage unit, so that the RTC outputs the real-time time adjusted to the PLD according to the other time in time, and timely updates the first storage unit in the PLD.
  • the stored real time ensures that the processor uses the updated real time stored by the first storage unit to perform the action.
  • the embodiment of the invention provides a PLC.
  • the PLC includes functional modules that perform the method of reading time provided by the above method embodiments, and/or the PLC includes functional modules that perform the method of updating time provided by the above method embodiments.
  • the application does not limit the division of the function modules in the PLC, and the function modules may be correspondingly divided according to the process steps of the method, or the function modules may be divided according to specific implementation requirements.
  • the PLD includes:
  • An obtaining unit 601, configured to acquire real time from the RTC;
  • the storage execution unit 602 is configured to store the real time.
  • the PLD further includes: an output unit 603, configured to output the real-time time to the at least one component.
  • the PLD includes:
  • the obtaining unit 701 is configured to acquire another time from the at least one component
  • the write execution unit 702 is configured to write the other time to the RTC for the RTC to update the real time.
  • the embodiment of the invention is a computer readable storage medium in which instructions are stored in a computer readable storage medium.
  • the PLD in the computer device executes the instruction, the PLD performs the step performed by the PLD in the method for reading the time provided by the foregoing method embodiment, or the method in which the PLD performs the update time provided by the foregoing method embodiment The steps performed by the PLD.
  • the embodiment of the invention is a computer readable storage medium in which instructions are stored in a computer readable storage medium.
  • the step of executing the read time provided by the method embodiment is performed by the component, or the method for executing the update time provided by the method embodiment is The steps performed by the component.
  • Embodiments of the invention are a computer program product comprising instructions stored in a computer readable storage medium.
  • the PLD in the computer device executes the instruction, the PLD performs the step performed by the PLD in the method for reading the time provided by the foregoing method embodiment, or the method in which the PLD performs the update time provided by the foregoing method embodiment The steps performed by the PLD.
  • Embodiments of the invention are a computer program product comprising instructions stored in a computer readable storage medium. The steps performed by the component in the method of performing the read time provided by the above method embodiment, or the steps performed by the component in the method of executing the update time provided by the above method embodiment.
  • a component in the computer device replaces the PLD in the architecture shown in FIG. 2, including implementing the architecture shown in FIG. 2 instead of the PLD, and further comprising: replacing the PLD to implement the PLD in the FIG.
  • FIG. 8 exemplifies the architecture of the BMC instead of the PLD shown in FIG. 2.
  • the role of the PLD described above in the embodiment of the present invention is similarly applied to the BMC shown in FIG.
  • the above-described function of the PLD in the reading time and the function of the above-described PLD in the update time are similarly applied to the BMC shown in FIG.
  • first in the above “first storage unit”, “second” in the above “second storage unit”, and “third” in the above “third storage unit” are only used to distinguish each other. . That is, the “first storage unit”, the “second storage unit”, and the “third storage unit” do not represent specific storage units, nor do they represent a sequential relationship between them.
  • the names of the "first storage unit”, the “second storage unit” and the “third storage unit” may be interchanged or the "first storage unit” may be renamed as “the first storage unit” without departing from the scope of protection of the embodiments of the present invention.
  • the fourth storage unit ” and the “second storage unit” are referred to as “fifth storage unit”.

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Abstract

本发明涉及计算机领域，并公开了一种计算机设备、读取时间的方法和写入时间的方法。该计算机设备包括实时时钟(real-time clock，RTC)和可编程式逻辑器件(programmable logic device，PLD)，该PLD与该RTC连接。该PLD从该RTC获取实时时间，存储该实时时间。这样，计算机设备中需要使用该实时时间的组件可以从该PLD获取该实时时间。

Description

计算机设备、读取时间的方法和写入时间的方法 技术领域
本发明实施例涉及计算机领域，尤其涉及计算机设备、读取时间的方法和写入时间的方法。
背景技术
实时时钟(real-time clock，RTC)是指可以输出时间的电子设备，该电子设备可以是集成电路，也可以是时钟芯片。
计算机设备部署有RTC，该RTC为计算机设备提供精确的实时时间；计算机设备将RTC输出的实时时间作为时间基准来执行任务。
如果该计算机设备是高级精简指令集机器(Advanced RISC Machine，ARM)服务器，该ARM服务器访问RTC的架构参见图1。在ARM处理器访问RTC时，ARM处理器请求复杂可编程式逻辑器件(complex programmable logic device，CPLD)将开关101连通，这样ARM处理器可以通过开关101连通的I 2C总线访问RTC，例如从RTC读取实时时间。在基板管理控制器(Baseboard Management Controller，BMC)访问RTC时，BMC请求CPLD将开关102连通，这样BMC可以通过开关102连通的I 2C总线访问RTC。但是，在图1所示的架构中，RTC不能同时被ARM处理器和BMC访问，需要通过CPLD控制开关(101,102)来决定是ARM处理器或者BMC访问RTC。
发明内容
有鉴于此，本申请提供了一种计算机设备、读取时间的方法和写入时间的方法,以便通过可编程式逻辑器件(programmable logic device，PLD)提供访问实时时钟(real-time clock，RTC)的实时时间。
第一方面，本申请提供一种计算机设备，该计算机设备包括RTC和PLD。
该PLD与该RTC连接。该PLD从该RTC获取实时时间，存储该实时时间。这样，计算机设备中需要使用该实时时间的组件可以从该PLD获取该实时时间。
第一方面的一个可能设计，该PLD具有第一存储单元。该PLD将从RTC获取的实时时间存储在该第一存储单元中。
计算机设备中需要使用该实时时间的组件可以访问该PLD的第一存储单元，从该第一存储单元获取该实时时间。
第一方面的一个可能设计，该计算机设备还包括至少一个组件。该至少一个组件中的每个组件与该PLD连接。
该至少一个组件中的每个组件可以获取该PLD存储的该实时时间。该至少一个组件中的所有组件相对独立地从该PLD获取实时时间，因此，该至少一个组件中的任一组件可以在任意时间从该PLD获取该实时时间。
如果多个组件分别从该PLD获取该实时时间，由于该多个组件中的每个组件是独立地从该PLD获取该实时时间，该多个组件从该PLD获取该实时时间互不干扰，因此，该多个组件可以同时从该PLD获取该实时时间。
第一方面的一个可能设计，该至少一个组件与该PLD通过总线连接。这样，该至少一个组件可以基于该总线的总线协议从该PLD获取该实时时间。
第一方面的一个可能设计，该至少一个组件与该PLD通过局部总线(local bus)连接。这样，该至少一个组件可以基于该局部总线的总线协议从该PLD获取该实时时间。
第一方面的一个可能设计，RTC与PLD通过总线连接。这样，该PLD可以基于该总线的总线协议从该RTC获取该实时时间。
第一方面的一个可能设计，该PLD与该RTC通过连接内部集成电路I 2C总线连接。这样，该PLD可以基于该I 2C总线的总线协议从该RTC获取该实时时间。
第一方面的一个可能设计，该至少一个组件包括处理器或者基板管理控制器BMC。
相对于传统技术(例如图1所示的架构)，处理器从PLD读取该实时时间不会受其它组件读取该实时时间的干扰，处理器在任意需要使用该实时时间时均可以从PLD读取该实时时间，从而有效保证处理器基于该实时时间执行动作。
类似地，相对于传统技术(例如图1所示的架构)，BMC从PLD读取该实时时间不会受其它组件读取该实时时间的干扰，BMC在任意需要使用该实时时间时均可以从PLD读取该实时时间，从而有效保证BMC基于该实时时间管理计算机设备。
第二方面，本申请提供一种读取时间的方法，应用于第一方面或第一方面的任意可能设计提供的计算机设备。
在该方法中，由于该PLD与该RTC连接，该PLD直接从RTC获取实时时间并存储该实时时间。后续计算机设备中需要使用该实时时间的组件可以从该PLD的第一存储单元获取该实时时间，而不是直接从该RTC读取实时时间。
第二方面的一种可能设计，在该方法中，至少一个组件中的每个组件可以在任意时间从该PLD获取实时时间，在获取实时时间的过程中该PLD分别向该至少一个组件中的每个组件输出该实时时间。这样，至少一个组件可以并行从该PLD获取实时时间，甚至可以同时从该PLD获取该实时时间。
第三方面，本申请提供一种更新时间的方法，应用于第一方面或第一方面的任意可能设计提供的计算机设备。
在该更新时间的方法中，PLD从至少一个组件获取另一个时间；该PLD向该RTC写入该另一个时间，该RTC在该另一个时间的基础上实时更新该实时时间。
这样，如果需要使用该另一个时间调整实时时间，可以通过PLD向RTC写入该另一个时间。后续，RTC从该另一个时间开始实时更新实时时间。
第四方面，本申请提供一种PLC。该PLC包括执行第二方面或第二方面的任意可能设计提供的读取时间的方法的功能模块，和/或该PLC包括执行第三方面或第三方面的任意可能设计提供的更新时间的方法的功能模块。本申请对该PLC中的功能模块的划分不做限定，可以按照方法的流程步骤对应划分功能模块，也可以按照具体实现需要划分功能模块。
第五方面，提供一种计算机可读存储介质，计算机可读存储介质中存储有指令。当计算机设备中的PLD执行该指令时，该PLD执行上述第二方面或者第二方面的各种可能设计提供的读取时间的方法，或者该PLD执行上述第三方面或者第三方面的各种可能设计提供的更新时间的方法。
第六方面，提供一种计算机程序产品，该计算机程序产品包括指令，该指令存储在计算机可读存储介质中。当计算机设备中的PLD执行该指令时，该PLD执行上述第二方面或者第二方面的各种可能设计提供的读取时间的方法，或者该PLD执行上述第三方面或者第三方面的各种可能设计提供的更新时间的方法。
附图说明
图1为ARM服务器的一种系统架构示意图；
图2为本发明实施例提供的计算机设备的一种系统架构示意图；
图3为本发明实施例提供的读取时间的一种流程示意图；
图4为本发明实施例提供的读取时间的一种流程示意图；
图5为本发明实施例提供的更新时间的一种流程示意图；
图6为本发明实施例提供的PLD的一种逻辑结构示意图；
图7为本发明实施例提供的PLD的一种逻辑结构示意图；
图8为本发明实施例提供的计算机设备的一种系统架构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例提供的技术方案进行描述。
本发明实施例提供一种计算机设备；该计算机设备可以是服务器，例如高级精简指令集机器(Advanced RISC Machine，ARM)服务器；该计算机设备也可以是其他具有计算能力的设备。
参见图2，该计算机设备包括实时时钟(real-time clock，RTC)和可编程式逻辑器件(programmable logic device，PLD)。
参见图2，该RTC与该PLD连接。这样，该PLD可以从该RTC获取实时时间。
可选地，RTC与PLD通过总线连接，例如该总线可以是内部集成电路(Inter-Integrated Circuit，I 2C)总线，当然，该总线也可以是其它能够实现在该RTC与该PLD之间传输数据的总线。
该PLD具有至少一个存储单元。该至少一个存储单元包括第一存储单元，该PLD将实时时间存储在该第一存储单元中。可选地，该实时时间在该第一存储单元中按照以下存储格式存储,该存储格式为年、月、日、星期、时、分、秒。
可选地，该第一存储单元可以是寄存器，也可以是其它具有存储能力的介质。例如，该第一存储单元包括7个寄存器，该7个寄存器存储该实时时间包含的年、月、日、星期、时、分、秒。
在本发明实施例中，该PLD与该RTC连接，该PLD从该RTC获取实时时间并存储该实时时间。这样，计算机设备中需要使用该实时时间的组件可以从该PLD的第一存储单元获取该实时时间。
在传统技术中，计算机设备部署有复杂可编程式逻辑器件(complex programmable logic device，CPLD)，该CPLD可以使能计算机设备中的各组件以触发组件启动或停止工作。可选地，在本发明实施例中，图2所示的该PLD替换传统技术提供的计算机设备的CPLD,并替代该CPLD在计算机设备中所起的作用(例如使能计算机设备中的各组件以 触发组件启动或停止工作)；这样可以避免在计算机设备中需要同时部署具有传统功能的该CPLD和本发明实施例提供的该PLD所带来的器件浪费。可选地，在本发明实施例中，采用传统技术提供的计算机设备的CPLD实现图2所示的该PLD，包括替代该PLD实现图2所示的架构，还包括替代该PLD实现该PLD在该图2所示的架构下具有的在本发明实施例中的功能；这样可以避免在计算机设备中需要同时部署具有传统功能的该CPLD和本发明实施例提供的该PLD所带来的器件浪费。
参见图2，该计算机设备包括n个组件，n为大于或等于1的正整数。
n个组件分别与该PLD连接。图2示意了三个组件(组件1、组件2、组件n)，组件1与该PLD的端口out1连接，组件2与该PLD的端口out2连接，组件n与该PLD的端口outn连接。可选地，n个组件分别通过总线与该PLD连接，该总线可以是局部总线(local bus)，该总线可以是其它能够实现在该组件与该PLD之间传输数据的总线。
在n个组件分别与该PLD连接的情况下，n个组件可以分别从该PLD获取该实时时间。
举例说明，组件1为计算机设备中的处理器，该处理器可以通过端口out1访问该PLD的第一存储单元，并读取该第一存储单元存储的该实时时间。组件2为计算机设备中的基板管理控制器(Baseboard Management Controller，BMC)，该BMC可以通过端口out2访问该PLD的第一存储单元，并读取该第一存储单元存储的该实时时间。
在本发明实施例中，如果多个组件分别从该PLD获取该实时时间，由于该多个组件中的每个组件是独立地从该PLD获取该实时时间，该多个组件从该PLD获取该实时时间互不干扰，因此，该多个组件可以同时从该PLD获取该实时时间，当然，该多个组件中的每个组件可以在任意时间从该PLD获取该实时时间。
另外，相对于传统技术(如图1提供的架构)，本发明实施例(如图2提供的架构)省去了开关，节省了成本，并且省去了CPLD控制开关的动作，提高多个组件获取该实时时间的效率。
本发明实施例对组件从该PLD获取该实时时间的具体实现方式不做限定，下面提供举例提供两种实现方式。
第一种实现方式，组件1和组件2对应为计算机设备中的处理器和BMC，该处理器和该BMC可以分别读取PLD的第一存储单元来实现对该实时时间的获取。
第二种实现方式，组件n向该PLD请求该实时时间，该PLD从第一存储单元获取该实时时间并将获取的该实时时间向该组件n发送。
可选地，n个组件包括计算机设备中的处理器或者BMC。
处理器可以读取PLD的第一存储单元中存储的该实时时间,基于该实时时间执行动作，例如基于该实时时间分配任务和调度任务，例如基于该实时时间与其它组件进行数据交互。相对于传统技术，处理器从PLD读取该实时时间不会受其它组件读取该实时时间的干扰，处理器在任意需要使用该实时时间时均可以从PLD读取该实时时间，从而有效保证处理器基于该实时时间执行动作。
BMC可以读取PLD的第一存储单元中存储的该实时时间,基于该实时时间管理计算机设备。相对于传统技术，BMC从PLD读取该实时时间不会受其它组件读取该实时时间的干扰，BMC在任意需要使用该实时时间时均可以从PLD读取该实时时间，从而有效保证BMC基于该实时时间管理计算机设备。
下面提供一种读取时间的方法。图3示意了该读取时间的方法的流程，该方法包括步骤S301和步骤S302。
步骤S301，PLD从该RTC获取实时时间。
具体地，该PLD与该RTC连接，该PLD通过该连接从该RTC获取该实时时间。
本发明实施例对PLD从RTC获取实时时间的具体获取方式不做限定，下面具体提供两种实现方式。
第一种实现方式，该RTC生成实时时间，并将该实时时间向该PLD输出。
第二种实现方式，该RTC具有第二存储单元(例如寄存器)，该第二存储单元用于存储实时时间，本发明实施例实现该第二存储单元的实现方式与本发明实施例实现第一存储单元的实现方式可以是类似的实现方式，在此不再赘述。该RTC实时更新该RTC的第二存储单元中存储的实时时间，例如按照时间步长(比如1秒)实时增加该第二存储单元中存储的实时时间；该PLD实时或者定期从该RTC的第二存储单元中读取实时时间。
步骤S302，PLD存储该实时时间。
具体地，PLD具有第一存储单元，PLD将从RTC获取的实时时间在该第一存储单元中存储。
在本发明实施例中，该PLD与该RTC连接，通过执行读取时间的方法中的步骤S301和步骤S302，该PLD可以获取并存储该RTC的实时时间，后续计算机设备中需要使用该实时时间的组件可以从该PLD的第一存储单元获取该实时时间，而不是直接从该RTC读取实时时间。
可选地，参见图4，该读取时间的方法还可以包括步骤S303。
步骤S303，组件从该PLD获取实时时间。
本发明实施例对组件从该PLD获取实时时间的具体获取方式不做限定，下面具体提供两种实现方式。
第一种实现方式，组件直接访问该PLD的第一存储单元，从该第一存储单元中读取实时时间，在读取过程中，该PLD将该第一存储单元存储的实时时间向该组件输出。
第二种实现方式，组件向该PLD请求最新的实时时间，该PLD将该第一存储单元存储的实时时间向该组件输出。
在本发明实施例中，组件与该PLD连接，组件可以在任意时间从该PLD获取实时时间。如果计算机设备包括多个组件，该多个组件是分别与该PLD连接的，该多个组件都可以在任意时间从该PLD获取实时时间，该多个组件中的每个组件是独立地从该PLD获取该实时时间，该多个组件从该PLD获取该实时时间互不干扰；因此，该多个组件不但可以在任意时间从该PLD获取该实时时间，还可以同时分别从该PLD获取该实时时间。
可选地，该PLD的第一存储单元包括n个存储模块，每个存储模块可以是寄存器，也可以是其它具有存储能力的介质。
n个存储模块中的存储模块与n个组件中的组件一一对应。每个组件可以访问对应的存储模块。
在本可选实施方式中，该PLD从RTC获取实时时间，并将每次获取的实时时间同步更新至n个存储模块中的每个存储模块。n个组件中的每个组件访问n个存储模块中对应 的存储模块，并从对应的存储模块获取实时时间。这样，n个组件可以独立从该PLD获取该实时时间，该多个组件从该PLD获取该实时时间互不干扰。
下面提供一种更新时间的方法。图5示意该更新时间的方法的流程，该方法包括步骤S501、步骤S502和步骤S503。
步骤S501，组件向PLD写入另一个时间。
PLD具有的至少一个存储单元包括第三存储单元。本发明实施例实现该第三存储单元的实现方式与本发明实施例实现第一存储单元的实现方式可以是类似的实现方式，在此不再赘述。
组件可以访问该PLD的该第三存储单元，向该第三存储单元写入该另一个时间；这样PLD从该组件获取到该另一个时间。
可选地，在该更新时间的方法中，组件具体为计算机设备中的处理器。这样，计算机设备中，仅处理器能通过该另一个时间更新实时时间，避免计算机设备中除处理器以外的其它组件非法更改实时时间。
举例说明，处理器运行的操作系统(operating system，OS)或者基本输入/输出系统BIOS(basic input/output system,BIOS)可以访问PLD的第三存储单元，并在该第三存储单元写入该另一个时间。
可选地，在该更新时间的方法中，如果计算机设备中的多个组件分别向该第三存储单元写入该另一个时间，则在每个时刻，只有获得授权(例如处理器对组件授权)的一个组件可以向该第三存储单元写入该另一个时间，即该多个组件不能同时向该第三存储单元写入该另一个时间，这样可以保证该另一个时间在每个时间均是唯一的。
可选地，该第三存储单元与该第一存储单元为同一个存储单元。相对于需要在PLD中配置两个存储单元(该第三存储单元和该第一存储单元)，配置一个存储单元可以节省存储资源；另外，使用组件写入的该另一个时间实时更新该第一存储单元中的实时时间，能够提高处理器使用该第一存储单元中的该另一个时间来执行动作的实时性。
可选地，该第三存储单元与该第一存储单元为不同存储单元。在使用第三单元存储的该另一个时间更新RTC的过程中处理器可以使用第一存储单元的实时时间继续执行动作，保证执行动作的不间断。
可选地，该PLD向组件请求该另一个时间，该组件将该另一个时间向该PLD发送；这样PLD从该组件获取到该另一个时间。
可选地，该PLD的第三存储单元包括n个存储模块，每个存储模块可以是寄存器，也可以是其它具有存储能力的介质。
第三存储单元的n个存储模块中的存储模块与n个组件中的组件一一对应。每个组件可以访问对应的存储模块。
在本可选实施方式中，n个组件中的每个组件可以向n个存储模块中对应的存储模块写入该另一个时间。后续，PLD可以将该存储模块中的该另一个时间向RTC写入。
步骤S502，该PLD向RTC写入该另一个时间。
RTC具有第二存储单元。PLD可以访问该RTC的该第二存储单元，向该第二存储单元写入该另一个时间。
步骤S503，该RTC基于该另一个时间更新该实时时间。
具体地，该RTC在该另一个时间的基础上继续更新该第二存储单元中存储的实时时间。
举例说明，该第二存储单元中存储的未更新的实时时间为“2017年、6月、22日、星期四、15点、20分、20秒”，该另一个时间为“2017年、6月、23日、星期五、15点、20分、20秒”，PLD将该另一个时间写入该第二存储单元后，该第二存储单元中存储的实时时间为“2017年、6月、23日、星期五、15点、20分、20秒”；后续，RTC实时更新该第二存储单元中存储的实时时间，比如每过一秒便更新一次该第二存储单元中存储的实时时间，在过了1秒时该第二存储单元中存储的实时时间更新为“2017年、6月、23日、星期五、15点、20分、21秒”，在过了1分钟时该第二存储单元中存储的实时时间更新为“2017年、6月、23日、星期五、15点、21分、20秒”。
在本发明实施例中，RTC使用该另一个时间更新该第二存储单元中的实时时间，使得RTC及时向PLD输出根据该另一个时间调整后的实时时间，及时更新PLD中的第一存储单元存储的实时时间，保证处理器使用该第一存储单元存储的更新的实时时间来执行动作。
本发明实施例提供一种PLC。该PLC包括执行上述方法实施例提供的读取时间的方法的功能模块，和/或该PLC包括执行上述方法实施例提供的更新时间的方法的功能模块。本申请对该PLC中的功能模块的划分不做限定，可以按照方法的流程步骤对应划分功能模块，也可以按照具体实现需要划分功能模块。
举例提供与读取时间的方法对应的功能模块，参见图6，该PLD包括：
获取单元601，用于从该RTC获取实时时间；
存储执行单元602，用于存储该实时时间。
可选地，该PLD还包括：输出单元603，用于向该至少一个组件输出该实时时间。
举例提供与更新时间的方法对应的功能模块，参见图7，该PLD包括：
获取单元701，用于从该至少一个组件获取另一个时间；
写入执行单元702，用于向该RTC写入该另一个时间，该另一个时间用于该RTC更新该实时时间。
本发明实施例一种计算机可读存储介质，计算机可读存储介质中存储有指令。当计算机设备中的PLD执行该指令时，该PLD执行上述方法实施例提供的读取时间的方法中由该PLD执行的步骤，或者该PLD执行上述方法实施例提供的更新时间的方法中由该PLD执行的步骤。
本发明实施例一种计算机可读存储介质，计算机可读存储介质中存储有指令。当计算机设备中的组件执行该指令时，该组建执行上述方法实施例提供的读取时间的方法中由该组件执行的步骤，或者该组建执行上述方法实施例提供的更新时间的方法中由该组件执行的步骤。
本发明实施例一种计算机程序产品，该计算机程序产品包括指令，该指令存储在计算机可读存储介质中。当计算机设备中的PLD执行该指令时，该PLD执行上述方法实施例提供的读取时间的方法中由该PLD执行的步骤，或者该PLD执行上述方法实施例提供的更新时间 的方法中由该PLD执行的步骤。
本发明实施例一种计算机程序产品，该计算机程序产品包括指令，该指令存储在计算机可读存储介质中。该组建执行上述方法实施例提供的读取时间的方法中由该组件执行的步骤，或者该组建执行上述方法实施例提供的更新时间的方法中由该组件执行的步骤。
可选地,计算机设备中的组件(例如BMC)替代图2所示架构中的PLD,包括替代该PLD实现图2所示的架构，还包括替代该PLD实现该PLD在该图2所示的架构下具有的在本发明实施例中的功能,例如替换PLD从该RTC获取实时时间和存储该实时时间。
图8举例示意了BMC替代图2所示的PLD的架构。上述描述的PLD在本发明实施例所起的作用，类似适用于图8所示的BMC。另外，上述描述的PLD在读取时间的方法所起的作用，以及上述描述的PLD在更新时间的方法所起的作用，类似适用于图8所示的BMC。
应当理解，上述“第一存储单元”中的“第一”，上述“第二存储单元”中的“第二”，上述“第三存储单元”中的“第三”都仅用于相互区分。即，“第一存储单元”、“第二存储单元”和“第三存储单元”并不代表特指的存储单元，也不代表它们之间存在顺序关系。在不脱离本发明实施例保护范围的情况下，可以对“第一存储单元”、“第二存储单元”和“第三存储单元”互换名称，或者将“第一存储单元”改称为“第四存储单元”和将“第二存储单元”改称为“第五存储单元”。
以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的保护范围。

Claims (15)

  1. 一种计算机设备，其特征在于，包括实时时钟RTC和可编程式逻辑器件PLD；所述PLD与所述RTC连接，所述PLD用于从所述RTC获取实时时间和存储所述实时时间。
  2. 根据权利要求1所述的计算机设备，其特征在于，所述计算机设备还包括至少一个组件；
    所述至少一个组件与所述PLD连接，所述至少一个组件用于获取所述PLD存储的所述实时时间。
  3. 根据权利要求2所述的计算机设备，其特征在于，
    所述至少一个组件用于向所述PLD写入另一个时间；
    所述PLD用于向所述RTC写入所述另一个时间；
    所述RTC用于基于所述另一个时间更新所述实时时间。
  4. 根据权利要求2或3所述的计算机设备，其特征在于，
    所述至少一个组件与所述PLD通过局部总线连接。
  5. 根据权利要求1所述的计算机设备，其特征在于，
    所述PLD与所述RTC通过连接内部集成电路I2C总线连接。
  6. 根据权利要求2所述的计算机设备，其特征在于，所述至少一个组件包括处理器或者基板管理控制器BMC。
  7. 一种读取时间的方法，其特征在于，应用于包括实时时钟RTC和可编程式逻辑器件PLD的计算机设备；所述方法包括：
    所述PLD从所述RTC获取实时时间，所述PLD与所述RTC连接；
    所述PLD存储所述实时时间。
  8. 根据权利要求7所述的方法，其特征在于，所述计算机设备包括至少一个组件；所述方法包括：所述PLD向所述至少一个组件输出所述实时时间。
  9. 一种更新时间的方法，其特征在于，应用于计算机设备；所述计算机设备包括实时时钟RTC、可编程式逻辑器件PLD和至少一个组件，所述PLD与所述RTC连接，所述PLD用于从所述RTC获取实时时间；所述方法包括：
    所述PLD从所述至少一个组件获取另一个时间；
    所述PLD向所述RTC写入所述另一个时间，所述另一个时间用于所述RTC更新所述实时时间。
  10. 根据权利要求9所述的方法，其特征在于，所述至少一个组件包括处理器或者基板管理控制器BMC。
  11. 一种可编程式逻辑器件PLD，其特征在于，计算机设备包括所述PLD和实时时钟RTC，所述PLD与所述RTC连接；所述PLD包括：
    获取单元，用于从所述RTC获取实时时间；
    存储执行单元，用于存储所述实时时间。
  12. 根据权利要求11所述的PLD，其特征在于，所述计算机设备包括至少一个组件；所述PLD包括：输出单元，用于向所述至少一个组件输出所述实时时间。
  13. 一种可编程式逻辑器件PLD，其特征在于，计算机设备包括所述PLD、实时时钟RTC和至少一个组件，所述PLD与所述RTC连接；所述PLD包括：
    获取单元，用于从所述至少一个组件获取另一个时间；
    写入执行单元，用于向所述RTC写入所述另一个时间，所述另一个时间用于所述RTC更新实时时间。
  14. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储指令；当计算机设备中的可编程式逻辑器件PLD执行所述指令时，所述PLD执行权利要求7或8所述的方法。
  15. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储指令；当计算机设备中的可编程式逻辑器件PLD执行所述指令时，所述PLD执行权利要求9或10所述的方法。
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