WO2019000496A1 - 像素补偿电路及显示装置 - Google Patents

像素补偿电路及显示装置 Download PDF

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Publication number
WO2019000496A1
WO2019000496A1 PCT/CN2017/092923 CN2017092923W WO2019000496A1 WO 2019000496 A1 WO2019000496 A1 WO 2019000496A1 CN 2017092923 W CN2017092923 W CN 2017092923W WO 2019000496 A1 WO2019000496 A1 WO 2019000496A1
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Prior art keywords
controllable switch
switch
control
capacitor
controllable
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PCT/CN2017/092923
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English (en)
French (fr)
Inventor
刘婕
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武汉华星光电半导体显示技术有限公司
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Priority to US15/554,220 priority Critical patent/US10204554B2/en
Publication of WO2019000496A1 publication Critical patent/WO2019000496A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel compensation circuit and a display device.
  • the basic driving circuit of the existing AMOLED display device includes a switching thin film transistor T1, a driving thin film transistor T2 and a storage capacitor Cst.
  • the threshold voltage Vth of the transistor T1 is easily drifted, resulting in unstable driving current of the organic light emitting diode OLED, which affects panel quality.
  • the technical problem to be solved by the present invention is to provide a pixel compensation circuit and a display device to avoid the instability of the current of the organic light emitting diode caused by the threshold voltage drift, thereby improving the panel image quality.
  • a technical solution adopted by the present invention is to provide a pixel compensation circuit, including:
  • the first controllable switch includes a control end, a first end, and a second end, the first end of the first controllable switch is connected to the first voltage end, and the first controllable switch is The control terminal is connected to the illumination control terminal;
  • the second controllable switch comprising a control end, a first end and a second end, the control end of the second controllable switch being connected to the second end of the second controllable switch and the a second end of the first controllable switch, the first end of the second controllable switch receiving a first reset signal;
  • the third controllable switch comprising a control end, a first end and a second end, the control end of the third controllable switch receiving a control signal, the first end of the third controllable switch Receiving a data signal;
  • Driving a switch comprising a control end, a first end and a second end, the driving switch The control end is connected to the second end of the third controllable switch, and the first end of the drive switch is connected to the second end of the first controllable switch;
  • the fourth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fourth controllable switch receives the first scan signal, and the fourth controllable switch One end is connected to the second voltage end, and the second end of the fourth controllable switch is connected to the second end of the driving switch;
  • the fifth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fifth controllable switch receives a second scan signal, and the fifth controllable switch One end is connected to the second end of the driving switch;
  • An organic light emitting diode comprising an anode and a cathode, the anode being connected to a second end of the fifth controllable switch, the cathode being connected to a third voltage end;
  • the first capacitor includes a first end and a second end, a first end of the first capacitor is connected to a second end of the second controllable switch, and a second end of the first capacitor is connected a second end of the third controllable switch;
  • the second capacitor includes a first end and a second end, the first end of the second capacitor is connected to the second end of the second controllable switch, and the second end of the second capacitor is received Second reset signal;
  • the driving switch, the first controllable switch, the second controllable switch, the fourth controllable switch, and the fifth controllable switch are all PMOS type transistors, and the driving switch, the first a control terminal, a first controllable switch, a fourth controllable switch, and a control terminal, a first end, and a second end of the fifth controllable switch respectively corresponding to a gate of the PMOS transistor, Drain and source;
  • a technical solution adopted by the present invention is to provide a pixel compensation circuit, including:
  • the first controllable switch includes a control end, a first end, and a second end, the first end of the first controllable switch is connected to the first voltage end, and the first controllable switch is The control terminal is connected to the illumination control terminal;
  • the second controllable switch comprising a control end, a first end and a second end, the control end of the second controllable switch being connected to the second end of the second controllable switch and the a second end of the first controllable switch, the first end of the second controllable switch receiving a first reset signal;
  • the third controllable switch comprising a control end, a first end and a second end, wherein the The control end of the three controllable switch receives the control signal, and the first end of the third controllable switch receives the data signal;
  • the driving switch includes a control end, a first end and a second end, the control end of the driving switch is connected to the second end of the third controllable switch, and the first end of the driving switch is connected to the a second end of the first controllable switch;
  • the fourth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fourth controllable switch receives the first scan signal, and the fourth controllable switch One end is connected to the second voltage end, and the second end of the fourth controllable switch is connected to the second end of the driving switch;
  • the fifth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fifth controllable switch receives a second scan signal, and the fifth controllable switch One end is connected to the second end of the driving switch;
  • An organic light emitting diode comprising an anode and a cathode, the anode being connected to a second end of the fifth controllable switch, the cathode being connected to a third voltage end;
  • the second capacitor includes a first end and a second end, the first end of the second capacitor is connected to the second end of the second controllable switch, and the second end of the second capacitor is received The second reset signal.
  • the present invention adopts a technical solution to provide a display device, the display device includes a pixel compensation circuit, and the pixel compensation circuit includes:
  • the first controllable switch includes a control end, a first end, and a second end, the first end of the first controllable switch is connected to the first voltage end, and the first controllable switch is The control terminal is connected to the illumination control terminal;
  • the second controllable switch comprising a control end, a first end and a second end, the control end of the second controllable switch being connected to the second end of the second controllable switch and the a second end of the first controllable switch, the first end of the second controllable switch receiving a first reset signal;
  • the fifth controllable switch includes a control end, a first end, and a second end, wherein the control end of the fifth controllable switch receives a second scan signal, and the fifth controllable switch One end is connected to the second end of the driving switch;
  • An organic light emitting diode comprising an anode and a cathode, the anode being connected to a second end of the fifth controllable switch, the cathode being connected to a third voltage end;
  • the first capacitor includes a first end and a second end, a first end of the first capacitor is connected to a second end of the second controllable switch, and a second end of the first capacitor is connected a second end of the third controllable switch;
  • the second capacitor includes a first end and a second end, the first end of the second capacitor is connected to the second end of the second controllable switch, and the second end of the second capacitor is received The second reset signal.
  • the beneficial effects of the present invention are: different from the prior art, the pixel compensation circuit and the display device of the present invention are reset by the second controllable switch, and the driving switch is grasped by the first capacitor discharge
  • the threshold voltage is compensated, and in the compensation phase, the current is completely discharged from the fourth controllable switch without passing through the organic light emitting diode, thereby avoiding the organic light emitting diode from being smuggled, thereby avoiding threshold voltage drift and causing the organic light emitting diode
  • the current is unstable, which improves the panel quality.
  • 1 is a circuit diagram of a basic driving circuit of a conventional display device
  • FIG. 2 is a circuit diagram of a first embodiment of a pixel compensation circuit of the present invention.
  • FIG. 3 is a schematic diagram showing the timing waveform of the circuit of Figure 2;
  • FIG. 4 is a schematic diagram of a set timing waveform of FIG. 2;
  • Figure 5 is a schematic diagram of the simulation waveform of Figure 2;
  • FIG. 6 is a circuit diagram of a second embodiment of a pixel compensation circuit of the present invention.
  • Figure 7 is a schematic diagram showing the timing waveform of the circuit of Figure 6;
  • Figure 8 is a schematic diagram of the set timing waveform of Figure 6;
  • Figure 9 is a schematic diagram of the simulation waveform of Figure 6;
  • Figure 10 is a schematic view showing the structure of a display device of the present invention.
  • FIG. 2 is a circuit diagram of a first embodiment of the pixel compensation circuit of the present invention.
  • the pixel compensation circuit includes a first controllable switch T1, the first controllable switch T1 includes a control end, a first end, and a second end, and the first end of the first controllable switch T1 is connected to the first voltage end VDD, the control end of the first controllable switch T1 is connected to the illumination control terminal EM;
  • the second controllable switch T2 includes a control end, a first end and a second end, and a control end of the second controllable switch T2 is connected to the second controllable switch T2 And the second end of the first controllable switch T1, the first end of the second controllable switch T2 receives the first reset signal SW;
  • the third controllable switch T3 includes a control end, a first end and a second end, the control end of the third controllable switch T3 receives a control signal, and the third controllable switch T3 The first end receives the data signal Data;
  • the driving switch T0 includes a control end, a first end and a second end, the control end of the driving switch T0 is connected to the second end of the third controllable switch T3, and the driving switch T0 One end is connected to the second end of the first controllable switch T1;
  • the fourth controllable switch T4 includes a control end, a first end and a second end, and the control end of the fourth controllable switch T4 receives a first scan signal Xscan, the fourth The first end of the control switch T4 is connected to the second voltage terminal VCC, and the second end of the fourth controllable switch T4 is connected to the second end of the driving switch T0;
  • the fifth controllable switch T5 includes a control end, a first end and a second end, and a control end of the fifth controllable switch T5 receives a second scan signal Yscan, the fifth The first end of the control switch T5 is connected to the second end of the driving switch T0;
  • the organic light emitting diode D1 includes an anode and a cathode, the anode is connected to the second end of the fifth controllable switch T5, the cathode is connected to the third voltage terminal VSS;
  • the first capacitor C1 includes a first end and a second end, and the first end of the first capacitor C1 is connected to the second end of the second controllable switch T2, the first capacitor C1 The second end is connected to the second end of the third controllable switch T3; and
  • the second capacitor C2 includes a first end and a second end, the first end of the second capacitor C2 is connected to the second end of the second controllable switch T2, and the second capacitor C2 The second end receives the second reset signal Reset.
  • the driving switch T0, the first controllable switch T1, the second controllable switch T2, the fourth controllable switch T4, and the fifth controllable switch T5 are all PMOS Type transistor, the driving switch T0, the first controllable switch T1, the second controllable switch T2, the fourth controllable The control terminal, the first terminal and the second terminal of the switch T4 and the fifth controllable switch T5 respectively correspond to the gate, the drain and the source of the PMOS transistor.
  • the third controllable switch T3 is a PMOS type transistor, and the control signal received by the control end of the third controllable switch T3 is a third scan signal scan, and the third controllable switch T3
  • the control terminal, the first terminal and the second terminal respectively correspond to a gate, a source and a drain of the PMOS transistor.
  • the voltage setting value of the second voltage terminal VCC is smaller than the voltage setting value of the third voltage terminal VSS
  • the organic light emitting diode D1 is an active array organic light emitting diode
  • the first capacitor C1 and the second capacitor C2 are storage capacitors.
  • the working principle of the pixel compensation circuit is as follows:
  • the compensation phase when the potential of the second reset signal Reset changes from a low level to a high level, the potential of the S point is further pulled up by the coupling effect of the second capacitor C2.
  • the driving switch T0 is turned off, the threshold voltage Vth of the driving switch T0 is stored in the first capacitor C1, at this time, the fourth controllable switch T4 is turned on, the fifth controllable switch T5 is turned off, the current in the process of grabbing the threshold voltage Vth of the driving switch T0 flows out from the fourth controllable switch T4, and the organic light emitting diode D1 is prevented from being smuggled;
  • the third controllable switch T3 is turned on, and the fourth controllable switch T4 and the fifth controllable switch T5 are turned off.
  • the G point potential Vg Vdata
  • Vdata is The output voltage of the data signal is caused by the series connection of the first capacitor C1 and the second capacitor C2
  • the S point potential Vs [C2/(C1+C2)]*Vref+[C1/(C1+C2)] *Vdata-Vth, where C1 is the capacitance value of the first capacitor C1, C2 is the capacitance value of the second capacitor C2, Vref is the reference voltage, Vdata is the data voltage of the data signal, and Vth is the driving switch T0. Threshold voltage.
  • the first controllable switch T1 and the fifth controllable switch T5 are both turned on, the second controllable switch T2, the third controllable switch T3 and the fourth controllable switch T4 is turned off, and the organic light emitting diode D1 emits light.
  • the pixel compensation circuit resets the S point by the second controllable switch T2, discharges the threshold voltage Vth of the driving switch T0 by the first capacitor C1, and compensates, and makes the current all in the compensation phase. Flowing out from the fourth controllable switch T4 without passing through the organic light emitting diode D1, avoiding the illuminating of the organic light emitting diode D1, thereby avoiding the instability of the current of the organic light emitting diode D1 caused by the threshold voltage drift, thereby improving the panel drawing quality.
  • FIG. 5 is a schematic diagram of simulation waveforms of the pixel compensation circuit of the present invention.
  • the pixel compensation circuit grabs the threshold voltage Vth of the driving switch T0 by S-point discharge, and captures the threshold voltage Vth so that the current is all from the fourth controllable switch.
  • T4 flows out without passing through the organic light emitting diode D1, thereby avoiding the illuminating of the organic light emitting diode D1, thereby avoiding instability of the current of the organic light emitting diode D1 caused by the threshold voltage drift, thereby improving the panel image quality.
  • FIG. 6 is a circuit diagram of a second embodiment of the pixel compensation circuit of the present invention.
  • the second embodiment of the pixel compensation circuit is different from the first embodiment in that the third controllable switch T3 is an NMOS transistor, and the control signal received by the control terminal of the third controllable switch T3 is For the control signal outputted by the illumination control terminal EM, the control terminal, the first terminal and the second terminal of the third controllable switch T3 respectively correspond to the gate, the source and the drain of the NMOS transistor.
  • the working principle of the pixel compensation circuit is as follows:
  • the compensation phase when the potential of the second reset signal Reset changes from a low level to a high level, the potential of the S point is further pulled up by the coupling effect of the second capacitor C2.
  • the driving switch T0 is turned off, the threshold voltage Vth of the driving switch T0 is stored in the first capacitor C1, at this time, the fourth controllable switch T4 is turned on, the fifth controllable switch T5 is turned off, the current in the process of grabbing the threshold voltage Vth of the driving switch T0 flows out from the fourth controllable switch T4, and the organic light emitting diode D1 is prevented from being smuggled;
  • the third controllable switch T3 is turned on, and the fourth controllable switch T4 and the fifth controllable switch T5 are turned off.
  • the G point potential Vg Vdata
  • Vdata is The output voltage of the data signal is caused by the series connection of the first capacitor C1 and the second capacitor C2
  • the S point potential Vs [C2/(C1+C2)]*Vref+[C1/(C1+C2)] *Vdata-Vth, where C1 is the capacitance value of the first capacitor C1, C2 is the capacitance value of the second capacitor C2, Vref is the reference voltage, Vdata is the data voltage of the data signal, and Vth is the driving switch T0. Threshold voltage.
  • the first controllable switch T1 and the fifth controllable switch T5 are both turned on, the second controllable switch T2, the third controllable switch T3 and the fourth controllable switch T4 is turned off, and the organic light emitting diode D1 emits light.
  • the pixel compensation circuit resets the S point by the second controllable switch T2, discharges the threshold voltage Vth of the driving switch T0 by the first capacitor C1, and compensates, and makes the current all in the compensation phase. Flowing out from the fourth controllable switch T4 without passing through the organic light emitting diode D1, avoiding the illuminating of the organic light emitting diode D1, thereby avoiding the instability of the current of the organic light emitting diode D1 caused by the threshold voltage drift, thereby improving the panel drawing quality.
  • FIG. 9 is a schematic diagram of simulation waveforms of the pixel compensation circuit of the present invention.
  • the pixel compensation circuit captures the threshold voltage Vth of the drive switch by S-point discharge, and captures the threshold voltage Vth such that the current is all from the fourth controllable switch T4.
  • the organic light emitting diode D1 is prevented from being sneaked out by the organic light emitting diode D1, thereby preventing the threshold voltage from drifting and causing the current of the organic light emitting diode D1 to be unstable, thereby improving the panel image quality.
  • the control end of the third controllable switch and the control end of the first controllable switch are both connected to the light-emitting control end, thereby reducing the number of signal lines, which is beneficial to product development. .
  • FIG. 10 is a schematic structural view of a display device of the present invention.
  • the display device includes any one of the above-mentioned pixel compensation circuits.
  • Other devices and functions of the display device are the same as those of the existing display device, and are not described herein again.
  • the pixel compensation circuit and the display device are reset by the second controllable switch, and the threshold voltage of the driving switch is captured by the first capacitor discharge and compensated, and the current is completely from the first stage in the compensation phase
  • the four controllable switches flow out without passing through the organic light emitting diode, avoiding the organic
  • the LED is smuggled, thereby avoiding the instability of the current of the organic light emitting diode caused by the threshold voltage drift, thereby improving the panel image quality.

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  • Computer Hardware Design (AREA)
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Abstract

一种像素补偿电路及显示装置，第一、第三、第四、第五可控开关（T1，T3，T4，T5）的控制端分别连发光控制端（EM）、控制信号（scan，EM）、第一及第二扫描信号（Xscan，Yscan）；第二可控开关（T2）的控制端连第二及第一可控开关（T2，T1）的第二端；驱动开关（T0）的控制端连第三可控开关（T3）的第二端，第一端连第一可控开关（T1）的第二端，第二端连第四可控开关（T4）的第二端及第五可控开关（T5）的第一端；第五可控开关（T5）的第二端连有机发光二极管（D1）的阳极；第二可控开关（T2）的第二端经第一电容（C1）连第三可控开关（T3）的第二端；第二可控开关（T2）的第二端经第二电容（C2）接收第二复位信号（Reset）。

Description

像素补偿电路及显示装置 【技术领域】
本发明涉及显示技术领域，特别是涉及一种像素补偿电路及显示装置。
【背景技术】
在显示装置领域，由于OLED显示装置相对LCD显示装置具有色域广、对比度高、节能、可折叠性等优点，在新世代显示装置中具有强有力的竞争力。此外，AMOLED技术是柔性显示重点发展方向之一。如图1所示，现有AMOLED显示装置的基本驱动电路包括一个开关薄膜晶体管T1、一个驱动薄膜晶体管T2和一个存储电容Cst，有机发光二极管OLED的驱动电流由驱动薄膜晶体管T1控制，其电流大小为：IOLED＝k(Vgs-Vth)2，其中，k为驱动薄膜晶体管T1的电流放大系数，由驱动薄膜晶体管T1本身特性决定，Vth为驱动薄膜晶体管T1的阈值电压，由于驱动薄膜晶体管T1的阈值电压Vth容易漂移，导致有机发光二极管OLED的驱动电流不稳定，影响面板画质。
【发明内容】
本发明主要解决的技术问题是提供一种像素补偿电路及显示装置，以避免阈值电压漂移造成有机发光二极管的电流不稳定，以此提升面板画质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素补偿电路，包括：
第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的第一端连接第一电压端，所述第一可控开关的控制端连接发光控制端；
第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接所述第二可控开关的第二端及所述第一可控开关的第二端，所述第二可控开关的第一端接收第一复位信号；
第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端接收控制信号，所述第三可控开关的第一端接收数据信号；
驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的 控制端连接所述第三可控开关的第二端，所述驱动开关的第一端连接所述第一可控开关的第二端；
第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端接收第一扫描信号，所述第四可控开关的第一端连接第二电压端，所述第四可控开关的第二端连接所述驱动开关的第二端；
第五可控开关，所述第五可控开关包括控制端、第一端及第二端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第一端连接所述驱动开关的第二端；
有机发光二极管，所述有机发光二极管包括阳极及阴极，所述阳极连接所述第五可控开关的第二端，所述阴极连接第三电压端；
第一电容，所述第一电容包括第一端及第二端，所述第一电容的第一端连接所述第二可控开关的第二端，所述第一电容的第二端连接所述第三可控开关的第二端；及
第二电容，所述第二电容包括第一端及第二端，所述第二电容的第一端连接所述第二可控开关的第二端，所述第二电容的第二端接收第二复位信号；
所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关均为PMOS型晶体管，所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、漏极及源极；
所述第三可控开关为PMOS型晶体管，所述第三可控开关的控制端接收的控制信号为第三扫描信号，所述第三可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、源极及漏极。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素补偿电路，包括：
第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的第一端连接第一电压端，所述第一可控开关的控制端连接发光控制端；
第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接所述第二可控开关的第二端及所述第一可控开关的第二端，所述第二可控开关的第一端接收第一复位信号；
第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第 三可控开关的控制端接收控制信号，所述第三可控开关的第一端接收数据信号；
驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第三可控开关的第二端，所述驱动开关的第一端连接所述第一可控开关的第二端；
第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端接收第一扫描信号，所述第四可控开关的第一端连接第二电压端，所述第四可控开关的第二端连接所述驱动开关的第二端；
第五可控开关，所述第五可控开关包括控制端、第一端及第二端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第一端连接所述驱动开关的第二端；
有机发光二极管，所述有机发光二极管包括阳极及阴极，所述阳极连接所述第五可控开关的第二端，所述阴极连接第三电压端；
第一电容，所述第一电容包括第一端及第二端，所述第一电容的第一端连接所述第二可控开关的第二端，所述第一电容的第二端连接所述第三可控开关的第二端；及
第二电容，所述第二电容包括第一端及第二端，所述第二电容的第一端连接所述第二可控开关的第二端，所述第二电容的第二端接收第二复位信号。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示装置，所述显示装置包括像素补偿电路，所述像素补偿电路包括：
第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的第一端连接第一电压端，所述第一可控开关的控制端连接发光控制端；
第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接所述第二可控开关的第二端及所述第一可控开关的第二端，所述第二可控开关的第一端接收第一复位信号；
第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端接收控制信号，所述第三可控开关的第一端接收数据信号；
驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第三可控开关的第二端，所述驱动开关的第一端连接所述第一可控开关的第二端；
第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第 四可控开关的控制端接收第一扫描信号，所述第四可控开关的第一端连接第二电压端，所述第四可控开关的第二端连接所述驱动开关的第二端；
第五可控开关，所述第五可控开关包括控制端、第一端及第二端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第一端连接所述驱动开关的第二端；
有机发光二极管，所述有机发光二极管包括阳极及阴极，所述阳极连接所述第五可控开关的第二端，所述阴极连接第三电压端；
第一电容，所述第一电容包括第一端及第二端，所述第一电容的第一端连接所述第二可控开关的第二端，所述第一电容的第二端连接所述第三可控开关的第二端；及
第二电容，所述第二电容包括第一端及第二端，所述第二电容的第一端连接所述第二可控开关的第二端，所述第二电容的第二端接收第二复位信号。
本发明的有益效果是：区别于现有技术的情况，本发明的所述像素补偿电路及显示装置通过所述第二可控开关进行复位，通过所述第一电容放电抓取所述驱动开关的阈值电压并进行补偿，并在补偿阶段使得电流全部从所述第四可控开关流出而不经过所述有机发光二极管，避免所述有机发光二极管偷亮，进而避免阈值电压漂移造成有机发光二极管的电流不稳定，以此提升面板画质。
【附图说明】
图1是现有显示装置的基本驱动电路的电路示意图；
图2是本发明的像素补偿电路的第一实施例的电路示意图；
图3是图2的电路时序波形示意图；
图4是图2的设定时序波形示意图；
图5是图2的仿真波形示意图；
图6是本发明的像素补偿电路的第二实施例的电路示意图；
图7是图6的电路时序波形示意图；
图8是图6的设定时序波形示意图；
图9是图6的仿真波形示意图；
图10是本发明的显示装置的结构示意图。
【具体实施方式】
请参阅图2，是本发明的像素补偿电路的第一实施例的电路示意图。所述像素补偿电路包括第一可控开关T1，所述第一可控开关T1包括控制端、第一端及第二端，所述第一可控开关T1的第一端连接第一电压端VDD，所述第一可控开关T1的控制端连接发光控制端EM；
第二可控开关T2，所述第二可控开关T2包括控制端、第一端及第二端，所述第二可控开关T2的控制端连接所述第二可控开关T2的第二端及所述第一可控开关T1的第二端，所述第二可控开关T2的第一端接收第一复位信号SW；
第三可控开关T3，所述第三可控开关T3包括控制端、第一端及第二端，所述第三可控开关T3的控制端接收控制信号，所述第三可控开关T3的第一端接收数据信号Data；
驱动开关T0，所述驱动开关T0包括控制端、第一端及第二端，所述驱动开关T0的控制端连接所述第三可控开关T3的第二端，所述驱动开关T0的第一端连接所述第一可控开关T1的第二端；
第四可控开关T4，所述第四可控开关T4包括控制端、第一端及第二端，所述第四可控开关T4的控制端接收第一扫描信号Xscan，所述第四可控开关T4的第一端连接第二电压端VCC，所述第四可控开关T4的第二端连接所述驱动开关T0的第二端；
第五可控开关T5，所述第五可控开关T5包括控制端、第一端及第二端，所述第五可控开关T5的控制端接收第二扫描信号Yscan，所述第五可控开关T5的第一端连接所述驱动开关T0的第二端；
有机发光二极管D1，所述有机发光二极管D1包括阳极及阴极，所述阳极连接所述第五可控开关T5的第二端，所述阴极连接第三电压端VSS；
第一电容C1，所述第一电容C1包括第一端及第二端，所述第一电容C1的第一端连接所述第二可控开关T2的第二端，所述第一电容C1的第二端连接所述第三可控开关T3的第二端；及
第二电容C2，所述第二电容C2包括第一端及第二端，所述第二电容C2的第一端连接所述第二可控开关T2的第二端，所述第二电容C2的第二端接收第二复位信号Reset。
在本实施例中，所述驱动开关T0、所述第一可控开关T1、所述第二可控开关T2、所述第四可控开关T4及所述第五可控开关T5均为PMOS型晶体管，所述驱动开关T0、所述第一可控开关T1、所述第二可控开关T2、所述第四可控 开关T4及所述第五可控开关T5的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、漏极及源极。
在本实施例中，所述第三可控开关T3为PMOS型晶体管，所述第三可控开关T3的控制端接收的控制信号为第三扫描信号scan，所述第三可控开关T3的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、源极及漏极。
在本实施例中，所述第二电压端VCC的电压设定值小于所述第三电压端VSS的电压设定值，所述有机发光二极管D1为主动阵列有机发光二极管，所述第一电容C1及所述第二电容C2为存储电容。
请参阅图2至图4，所述像素补偿电路的工作原理如下所示：
在复位阶段：所述第二可控开关T2导通，通过所述第二可控开关T2将S点电位拉高至Vs＝Vsw+Vth，其中，Vsw为所述第一复位信号SW输出的电压，Vth为所述第二可控开关T2的阈值电压，此时所述第二复位信号Reset的电位从电平变为高电平，G点电位Vg＝Vref，其中，Vref为参考电压；
在补偿阶段：当所述第二复位信号Reset电位从低电平变为高电平时，通过所述第二电容C2的耦合效应，S点电位被进一步拉高，此时，所述驱动开关T0导通，电位差储存在所述第一电容C1中，所述第一电容C1开始放电至S点电位为Vs＝Vref-Vth时，其中，Vref为参考电压，Vth为所述驱动开关T0的阈值电压，所述驱动开关T0截止，所述驱动开关T0的阈值电压Vth存储在所述第一电容C1中，此时，所述第四可控开关T4导通，所述第五可控开关T5截止，抓取所述驱动开关T0的阈值电压Vth的过程中电流全部从所述第四可控开关T4流出，避免了所述有机发光二极管D1偷亮；
在数据写入阶段：所述第三可控开关T3导通，所述第四可控开关T4及所述第五可控开关T5截止，此时G点电位Vg＝Vdata，其中，Vdata为所述数据信号的输出电压，通过所述第一电容C1和所述第二电容C2串联的作用，S点电位Vs＝[C2/(C1+C2)]*Vref+[C1/(C1+C2)]*Vdata-Vth，其中，C1为所述第一电容C1的电容值，C2为所述第二电容C2的电容值，Vref为参考电压，Vdata为数据信号的数据电压，Vth为驱动开关T0的阈值电压。因此，Vgs＝Vg-Vs＝[C2/(C1+C2)]*(Vdata-Vref)+Vth，因为通过所述有机发光二极管D1的电流I＝K*(Vgs-Vth)2，其中，K为所述驱动开关T0的电流放大系数，因此，I＝K*[C2/(C1+C2)]2*(Vdata-Vret)2；
在发光阶段：所述第一可控开关T1及所述第五可控开关T5均导通，所述第二可控开关T2、所述第三可控开关T3及所述第四可控开关T4均截止，所述有机发光二极管D1发光。
所述像素补偿电路通过所述第二可控开关T2对S点进行复位，通过所述第一电容C1放电抓取所述驱动开关T0的阈值电压Vth并进行补偿，并在补偿阶段使得电流全部从所述第四可控开关T4流出而不经过所述有机发光二极管D1，避免所述有机发光二极管D1偷亮，进而避免阈值电压漂移造成有机发光二极管D1的电流不稳定，以此提升面板画质。
请参阅图5，是本发明所述像素补偿电路的仿真波形示意图。从图5中可以看出，所述像素补偿电路通过S点放电抓取所述驱动开关T0的阈值电压Vth，并在抓取所述阈值电压Vth是使得电流全部从所述第四可控开关T4流出而不经过所述有机发光二极管D1，避免所述有机发光二极管D1发生偷亮，进而避免阈值电压漂移造成有机发光二极管D1的电流不稳定，以此提升面板画质。
请参阅图6，是本发明的像素补偿电路的第二实施例的电路示意图。所述像素补偿电路的第二实施例与上述第一实施例的区别之处在于：所述第三可控开关T3为NMOS型晶体管，所述第三可控开关T3的控制端接收的控制信号为所述发光控制端EM输出的控制信号，所述第三可控开关T3的控制端、第一端及第二端分别对应所述NMOS型晶体管的栅极、源极及漏极。
请参阅图6至图8，所述像素补偿电路的工作原理如下所示：
在复位阶段：所述第二可控开关T2导通，通过所述第二可控开关T2将S点电位拉高至Vs＝Vsw+Vth，其中，Vsw为所述第一复位信号SW输出的电压，Vth为所述第二可控开关T2的阈值电压，此时所述第二复位信号Reset的电位从电平变为高电平，G点电位Vg＝Vref，其中，Vref为参考电压；
在补偿阶段：当所述第二复位信号Reset电位从低电平变为高电平时，通过所述第二电容C2的耦合效应，S点电位被进一步拉高，此时，所述驱动开关T0导通，电位差储存在所述第一电容C1中，所述第一电容C1开始放电至S点电位为Vs＝Vref-Vth时，其中，Vref为参考电压，Vth为所述驱动开关T0的阈值电压，所述驱动开关T0截止，所述驱动开关T0的阈值电压Vth存储在所述第一电容C1中，此时，所述第四可控开关T4导通，所述第五可控开关T5截止，抓取所述驱动开关T0的阈值电压Vth的过程中电流全部从所述第四可控开关T4流出，避免了所述有机发光二极管D1偷亮；
在数据写入阶段：所述第三可控开关T3导通，所述第四可控开关T4及所述第五可控开关T5截止，此时G点电位Vg＝Vdata，其中，Vdata为所述数据信号的输出电压，通过所述第一电容C1和所述第二电容C2串联的作用，S点电位Vs＝[C2/(C1+C2)]*Vref+[C1/(C1+C2)]*Vdata-Vth，其中，C1为所述第一电容C1的电容值，C2为所述第二电容C2的电容值，Vref为参考电压，Vdata为数据信号的数据电压，Vth为驱动开关T0的阈值电压。因此，Vgs＝Vg-Vs＝[C2/(C1+C2)]*(Vdata-Vref)+Vth，因为通过所述有机发光二极管D1的电流I＝K*(Vgs-Vth)2，其中，K为所述驱动开关T0的电流放大系数，因此，I＝K*[C2/(C1+C2)]2*(Vdata-Vref)2；
在发光阶段：所述第一可控开关T1及所述第五可控开关T5均导通，所述第二可控开关T2、所述第三可控开关T3及所述第四可控开关T4均截止，所述有机发光二极管D1发光。
所述像素补偿电路通过所述第二可控开关T2对S点进行复位，通过所述第一电容C1放电抓取所述驱动开关T0的阈值电压Vth并进行补偿，并在补偿阶段使得电流全部从所述第四可控开关T4流出而不经过所述有机发光二极管D1，避免所述有机发光二极管D1偷亮，进而避免阈值电压漂移造成有机发光二极管D1的电流不稳定，以此提升面板画质。
请参阅图9，是本发明所述像素补偿电路的仿真波形示意图。从图9中可以看出，所述像素补偿电路通过S点放电抓取所述驱动开关的阈值电压Vth，并在抓取所述阈值电压Vth是使得电流全部从所述第四可控开关T4流出而不经过所述有机发光二极管D1，避免所述有机发光二极管D1发生偷亮，进而避免阈值电压漂移造成有机发光二极管D1的电流不稳定，以此提升面板画质。在图6所述的像素补偿电路中将所述第三可控开关的控制端与所述第一可控开关的控制端均连接至发光控制端，以此减少信号线数量，有利于产品开发。
请参阅图10，是本发明的显示装置的结构示意图。所述显示装置包括上述的像素补偿电路的任何一种，所述显示装置的其他器件及功能与现有显示装置的器件及功能相同，在此不再赘述。
所述像素补偿电路及显示装置通过所述第二可控开关进行复位，通过所述第一电容放电抓取所述驱动开关的阈值电压并进行补偿，并在补偿阶段使得电流全部从所述第四可控开关流出而不经过所述有机发光二极管，避免所述有机 发光二极管偷亮，进而避免阈值电压漂移造成有机发光二极管的电流不稳定，以此提升面板画质。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种像素补偿电路，其中，所述像素补偿电路包括：
    第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的第一端连接第一电压端，所述第一可控开关的控制端连接发光控制端；
    第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接所述第二可控开关的第二端及所述第一可控开关的第二端，所述第二可控开关的第一端接收第一复位信号；
    第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端接收控制信号，所述第三可控开关的第一端接收数据信号；
    驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第三可控开关的第二端，所述驱动开关的第一端连接所述第一可控开关的第二端；
    第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端接收第一扫描信号，所述第四可控开关的第一端连接第二电压端，所述第四可控开关的第二端连接所述驱动开关的第二端；
    第五可控开关，所述第五可控开关包括控制端、第一端及第二端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第一端连接所述驱动开关的第二端；
    有机发光二极管，所述有机发光二极管包括阳极及阴极，所述阳极连接所述第五可控开关的第二端，所述阴极连接第三电压端；
    第一电容，所述第一电容包括第一端及第二端，所述第一电容的第一端连接所述第二可控开关的第二端，所述第一电容的第二端连接所述第三可控开关的第二端；及
    第二电容，所述第二电容包括第一端及第二端，所述第二电容的第一端连接所述第二可控开关的第二端，所述第二电容的第二端接收第二复位信号；
    所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关均为PMOS型晶体管，所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、漏极及源极；
    所述第三可控开关为PMOS型晶体管，所述第三可控开关的控制端接收的控制信号为第三扫描信号，所述第三可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、源极及漏极。
  2. 一种像素补偿电路，其中，所述像素补偿电路包括：
    第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的第一端连接第一电压端，所述第一可控开关的控制端连接发光控制端；
    第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接所述第二可控开关的第二端及所述第一可控开关的第二端，所述第二可控开关的第一端接收第一复位信号；
    第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端接收控制信号，所述第三可控开关的第一端接收数据信号；
    驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第三可控开关的第二端，所述驱动开关的第一端连接所述第一可控开关的第二端；
    第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端接收第一扫描信号，所述第四可控开关的第一端连接第二电压端，所述第四可控开关的第二端连接所述驱动开关的第二端；
    第五可控开关，所述第五可控开关包括控制端、第一端及第二端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第一端连接所述驱动开关的第二端；
    有机发光二极管，所述有机发光二极管包括阳极及阴极，所述阳极连接所述第五可控开关的第二端，所述阴极连接第三电压端；
    第一电容，所述第一电容包括第一端及第二端，所述第一电容的第一端连接所述第二可控开关的第二端，所述第一电容的第二端连接所述第三可控开关的第二端；及
    第二电容，所述第二电容包括第一端及第二端，所述第二电容的第一端连接所述第二可控开关的第二端，所述第二电容的第二端接收第二复位信号。
  3. 根据权利要求2所述的像素补偿电路，其中，所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关均为PMOS型晶体管，所述驱动开关、所述第一可控开关、所述第二可控开关、所 述第四可控开关及所述第五可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、漏极及源极。
  4. 根据权利要求2所述的像素补偿电路，其中，所述第三可控开关为PMOS型晶体管，所述第三可控开关的控制端接收的控制信号为第三扫描信号，所述第三可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、源极及漏极。
  5. 根据权利要求2所述的像素补偿电路，其中，所述第三可控开关为NMOS型晶体管，所述第三可控开关的控制端接收的控制信号为所述发光控制端输出的控制信号，所述第三可控开关的控制端、第一端及第二端分别对应所述NMOS型晶体管的栅极、源极及漏极。
  6. 根据权利要求2所述的像素补偿电路，其中，所述第二电压端的电压设定值小于所述第三电压端的电压设定值，所述有机发光二极管为主动阵列有机发光二极管，所述第一电容及所述第二电容为存储电容。
  7. 一种显示装置，其中，所述显示装置包括像素补偿电路，所述像素补偿电路包括：
    第一可控开关，所述第一可控开关包括控制端、第一端及第二端，所述第一可控开关的第一端连接第一电压端，所述第一可控开关的控制端连接发光控制端；
    第二可控开关，所述第二可控开关包括控制端、第一端及第二端，所述第二可控开关的控制端连接所述第二可控开关的第二端及所述第一可控开关的第二端，所述第二可控开关的第一端接收第一复位信号；
    第三可控开关，所述第三可控开关包括控制端、第一端及第二端，所述第三可控开关的控制端接收控制信号，所述第三可控开关的第一端接收数据信号；
    驱动开关，所述驱动开关包括控制端、第一端及第二端，所述驱动开关的控制端连接所述第三可控开关的第二端，所述驱动开关的第一端连接所述第一可控开关的第二端；
    第四可控开关，所述第四可控开关包括控制端、第一端及第二端，所述第四可控开关的控制端接收第一扫描信号，所述第四可控开关的第一端连接第二电压端，所述第四可控开关的第二端连接所述驱动开关的第二端；
    第五可控开关，所述第五可控开关包括控制端、第一端及第二端，所述第五可控开关的控制端接收第二扫描信号，所述第五可控开关的第一端连接所述 驱动开关的第二端；
    有机发光二极管，所述有机发光二极管包括阳极及阴极，所述阳极连接所述第五可控开关的第二端，所述阴极连接第三电压端；
    第一电容，所述第一电容包括第一端及第二端，所述第一电容的第一端连接所述第二可控开关的第二端，所述第一电容的第二端连接所述第三可控开关的第二端；及
    第二电容，所述第二电容包括第一端及第二端，所述第二电容的第一端连接所述第二可控开关的第二端，所述第二电容的第二端接收第二复位信号。
  8. 根据权利要求7所述的显示装置，其中，所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关均为PMOS型晶体管，所述驱动开关、所述第一可控开关、所述第二可控开关、所述第四可控开关及所述第五可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、漏极及源极。
  9. 根据权利要求7所述的显示装置，其中，所述第三可控开关为PMOS型晶体管，所述第三可控开关的控制端接收的控制信号为第三扫描信号，所述第三可控开关的控制端、第一端及第二端分别对应所述PMOS型晶体管的栅极、源极及漏极。
  10. 根据权利要求7所述的显示装置，其中，所述第三可控开关为NMOS型晶体管，所述第三可控开关的控制端接收的控制信号为所述发光控制端输出的控制信号，所述第三可控开关的控制端、第一端及第二端分别对应所述NMOS型晶体管的栅极、源极及漏极。
  11. 根据权利要求7所述的显示装置，其中，所述第二电压端的电压设定值小于所述第三电压端的电压设定值，所述有机发光二极管为主动阵列有机发光二极管，所述第一电容及所述第二电容为存储电容。
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