WO2019000426A1 - 一种用于时分双工模式的功率放大电路 - Google Patents

一种用于时分双工模式的功率放大电路 Download PDF

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Publication number
WO2019000426A1
WO2019000426A1 PCT/CN2017/091244 CN2017091244W WO2019000426A1 WO 2019000426 A1 WO2019000426 A1 WO 2019000426A1 CN 2017091244 W CN2017091244 W CN 2017091244W WO 2019000426 A1 WO2019000426 A1 WO 2019000426A1
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circuit
time division
division duplex
power
resistance
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PCT/CN2017/091244
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English (en)
French (fr)
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黎峰
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上海诺基亚贝尔股份有限公司
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Priority to CN201780091318.7A priority Critical patent/CN110771034B/zh
Priority to PCT/CN2017/091244 priority patent/WO2019000426A1/zh
Publication of WO2019000426A1 publication Critical patent/WO2019000426A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • the utility model relates to the field of electronic technology, in particular to a power amplifying circuit for a time division duplex mode.
  • RF and microwave amplifiers provide optimum performance under specific bias conditions.
  • the quiescent current established by the bias point affects key performance indicators such as linearity and efficiency. Therefore, even if the ambient and device temperatures change significantly, the bias point of the RF amplifier needs to be properly stabilized to keep the quiescent current constant.
  • TDD Time division duplexing
  • FIG. 1 shows a schematic diagram of a prior art TDD RF/RF power amplifier circuit.
  • the FET Q1 acts as the main power transmitter, and the bias current is kept constant by the software control voltage Vg in the case of a change in operating temperature, thus requiring a temperature sensor. still need
  • Related peripheral resources ADC and FPGA For large-scale MIMO applications (up to 256 channels), a large number of temperature sensors, ADCs, and FPGA resources result in increased PCB size and cost. Since the bias current of each power transmitter needs to be kept constant, the use of a large number of power amplifiers at the same time results in software resource consumption.
  • a power amplifying circuit for a time division duplex mode characterized in that the power amplifying circuit comprises a power amplifying bias circuit and a time division duplex switching circuit;
  • the power amplification bias circuit is for generating a constant quiescent current in a power amplifier;
  • the power amplification bias circuit includes a first FET and a second FET, and the first FET and the second field
  • the effect tube forms a mirror current source;
  • the time division duplex switching circuit is configured to switch a resistance of a gate circuit connected in series to the power amplification bias circuit.
  • the utility model has the advantages of switching the resistance of the gate circuit connected in series to the power amplification bias circuit by the design of the mirror current source and by the time division duplex switching circuit, thereby satisfying the fast time division Simultaneously with the need for duplex switching, the quiescent current is kept constant in the RF amplifier;
  • the power amplifying circuit according to the present invention is realized by a simple and low-cost component, and does not require an additional temperature sensor, ADC or FPGA, etc., thereby facilitating integration
  • the chip to the power transmitter is less expensive.
  • Figure 1 illustrates a schematic diagram of a conventional TDD RF/RF power amplifier circuit
  • FIG. 2 is a schematic view of a power amplifying circuit in accordance with the present invention.
  • FIG. 3 schematically shows a schematic diagram of a power amplifying circuit in accordance with a preferred embodiment of the present invention.
  • FIG. 2 shows a schematic diagram of a power amplifying circuit in accordance with the present invention.
  • the power amplifying circuit according to the present invention is included in an amplifier.
  • the power amplifying circuit according to the present invention is included in a TDD Radio Radio Head (RRH).
  • RRH TDD Radio Radio Head
  • the power amplifying circuit includes a power amplifying bias circuit 1 and a time division duplex switching circuit 2.
  • the power amplification bias circuit 1 is used to generate a constant quiescent current in a power amplifier.
  • the power amplification bias circuit includes a first field effect transistor and a second field effect transistor, and the first field effect transistor and the second field effect transistor form a mirror current source.
  • the time division duplex switching circuit 2 is for switching the resistance of the gate circuit connected in series to the power amplification bias circuit 1.
  • the one end of the time division duplex switching circuit 2 is connected to a capacitor device, and the capacitor device is composed of a plurality of coupled capacitors.
  • the capacitive device is used for filtering and energy storage.
  • the first FET is used as a radio frequency power amplifier
  • the second FET is used as a mirror image of the first FET. If the quiescent current in the second FET is kept constant, the first FET The quiescent current in is kept constant.
  • the time division duplex switching circuit 2 switches the resistance of the gate circuit connected in series to the power amplification bias circuit based on the following rules: during the transient switching of the bias voltage, the power amplification bias is connected in series
  • the resistance of the gate circuit of the circuit 1 is a resistance with a small resistance value to meet the requirement of fast time division duplex conversion; when the ambient temperature changes, the resistance of the gate circuit connected in series to the power amplification bias circuit 1 has a large resistance value. Resistor to obtain better quiescent current temperature compensation in the power amplification bias circuit.
  • the time division duplex switching circuit 2 includes a plurality of switching transistors, a diode, and a plurality of resistors.
  • the switching transistor switches the resistance of the gate circuit connected in series to the power amplification bias circuit by a switch that controls the Vgs voltage.
  • the diode is used to compensate for the change in the turn-on time of the triode Vbe voltage as a function of temperature.
  • the switching transistor and the diode are made of the same semiconductor material to obtain a better temperature compensation effect.
  • a resistor is further included between the power amplification bias circuit 1 and the time division duplex switching circuit 2 for suppressing an oscillation peak generated by the power amplification bias circuit.
  • FIG. 3 shows a schematic diagram of a power amplifying circuit in accordance with a preferred embodiment of the present invention.
  • the power amplifying circuit includes a power amplifying bias circuit and a time division duplex switching circuit.
  • the power amplification bias circuit is used to generate a constant quiescent current in the power amplifier.
  • the time division duplex switching circuit is for switching the resistance of the gate circuit connected in series to the power amplification bias circuit.
  • the power amplification bias circuit comprises two FETs: Q1 and Q2; the time division duplex switching circuit comprises three switching transistors: Q3, Q4 and Q5, one diode D1, and eight resistors: R2 to R9, Among them, the resistance of R2 is greater than 1kohm, and the resistance of R3 is less than 10ohm (the resistance of R3 can be determined according to the switching speed of TDD transmission and transmission, and the product of it and C1 is time constant. If C1 is unchanged, the smaller the R3 is, the longer the switching time is. short).
  • One end of the time division duplex switching circuit is connected to a capacitor device C1 composed of a plurality of coupled capacitors, and the other end of C1 is grounded.
  • a resistor R1 and a choke inductor L1 are connected between the time division duplex switching circuit and the power amplifying bias circuit for suppressing an oscillation peak generated by the power amplifying bias circuit.
  • Q1 acts as the RF power amplifier and Q2 acts as the mirror image of the first FET. If the quiescent current in Q2 remains constant, the quiescent current in Q1 remains constant.
  • Q3, Q4, and Q5 switch the resistance of the gate circuit connected in series to the power amplification bias circuit by a switch that controls the Vgs voltage.
  • Switching transistors Q3, Q4 and Q5 and diode D1 use the same semiconductor materials. D1 compensates for the change in turn-on time of the Vbe voltage of Q4 as a function of temperature.
  • the working principle of the time division duplex switching circuit is as follows: during the transient switching of the bias voltage, the resistance of the gate circuit connected in series to the power amplification bias circuit is a resistance with a small resistance to meet the fast time division duplex conversion. It is required that when the ambient temperature changes, the resistance of the gate circuit connected in series to the power amplification bias circuit is a resistance with a large resistance value to obtain better quiescent current temperature compensation in the power amplification bias circuit.
  • Vg is set to the bias voltage of Q1.
  • Q5 also changes from on to off.
  • Vg together with R4, R5 and D1
  • D1 compensates for the change in the turn-on time of the Vbe voltage of Q4 as a function of temperature.
  • C1 is charged by R3. Due to the small resistance of R3, it can meet the requirements of fast TDD exchange.
  • Vgs desired gate voltage
  • R2 high value resistor
  • the resistance of the gate circuit connected in series to the power amplification bias circuit is switched by the design of the mirror current source and by the time division duplex switching circuit, thereby satisfying the requirement of fast time division duplex switching
  • the quiescent current is kept constant in the RF amplifier;
  • the power amplifying circuit according to the present invention is realized by a simple and low-cost component, and does not require an additional temperature sensor, ADC or FPGA, etc., so that it is easy to integrate into the chip of the power transmitter. And the cost is lower.

Abstract

一种用于时分双工模式的功率放大电路，其特征在于，所述功率放大电路包括功率放大偏置电路（1）和时分双工切换电路（2）；所述功率放大偏置电路（1）用于在功率放大器中产生恒定的静态电流；所述功率放大偏置电路（1）包括第一场效应管和第二场效应管，并且，第一场效应管和第二场效应管形成镜像电流源；所述时分双工切换电路（2）用于切换串联至所述功率放大偏置电路（1）的门电路的电阻。该功率放大电路具有以下优点：满足快速时分双工切换的需求的同时，在射频放大器中保持静态电流恒定；由简单且造价较低的元件实现，易于集成到功率发射器的芯片，且成本较低。

Description

一种用于时分双工模式的功率放大电路 技术领域
本实用新型涉及电子技术领域，尤其涉及一种用于时分双工模式的功率放大电路。
背景技术
射频和微波放大器可在特定偏置条件下提供最佳性能。由偏置点建立的静态电流会影响线性和效率等关键性能指标。因此，即使环境和器件温度发生显著变化，仍需适当地稳定射频放大器的偏置点，以维持静态电流恒定。
在即将到来的5G时代，大规模的MIMO技术将被广泛应用于提高4G和5G频段的覆盖率和用户体验。软件工程师通常必须面对大规模MIMO技术所带来的、多达256个通道的功率放大器的实时偏置温度补偿(Temperature Compensation，TC)。此外，为了获得功率放大器的工作温度作为SW温度补偿(TC)的参考，需要在每一个功率放大器附近放置一个温度传感器。这导致了对大量的信号线路(数字温度传感器，如SPI接口)或ADC通道(模拟温度传感器，模拟值通过ADC转换成数字值)的需求。这无疑增加了印制电路板(Printed Circuit Board，PCB)尺寸和复杂度以及元件成本。
为了改善这种情况，一种纯硬件的偏置TC设计被提出。有源偏置补偿电路能在功率放大器的静态电流下获得良好的热跟踪效果，并且由于所需元件不多，可以很容易地集成到目标功率放大器器件中。由于频谱划分的灵活性，时分双工(TDD)仍然是5G技术的关键要素。然而，传统的有源偏置补偿放大器在TDD工作模式下会面临两难选择，因为阻值较大的反馈电阻有利于热跟踪，但对TDD偏置开关速度不利。
图1示了一种现有的TDD射频/射频功率放大器电路的示意图。场效应管Q1作为主功率发射器，在工作温度变化的情况下，通过软件控制电压Vg来保持其偏置电流恒定，因此需要一个温度传感器。还需要 相关的外围资源ADC和FPGA。对于大规模的MIMO应用程序(最多256个通道)，大量的温度传感器、ADC和FPGA资源导致PCB尺寸和成本的增加。由于每一个功率发射器的偏置电流都需要保持恒定，所以同时采用大量功率放大器会导致软件资源消耗。
因此，如图1所示的方案对于4G等较少的信道应用是可以接受的，但对于5G时代，特别是大规模MIMO应用，硬件和软件成本的巨大增长是不可接受的。
实用新型内容
本实用新型的目的是提供一种用于时分双工模式的功率放大电路。
根据本实用新型的一个方面，提供了一种用于时分双工模式的功率放大电路，其特征在于，所述功率放大电路包括功率放大偏置电路和时分双工切换电路；
所述功率放大偏置电路用于在功率放大器中产生恒定的静态电流；所述功率放大偏置电路包括第一场效应管和第二场效应管，并且，第一场效应管和第二场效应管形成镜像电流源；
所述时分双工切换电路用于切换串联至所述功率放大偏置电路的门电路的电阻。
与现有技术相比，本实用新型具有以下优点：通过镜像电流源的设计，并通过时分双工切换电路来切换串联至所述功率放大偏置电路的门电路的电阻，从而在满足快速时分双工切换的需求的同时，在射频放大器中保持静态电流恒定；根据本实用新型的功率放大电路由简单且造价较低的元件实现，无需额外的温度传感器、ADC或FPGA等器件，从而易于集成到功率发射器的芯片，且成本较低。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本实用新型的其它特征、目的和优点将会变得更明显：
图1示意出了一种现有的TDD射频/射频功率放大器电路的示意图；
图2示意出了根据本实用新型的一种功率放大电路的示意图；
图3示意示出了根据本实用新型的一个优选实施例的功率放大电路的示意图。
附图中相同或相似的附图标记代表相同或相似的部件。
具体实施方式
下面结合附图对本实用新型作进一步详细描述。
图2示出了根据本实用新型的一种功率放大电路的示意图。
优选地，根据本实用新型的功率放大电路包含于放大器中。
更优选地，根据本实用新型的功率放大电路包含于TDD射频拉远头(Remote Radio Head，RRH)中。
参照图2，根据本实用新型的功率放大电路包括功率放大偏置电路1和时分双工切换电路2。
所述功率放大偏置电路1用于在功率放大器中产生恒定的静态电流。所述功率放大偏置电路包括第一场效应管和第二场效应管，并且，第一场效应管和第二场效应管形成镜像电流源。
所述时分双工切换电路2用于切换串联至所述功率放大偏置电路1的门电路的电阻。
其中，所述时分双工切换电路2的一端与电容装置相连，所述电容装置由多个耦合的电容器组成。所述电容装置用于滤波和储能。
优选地，所述第一场效应管作为射频功率放大器，所述第二场效应管作为第一场效应管的镜像，如果第二场效应管中的静态电流保持恒定，则第一场效应管中的静态电流保持恒定。
优选地，所述时分双工切换电路2基于以下规则对串联至所述功率放大偏置电路的门电路的电阻进行切换：在偏置电压的瞬态切换期间，串联至所述功率放大偏置电路1的门电路的电阻为阻值小的电阻，以满足快速时分双工转换的要求；在环境温度变化时，串联至所述功率放大偏置电路1的门电路的电阻为阻值大的电阻，以在功率放大偏置电路中获得较好的静态电流温度补偿。
优选地，所述时分双工切换电路2包括多个开关三极管，一个二极管，以及多个电阻。
其中，所述开关三极管通过控制Vgs电压的开关来切换串联至所述功率放大偏置电路的门电路的电阻。
所述二极管用于对开关三极管的进行补偿由于三极管Vbe电压随温度变化而带来的开启时间的变化。
优选地，所述开关三极管和二极管采用同类半导体材料，以获得较好的温度补偿效果。
优选地，在所述功率放大偏置电路1和时分双工切换电路2之间还包括电阻，该电阻用于抑制功率放大偏置电路所产生的振荡峰值。
图3示出了根据本实用新型的一个优选实施例的功率放大电路的示意图。参照图3，该功率放大电路包括功率放大偏置电路和时分双工切换电路。该功率放大偏置电路用于在功率放大器中产生恒定的静态电流。该时分双工切换电路用于切换串联至所述功率放大偏置电路的门电路的电阻。
其中，该功率放大偏置电路包括两个场效应管：Q1和Q2；该时分双工切换电路包括三个开关三极管：Q3、Q4和Q5，一个二极管D1，以及8个电阻：R2至R9，其中，R2的阻值大于1kohm，R3的阻值小于10ohm(R3的阻值可以根据TDD的收发切换速度决定，它和C1的乘积为时间常数，如果C1不变，R3越小则切换时间越短)。
该时分双工切换电路的一端与电容装置C1相连，该电容装置C1由多个耦合的电容器组成，C1的另一端接地。在时分双工切换电路和功率放大偏置电路之间，连接有电阻R1和扼流电感L1，用于抑制功率放大偏置电路所产生的振荡峰值。
在功率放大偏置电路中，Q1作为射频功率放大器，Q2作为第一场效应管的镜像，如果Q2中的静态电流保持恒定，则Q1中的静态电流保持恒定。
在时分双工切换电路中，Q3、Q4和Q5通过控制Vgs电压的开关来切换串联至功率放大偏置电路的门电路的电阻。开关三极管Q3、Q4和 Q5和二极管D1采用同类半导体材料。D1可补偿Q4的Vbe电压随温度变化而带来的开启时间的变化。
该时分双工切换电路的工作原理如下：在偏置电压的瞬态切换期间，串联至所述功率放大偏置电路的门电路的电阻为阻值小的电阻，以满足快速时分双工转换的要求；在环境温度变化时，串联至所述功率放大偏置电路的门电路的电阻为阻值大的电阻，以在功率放大偏置电路中获得较好的静态电流温度补偿。
Vg设置为Q1的偏置电压。当Q3从开启变为关闭，Q5也从开启变为关闭。Vg，与R4、R5和D1一起构成分压器，其输出电压将Q4开启。D1补偿Q4的Vbe电压随温度变化而带来的开启时间的变化。然后，在Q4接通后，C1被R3充电。由于R3的阻值较小，可以满足快速TDD交换的要求。当C1的电压要接近想要的栅极电压(Vgs)，其等于或高于电压分压器的输出电压(VG，R4和R5)，Q4逐渐的由开启变为关闭。门电路中串联的电阻由R3(低值电阻)转变为R2(高值电阻)，则Q1工作时可获得良好的静态电流温度补偿。
根据本实用新型的方案，通过镜像电流源的设计，并通过时分双工切换电路来切换串联至所述功率放大偏置电路的门电路的电阻，从而在满足快速时分双工切换的需求的同时，在射频放大器中保持静态电流恒定；根据本实用新型的功率放大电路由简单且造价较低的元件实现，无需额外的温度传感器、ADC或FPGA等器件，从而易于集成到功率发射器的芯片，且成本较低。
对于本领域技术人员而言，显然本实用新型不限于上述示范性实施例的细节，而且在不背离本实用新型的精神或基本特征的情况下，能够以其他的具体形式实现本实用新型。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本实用新型的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化涵括在本实用新型内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。此外，显然“包括”一词不排除其他单元或步骤，单数不排除复数。系统权利要求中 陈述的多个单元或装置也可以由一个单元或装置通过软件或者硬件来实现。第一，第二等词语用来表示名称，而并不表示任何特定的顺序。

Claims (7)

  1. 一种用于时分双工模式的功率放大电路，其特征在于，所述功率放大电路包括功率放大偏置电路和时分双工切换电路；
    所述功率放大偏置电路用于在功率放大器中产生恒定的静态电流；所述功率放大偏置电路包括第一场效应管和第二场效应管，并且，第一场效应管和第二场效应管形成镜像电流源；
    所述时分双工切换电路用于切换串联至所述功率放大偏置电路的门电路的电阻。
  2. 根据权利要求1所述的功率放大电路，其特征在于，所述第一场效应管作为射频功率放大器，所述第二场效应管作为第一场效应管的镜像，如果第二场效应管中的静态电流保持恒定，则第一场效应管中的静态电流保持恒定。
  3. 根据权利要求1所述的功率放大电路，其特征在于，所述时分双工切换电路基于以下规则对串联至所述功率放大偏置电路的门电路的电阻进行切换：在偏置电压的瞬态切换期间，串联至所述功率放大偏置电路的门电路的电阻为阻值小的电阻，以满足快速时分双工转换的要求；在环境温度变化时，串联至所述功率放大偏置电路的门电路的电阻为阻值大的电阻，以在功率放大偏置电路中获得较好的静态电流温度补偿。
  4. 根据权利要求3所述的功率放大电路，其特征在于，所述时分双工切换电路包括多个开关三极管，一个二极管，以及多个电阻；
    其中，所述开关三极管通过控制Vgs电压的开关来切换串联至所述功率放大偏置电路的门电路的电阻；
    所述二极管用于对开关三极管的进行补偿由于三极管Vbe电压随温度变化而带来的开启时间的变化。
  5. 根据权利要求3所述的功率放大电路，其特征在于，所述开关三极管和二极管采用同类半导体材料。
  6. 根据权利要求1所述的功率放大电路，其特征在于，所述时分双 工切换电路的一端与电容装置相连，所述电容装置由多个耦合的电容器组成。
  7. 根据权利要求1所述的功率放大电路，其特征在于，在所述功率放大偏置电路和时分双工切换电路之间还包括电阻，该电阻用于抑制功率放大偏置电路所产生的振荡峰值。
PCT/CN2017/091244 2017-06-30 2017-06-30 一种用于时分双工模式的功率放大电路 WO2019000426A1 (zh)

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