WO2022095026A1 - 放大电路、芯片及电子设备 - Google Patents

放大电路、芯片及电子设备 Download PDF

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Publication number
WO2022095026A1
WO2022095026A1 PCT/CN2020/127517 CN2020127517W WO2022095026A1 WO 2022095026 A1 WO2022095026 A1 WO 2022095026A1 CN 2020127517 W CN2020127517 W CN 2020127517W WO 2022095026 A1 WO2022095026 A1 WO 2022095026A1
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Prior art keywords
transistor
gate
amplifying circuit
capacitance
voltage
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PCT/CN2020/127517
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English (en)
French (fr)
Inventor
刘伟
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/127517 priority Critical patent/WO2022095026A1/zh
Priority to CN202080106959.7A priority patent/CN116569481A/zh
Publication of WO2022095026A1 publication Critical patent/WO2022095026A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

Definitions

  • the present application relates to the field of electronic technology, and in particular, to an amplifier circuit, a chip and an electronic device.
  • Amplifier circuits are the most widely used circuits in analog electronics.
  • the amplifying circuit usually adopts a Cascode (cascade) structure, also known as a cascode-cascode structure or a cascode-cascode structure.
  • Cascode cascade
  • the transistor Q1 and the transistor Q2 form a Cascode structure, that is, the emitter/source of the transistor Q1 is coupled to the collector/drain of the transistor Q2.
  • the amplification factor of the amplifier circuit in FIG. 1 is related to the transistor Q1 , the transistor Q2 , the resistor R1 , and the like.
  • the amplifier circuit in the prior art can only achieve a fixed amplification factor. If the amplification factor of the amplifier circuit needs to be changed, the resistance R1 in the amplifier circuit is usually changed to change the amplification factor of the amplifier circuit. The way the technology changes the magnification of the amplifying circuit has large constraints and is not flexible enough.
  • the present application provides an amplifying circuit, a chip and an electronic device, which can improve the flexibility and applicability of changing the magnification of the amplifying circuit.
  • an embodiment of the present application provides an amplifier circuit, the amplifier circuit includes a first transistor, a second transistor and a variable capacitance unit, the first transistor and the second transistor form a Cascode (cascade) structure, wherein the The gate/base terminal of the first transistor is used for receiving the first bias voltage and the input signal, the source/emitter terminal of the first transistor is coupled with the reference ground; the gate/base terminal of the second transistor is used for receiving the first transistor.
  • variable capacitance unit Two bias voltages, coupled with the variable capacitance unit, the variable capacitance unit is used to adjust the capacitance value between the gate/base terminal of the second transistor and the reference ground; the drain/collection of the second transistor
  • the electrode terminal is used for outputting the output signal obtained after the above-mentioned input signal is amplified by the amplifying circuit.
  • the present application changes the amplification factor of the amplification circuit by adjusting the capacitance value between the gate/base terminal of the second transistor and the reference ground in the amplification circuit, which can improve the flexibility of changing the amplification factor of the amplification circuit, and has strong applicability.
  • variable capacitance unit is configured to adjust the capacitance value between the gate/base terminal of the second transistor and the reference ground according to the operating temperature of the amplifier circuit.
  • the operating temperature of the amplifying circuit may specifically refer to the temperature of the chip where the amplifying circuit is located or the temperature of a printed circuit board (PCB) where the amplifying circuit is located.
  • the capacitance value between the gate/base terminal of the second transistor and the reference ground is controlled according to the operating temperature of the amplifying circuit, so as to control the amplification factor of the amplifying circuit.
  • the working temperature of the amplifying circuit is not normal temperature, the gain temperature drift of the amplifying circuit can be compensated.
  • the amplification circuit provided by the embodiment of the present application can keep its own amplification factor unchanged when its own operating temperature changes.
  • the amplifying circuit further includes a temperature monitoring module, and the temperature monitoring module is configured to generate a capacitance control signal according to the monitored operating temperature of the amplifying circuit , so that the variable capacitance unit adjusts the capacitance value according to the capacitance value control signal.
  • variable capacitance unit in combination with the second possible implementation manner of the first aspect, includes a varactor diode, and the capacitance control signal includes a voltage signal applied to one end of the varactor diode, Used to control the voltage difference across the varactor.
  • variable capacitance unit includes a field effect transistor
  • the capacitance control signal includes a gate or source applied to the field effect transistor.
  • the voltage signal is used to control the voltage difference between the gate electrode and the source electrode of the field effect transistor, wherein the source electrode and the drain electrode of the field effect transistor are connected.
  • variable capacitance unit includes a triode
  • the capacitance control signal includes a voltage signal applied to the base of the triode for controlling The voltage difference between the base and the collector of the triode, wherein the base of the triode is connected to the emitter; or used to control the voltage difference between the base and the emitter of the triode, wherein the base of the triode is connected to the emitter.
  • Collector is connected.
  • variable capacitance unit in combination with the first aspect or in combination with any of the first to second possible implementation manners of the first aspect, includes at least two capacitors and at least one switch.
  • a switch is used to control any one or more of the at least two capacitors to be connected between the gate/base terminal of the second transistor and the reference ground according to the capacitance control signal.
  • the above-mentioned first bias voltage and/or the above-mentioned second bias voltage are generated by a bias current source.
  • the above-mentioned amplifying circuit further includes a third transistor, wherein the drain/collector terminal of the third transistor is connected to the above-mentioned bias current source coupled, and the drain/collector terminal of the third transistor and the gate/base terminal of the third transistor are both coupled with the gate/base terminal of the first transistor, and the source/emitter terminal of the third transistor is The above is coupled with reference to ground.
  • an embodiment of the present application provides a chip, on which the amplifying circuit of the first aspect or any possible implementation manner of the first aspect is disposed.
  • an embodiment of the present application provides an electronic device, where the electronic device includes the chip described in the second aspect.
  • 1 is a circuit diagram of an amplifier circuit in the prior art
  • FIG. 2 is a structural block diagram of an amplifying circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a gain temperature drift of an amplifying circuit in the prior art
  • FIG. 4 is another structural block diagram of an amplifier circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a gain temperature drift compensation of an amplifier circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a linearity temperature drift of an amplifier circuit provided by an embodiment of the present application.
  • FIG. 7 is a circuit diagram of an amplifying circuit provided by an embodiment of the present application.
  • FIG. 8 is another circuit diagram of the amplifying circuit provided by the embodiment of the present application.
  • FIG. 9 is another circuit diagram of the amplifying circuit provided by the embodiment of the present application.
  • FIG. 10 is another circuit diagram of the amplifying circuit provided by the embodiment of the application.
  • FIG. 11 is a structural block diagram of a variable capacitance unit provided by an embodiment of the present application.
  • FIG. 12 is another structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • FIG. 13 is another structural block diagram of a variable capacitance unit provided by an embodiment of the present application.
  • variable capacitance unit 14 is another structural block diagram of a variable capacitance unit provided by an embodiment of the present application.
  • variable capacitance unit 15 is another structural block diagram of a variable capacitance unit provided by an embodiment of the present application.
  • 16 is another structural block diagram of a variable capacitance unit provided by an embodiment of the present application.
  • FIG. 17 is a schematic diagram of a chip provided by an embodiment of the present application.
  • the amplifying circuit provided by the embodiment of the present application is suitable for a scenario of amplifying the amplitude of an electrical signal, and can be specifically applied to various devices such as communication, broadcasting, television, and automatic control.
  • the amplifying circuit may be located between the input source and the load.
  • the input source is used to provide an input signal to the amplifying circuit, and the input source may be, for example, an output terminal of an electronic circuit, a digital-to-analog converter (Digital to Analog Converter, DAC), and the like.
  • the load is used to receive the amplified output signal of the amplifying circuit, and the load may be, for example, a speaker, an input end of an electronic circuit, or the like.
  • the above-mentioned electronic circuits include but are not limited to the amplifier circuits provided in the embodiments of the present application.
  • the amplifier circuit provided in the embodiment of the present application may be disposed inside the chip, and the components included in the amplifier circuit may be made of silicon by doping, exposing and other processes on the silicon. completed.
  • FIG. 2 is a structural block diagram of an amplifying circuit provided by an embodiment of the present application.
  • the amplifier circuit 20 includes a first transistor 201 , a second transistor 202 and a variable capacitance unit 203 .
  • the gate/base terminal of the first transistor 201 receives the first bias voltage and the input signal VIN, and the source/emitter terminal of the first transistor 201 is coupled to the reference ground.
  • the reference ground can be understood as having a potential terminal for providing the AC ground. For example, it may be 1.8V, 1.25V, or 0V, etc. The application does not limit the voltage value of the reference ground.
  • connection between A and B can be either a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as a direct connection between A and C, and a direct connection between C and B. , so that A and B are connected through C.
  • the source/emitter terminal of the first transistor 201 may be connected to the reference ground through a matching inductor.
  • the first transistor 201 and the second transistor 202 form a Cascode structure.
  • the drain/collector terminal of the first transistor 201 is coupled with the source/emitter terminal of the second transistor 202
  • the gate/base terminal of the second transistor 202 receives the second bias voltage, and is connected with the variable capacitor Unit 203 is coupled.
  • variable capacitance unit 203 can control the amplification factor of the input signal VIN by the amplifying circuit 20 by adjusting the capacitance value between the gate/base terminal of the second transistor 202 and the reference ground.
  • the amplification factor of the input signal VIN by the amplifier circuit 20 is positively correlated with the capacitance value of the variable capacitance unit 203 (ie, positively correlated with the capacitance value between the gate/base terminal of the second transistor 202 and the reference ground).
  • the capacitance value between the gate/base terminal of the second transistor 202 and the reference ground increases, and the amplification factor of the input signal VIN by the amplifier circuit 20 also increases.
  • the drain/collector terminal of the second transistor 202 outputs the output signal VOUT obtained after the above-mentioned input signal VIN is amplified by the amplifying circuit 20 .
  • the amplification factor of the amplification circuit is changed by adjusting the capacitance value between the gate/base terminal of the second transistor in the amplification circuit and the reference ground, which can improve the flexibility of changing the amplification factor of the amplification circuit, and has strong applicability .
  • the first bias voltage and/or the second bias voltage may be generated by a voltage source.
  • the gate/base terminal of the first transistor 201 is coupled to the first voltage source
  • the gate/base terminal of the second transistor 202 is coupled to the second voltage source. It can be understood that the first voltage source and the second voltage source The source can be the same voltage source or different voltage sources.
  • the first bias voltage and/or the second bias voltage may be generated by a bias current source.
  • the gate/base terminals of the first transistor 201 are coupled to a first bias current source, which may, for example, provide the bias current i1 shown in FIG. 2 .
  • the gate/base terminals of the second transistor 202 are coupled to a second bias current source. It can be understood that the first bias current source and the second bias current source may be the same bias current source, or may be different bias current sources.
  • first bias voltage and the second bias voltage may be generated in the same manner, or may be different, for example, the first bias voltage and the second bias voltage are both generated by a bias current source; or the first bias voltage The voltage is generated by the bias current source, the second bias voltage is generated by the voltage source; or the first bias voltage is generated by the voltage source, the second bias voltage is generated by the bias current source, etc. . This application does not limit how this bias voltage is generated.
  • FIG. 3 is a schematic diagram of a gain temperature drift of an amplifying circuit in the prior art. As shown in Figure 3, due to the different operating temperatures of the amplifier circuit, such as the chip temperature of the chip where the amplifier circuit is located or the temperature of the PCB where the amplifier circuit is located, the positions of curve 1, curve 2 and curve 3 are different.
  • the gain curve of the amplifier circuit in the prior art is the curve 1 shown in FIG. 3 .
  • the room temperature is used as the reference temperature for illustrative description, and should not be construed as limiting the reference temperature, and the operating temperature of the amplifier circuit may also be other preset temperatures.
  • the gain curve of the amplifying circuit in the prior art is the curve 2 shown in FIG. 3 , that is, when the operating temperature of the amplifying circuit increases, the amplification factor of the amplifying circuit decreases.
  • the gain curve of the amplifying circuit in the prior art is the curve 3 shown in FIG.
  • the gain temperature drift of the amplifier circuit can be embodied in that the loudness of the loudspeaker is low when the temperature is higher than the normal temperature, and the loudness is high when the temperature is lower than the normal temperature.
  • the gain temperature drift of the amplifying circuit can be embodied as the display screen has low brightness when the temperature is higher than normal temperature, and high brightness when the temperature is lower than the normal temperature.
  • the amplifier circuit provided by the embodiment of the present application can compensate for its own gain temperature drift in real time.
  • FIG. 4 is another structural block diagram of the amplifying circuit provided by the embodiment of the present application.
  • the amplifier circuit 40 includes a first transistor 401 , a second transistor 402 , a variable capacitance unit 403 and a temperature monitoring module 404 .
  • the relationship among the first transistor 401 , the second transistor 402 and the variable capacitance unit 403 can be referred to the embodiment described above in conjunction with FIG. 2 , and details are not repeated here.
  • variable capacitance unit 403 may adjust the capacitance value between the gate/base terminal of the second transistor 402 and the reference ground according to the operating temperature of the amplifying circuit 40 .
  • the above-mentioned capacitance control signal may be generated by the amplifying circuit 40 .
  • the variable capacitance unit 403 is coupled with the temperature monitoring module 404 .
  • the temperature monitoring module 404 can monitor the operating temperature of the amplifier circuit 40 , for example, monitor the chip temperature of the chip where the amplifier circuit 40 is located or the temperature of the PCB where the amplifier circuit 40 is located.
  • the temperature monitoring module 404 generates the capacitance control signal according to the monitored operating temperature of the amplifier circuit 40.
  • the temperature monitoring module 404 can obtain the output signal VOUT of the amplifier circuit 40 based on the amplitude of the output signal VOUT and the reference signal (for example, The amplifying circuit 40 outputs the amplitude of the signal at normal temperature) to determine whether the operating temperature of the amplifying circuit is higher or lower than the normal temperature, and generates a capacitance control signal.
  • the variable capacitance unit 403 adjusts its own capacitance according to the capacitance control signal (ie, adjusts the capacitance between the gate/base terminal of the second transistor 402 and the reference ground).
  • the temperature monitoring module 404 may send the capacitance control signal to the variable capacitance unit 403, so that the variable capacitance unit 403 adjusts the gate/base terminal and the reference of the second transistor 402 based on the capacitance control signal. capacitance between ground.
  • the temperature monitoring module 404 may be, for example, a current generation circuit proportional to absolute temperature (PTAT) in the prior art, the output current of the PTAT current generation circuit is applied to both ends of a resistor, and the voltage difference between the two ends of the resistor is That is, it can be the above-mentioned capacitance control signal.
  • the PTAT current generating circuit may be a circuit formed by coupling a cascode current mirror and a triode, the triode is used to generate the PTAT current, and the cascode current mirror is used to stabilize the PTAT current.
  • the PTAT current generating circuit is only illustratively described, and the PTAT current generating circuit has various possible implementation manners, which are not limited in this application.
  • the capacitance control signal may be input to the variable capacitance unit 403 from the outside of the amplifying circuit 40 .
  • the temperature monitoring module is not provided in the amplification circuit 40, for example, the PCB where the amplification circuit 40 is located is provided with a temperature sensor to sense the working temperature of the amplification circuit 40 in real time, and the temperature sensor will sense the working temperature of the amplification circuit 40.
  • the amplifying circuit 40 It is sent to the outside of the amplifying circuit 40 (for example, it may be a processor, other electronic circuits, etc.), so that the processor or electronic circuit, etc., generate a capacitance control signal based on the operating temperature of the amplifying circuit 40 and a preset temperature (for example, normal temperature), and The capacitance control signal is sent to the variable capacitance unit 403 in the amplifier circuit 40 .
  • a preset temperature for example, normal temperature
  • the above-mentioned capacitance value control signal may represent different voltage values.
  • the voltage value may be a continuous voltage (ie, an analog voltage) or a discontinuous voltage (ie, a digital voltage).
  • the variable capacitance unit 403 can adjust the capacitance value between the gate/base terminal of the second transistor 402 and the reference ground according to different voltage values.
  • the capacitance control signal can be expressed as the voltage difference across the resistor, and the input current of the resistor is the PTAT current output by the PTAT current generating circuit.
  • the amplification factor of the amplifying circuit 40 when the operating temperature of the amplifying circuit 40 is higher than normal temperature, the amplification factor of the amplifying circuit 40 is reduced, and the variable capacitance unit 403 can connect the gate/base terminal of the second transistor 402 to the reference according to the capacitance value control signal The capacitance value between the ground increases, so that the amplification factor of the amplifier circuit 40 increases.
  • the amplification factor of the amplifier circuit 40 can be increased to the amplification factor when the operating temperature of the amplifier circuit 40 is normal temperature.
  • FIG. 5 is a schematic diagram of the gain temperature drift compensation of the amplifier circuit provided by the embodiment of the present application. As shown in FIG.
  • the curve 4 is the gain curve when the operating temperature of the amplifier circuit 40 is higher than the normal temperature.
  • the temperature drift of the gain (that is, the amplification factor) of the amplifier circuit 40 in the embodiment of the present application is improved.
  • the amplification factor of the amplifier circuit 40 is improved. It is also close to the magnification when its own operating temperature is normal temperature. That is, curve 4 can overlap with curve 1 .
  • the amplification factor of the amplifying circuit 40 increases, and the variable capacitance unit 403 can connect the gate/base terminal of the second transistor 402 to the reference ground according to the capacitance control signal.
  • the capacitance value becomes smaller, so that the amplification factor of the amplifying circuit 40 can be reduced.
  • the amplification factor of the amplifying circuit 40 may be reduced to the amplification factor when the operating temperature of the amplifying circuit 40 is normal temperature.
  • reference may be made to the curve 5 shown in FIG. 5 and the curve 5 is the gain curve when the operating temperature of the amplifier circuit 40 is lower than the normal temperature. Compared with the curve 3 shown in FIG.
  • the amplifying circuit 40 in this embodiment of the present application may be applied to a speaker, a display screen, and the like.
  • the amplifying circuit 40 of the embodiment of the present application can compensate the temperature drift of its own gain in real time, so that the loudness of the sound played by the speaker at different temperatures is consistent, and/or the display brightness of the display screen at different temperatures is consistent.
  • the above is an example of the usage scenarios of the amplifier circuit provided by the embodiment of the present application, and is not exhaustive, and it should be understood that the amplifier circuit provided by the embodiment of the present application can be applied to any scene that needs to compensate for its own gain temperature drift.
  • the embodiment of the present application controls the amplification factor of the amplifying circuit by controlling the capacitance value between the gate/base terminal of the second transistor and the reference ground according to the operating temperature of the amplifying circuit.
  • the amplification circuit provided by the embodiment of the present application can keep its own amplification factor unchanged when its own operating temperature changes.
  • the performance index for measuring the amplifier circuit 40 also includes the linearity of the amplifier circuit 40 .
  • the linearity of the amplifier circuit 40 can be understood as the amplifier circuit 40 is in a linear dynamic range, and the output power increases linearly with the input power.
  • the first bias voltage received by the first transistor 401 is generated by a bias current source, and the bias current source provides a bias current i1 to the first transistor 401 .
  • the linearity of the amplifier circuit 40 is related to the bias current i1 of the first transistor 401 .
  • the bias current i1 may be a PTAT current.
  • the bias current i1 may be a current that does not vary with temperature, such as a bandgap reference (Bandgap, BG) current.
  • a bandgap reference Bandgap reference
  • FIG. 6 is a schematic diagram of the linearity temperature drift of the amplifying circuit provided by the embodiment of the present application. It should be noted first that the ordinate in Figure 6 is the output third-order intermodulation power (Output 3th Intercept Point, OIP3), and OIP3 is a parameter used to measure the linearity of the amplifier circuit. As shown in FIG.
  • the curve 6 is the linearity curve when the operating temperature of the amplifier circuit 40 is normal temperature and the bias current is the BG current.
  • Curve 7 and curve 9 are respectively the linearity curves when the bias current is BG current and the amplifier circuit 40 operates at lower than normal temperature and higher than normal temperature respectively.
  • Curve 8 and curve 10 are respectively the linearity curves when the bias current is the PTAT current, and the amplifier circuit 40 operates at lower than normal temperature and higher than normal temperature, respectively.
  • the bias current is the BG current
  • the linearity performance of the amplifier circuit 40 is better than that when the bias current is the PTAT current.
  • the PTAT current is proportional to the absolute temperature
  • the PTAT current increases, and the power consumption of the amplifying circuit 40 increases as its operating temperature increases.
  • the bias current adopts BG current, even if the operating temperature of the amplifying circuit 40 increases, the BG current remains unchanged, and the power consumption of the amplifying circuit 40 will not increase with the increase of its own operating temperature.
  • variable capacitance unit 403 may receive a capacitance control signal determined according to the operating temperature of the amplifier circuit 40, and adjust the gate/base terminal and the reference of the second transistor 402 according to the capacitance control signal. capacitance between ground.
  • the bias current received by the source/emitter terminals of the second transistor 402 may be a temperature-invariant current, such as a BG current. In this embodiment, while compensating the gain temperature drift of the amplifying circuit, the linearity performance of the amplifying circuit can be further ensured.
  • FIG. 7 is a circuit diagram of an amplifying circuit provided by an embodiment of the present application.
  • the gate/base terminals of the first transistor Q3 and the second transistor Q4 specifically refer to the base, and the first transistor Q3 and the second transistor Q4
  • the drain/collector terminals of the second transistor Q4 are specifically referred to as collectors, and the source/emitter terminals of the first transistor Q3 and the second transistor Q4 are specifically referred to as emitters.
  • the base of the first transistor Q3 receives the input signal VIN1 and the first bias voltage.
  • the first bias voltage may be generated by a first bias current source that provides a bias current i1 to the base of the first transistor Q3.
  • the first transistor Q3 and the second transistor Q4 form a Cascode structure, that is, the collector of the first transistor Q3 is coupled to the emitter of the second transistor Q4.
  • the emitter of the first transistor Q3 is coupled to the reference ground, for example, the first transistor Q3 may be indirectly coupled to the reference ground through a matching inductor.
  • the base of the second transistor Q4 receives the second bias voltage and is coupled to the first end of the variable capacitance unit, the second end of the variable capacitance unit is coupled to the reference ground, and the third end of the variable capacitance unit is connected to the temperature monitoring unit Module 701 is coupled.
  • the temperature monitoring module 701 can monitor the working temperature of the amplifying circuit in real time (for example, the chip temperature of the chip where the amplifying circuit is located or the temperature of the PCB where the amplifying circuit is located).
  • the temperature monitoring module 701 may be a part of the amplification circuit of the present application, or may be set independently of the amplification circuit. The present application does not limit the location of the temperature monitoring module 701 .
  • the second transistor Q4 amplifies the signal obtained by the amplification of the input signal VIN1 by the first transistor Q3, and outputs the amplified output signal VOUT at the collector.
  • the amplification factor of the second transistor Q4 can be expressed as:
  • g m is the transconductance of the second transistor Q4
  • r be is the AC input resistance of the second transistor Q4
  • w is the operating frequency of the second transistor Q4
  • c is the capacitance value between the base of the second transistor Q4 and the reference ground
  • R out is the output resistance of the second transistor Q4.
  • Equation 1 It can be known from Equation 1 that g m and r be are device properties of the second transistor Q4 and are fixed values.
  • the amplification factor of the second transistor Q4 is positively related to the size of c (ie the capacitance value between the base of the second transistor Q4 and the reference ground). Since the magnification of the amplifying circuit is the product of the magnifications of the first transistor Q3 and the second transistor Q4, the magnification of the amplifying circuit is also positively correlated with the size of c.
  • the capacitance value between the base of the second transistor Q4 and the reference ground becomes larger, and the amplification factor of the amplifier circuit increases; the capacitance value between the base electrode of the second transistor Q4 and the reference ground becomes smaller, and the amplifier circuit The magnification is reduced.
  • the second bias voltage received by the base of the second transistor Q4 is generated by a voltage source.
  • the amplifying circuit further includes a bias resistor R4 and a DC power supply VCAS, one end of the bias resistor R4 is coupled to the base of the second transistor Q4 and the first end of the variable capacitance unit CB, and the other end of the bias resistor R4 It is coupled to the positive terminal of the DC power supply VCAS, and the negative terminal of the DC power supply VCAS is coupled to the reference ground.
  • the bias resistor R4 can divide the voltage of the DC power supply VCAS, and provide a second bias voltage to the second transistor Q4 to further stabilize the amplification state of the second transistor Q4.
  • the amplifying circuit of the embodiment of the present application further includes a third transistor.
  • FIG. 8 provides another circuit diagram of the amplifying circuit of the embodiment of the present application.
  • the amplification circuit shown in FIG. 8 is based on the amplification circuit shown in FIG. 7 by adding a third transistor Q5 , a third transistor Q5 and a first transistor Q3 form a mirror current source.
  • the emitter of the third transistor Q5 is coupled to the reference ground, the base of the third transistor Q5 and the collector of the third transistor Q5 are both coupled to the base of the first transistor Q3, and the collector of the third transistor Q5 is also coupled to the first transistor Q3.
  • the three bias current sources are coupled, and the third bias current source can provide bias current i2 to the third transistor Q5.
  • the bias current i2 is shunted by the third transistor Q5 to obtain the bias current i1.
  • a mirror current source is formed by the third transistor and the first transistor, so as to provide a stable bias current for the second transistor, and the amplification state of the amplifying circuit can be stabilized.
  • the first transistor and the second transistor may be field effect transistors.
  • the field effect transistor may include, but is not limited to, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), High Electron Mobility Transistor (HEMT), Fin Field Effect Transistor ( FinField-EffectTransistor, FinFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • HEMT High Electron Mobility Transistor
  • Fin Field Effect Transistor FinField-EffectTransistor
  • FIG. 9 is another circuit diagram of the amplifying circuit provided by the embodiment of the present application.
  • the gate/base terminals of the first transistor Q6 and the second transistor Q7 specifically refer to the gate
  • the first transistor Q6 and the second transistor Q7 refer to the gate.
  • the drain/collector terminals of Q6 and the second transistor Q7 are specifically referred to as drains
  • the source/emitter terminals of the first transistor Q6 and the second transistor Q7 are specifically referred to as sources.
  • the amplifier circuit shown in Figure 9 is different from the amplifier circuit shown in Figure 7 in that the transistor is replaced by a MOSFET, the base of the transistor is replaced by the gate of the MOSFET, and the collector of the transistor is replaced by the drain of the MOSFET , the emitter of the transistor is replaced with the source of the MOSFET.
  • FIG. 10 is another circuit diagram of the amplifying circuit provided by the embodiment of the present application. As shown in FIG. 10 , taking the third transistor as an example of a MOSFET, the amplifying circuit shown in FIG. 10 differs from the amplifying circuit shown in FIG. 8 in that the triode is replaced with a MOSFET. Specifically, the third transistor Q8 and the first transistor Q6 form a mirror current source.
  • the source of the third transistor Q8 is coupled to the reference ground, the gate of the third transistor Q8 and the drain of the third transistor Q5 are both coupled to the gate of the first transistor Q6, and the drain of the third transistor Q8 is also coupled to the
  • the three bias current sources are coupled, and the third bias current source can provide bias current i2 to the third transistor Q8.
  • the bias current i2 is shunted by the third transistor Q8 to obtain the bias current i1.
  • the bias current i2 provided by the third bias current source is invariant with temperature, such as a BG current.
  • the source/emitter resistance of the third transistor and the resistance of the first transistor can be determined by setting the size ratio relationship between the third transistor and the first transistor (ie, Q5 and Q3, or Q8 and Q6). The proportional relationship between the source/emitter terminal resistances, thereby determining the ratio between the bias current i2 and the bias current i1. Exemplarily, if the size of the first transistor is larger than that of the third transistor, the bias current i1 may be larger than the bias current i2.
  • variable capacitance unit The specific implementation of the variable capacitance unit will be exemplarily described below with reference to FIGS. 11 to 16 .
  • FIG. 11 is a structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • the variable capacitance unit 1100 may include a varactor diode D1.
  • the above-mentioned capacitance control signal is a voltage signal and is applied to one end of the variable capacitance diode D1. It can be understood that the capacitance control signal can be applied to the anode of the varactor diode D1 and also can be applied to the cathode of the varactor diode D1.
  • the capacitance control signal is applied to the cathode of the varactor diode D1.
  • the cathode of the varactor diode D1 is coupled to the temperature monitoring module, and the anode of the varactor diode D1 is coupled to the gate/base terminal of the second transistor.
  • the varactor diode D1 is a semiconductor device made by utilizing the dependence between the capacitance of the PN junction and the voltage difference between the two ends of the PN junction.
  • the capacitance control signal can control the voltage difference across the varactor diode D1.
  • the specific performance is the voltage signal.
  • the amplitude of the voltage signal output by the temperature monitoring module is higher than the voltage value of the anode of the varactor diode D1
  • the varactor diode D1 is reverse biased.
  • the capacitance of the time varactor diode D1 is negatively correlated with the amplitude of the voltage signal. The larger the amplitude of the voltage signal is, the smaller the capacitance value of the varactor diode D1 is (that is, the smaller the capacitance value between the gate/base terminal of the second transistor and the reference ground).
  • the varactor diode D1 When the amplitude of the voltage signal output by the temperature monitoring module is lower than the voltage value of the anode of the varactor diode D1, the varactor diode D1 is forward biased. At this time, the capacitance value of the varactor diode D1 is positively related to the amplitude of the voltage signal. The larger the capacitance, the larger the capacitance of the varactor D1 (that is, the larger the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the capacitance control signal is applied to the anode of the varactor diode D1.
  • the anode of the varactor diode D1 is coupled to the temperature monitoring module, and the cathode of the varactor diode D1 is coupled to the gate/base terminal of the second transistor.
  • the varactor diode D1 When the amplitude of the voltage signal output by the temperature monitoring module is higher than the voltage value of the cathode of the varactor diode D1, the varactor diode D1 is forward biased, and the capacitance value of the varactor diode D1 is positively correlated with the amplitude of the voltage signal.
  • the greater the amplitude of the voltage signal the greater the capacitance of the varactor diode D1 (that is, the greater the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the varactor diode D1 When the amplitude of the voltage signal output by the temperature monitoring module is lower than the voltage value of the cathode of the varactor diode D1, the varactor diode D1 is reversely biased, and the capacitance value of the varactor diode D1 is negatively correlated with the amplitude of the voltage signal.
  • FIG. 12 is another structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • the variable capacitance unit 1200 may include a field effect transistor Q9.
  • the above capacitance control signal is a voltage signal and is applied to the gate or source of the field effect transistor Q9, wherein the source and drain of the field effect transistor Q9 are connected.
  • the capacitance control signal is applied to the gate of field effect transistor Q9.
  • the gate of the field effect transistor Q9 is coupled to the temperature monitoring module, and the source and drain of the field effect transistor Q9 are both coupled to the gate/base terminal of the second transistor.
  • the capacitance control signal as a voltage signal and the field effect transistor Q9 as a P-channel enhancement type field effect transistor as an example. That is, the source and drain of the field effect transistor Q9 are N-type doped regions, the gate of the field effect transistor is a P-type doped region, and a PN junction is formed between the gate and the source of the field effect transistor Q9.
  • the PN junction between the gate and the source of the field effect transistor Q9 is forward biased, at this time the gate of the field effect transistor Q9
  • the capacitance value between the source ie, the gate and drain of the field effect transistor Q9 is positively related to the amplitude of the voltage signal.
  • the greater the amplitude of the voltage signal the greater the capacitance between the gate and the source of the field effect transistor Q9 (ie, the greater the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the PN junction between the gate and the source of the field effect transistor Q9 is reverse biased.
  • the capacitance value between the sources is negatively related to the amplitude of the voltage signal. The larger the amplitude of the voltage signal, the smaller the capacitance between the gate and the source of the field effect transistor Q9 (ie, the smaller the capacitance between the gate/base of the second transistor and the reference ground).
  • the capacitance control signal is a voltage signal
  • the field effect transistor may be an N-channel enhancement type field effect transistor (not shown in the figure) as an example. That is, the source and drain of the field effect transistor are P-type doped regions, and the gate of the field effect transistor is an N-type doped region, that is, it can be understood that the field effect transistor is an N-channel enhancement type field effect transistor.
  • the PN junction between the source electrode and the gate electrode of the field effect transistor is reversely biased.
  • the capacitance value between the gate and the drain of the field effect transistor is negatively related to the amplitude of the voltage signal. The larger the amplitude of the voltage signal, the smaller the capacitance between the gate and the source of the field effect transistor (ie, the smaller the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the PN junction between the source electrode and the gate electrode of the field effect transistor is forward biased.
  • the capacitance value in between is positively related to the amplitude of the voltage signal. The greater the amplitude of the voltage signal, the greater the capacitance between the gate and the source of the field effect transistor (ie, the greater the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the capacitance control signal is applied to the source of the field effect transistor Q9.
  • both the source and drain of the field effect transistor Q9 are coupled to the temperature monitoring module, and the gate of the field effect transistor Q9 is coupled to the gate/base terminal of the second transistor.
  • the field effect transistor Q9 may be a P-channel enhancement type field effect transistor, and a PN junction is formed between the gate and the source of the field effect transistor Q9.
  • the PN junction between the gate and the source of the field effect transistor Q9 is reversely biased.
  • the capacitance value between the sources is negatively related to the amplitude of the voltage signal. The larger the amplitude of the voltage signal, the smaller the capacitance between the gate and the source of the field effect transistor Q9 (ie, the smaller the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the PN junction between the gate and the source of the field effect transistor Q9 is forward biased, and the gate of the field effect transistor Q9 is The capacitance value between the source and the source is positively related to the amplitude of the voltage signal.
  • the greater the amplitude of the voltage signal the greater the capacitance between the gate and the source of the field effect transistor Q9 (ie, the greater the capacitance between the gate/base terminals of the second transistor and the reference ground).
  • the capacitance control signal is a voltage signal
  • the field effect transistor may be an N-channel field effect transistor (not shown in the figure) as an example.
  • the amplitude of the output voltage signal of the temperature monitoring module is higher than the voltage value of the gate of the field effect transistor, the PN junction between the source and the gate of the field effect transistor is forward biased.
  • the capacitance value in between is positively related to the amplitude of the voltage signal. The greater the amplitude of the voltage signal, the greater the capacitance value between the gate and the source of the field effect transistor (ie the greater the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the PN junction between the source and the gate of the field effect transistor is reversely biased.
  • the capacitance value between is negatively related to the amplitude of the voltage signal. The larger the amplitude of the voltage signal, the smaller the capacitance value between the gate and the source of the field effect transistor (ie the smaller the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • FIG. 13 is another structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • the variable capacitance unit 1300 includes a transistor Q10.
  • the above-mentioned capacitance control signal is a voltage signal and is applied to the base of the transistor Q10.
  • the capacitance control signal can control the voltage difference between the base and the collector of the transistor Q10, wherein the base of the transistor Q10 is connected to the emitter.
  • both the base and the emitter of the transistor Q10 are coupled to the temperature monitoring module, and the collector of the transistor Q10 is coupled to the gate/base terminal of the second transistor.
  • the capacitance control signal as a voltage signal and the transistor Q10 as an NPN transistor as an example. That is, the base of the transistor Q10 is a P-type doped region, the collector and the emitter are N-type doped regions, and a PN junction is formed between the base and the collector of the transistor.
  • the capacitance value between the base and the collector of the transistor Q10 which is positively related to the amplitude of the voltage signal.
  • the greater the amplitude of the voltage signal the greater the capacitance between the base and the collector of the transistor Q10 (that is, the greater the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the PN junction between the base and the collector of the transistor Q10 is reverse biased, and the capacitance value between the base and the collector of the transistor Q10 , which is negatively related to the amplitude of the voltage signal.
  • the larger the amplitude of the voltage signal the smaller the capacitance between the base and collector of the transistor Q10 (ie, the smaller the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the capacitance control signal as a voltage signal and the triode as a PNP triode (not shown in the figure) as an example. That is, the base of the triode is an N-type doped region, the collector and the emitter are P-type doped regions, and a PN junction is formed between the collector and the base of the triode. If the amplitude of the voltage signal output by the temperature monitoring module is higher than the collector voltage value of the triode, and the PN junction between the collector and the base of the triode is reversely biased, the capacitance value between the base and the collector of the triode is proportional to the voltage The amplitude of the signal is negatively correlated. The larger the amplitude of the voltage signal, the smaller the capacitance between the base and the collector of the triode (ie, the smaller the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • the amplitude of the voltage signal output by the temperature monitoring module is lower than the collector voltage value of the triode, and the PN junction between the collector and the base of the triode is positively biased, the capacitance value between the base and the collector of the triode, and the voltage The amplitude of the signal is positively correlated.
  • the greater the amplitude of the voltage signal the greater the capacitance between the base and the collector of the triode (ie, the greater the capacitance between the gate/base terminal of the second transistor and the reference ground).
  • FIG. 14 is another structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • the variable capacitance unit 1400 includes a transistor Q11 , and the difference from FIG. 13 is that the base electrode of the transistor Q11 is connected to the collector electrode.
  • the capacitance control signal is applied to the base of the transistor Q11 to control the voltage difference between the base and the emitter of the transistor.
  • the base and collector of the transistor Q11 are coupled with the temperature monitoring module, and the emitter of the transistor Q11 is coupled with the gate/base terminal of the second transistor. Because whether it is an NPN-type triode or a PNP-type triode, the properties of collector and emitter doping are the same, that is, both are N-type doped regions or both are P-type doped regions. Therefore, the relationship between the capacitance value between the base electrode and the emitter electrode of the transistor Q11 and the amplitude of the output voltage signal of the temperature monitoring module can refer to the description of the capacitance value between the base electrode and the emitter electrode of the transistor Q10 in FIG. 13 , It is not repeated here.
  • FIG. 15 is another structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • the variable capacitance unit 1500 includes at least two capacitors and at least one switch.
  • the at least two capacitors are connected in series with at least one switch, and the at least one switch can control any one or more of the at least two capacitors to be connected between the gate/base terminal of the second transistor and the reference ground.
  • the switch K1 is connected in series with the capacitor C1
  • the switch K2 is connected in series with the capacitor C2. This application adjusts the capacitance value between the gate/base terminal of the second transistor and the reference ground by closing different switches.
  • the capacitance value between the gate/base terminal of the second transistor and the reference ground is the capacitance value of C1; when the switch K2 is closed, the capacitance value between the gate/base terminal of the second transistor and the reference ground is the capacitance value of C2; the switches K1 and K2 are closed at the same time, then the gate/base of the second transistor is The capacitance between the extreme and the reference ground is the sum of the capacitances of C1 and C2.
  • the switch K1 and/or the switch K2 may be embodied as mechanical switches, such as push button switches, rotary switches, and the like.
  • the switch K1 and the switch K2 can be integrated into one switching device, or can be set independently, and the application does not limit the set positions of the switches.
  • FIG. 16 is another structural block diagram of the variable capacitance unit provided by the embodiment of the present application.
  • the variable capacitance unit 1600 includes at least two capacitors and at least one switch, and the at least one switch is used to control the connection of any one or more of the at least two capacitors to the second transistor according to the capacitance control signal. Between the gate/base terminal and the reference ground. For example, switch K1 and/or switch K2 may be controlled by a capacitance control signal. Different from FIG.
  • the switch K1 and/or the switch K2 includes three terminals, wherein two terminals are connected in series between the gate/base terminal of the second transistor and the reference ground, and the other terminal is coupled to the temperature monitoring module.
  • the temperature monitoring module may generate a capacitance control control model based on the operating temperature of the amplifier circuit, and send the capacitance control signal to the switch K1 and/or the switch K2 to control the on-off of the switch K1 and/or the switch K2. , thereby adjusting the capacitance value between the gate/base terminal of the second transistor and the reference ground.
  • the switch K1 and/or the switch K2 may be embodied as a relay, a field effect transistor, a triode, an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) and an anti-parallel diode thereof, and the like.
  • IGBT Insulated Gate Bipolar Transistor
  • variable capacitance unit in the embodiments of the present application, and it should be understood that the variable capacitance unit may also have other implementations. This is only an exemplary description, and should not be construed as limiting the embodiments of the present application.
  • FIG. 17 is a schematic diagram of a chip provided by an embodiment of the present application. As shown in FIG. 17 , the amplifying circuit described above in conjunction with FIGS. 2 to 16 is provided on the chip.
  • the embodiment of the present application also provides an electronic device, and the electronic device may include the chip as shown in FIG. 17 .
  • the electronic device may include, but is not limited to, a speaker, a display screen, a communication device, and the like.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solutions of the embodiments of the present application.

Abstract

一种放大电路（20），适用于对增益温漂进行补偿的场景中。该放大电路（20）包括第一晶体管（201）、第二晶体管（202）以及可变电容单元（203），第一晶体管（201）和第二晶体管（202）构成Cascode级联结构，其中，第一晶体管（201）的栅极/基极端接收第一偏置电压和输入信号，第一晶体管（201）的源极/发射极与参考地耦合；第二晶体管（202）的栅极/基极端接收第二偏置电压，并且与可变电容单元（203）耦合，该可变电容单元（203）用于调整第二晶体管（202）的栅极/基极端与参考地之间的电容值；第二晶体管（202）的漏极/集电极端用于输出上述输入信号经放大电路（20）放大后得到的输出信号。可以提高改变放大电路（20）的放大倍数的灵活性和适用性，且在放大电路（20）的工作温度发生变化时可以对增益温漂进行补偿。

Description

放大电路、芯片及电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种放大电路、芯片及电子设备。
背景技术
放大电路是模拟电子中使用最为广泛的电路。放大电路通常采用Cascode(级联)结构，也称为共基-共射结构或共栅-共源结构。以图1示出的放大电路为例，晶体管Q1和晶体管Q2构成Cascode结构，即晶体管Q1的发射极/源极与晶体管Q2的集电极/漏极耦合。此时，图1中的放大电路的放大倍数与晶体管Q1、晶体管Q2以及电阻R1等有关。
如图1示出现有技术中的放大电路只能实现一个固定放大倍数，如果需要改变该放大电路的放大倍数，通常是改变该放大电路中的电阻R1来改变该放大电路的放大倍数，现有技术改变放大电路的放大倍数的方式具有较大的约束限制，不够灵活。
发明内容
本申请提供了一种放大电路、芯片及电子设备，可以提高改变放大电路的放大倍数的灵活性和适用性。
第一方面，本申请实施例提供了一种放大电路，该放大电路包括第一晶体管、第二晶体管以及可变电容单元，第一晶体管和第二晶体管构成Cascode(级联)结构，其中，该第一晶体管的栅极/基极端用于接收第一偏置电压和输入信号，该第一晶体管的源极/发射极端与参考地耦合；该第二晶体管的栅极/基极端用于接收第二偏置电压，并且与上述可变电容单元耦合，该可变电容单元用于调整第二晶体管的栅极/基极端与上述参考地之间的电容值；该第二晶体管的漏极/集电极端用于输出上述输入信号经放大电路放大后得到的输出信号。
本申请通过调整放大电路中第二晶体管的栅极/基极端与参考地之间的电容值来改变该放大电路的放大倍数，可以提高改变放大电路的放大倍数的灵活性，适用性强。
结合第一方面，在第一种可能的实现方式中，上述可变电容单元用于根据放大电路的工作温度，调整上述第二晶体管的栅极/基极端与上述参考地之间的电容值。
放大电路的工作温度具体可以指该放大电路所在芯片的温度或者该放大电路所在电路板(Printed Circuit Board，PCB)的温度。在该种可能的实现方式中，根据放大电路的工作温度控制第二晶体管的栅极/基极端与参考地之间的电容值，以控制放大电路的放大倍数。在放大电路的工作温度不是常温时，可以对放大电路的增益温漂进行补偿。换句话说，本申请实施例提供的放大电路可以在自身工作温度发生变化时，保持自身放大倍数不变。
结合第一方面第一种可能的实现方式，在第二种可能的实现方式中，上述放大电路还包括温度监测模块，该温度监测模块用于根据监测到放大电路的工作温度生成容值控制信号，以使上述可变电容单元根据该容值控制信号调整上述电容值。
结合第一方面第二种可能的实现方式，在第三种可能的实现方式中，上述可变电容单元包括变容二极管，上述容值控制信号包括施加于该变容二极管的一端的电压信号，用于控制该变容二极管两端的电压差。
结合第一方面第二种可能的实现方式，在第四种可能的实现方式中，上述可变电容单元包括场效应晶体管，上述容值控制信号包括施加与该场效应晶体管的栅极或源极的电压信号，用于控制该场效应晶体管的栅极与源极之间的电压差，其中，该场效应晶体管的源极与漏极 相连。
结合第一方面第二种可能的实现方式，在第五种可能的实现方式中，上述可变电容单元包括三极管，上述容值控制信号包括施加于该三极管的基极的电压信号，用于控制该三极管的基极与集电极之间的电压差，其中该三极管的基极与发射极相连；或者用于控制该三极管的基极与发射极之间的电压差，其中该三极管的基极与集电极相连。
结合第一方面或结合第一方面第一种至第二种任一可能的实现方式，在第六种可能的实现方式中，上述可变电容单元包括至少两个电容和至少一个开关，该至少一个开关用于根据上述容值控制信号控制上述至少两个电容中的任意一个或多个接入上述第二晶体管的栅极/基极端与上述参考地之间。
结合第一方面或第一方面上述任一种可能的实现方式，在第七种可能的实现方式中，上述第一偏置电压和/或上述第二偏置电压为偏置电流源产生的。
结合第一方面第七种可能的实现方式，在第八种可能的实现方式中，上述放大电路还包括第三晶体管，其中，该第三晶体管的漏极/集电极端与上述偏置电流源耦合，且该第三晶体管的漏极/集电极端和该第三晶体管的栅极/基极端均与上述第一晶体管的栅极/基极端耦合，该第三晶体管的源极/发射极端与上述参考地耦合。
第二方面，本申请实施例提供了一种芯片，该芯片上设置有第一方面或第一方面中的任一可能实现方式中的放大电路。
第三方面，本申请实施例提供了一种电子设备，该电子设备包括如第二方面所描述的芯片。
附图说明
图1为现有技术的一放大电路的电路图；
图2为本申请实施例提供的放大电路的一结构框图；
图3为现有技术的放大电路的增益温漂示意图；
图4为本申请实施例提供的放大电路的另一结构框图；
图5为本申请实施例提供的放大电路的增益温漂补偿示意图；
图6为本申请实施例提供的放大电路的线性度温漂示意图；
图7为本申请实施例提供的放大电路的一电路图；
图8为本申请实施例提供的放大电路的另一电路图；
图9为本申请实施例提供的放大电路的又一电路图；
图10为本申请实施例提供的放大电路的又一电路图；
图11为本申请实施例提供的可变电容单元的一结构框图；
图12为本申请实施例提供的可变电容单元的另一结构框图；
图13为本申请实施例提供的可变电容单元的又一结构框图；
图14为本申请实施例提供的可变电容单元的又一结构框图；
图15为本申请实施例提供的可变电容单元的又一结构框图；
图16为本申请实施例提供的可变电容单元的又一结构框图；
图17为本申请实施例提供的一种芯片的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描 述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供的放大电路适用于电信号幅度放大的场景，可以具体应用在通讯、广播、电视、自动控制等各种装置中。示例性的，该放大电路可以位于输入源与负载之间。该输入源用于向放大电路提供输入信号，该输入源例如可以是电子电路的输出端、数模转换器(Digital to Analog Convertor，DAC)等等。该负载用于接收放大电路放大后的输出信号，该负载例如可以是扬声器、电子电路的输入端等等。需要说明的是，上述电子电路包括但不限于本申请实施例提供的放大电路。
在一些可行的实施方式中，本申请实施例提供的放大电路可以设置于芯片内部，该放大电路中包括的元器件可以是以硅为本体，通过在硅上进行掺杂、曝光等工艺制作而成的。
下面结合附图对本申请实施例提供的放大电路的具体结构进行详细介绍。
参见图2，图2为本申请实施例提供的放大电路的一结构框图。如图2所示，放大电路20包括第一晶体管201、第二晶体管202以及可变电容单元203。
在本申请实施例中，第一晶体管201的栅极/基极端接收第一偏置电压和输入信号VIN，第一晶体管201的源极/发射极端与参考地耦合。参考地可以理解为具有一个用于提供交流地的电位端。例如可以是1.8V、1.25V或0V等，本申请不对参考地的电压值进行限制。
需要指出的是，本申请中所描述的“耦合”指的是直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元器件间接连接，例如可以是A与C直接连接，C与B直接连接，从而使得A与B之间通过C实现了连接。
示例性的，第一晶体管201的源极/发射极端可以通过匹配电感与参考地连接。
第一晶体管201和第二晶体管202构成Cascode结构。具体实现中，第一晶体管201的漏极/集电极端与第二晶体管202的源极/发射极端耦合，第二晶体管202的栅极/基极端接收第二偏置电压，并且与可变电容单元203耦合。
具体实现中，可变电容单元203可以通过调整第二晶体管202的栅极/基极端与参考地之间的电容值，控制放大电路20对输入信号VIN的放大倍数。放大电路20对输入信号VIN的放大倍数与可变电容单元203的电容值正相关(即与第二晶体管202的栅极/基极端与参考地之间的电容值正相关)。换句话说，第二晶体管202的栅极/基极端与参考地之间的电容值变大，放大电路20对输入信号VIN的放大倍数也变大。
第二晶体管202的漏极/集电极端输出上述输入信号VIN经放大电路20放大后得到的输出信号VOUT。
本申请实施例通过调整放大电路中第二晶体管的栅极/基极端与参考地之间的电容值来改变该放大电路的放大倍数，可以提高改变放大电路的放大倍数的灵活性，适用性强。
在一些可行的实施方式中，第一偏置电压和/或第二偏置电压可以是由电压源产生的。此时，第一晶体管201的栅极/基极端与第一电压源耦合，第二晶体管202的栅极/基极端与第二电压源耦合，可以理解的是，第一电压源和第二电压源可以是同一个电压源，也可以是不同的电压源。
可选的，在一些可行的实施方式中，第一偏置电压和/或第二偏置电压可以是由偏置电流源产生的。第一晶体管201的栅极/基极端与第一偏置电流源耦合，该第一偏置电流源例如可以提供图2中示出的偏置电流i1。第二晶体管202的栅极/基极端与第二偏置电流源耦合。可 以理解的是，第一偏置电流源和第二偏置电流源可以是同一个偏置电流源，也可以是不同的偏置电流源。
进一步的，第一偏置电压与第二偏置电压的产生方式可以相同，也可以不同，例如第一偏置电压和第二偏置电压均由偏置电流源产生的；或者第一偏置电压是由偏置电流源产生的，第二偏置电压是由电压源产生的；或者第一偏置电压是由电压源产生的，第二偏置电压是由偏置电流源产生的等等。本申请不对此偏置电压是如何产生的进行限制。
放大电路的放大倍数除了可以通过第二晶体管的栅极/基极端与参考地之间的电容值来改变之外，放大电路的放大倍数还会随自身工作温度变化，即可以理解为放大电路存在增益(即放大倍数)温漂的问题。参见图3，图3为现有技术的放大电路的增益温漂示意图。如图3所示，由于放大电路的工作温度不同，例如放大电路所在芯片的芯片温度不同或者放大电路所在PCB的温度不同，曲线1、曲线2和曲线3所处的位置不同。当放大电路的工作温度是常温时(一般指25℃)，现有技术中放大电路的增益曲线是图3中示出的曲线1。需要说明的是，此处只是以常温作为参照温度做示例性说明，并不应理解为对该参照温度进行限制，放大电路的工作温度也可以是其他预设温度。当放大电路的工作温度高于常温时，现有技术中放大电路的增益曲线是图3中示出的曲线2，即当放大电路的工作温度升高时，放大电路的放大倍数降低。当放大电路的工作温度低于常温时，现有技术中放大电路的增益曲线是图3中示出的曲线3，即当放大电路的工作温度降低时，放大电路的放大倍数升高。在具体的应用场景中，如果现有技术中的放大电路例如应用于扬声器，该放大电路的增益温漂可以具体表现为扬声器在高于常温的情况下响度低，低于常温的情况下响度高。如果现有技术中的放大电路例如应用于显示屏，该放大电路的增益温漂可以具体表现为显示屏在高于常温的情况下亮度小，低于常温的情况下亮度大。
为了进一步解决现有技术中放大电路存在增益温漂的问题，本申请实施例提供的放大电路可以实时对自身增益温漂进行补偿。
参见图4，图4为本申请实施例提供的放大电路的另一结构框图。如图4所示，放大电路40包括第一晶体管401、第二晶体管402、可变电容单元403以及温度监测模块404。其中第一晶体管401、第二晶体管402以及可变电容单元403之间的关系可以参考前文结合图2所描述的实施例，此处不作赘述。
在本申请实施例中，可变电容单元403可以根据放大电路40的工作温度，调整第二晶体管402的栅极/基极端与参考地之间的电容值。
在一些可行的实施方式中，上述容值控制信号可以是放大电路40产生的。此时，可变电容单元403与温度监测模块404耦合。温度监测模块404可以监测放大电路40的工作温度，例如监测放大电路40所在芯片的芯片温度或者放大电路40所在PCB的温度。温度监测模块404根据监测到放大电路40的工作温度生成容值控制信号，示例性的，温度监测模块404可以通过获取放大电路40的输出信号VOUT，基于该输出信号VOUT与参考信号的幅度(例如放大电路40在常温情况下输出信号的幅度)来确定放大电路的工作温度是高于常温还是低于常温，并生成容值控制信号。可变电容单元403根据该容值控制信号调整自身的容值(即调整第二晶体管402的栅极/基极端与参考地之间的电容值)。示例性的，温度监测模块404可以将该容值控制信号向可变电容单元403发送，以使可变电容单元403基于该容值控制信号调整调整第二晶体管402的栅极/基极端与参考地之间的电容值。
示例性的，温度监测模块404例如可以是现有技术中正比于绝对温度(Proportional to absolute temperature，PTAT)电流产生电路，PTAT电流产生电路的输出电流施加在电阻两端，该电阻两端的电压差即可以为上述容值控制信号。在一些可行的实施方式中，PTAT电流产生电路可以是共源共栅电流镜与三极管耦合而成的电路，该三极管用于产生PTAT电流，共源共栅电流镜用于稳定PTAT电流。此处只是对PTAT电流产生电路进行示例性说明，PTAT电流产生电路具有多种可能的实现方式，本申请不对此进行限制。
可选的，在一些可行的实施方式中，容值控制信号可以是从放大电路40的外部输入至可变电容单元403的。示例性的，温度监测模块没有设置在放大电路40中，比如放大电路40所在的PCB设置有温度传感器，实时感测放大电路40的工作温度，该温度传感器将感测到放大电路40的工作温度发送至放大电路40的外部(例如可以是处理器、其他电子电路等)，以使处理器或电子电路等基于放大电路40的工作温度与预设温度(例如常温)生成容值控制信号，并将该容值控制信号发送至放大电路40中的可变电容单元403。
示例性的，上述容值控制信号可以表现为不同的电压值。该电压值可以是连续的电压(即模拟电压)，也可以是不连续的电压(即数字电压)。可变电容单元403可以根据不同的电压值，调整第二晶体管402的栅极/基极端与参考地之间的电容值。又例如，容值控制信号可以表现为电阻两端的电压差，此时该电阻的输入电流是PTAT电流产生电路输出的PTAT电流。
具体实现中，当放大电路40的工作温度高于常温时，此时放大电路40的放大倍数降低，可变电容单元403可以根据容值控制信号将第二晶体管402的栅极/基极端与参考地之间的电容值变大，使放大电路40的放大倍数增大。例如放大电路40的放大倍数可以增大至放大电路40的工作温度是常温时的放大倍数。具体实现效果可以参考图5，图5为本申请实施例提供的放大电路的增益温漂补偿示意图。如图5所示，曲线4为放大电路40的工作温度高于常温时的增益曲线。相较于图3中示出的曲线2，本申请实施例的放大电路40的增益(即放大倍数)温漂得到了改善，即使放大电路40的工作温度高于常温，放大电路40的放大倍数也接近于自身工作温度是常温时的放大倍数。即曲线4可以与曲线1重合。
当放大电路40的工作温度低于常温时，此时放大电路40的放大倍数增大，可变电容单元403可以根据容值控制信号将第二晶体管402的栅极/基极端与参考地之间的电容值变小，使放大电路40的放大倍数可以降低。示例性的，放大电路40的放大倍数可以降低至放大电路40的工作温度是常温时的放大倍数。具体实现效果可以参考图5示出的曲线5，曲线5为放大电路40的工作温度低于常温时的增益曲线。相较于图3示出的曲线3，本申请实施例的放大电路40即使在自身工作温度低于常温的情况下，放大电路40的放大倍数也接近于自身工作温度是常温时的放大倍数。即曲线5可以与曲线1重合。
可选的，在一些具体的应用场景中，本申请实施例的放大电路40可以应用于扬声器、显示屏等。本申请实施例的放大电路40可以实时对自身增益温漂进行补偿，从而使得扬声器在不同温度下播放的声音响度一致、和/或使得显示屏在不同温度下显示亮度一致。上述为对本申请实施例提供的放大电路的使用场景进行示例，而非穷举，应当理解为本申请实施例提供的放大电路可以应用于任何需要对自身增益温漂进行补偿的场景。
本申请实施例通过根据放大电路的工作温度，控制第二晶体管的栅极/基极端与参考地之间的电容值，以控制放大电路的放大倍数。在放大电路的工作温度不是常温时，对放大电路的增益温漂进行补偿。换句话说，本申请实施例提供的放大电路可以在自身工作温度发生变化时，保持自身放大倍数不变。
进一步的，衡量放大电路40的性能指标除了包括增益温漂之外，还包括放大电路40的线性度。放大电路40的线性度可以理解为放大电路40在线性动态范围内，输出功率随着输入功率线性增加。以第一晶体管401接收的第一偏置电压是由偏置电流源产生为例，该偏置电流源向第一晶体管401提供偏置电流i1。放大电路40的线性度与第一晶体管401的偏置电流i1有关。在一些可行的实施方式中，偏置电流i1可以是PTAT电流。
可选的，在一些可行的实施方式中，偏置电流i1可以是一个不随温度变化的电流，例如带隙基准(Bandgap，BG)电流。偏置电流是PTAT电流或BG电流时的放大电路40的线性度可以参考图6，图6为本申请实施例提供的放大电路的线性度温漂示意图。需要首先说明的是，图6中的纵坐标是输出三阶交调功率(Output 3th Intercept Point，OIP3)，OIP3是一个用来衡量放大电路的线性度的参数。如图6所示，曲线7和曲线9相对于曲线8和曲线10来说，更接近曲线6。其中曲线6是放大电路40的工作温度是常温，偏置电流是BG电流时的线性度曲线。曲线7和曲线9分别是偏置电流是BG电流时，放大电路40分别工作在低于常温和高于常温时的线性度曲线。曲线8和曲线10分别是偏置电流是PTAT电流时，放大电路40分别工作在低于常温和高于常温时线性度曲线。换句话说，偏置电流是BG电流时，放大电路40的线性度性能优于偏置电流是PTAT电流时的线性度性能。并且由于PTAT电流正比于绝对温度，当放大电路40的工作温度升高时，PTAT的电流增大，此时放大电路40的功耗随着自身工作温度升高而提高。而偏置电流采用BG电流，即使放大电路40的工作温度升高，BG电流保持不变，放大电路40的功耗不会随着自身工作温度升高而升高。
在一可选实施例中，可变电容单元403可以接收根据放大电路40的工作温度而确定的容值控制信号，并根据该容值控制信号调整第二晶体管402的栅极/基极端与参考地之间的电容值。第二晶体管402的源极/发射极端接收的偏置电流可以是一个不随温度变化的电流，例如BG电流。在该实施例中，在对放大电路的增益温漂进行补偿的同时，可以进一步保证放大电路的线性度性能。
下面结合图7至图10对本申请实施例的放大电路的具体连接关系进行示例性说明。
参见图7，图7为本申请实施例提供的放大电路的一电路图。如图7所示，以第一晶体管和第二晶体管是NPN型三极管为例，此时第一晶体管Q3和第二晶体管Q4的栅极/基极端具体指的是基极，第一晶体管Q3和第二晶体管Q4的漏极/集电极端具体指的是集电极，第一晶体管Q3和第二晶体管Q4的源极/发射极端具体指的是发射极。第一晶体管Q3的基极接收输入信号VIN1和第一偏置电压。示例性的，该第一偏置电压可以是由第一偏置电流源产生的，该第一偏置电流源向第一晶体管Q3的基极提供偏置电流i1。
第一晶体管Q3与第二晶体管Q4构成Cascode结构，即第一晶体管Q3的集电极与第二晶体管Q4的发射极耦合。第一晶体管Q3的发射极耦合至参考地，例如第一晶体管Q3可以通过匹配电感间接与参考地耦合。第二晶体管Q4的基极接收第二偏置电压，并与可变电容单元的第一端耦合，可变电容单元的第二端耦合至参考地，可变电容单元的第三端与温度监测模块701耦合。温度监测模块701可以实时监测放大电路的工作温度(例如放大电路所在芯片的芯片温度或放大电路所在PCB的温度)。可选的，温度监测模块701可以是本申请放大电路中的一部分，也可以是独立于放大电路设置。本申请不对温度监测模块701所处位置进行限制。
第二晶体管Q4将输入信号VIN1经第一晶体管Q3放大后得到的信号进行放大，并将放 大后得到的输出信号VOUT在集电极输出。此时第二晶体管Q4的放大倍数可以表示为：
Figure PCTCN2020127517-appb-000001
其中g m为第二晶体管Q4的跨导，r be为第二晶体管Q4的交流输入电阻，w为第二晶体管Q4的工作频率，c为第二晶体管Q4基极与参考地之间的电容值，R out为第二晶体管Q4的输出电阻。
由公式1可知，g m和r be是第二晶体管Q4的器件属性，为固定值。在第二晶体管Q4的工作频率固定，输出电阻固定的情况下，第二晶体管Q4的放大倍数与c的大小(即第二晶体管Q4的基极与参考地之间的电容值)正相关。由于放大电路的放大倍数是第一晶体管Q3和第二晶体管Q4的放大倍数的乘积，所以放大电路的放大倍数与c的大小也是正相关。换句话说，第二晶体管Q4的基极与参考地之间的电容值变大，放大电路的放大倍数增大；第二晶体管Q4的基极与参考地之间的电容值变小，放大电路的放大倍数减小。
示例性的，第二晶体管Q4的基极接收的第二偏置电压是由电压源产生的。具体实现中，放大电路还包括偏置电阻R4和直流电源VCAS，偏置电阻R4的一端与第二晶体管Q4的基极以及可变电容单元CB的第一端耦合，偏置电阻R4的另一端耦合至直流电源VCAS的正极端，直流电源VCAS的负极端与参考地耦合。偏置电阻R4可以将直流电源VCAS的电压进行分压，并向第二晶体管Q4提供第二偏置电压，进一步稳定第二晶体管Q4的放大状态。
进一步的，本申请实施例的放大电路还包括第三晶体管，参见图8，图8为本申请实施例提供放大电路的又一电路图。如图8所示，以第三晶体管是三极管为例，图8所示的放大电路是在图7所示的放大电路的基础上增加了第三晶体管Q5，第三晶体管Q5和第一晶体管Q3构成镜像电流源。其中，第三晶体管Q5的发射极与参考地耦合，第三晶体管Q5的基极与第三晶体管Q5的集电极均与第一晶体管Q3的基极耦合，第三晶体管Q5的集电极还与第三偏置电流源耦合，该第三偏置电流源可以向第三晶体管Q5提供偏置电流i2。偏置电流i2经第三晶体管Q5分流后得到偏置电流i1。
在本申请实施例中，通过第三晶体管与第一晶体管构成镜像电流源，从而为第二晶体管提供稳定的偏置电流，可以稳定放大电路的放大状态。
可选的，在一些可行的实施方式中，第一晶体管和第二晶体管可以是场效应晶体管。该场效应晶体管可以包括但不限于金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)、高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)、鳍式场效晶体管(FinField-EffectTransistor，FinFET)。
参见图9，图9为本申请实施例提供的放大电路的又一电路图。如图9所示，以第一晶体管和第二晶体管是P沟道增强型场MOSFET为例，第一晶体管Q6和第二晶体管Q7的栅极/基极端具体指的是栅极，第一晶体管Q6和第二晶体管Q7的漏极/集电极端具体指的是漏极，第一晶体管Q6和第二晶体管Q7的源极/发射极端具体指的是源极。换句话说，图9示出的放大电路与图7示出的放大电路不同之处在于将三极管替换为MOSFET，三极管的基极替换为MOSFET的栅极，三极管的集电极替换为MOSFET的漏极，三极管的发射极替换为MOSFET的源极。
同理的，也可以在图9示出的放大电路的基础上增加第三晶体管。参见图10，图10为本申请实施例提供的放大电路的又一电路图。如图10所示，以第三晶体管是MOSFET为例，图10示出的放大电路与图8示出的放大电路的不同之处在于将三极管替换为MOSFET。具 体的，第三晶体管Q8与第一晶体管Q6构成镜像电流源。其中，第三晶体管Q8的源极与参考地耦合，第三晶体管Q8的栅极与第三晶体管Q5的漏极均与第一晶体管Q6的栅极耦合，第三晶体管Q8的漏极还与第三偏置电流源耦合，该第三偏置电流源可以向第三晶体管Q8提供偏置电流i2。偏置电流i2经第三晶体管Q8分流后得到偏置电流i1。
在一些可行的实施方式中，第三偏置电流源提供的偏置电流i2是不随温度变化的，例如BG电流。
在一些可行的实施方式中，可以通过设置第三晶体管和第一晶体管(即Q5和Q3，或者Q8和Q6)的尺寸比例关系来确定第三晶体管的源极/发射极端电阻与第一晶体管的源极/发射极端电阻之间的比例关系，从而确定偏置电流i2与偏置电流i1之间的比例。示例性的，第一晶体管的尺寸大于第三晶体管的尺寸，则偏置电流i1可以大于偏置电流i2。
下面结合图11至图16对可变电容单元的具体实现方式进行示例性说明。
在一些可行的实施方式中，参见图11，图11为本申请实施例提供的可变电容单元的一结构框图。如图11所示，可变电容单元1100可以包括变容二极管D1。上述容值控制信号是电压信号，并施加于变容二极管D1的一端。可以理解的是，该容值控制信号既可以施加于变容二极管D1的阳极，也可以施加于变容二极管D1的阴极。
例如，容值控制信号施加于变容二极管D1的阴极。此时，变容二极管D1的阴极与温度监测模块耦合，变容二极管D1的阳极与第二晶体管的栅极/基极端耦合，。
变容二极管D1是利用PN结电容与PN结两端电压差之间的依赖关系制成的半导体器件。具体实现中，容值控制信号可以控制变容二极管D1两端的电压差。以容值控制信号是由温度监测模块产生，具体表现是电压信号为例，当温度监测模块输出的电压信号的幅度高于变容二极管D1阳极的电压值时，变容二极管D1反偏，此时变容二极管D1的容值与电压信号的幅度负相关。电压信号的幅度越大，变容二极管D1的容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
当温度监测模块输出的电压信号的幅度低于变容二极管D1阳极的电压值时，变容二极管D1正偏，此时变容二极管D1的容值与电压信号的幅度正相关，电压信号的幅度越大，变容二极管D1的容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
又例如，容值控制信号施加于变容二极管D1的阳极。此时，变容二极管D1的阳极与温度监测模块耦合，变容二极管D1的阴极与第二晶体管的栅极/基极端耦合，。
当温度监测模块输出的电压信号的幅度高于变容二极管D1阴极的电压值时，变容二极管D1正偏，此时变容二极管D1的容值与电压信号的幅度正相关。电压信号的幅度越大，变容二极管D1的容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
当温度监测模块输出的电压信号的幅度低于变容二极管D1阴极的电压值时，变容二极管D1反偏，此时变容二极管D1的容值与电压信号的幅度负相关。电压信号的幅度越大，变容二极管D1的容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
可选的，在一些可行的实施方式中，参见图12，图12为本申请实施例提供的可变电容单元的另一结构框图。如图12所示，可变电容单元1200可以包括场效应晶体管Q9。上述容值控制信号是电压信号，并施加于场效应晶体管Q9的栅极或源极，其中场效应晶体管Q9的源极与漏极相连。
例如，容值控制信号施加于场效应晶体管Q9的栅极。此时，场效应晶体管Q9的栅极与 温度监测模块耦合，场效应晶体管Q9的源极与漏极均与第二晶体管的栅极/基极端耦合。
以容值控制信号是电压信号、场效应晶体管Q9是P沟道增强型场效应晶体管为例。即场效应晶体管Q9的源极和漏极为N型掺杂区，场效应晶体管的栅极为P型掺杂区，场效应晶体管Q9的栅极与源极之间形成PN结。
当温度监测模块输出的电压信号的幅度高于场效应晶体管Q9源极的电压值时，场效应晶体管Q9的栅极与源极之间的PN结正偏，此时场效应晶体管Q9的栅极与源极(即场效应晶体管Q9栅极与漏极)之间的电容值，与电压信号的幅度正相关。电压信号的幅度越大，场效应晶体管Q9的栅极与源极之间的电容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
当温度监测模块输出的电压信号的幅度低于场效应晶体管Q9源极的电压值时，场效应晶体管Q9的栅极与源极之间的PN结反偏，此时场效应晶体管Q9栅极与源极之间的电容值，与电压信号的幅度负相关。电压信号的幅度越大，场效应晶体管Q9栅极与源极之间的电容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
以容值控制信号是电压信号、场效应晶体管可以是N沟道增强型场效应晶体管(图中未示出)为例。即场效应晶体管的源极和漏极为P型掺杂区，场效应晶体管的栅极为N型掺杂区，即可以理解为场效应晶体管是N沟道增强型场效应晶体管时与场效应晶体管是P沟道增强型场效应晶体管时的形成的PN结极性相反。
当温度监测模块输出的电压信号的幅度高于场效应晶体管源极的电压值时，场效应晶体管的源极与栅极之间的PN结反偏，此时场效应晶体管的栅极与源极(即场效应晶体管栅极与漏极)之间的电容值，与电压信号的幅度负相关。电压信号的幅度越大，场效应晶体管栅极与源极之间的电容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
当温度监测模块输出的电压信号的幅度低于场效应晶体管源极的电压值时，场效应晶体管的源极与栅极之间的PN结正偏，此时场效应晶体管栅极与源极之间的电容值，与电压信号的幅度正相关。电压信号的幅度越大，场效应晶体管栅极与源极之间的电容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
又例如，容值控制信号施加于场效应晶体管Q9的源极。此时，场效应晶体管Q9的源极和漏极均与温度监测模块耦合，场效应晶体管Q9的栅极与第二晶体管的栅极/基极端耦合。
以容值控制信号是电压信号、场效应晶体管Q9可以是P沟道增强型场效应晶体管，场效应晶体管Q9的栅极与源极之间形成PN结。
当温度监测模块输出的电压信号的幅度高于场效应晶体管Q9栅极的电压值时，场效应晶体管Q9的栅极与源极之间的PN结反偏，此时场效应晶体管Q9栅极与源极之间的电容值，与电压信号的幅度负相关。电压信号的幅度越大，场效应晶体管Q9的栅极与源极之间的电容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
当温度监测模块输出的电压信号的幅度低于场效应晶体管Q9栅极的电压值时，场效应晶体管Q9的栅极与源极之间的PN结正偏，此时场效应晶体管Q9的栅极与源极之间的电容值，与电压信号的幅度正相关。电压信号的幅度越大，场效应晶体管Q9栅极与源极之间的电容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
以容值控制信号是电压信号、场效应晶体管可以是N沟道场效应晶体管(图中未示出)为例。当温度监测模块输出电压信号的幅度高于场效应晶体管栅极的电压值时，场效应晶体管的源极与栅极之间的PN结正偏，此时场效应晶体管的栅极与源极之间的电容值，与电压 信号的幅度正相关。电压信号的幅度越大，场效应晶体管的栅极与源极之间的电容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
当温度监测模块输出的电压信号的幅度低于场效应晶体管栅极的电压值时，场效应晶体管的源极与栅极之间的PN结反偏，此时场效应晶体管的栅极与源极之间的电容值，与电压信号的幅度负相关。电压信号的幅度越大，场效应晶体管的栅极与源极之间的电容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
可选的，在一些可行的实施方式中，参见图13，图13为本申请实施例提供的可变电容单元的又一结构框图。如图13所示，可变电容单元1300包括三极管Q10。上述容值控制信号是电压信号，并施加于三极管Q10的基极。该容值控制信号可以控制三极管Q10的基极与集电极之间的电压差，其中三极管Q10的基极与发射极相连。
此时，三极管Q10的基极和发射极均与温度监测模块耦合，三极管Q10的集电极与第二晶体管的栅极/基极端耦合。
以容值控制信号是电压信号、三极管Q10是NPN型三极管为例。即三极管Q10的基极是P型掺杂区，集电极和发射极是N型掺杂区，三极管的基极与集电极之间形成PN结。
若温度监测模块输出的电压信号的幅度高于三极管Q10的集电极电压值，三极管Q10的基极与集电极之间的PN结正偏，则三极管Q10的基极与集电极之间的电容值，与电压信号的幅度正相关。电压信号的幅度越大，三极管Q10的基极与集电极之间的电容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
若温度监测模块输出的电压信号的幅度低于三极管Q10的集电极电压值，三极管Q10的基极与集电极之间的PN结反偏，则三极管Q10的基极与集电极之间的电容值，与电压信号的幅度负相关。电压信号的幅度越大，三极管Q10的基极与集电极之间的电容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
以容值控制信号是电压信号、三极管是PNP型三极管(图中未示出)为例。即三极管的基极是N型掺杂区，集电极和发射极是P型掺杂区，三极管的集电极与基极之间形成PN结。若温度监测模块输出的电压信号的幅度高于三极管的集电极电压值，三极管的集电极与基极之间的PN结反偏，则三极管的基极与集电极之间的电容值，与电压信号的幅度负相关。电压信号的幅度越大，三极管的基极与集电极之间的电容值越小(即第二晶体管的栅极/基极端与参考地之间的电容值越小)。
若温度监测模块输出的电压信号的幅度低于三极管的集电极电压值，三极管的集电极与基极之间的PN结正偏，则三极管的基极与集电极之间的电容值，与电压信号的幅度正相关。电压信号的幅度越大，三极管的基极与集电极之间的电容值越大(即第二晶体管的栅极/基极端与参考地之间的电容值越大)。
可选的，在一些可行的实施方式中，参见图14，图14为本申请实施例提供的可变电容单元的又一结构框图。如图14所示，可变电容单元1400包括三极管Q11，与图13不同的是，三极管Q11的基极与集电极相连。容值控制信号施加于三极管Q11的基极，控制三极管的基极与发射极之间的电压差。
此时，三极管Q11的基极和集电极与温度监测模块耦合，三极管Q11的发射极与第二晶体管的栅极/基极端耦合。由于无论是NPN型三极管还是PNP型三极管，集电极和发射极掺杂的性质都是一样的，即都是N型掺杂区或都是P型掺杂区。因此三极管Q11的基极与发射极之间的电容值，与温度监测模块输出电压信号的幅度之间的关系可以参考图13中对三极管 Q10的基极与发射极之间的电容值的描述，此处不作赘述。
可选的，在一些可行的实施方式中，参见图15，图15为本申请实施例提供的可变电容单元的又一结构框图。如图15所示，可变电容单元1500包括至少两个电容和至少一个开关。
该至少两个电容与至少一个开关串联，该至少一个开关可以控制至少两个电容中的任意一个或多个接入第二晶体管的栅极/基极端与参考地之间。示例性的，开关K1与电容C1串联，开关K2与电容C2串联。本申请通过闭合不同的开关来调整第二晶体管的栅极/基极端与参考地之间的电容值，例如开关K1闭合，则第二晶体管的栅极/基极端与参考地之间的电容值为C1的电容值；开关K2闭合，则第二晶体管的栅极/基极端与参考地之间的电容值为C2的电容值；开关K1和K2同时闭合，则第二晶体管的栅极/基极端与参考地之间的电容值为C1与C2的电容值之和。
开关K1和/或开关K2可以具体实现为机械开关，例如按钮开关、旋钮开关等。开关K1和开关K2可以集成到一个开关器件中，也可以单独设置，本申请不对开关之间的设置位置进行限制。
可选的，在一些可行的实施方式中，参见图16，图16为本申请实施例提供的可变电容单元的又一结构框图。如图16所示，可变电容单元1600包括至少两个电容和至少一个开关，该至少一个开关用于根据容值控制信号控制至少两个电容中的任意一个或多个接入第二晶体管的栅极/基极端与参考地之间。例如开关K1和/或开关K2可以是由容值控制信号控制的。与图15不同的是，开关K1和/或开关K2包括三端，其中两端串联在第二晶体管的栅极/基极端与参考地之间，另一端与温度监测模块耦合。示例性的，温度监测模块可以基于放大电路的工作温度生成容值控制控制型号，并将该容值控制信号向开关K1和/或开关K2发送，以控制开关K1和/或开关K2的通断，从而调整第二晶体管的栅极/基极端与参考地之间的电容值。
开关K1和/或开关K2可以具体实现为继电器、场效应晶体管、三极管、绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)及其反并联二极管等。
需要说明的是，前文结合图11至图16所描述的实施例是本申请实施例中可变电容单元的具体实现方式的示例性说明，应当理解为可变电容单元还可以具有其他实现方式，此处只是作出示例性说明，并不应理解为对本申请实施例进行限制。
此外，本申请实施例还提供了一种芯片。参考图17，图17为本申请实施例提供的一种芯片的示意图。如图17所示，该芯片上设置有前文结合图2至图16所描述的放大电路。
本申请实施例还提供了一种电子设备，该电子设备可以包括如图17所示的芯片。例如，该电子设备可以包括但不限于扬声器、显示屏、通信设备等。
需要说明的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
以上，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (11)

  1. 一种放大电路，其特征在于，所述放大电路包括第一晶体管、第二晶体管以及可变电容单元，所述第一晶体管和所述第二晶体管构成Cascode(级联)结构，其中：
    所述第一晶体管的栅极/基极端用于接收第一偏置电压和输入信号，所述第一晶体管的源极/发射极端与参考地耦合；
    所述第二晶体管的栅极/基极端用于接收第二偏置电压，并且与所述可变电容单元耦合，所述可变电容单元用于调整所述第二晶体管的栅极/基极端与所述参考地之间的电容值；
    所述第二晶体管的漏极/集电极端用于输出所述输入信号经所述放大电路放大后得到的输出信号。
  2. 如权利要求1所述的放大电路，其特征在于，所述可变电容单元用于根据所述放大电路的工作温度，调整所述第二晶体管的栅极/基极端与所述参考地之间的电容值。
  3. 如权利要求2所述的放大电路，其特征在于，所述放大电路还包括温度监测模块，所述温度监测模块用于根据监测到所述放大电路的工作温度生成容值控制信号，所述可变电容单元根据所述容值控制信号调整所述电容值。
  4. 如权利要求3所述的放大电路，其特征在于，所述可变电容单元包括变容二极管；
    所述容值控制信号包括施加于所述变容二极管的一端的电压信号，用于控制所述变容二极管两端的电压差。
  5. 如权利要求3所述的放大电路，其特征在于，所述可变电容单元包括场效应晶体管，
    所述容值控制信号包括施加于所述场效应晶体管的栅极或源极的电压信号，用于控制所述场效应晶体管的栅极与源极之间的电压差，其中，所述场效应晶体管的源极与漏极相连。
  6. 如权利要求3所述的放大电路，其特征在于，所述可变电容单元包括三极管；
    所述容值控制信号包括施加于所述三极管的基极的电压信号，用于控制所述三极管的基极与集电极之间的电压差，其中所述三极管的基极与发射极相连；或者用于控制所述三极管的基极与发射极之间的电压差，其中所述三极管的基极与集电极相连。
  7. 如权利要求1-3任一项所述的放大电路，其特征在于，所述可变电容单元包括至少两个电容和至少一个开关，所述至少一个开关用于根据所述容值控制信号控制所述至少两个电容中的任意一个或多个接入所述第二晶体管的栅极/基极端与所述参考地之间。
  8. 如权利要求1-7任一项所述的放大电路，其特征在于，所述第一偏置电压和/或所述第二偏置电压为偏置电流源产生的。
  9. 如权利要求8所述的放大电路，其特征在于，所述放大电路还包括第三晶体管，其中，所述第三晶体管的漏极/集电极端与所述偏置电流源耦合，且所述第三晶体管的漏极/集电极端 和所述第三晶体管的栅极/基极端均与所述第一晶体管的栅极/基极端耦合，所述第三晶体管的源极/发射极端与所述参考地耦合。
  10. 一种芯片，其特征在于，所述芯片中包括如权利要求1-9任一项所述的放大电路。
  11. 一种电子设备，其特征在于，所述电子设备包括如权利要求10所述的芯片。
PCT/CN2020/127517 2020-11-09 2020-11-09 放大电路、芯片及电子设备 WO2022095026A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204089737U (zh) * 2014-07-29 2015-01-07 无锡华润矽科微电子有限公司 实现可变增益的高精度放大器结构
US20170126180A1 (en) * 2015-11-04 2017-05-04 Infineon Technologies Ag Optimum current control cmos cascode amplifier
CN107565912A (zh) * 2017-08-25 2018-01-09 东南大学 一种具有干扰抑制的低噪声放大器电路
CN109687885A (zh) * 2017-10-13 2019-04-26 三星电子株式会社 接收器、低噪声放大器以及无线通信装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN204089737U (zh) * 2014-07-29 2015-01-07 无锡华润矽科微电子有限公司 实现可变增益的高精度放大器结构
US20170126180A1 (en) * 2015-11-04 2017-05-04 Infineon Technologies Ag Optimum current control cmos cascode amplifier
CN107026619A (zh) * 2015-11-04 2017-08-08 英飞凌科技股份有限公司 最佳电流控制cmos级联放大器
CN107565912A (zh) * 2017-08-25 2018-01-09 东南大学 一种具有干扰抑制的低噪声放大器电路
CN109687885A (zh) * 2017-10-13 2019-04-26 三星电子株式会社 接收器、低噪声放大器以及无线通信装置

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