WO2016127752A1 - 一种用于功率放大器的有源偏置电路及移动终端 - Google Patents

一种用于功率放大器的有源偏置电路及移动终端 Download PDF

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Publication number
WO2016127752A1
WO2016127752A1 PCT/CN2016/070729 CN2016070729W WO2016127752A1 WO 2016127752 A1 WO2016127752 A1 WO 2016127752A1 CN 2016070729 W CN2016070729 W CN 2016070729W WO 2016127752 A1 WO2016127752 A1 WO 2016127752A1
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circuit
voltage
transistor
bias
resistor
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PCT/CN2016/070729
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English (en)
French (fr)
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牛旭
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上海唯捷创芯电子技术有限公司
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Priority to US15/551,042 priority Critical patent/US10153733B2/en
Publication of WO2016127752A1 publication Critical patent/WO2016127752A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/411—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising two power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present invention relates to an active bias circuit for a power amplifier, and to a mobile terminal including the active bias circuit, and belongs to the technical field of power amplifiers.
  • 3G communication systems including WCDMA/TDSCDMA and 4G communication systems including TD-LTE/LTE-FDD have higher linearity requirements for power amplifier output signals than GSM850/EDGE900/DCS1800/PCS1900 in order to achieve high-speed data transmission.
  • the communication mode is required, so the power amplifier is required to have a high linear output power.
  • the duplexer and the filter are bound to bring signal loss, which greatly increases the difficulty of maintaining high linearity of the power amplifier.
  • the bias circuit In power amplifiers, the bias circuit is responsible for providing a suitable and stable bias state for the power amplifier tube, which plays an important role in maintaining the linearity of the power amplifier.
  • the bias circuit of the power amplifier under the existing GSM/EDGE/GPRS system is not fully applicable to the current mainstream 3G/4G mobile phone.
  • the 3G/4G communication standard requires a higher power output from the power amplifier.
  • the temperature of the power amplifier chip will gradually increase (mainly in the rise of the junction temperature of the power amplifier tube).
  • the bias circuit should ensure that the power amplifier tube maintains a stable bias state as much as possible.
  • the temperature of the chip can be controlled to avoid loss of control or even burnout of the chip due to continuous temperature rise and current increase;
  • the power amplifier tube is always operated in a relatively stable state by the feedback mechanism, and the drift of the bias state and the deterioration of the linearity caused by the temperature drift are suppressed.
  • the primary technical problem to be solved by the present invention is to provide an active bias circuit for a power amplifier based on an existing chip production process.
  • Another technical problem to be solved by the present invention is to provide a mobile terminal including the above-described active bias circuit.
  • An active bias circuit for a power amplifier comprising a PTAT current source circuit, a reference voltage circuit, an isolation voltage stabilization circuit, and a bias voltage circuit;
  • the input end of the PTAT current source circuit is connected to a voltage source, and the output end is connected to a reference voltage circuit for generating a current proportional to the voltage source and temperature;
  • the reference voltage circuit generates a reference voltage proportional to the current and temperature
  • the isolation voltage stabilizing circuit isolates the reference voltage circuit and the bias voltage circuit, and provides a stable voltage to the bias voltage circuit through a loop of negative feedback;
  • the bias voltage circuit receives the voltage of the isolated voltage circuit while connecting the voltage source for generating a bias voltage of the power amplifier tube.
  • the PTAT current source circuit comprises two sets of current mirror circuits, a plurality of transistors and a resistor; wherein
  • the first set of current mirror circuits includes three PMOS transistors; the sources of the three PMOS transistors are connected to the voltage source, the gates are docked; the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor; and the second PMOS transistor is The drain is connected to the drain of the second NMOS transistor; the drain of the third PMOS transistor is connected to the reference voltage circuit;
  • the second group of current mirror circuits includes the first NMOS transistor and the second NMOS transistor; the gate of the first NMOS transistor is connected to the drain and the gate of the second NMOS transistor, and the source is connected to the first three a diode; a source of the second NMOS transistor is connected to the first resistor;
  • the first triode and the second triode are connected in series and grounded.
  • the first resistor, the third transistor, and the fourth transistor are connected in series and grounded.
  • the first triode and the second triode have equal emission junction areas
  • the third triode and the fourth triode have equal emission junction areas
  • the first The emitter junction area of the transistor needs to be larger than the emitter junction area of the third transistor.
  • the reference voltage circuit comprises a triode and a resistor; wherein
  • One end of the second resistor is respectively connected to the PTAT current source circuit and the isolation voltage stabilizing circuit;
  • the other end of the second resistor is connected to the collector and the base of the fifth transistor; the emitter of the fifth transistor is connected to the collector and the base of the sixth transistor; the sixth three pole The emitter of the tube is grounded.
  • the isolation voltage stabilizing circuit comprises a resistor and a triode; wherein
  • the collector of the seventh triode is connected to the output end of the reference voltage circuit and one end of the third resistor, the base is connected to the other end of the third resistor and the collector of the eighth triode, and the emitter is connected to the fourth a resistor and a base of the eighth transistor;
  • the emitter of the eighth transistor and the other end of the fourth resistor are respectively grounded;
  • a connection point of the seventh transistor, the third resistor, and the eighth transistor is connected to the bias voltage circuit.
  • the emitter of the eighth transistor is grounded through a resistor.
  • the bias voltage circuit is a triode
  • the collector of the ninth transistor is connected to the voltage source, the base receives the voltage provided by the isolation regulator circuit, and the emitter is connected to the base of the power amplifier tube.
  • the bias voltage circuit further includes a plurality of diodes connected in parallel; wherein
  • the anode of each of the diodes is grounded, and the cathode is connected to the collector of the ninth transistor.
  • the active bias circuit further comprises an auto-thermal compensation circuit:
  • the self-heating compensation circuit comprises a triode and a resistor; a base of the thirteenth pole tube is connected to a base of the power amplifier tube, a collector is grounded through a fifth resistor, and an emitter is connected to a collector of the power amplifier tube .
  • the active bias circuit provided by the invention can be implemented based on the existing chip production process, can suppress the bias state drift caused by temperature drift to a certain extent, and provide a stable bias state for the power amplifier tube; Mechanism can effectively overcome the deterioration of linearity caused by temperature rise under high power output state, effectively improve the power amplifier Linearity.
  • Figure 1 is a block diagram of a zero-IF radio frequency transceiver
  • FIG. 2 is a schematic block diagram of an active bias circuit provided by the present invention.
  • FIG. 3 is a schematic structural view of a circuit of a first embodiment of the present invention.
  • FIG. 4 is an equivalent circuit diagram of a diode of the bias voltage circuit of FIG. 3;
  • Figure 5 is a circuit diagram of a bias voltage circuit in the present invention.
  • FIG. 6 is an equivalent circuit diagram of the self-heat compensation circuit of FIG.
  • the active bias circuit includes a PTAT (proportional to absolute temperature) current source circuit 10, a reference voltage circuit 20, an isolation voltage stabilizing circuit 30, and a bias voltage circuit 40.
  • the input end of the PTAT current source circuit 10 is connected to a voltage source, and the output end is connected to the reference voltage circuit 20 for generating a current proportional to the voltage source and the temperature; the reference voltage circuit 20 generates a voltage proportional to the current and the temperature;
  • the isolation voltage stabilizing circuit 30 isolates the reference voltage circuit 20 and the bias voltage circuit 40, and supplies a stable voltage to the bias voltage circuit 40 through a loop of negative feedback; the bias voltage circuit 40 receives the voltage of the isolation voltage stabilizing circuit 30 while connecting the voltage Source, used to generate the bias voltage required by the power amplifier.
  • the active bias circuit does not limit the number of stages of the power amplifier, such as a single-stage power amplifier including a primary power amplifier tube, a multi-stage power amplifier including a three-stage power amplifier tube, and the like.
  • a two-stage power amplifier including two power amplifier tubes will be described below as an embodiment.
  • the power amplifier includes two power amplifier tubes Q1 and Q2, an input matching network, an input bond wire (Bond wire), an inductance of the power amplifier tube Q1, an interstage matching network, an inductance of the power amplifier tube Q2, and an output weld.
  • the bias circuits each include a PTAT current source circuit 10, a reference voltage circuit 20, an isolation voltage stabilizing circuit 30, and a bias voltage circuit 40, and an auto-thermal compensation circuit 50.
  • the PTAT current source circuit 10 and the reference voltage circuit 20 can be shared by two power amplifier tubes.
  • each power amplifier tube needs to be separately configured. The design requirements of each power amplifier tube are different, so the isolation voltage regulator circuit 30 and the bias voltage circuit 40 and the self-heat compensation circuit 50
  • the parameters and the number of components in the medium are adaptively adjusted according to actual needs.
  • the PTAT current source circuit 10 is operative to generate a PTAT current proportional to the voltage source and ambient temperature, including two sets of current mirror circuits, a plurality of transistors, and a resistor.
  • the first set of current mirror circuits includes three PMOS tubes (101a, 101b, 101c).
  • the PMOS transistors 101a and 101b are a pair of mirror current sources, and 101b and 101c are also a pair of mirror current sources.
  • the sources of the three PMOS transistors are connected to the voltage source of the mobile terminal, and the gates are connected to each other.
  • the drains of the PMOS transistors 101a and 101b are respectively connected to a pair of mirror current sources in the second group of current mirror circuits, and the drain of 101c is used as an output terminal of the PTAT current source circuit 10, and is connected to the reference voltage circuit 20.
  • the second set of current mirror circuits includes two NMOS transistors 102a and 102b.
  • the gates of the NMOS transistors 102a and 102b are connected to each other, and are respectively connected to the drains of the PMOS transistor 101a and the NMOS transistor 102a.
  • the drain of the NMOS transistor 102b is connected to the drain of the PMOS transistor 101b.
  • the source of the NMOS transistor 102a is grounded through a series path of two NPN heterojunction bipolar transistors (103a, 104a).
  • the bases of the two transistors 103a, 104a are respectively connected to the respective collectors, and the emitter of the transistor 103a is connected to the collector of the 104a.
  • the emitter of transistor 104a is grounded.
  • the source of the NMOS transistor 102 is grounded through a resistor R1 and a series path of two NPN heterojunction bipolar transistors 103b, 104b.
  • the bases of the two transistors 103b and 104b are connected to the respective collectors, and the emitter of the transistor 103b is connected to the collector of the 104b.
  • the emitter of transistor 104b is grounded.
  • the reference voltage circuit 20 generates a reference voltage Vref proportional to the PTAT current and temperature based on the PTAT current of the PTAT current source circuit 10.
  • Vref is generated using the BE junction of the NPN heterojunction bipolar transistors 202 and 203.
  • the reference voltage circuit 20 includes transistors 202, 203 and a resistor R2.
  • the resistor R2 is connected to the PTAT current source circuit 10 and the isolation regulator circuit 30, and the other end is connected to the collector and the base of the transistor 202.
  • the emitter of transistor 202 is coupled to the collector and base of transistor 203, and the emitter of transistor 203 is coupled to ground.
  • the generation of the reference voltage Vref will be described below in conjunction with a specific calculation process.
  • the emitter junction areas of the PTAT current source circuit 10 transistors 103a and 104a need to be equal to S1; the emitter junction areas of the transistors 103b and 104b are equal, and if S2 is set, S1 is satisfied. S2.
  • V BE1 V BE103a +V BE104a
  • V BE2 the sum of the BE junction voltages of the transistors 103b and 104b, V BE2 .
  • V BE2 V BE103b +V BE104b
  • the BE junction voltages V BE1 and V BE2 have the following relationship with the voltage V R1 on the resistor R1, namely:
  • the bandgap reference source and the temperature characteristics of the NPN transistor, it can be known that it has a positive temperature coefficient, that is,
  • the reference voltage circuit 20 In order to obtain a reference voltage Vref having a zero temperature coefficient, the reference voltage circuit 20 must include a component having a negative temperature coefficient, and the transistor of the NPN has exactly this characteristic, that is,
  • a reference voltage Vref having a zero temperature coefficient can be obtained.
  • a reference voltage having a zero temperature coefficient is obtained by selecting an appropriate resistance value of R1, R2:
  • the isolation regulator circuit 30 is used to achieve effective isolation of the reference voltage circuit 20 from the bias voltage circuit 40, to avoid the reference voltage circuit 20 from being disturbed by load variations, and to pass negative feedback.
  • the loop guarantees the stability of the output voltage.
  • the isolation regulator circuit 30 of the first stage power amplifier tube of FIG. 3 includes two NPN heterojunction bipolar transistors 301, 302 and two resistors R3, R4.
  • the resistor R3 and the collector of the transistor 301 are simultaneously connected to the output terminal of the reference voltage circuit 20.
  • the other end of the resistor R3 serves as an output of the isolation regulator circuit 30, and is also connected to the base of the transistor 301 and the collector of the transistor 302, respectively.
  • the emitter of transistor 301 is on the one hand the base of transistor 302 The pole is connected, and the other end is grounded through the resistor R4. The emitter of transistor 302 is directly grounded.
  • the transistor in the second-stage isolation regulator circuit is grounded through a resistor. Specifically, the components are set according to actual needs. The voltage regulation principle of the isolation regulator circuit 30 will be described in detail below.
  • the BE junction potential V BE301 and the collector current I CC301 of the transistor 301 rise, that is:
  • the BE junction voltage of the transistor 302 rises, the collector current of the transistor 302 rises, and the voltage drop of the resistor R3 rises.
  • the isolation regulator circuit 30 can maintain the potential of the Vb in a stable state by introducing a negative feedback loop, thereby effectively isolating the reference voltage circuit 20 from the load.
  • the bias voltage circuit 40 is coupled to the output of the isolation regulator circuit 30 and the device voltage source Vbat for generating a voltage Vbias for biasing the power amplifier tube Q1.
  • the bias voltage circuit 40 in this embodiment can not only realize the bias voltage but also introduce a compensation mechanism. Through the action of compensation, the power amplifier tube is always in a relatively stable bias state.
  • the bias voltage circuit 40 of the first stage power amplifier tube includes an NPN heterojunction bipolar transistor 401 and a PN junction diode 402.
  • the base of the transistor 401 is connected to the output end of the isolation voltage stabilizing circuit 30, and the cathode of the diode 402 is connected to the device voltage source Vbat, and the emitter is used as an output terminal, and is directly connected to the base of the power amplifier tube Q1. .
  • the emitter of the transistor 401 is connected to the base of the power amplifying tube Q2 through a resistor.
  • the anode of diode 402 is grounded.
  • a parallel path of a plurality of diodes is used, and the number of diodes used herein is not specifically limited.
  • the compensation mechanism of the bias voltage circuit 40 will be described below.
  • the BE junction turn-on voltage decreases, which in turn causes the bias current to rise.
  • the specific function of the transistor 401 and the diode parallel path 402 is to compensate for the BE junction turn-on voltage of the power amplifier tube Q1, and the BE junction voltage also drops, and the power amplifier tube Q1 can always be in a stable bias state.
  • 4 is an equivalent circuit diagram of the diode 402 of FIG.
  • the reverse-connected diode 402 can be equivalent to a parallel network of variable capacitor C1 and resistor R1. As shown in FIG. 5, the presence of capacitors C1 and R1 causes the base portion of the transistor 401 to the left to have a characteristic impedance R at the radio frequency point, that is,
  • a decrease in the characteristic impedance value R causes the RF power to leak to the ground by the reverse biased diode 402.
  • the leaked power produces a compensation current at the BE junction of transistor 401.
  • the power leaked through diode 402 to ground increases.
  • the temperature of the chip rises and the turn-on voltage of the power amplifier tube Q1 drops.
  • the compensation current continues to rise, the transistor
  • the bias voltage obtained by the BE junction of 401 is decreasing, and the collector current does not continue to increase so as to burn out the tube, so that the power amplifier tube Q1 is always in a relatively stable bias state.
  • the bias circuit also adds an auto-thermal compensation circuit 50.
  • the circuit can automatically compensate the gain of the RF power amplifier tube Q1 according to the temperature inside the chip.
  • the self-heating compensation circuit 50 occupies a small chip area, and can be realized by a conventional process. For details, see FIG.
  • the self-heat compensation circuit 50 includes an NPN heterojunction bipolar transistor 501 and a resistor R5.
  • the base of the transistor 501 is connected to the output end of the reference voltage circuit 20 and the base of the power amplifier tube Q1, the emitter is connected to the collector of the power amplifier tube Q1, and the collector is grounded through the resistor R5.
  • the transistor 501 in the compensation circuit 50 serves as a switch for compensating the path. Selecting a resistor R5 of a suitable size can control the time during which the switch is turned on and determine the amount of compensation.
  • the increase in the junction temperature of the internal transistor of the chip causes the power gain of the transistor to decrease.
  • an increase in the voltage V CE between the collector and the emitter further reduces the gain.
  • the specific performance is that the mobile phone is hot, the output power is reduced, and the signal quality is deteriorated.
  • the self-heating compensation circuit 50 can be equivalent to a variable resistor that bases the power amplifier tube Q1 to ground, and the switch in the path is controlled by the power tube Q1 voltage V CE .
  • the variable resistance value controls the compensation current value, and the switch determines whether the compensation path is opened or closed.
  • the compensation path switch turns on, generating a compensation current I B1 . Since the power amplifier tube Q1 operates in a constant current drive state, in order to maintain the overall current I B , the voltage V CE between the collector and the emitter of the power amplifier tube Q1 rises, and the V BE between the base and the emitter When it is lowered, the compensation current I B1 is lowered, and the current I B -I B1 entering the power tube Q1 is increased. Although the junction temperature rise causes the gain of the power tube to decrease, the compensation current generated by the self-heat compensation circuit 50 of the present invention maintains the collector current of the power tube not to decrease, so that the power amplifier tube generally exhibits a constant power gain.
  • the above is mainly introduced to the bias circuit composition of the first-stage power amplifier tube Q1. Since the working state of the second-stage power amplifier tube Q2 and the first-stage power amplifier tube Q1 are not completely the same, including the working temperature, the emitter area, and the offset type (Class A, Class AB) Or Class B) is not the same. Therefore, when the power amplifier includes a multi-stage power amplifier tube, the schematic diagrams of the bias voltage circuit and the self-heat compensation circuit of each stage are similar to those of the first-stage power amplifier tube, but the number of parallel diodes and the compensation resistor are specifically The values vary and need to be based on the specific power amplifier design needs.
  • the invention also discloses a mobile terminal, wherein the power amplifier of the mobile terminal adopts the above-mentioned active bias circuit.
  • the term "communication terminal” as used herein refers to a computer device that can be used in a mobile environment and supports various communication systems such as Wi-Fi, GSM, EDGE, TD_SCDMA, TDD_LTE, FDD_LTE, etc., including but not limited to 3G/4G mobile phones, notebook computers, Tablet PC, car computer, etc.
  • the active bias circuit is also suitable for other power amplifier applications, such as communication base stations compatible with a variety of communication systems.
  • the PTAT current source circuit and the reference voltage circuit can generate current and voltage proportional to temperature, and the isolation voltage regulator circuit simultaneously ensures the bias circuit through the negative feedback loop.
  • the stable output to some extent, suppresses the drift of the bias state caused by temperature drift, providing a stable bias state for the chip.
  • the bias voltage circuit and the self-heating compensation circuit overcome the deterioration of the linearity caused by the temperature rise under the high power output state through the compensation principle, and effectively improve the linearity of the RF power amplifier.

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Abstract

一种用于功率放大器的有源偏置电路及移动终端。该电路包括PTAT电流源电路(10)、基准电压电路(20)、隔离稳压电路(30)以及偏置电压电路(40)；其中，PTAT电流源电路(10)输入端连接到电压源(Vbat)，输出端连接基准电压电路(20)，用于产生与电压源(Vbat)和温度成比例的电流；基准电压电路(20)产生与电流和温度成比例的基准电压；隔离稳压电路(30)隔离基准电压电路(20)和偏置电压电路(40)，通过负反馈的环路为偏置电压电路(40)提供稳定电压；偏置电压电路(40)接收隔离稳压电路(30)的电压，同时连接电压源(Vbat)，用于产生功率放大管(Q1)的偏置电压。所述有源偏置电路能够在一定程度上抑制温度漂移导致的偏置状态漂移，同时克服大功率输出状态下温度升高所导致的线性度恶化。

Description

一种用于功率放大器的有源偏置电路及移动终端 技术领域
本发明涉及一种用于功率放大器的有源偏置电路，同时还涉及一种包含该有源偏置电路的移动终端，属于功率放大器技术领域。
背景技术
众所周知，包括WCDMA/TDSCDMA的3G通信系统，以及包括TD-LTE/LTE-FDD的4G通信系统，为了实现高速数据传输，对功率放大器输出信号的线性度要求远高于GSM850/EDGE900/DCS1800/PCS1900等通信模式，所以要求功率放大器具有较高的线性输出功率。从图1可以看出，双工器、滤波器势必带来信号损耗，大大增加了保持功率放大器高线性度的难度。
在功率放大器中，偏置电路负责为功率放大管提供合适的且稳定偏置状态，对于保持功率放大器的线性度有着重要作用。但是，现有GSM/EDGE/GPRS制式下功率放大器的偏置电路已经不能完全适用于当下主流的3G/4G手机。3G/4G通信标准要求功率放大器有更高功率输出。然而在高功率的输出状态下，功率放大器芯片的温度会逐渐升高(主要表现在功率放大管结温的升高)。而偏置电路要使功率放大管尽量保持稳定的偏置状态，需要满足两个条件：其一，实现芯片温度可控，避免因温度持续上升与电流增加造成的失控甚至烧毁芯片；其二，通过反馈机制使功率放大管始终工作于相对稳定的状态中，抑制了温漂所导致的偏置状态的漂移和线性度的恶化。
目前，工业界及学术界虽然已经提出过一些满足上述条件的偏置电路结构，但其中很多偏置电路结构在生产和使用过程中表现出一定的不足，例如增加工艺难度、损失功率增益和效率、增加芯片面积和成本等。例如，专利号为ZL 200780009732.5的中国发明专利中，公开了一种功率放大器中的动态偏置控制电路。然而，功率放大器本身是一种比较浪费芯片面积的设计方案，相应此专利所引入的偏置电路结构也较为复杂，不适用于3G/4G手机功率放大器芯片。再例如，专利号为ZL 01122022.8的中国发明专利中，公开了一种用于射频放大 器的有源偏置网络电路。而该专利中的功率放大器偏置电路是一种繁琐的结构，需要功率放大器模组中必须包含单独的一颗基于CMOS工艺的偏置电路芯片，增加了射频功率放大器芯片的设计实现难度和成本。
基于上述可知，目前真正适用于移动通信的功率放大器偏置电路还不能满足实践中的需要。
发明内容
针对现有技术的不足，本发明所要解决的首要技术问题在于提供一种基于现有芯片生产工艺、用于功率放大器的有源偏置电路。
本发明所要解决的另一技术问题在于提供一种包含上述有源偏置电路的移动终端。
为实现上述发明目的，本发明采用下述的技术方案：
一种用于功率放大器的有源偏置电路，包括PTAT电流源电路、基准电压电路、隔离稳压电路以及偏置电压电路；其中，
所述PTAT电流源电路输入端连接到电压源，输出端连接基准电压电路，用于产生与所述电压源和温度成比例的电流；
所述基准电压电路产生与所述电流和温度成比例的基准电压；
所述隔离稳压电路隔离所述基准电压电路和所述偏置电压电路，通过负反馈的环路为所述偏置电压电路提供稳定电压；
所述偏置电压电路接收所述隔离电压电路的电压，同时连接所述电压源，用于产生功率放大管的偏置电压。
其中较优地，所述PTAT电流源电路包括两组电流镜电路、多个三极管和电阻；其中，
第一组电流镜电路包括三个PMOS管；三个PMOS管的源极连接所述电压源，栅极对接；第一PMOS管的漏极连接第一NMOS管的漏极；第二PMOS管的漏极连接第二NMOS管的漏极；第三PMOS管的漏极连接所述基准电压电路；
第二组电流镜电路包括所述第一NMOS管和所述第二NMOS管；所述第一NMOS管的栅极连接漏极和所述第二NMOS管的栅极，源极连接第一三极管；所述第二NMOS管的源极连接第一电阻；
所述第一三极管与第二三极管串联后接地，
所述第一电阻、第三三极管和第四三极管串联后接地。
其中较优地，所述第一三极管和第二三极管的发射结面积相等，所述第三三极管和所述第四三极管的发射结面积相等，且所述第一三极管的发射结面积需大于所述第三三极管的发射结面积。
其中较优地，所述基准电压电路包括三极管和一个电阻；其中，
第二电阻的一端分别连接所述PTAT电流源电路和所述隔离稳压电路；
所述第二电阻的另一端连接第五三极管的集电极和基极；所述第五三极管的发射极连接第六三极管的集电极和基极；所述第六三极管的发射极接地。
其中较优地，所述隔离稳压电路包括电阻和三极管；其中，
第七三极管的集电极连接所述基准电压电路的输出端和第三电阻的一端，基极连接所述第三电阻的另一端与第八三极管的集电极，发射极连接第四电阻和所述第八三极管的基极；
所述第八三极管的发射极和所述第四电阻的另一端分别接地；
所述第七三极管、所述第三电阻和所述第八三极管的连接点连接所述偏置电压电路。
其中较优地，所述第八三极管的发射极通过电阻接地。
其中较优地，所述偏置电压电路为三极管；其中，
第九三极管的集电极连接所述电压源，基极接收所述隔离稳压电路提供的电压，发射极连接所述功率放大管的基极。
其中较优地，所述偏置电压电路还包括多个并联的二极管；其中，
各所述二极管的阳极接地，阴极连接所述第九三极管的集电极。
其中较优地，所述有源偏置电路还包括自热补偿电路：
所述自热补偿电路包括三极管和电阻；第十三极管的基极与所述功率放大管的基极相连接，集电极通过第五电阻接地，发射极连接所述功率放大管的集电极。
一种移动终端，其中的功率放大器采用上述的有源偏置电路。
本发明所提供的有源偏置电路可以基于现有的芯片生产工艺实现，能够在一定程度上抑制温度漂移导致的偏置状态漂移，为功率放大管提供稳定的偏置状态；同时引入的补偿机制，可以有效克服大功率输出状态下温度升高所导致的线性度恶化，有效提高功率放大器的 线性度。
附图说明
图1为一个零中频射频收发机的结构框图；
图2为本发明所提供的有源偏置电路的原理框图；
图3为本发明中，第一实施例的电路结构示意图；
图4为图3中偏置电压电路的二极管的等效电路图；
图5为本发明中，偏置电压电路的电路图；
图6为图3中自热补偿电路的等效电路图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容进行详细说明。
参见图2，本发明所提供的有源偏置电路包括PTAT(proportional to absolute temperature,与绝对温度成正比)电流源电路10、基准电压电路20、隔离稳压电路30以及偏置电压电路40。其中，PTAT电流源电路10的输入端连接到电压源，输出端连接基准电压电路20，用于产生与电压源和温度成比例的电流；基准电压电路20产生与电流和温度成比例的电压；隔离稳压电路30隔离基准电压电路20和偏置电压电路40，通过负反馈的环路为偏置电压电路40提供稳定电压；偏置电压电路40接收隔离稳压电路30的电压，同时连接电压源，用于产生功率放大器所需的偏置电压。需要说明的是，本有源偏置电路不限制功率放大器的级数，例如包含一级功率放大管的单级功率放大器、包含三级功率放大管的多级功率放大器等。下面以包含两个功率放大管的两级功率放大器为实施例进行说明。
参见图3，该功率放大器包括两个功率放大管Q1和Q2、输入匹配网络、输入焊线(Bond wire)、功率放大管Q1的电感、级间匹配网络、功率放大管Q2的电感、输出焊线、输出匹配网络以及功率放大管Q1和Q2相应的偏置电路。偏置电路均包括PTAT电流源电路10、基准电压电路20、隔离稳压电路30以及偏置电压电路40以及自热补偿电路50。其中PTAT电流源电路10、基准电压电路20可以为两个功率放大管共用。而隔离稳压电路30以及偏置电压电路40以及自热补偿电路50中则每个功率放大管需要单独配置。每个功率放大管的设计需求不同，因此隔离稳压电路30以及偏置电压电路40以及自热补偿电路50 中元件的参数、个数等根据实际需求进行适应性调整。
在本发明的一个实施例中，PTAT电流源电路10是用于产生与电压源和环境温度成比例的PTAT电流包括两组电流镜电路、多个三极管和电阻。第一组电流镜电路包括三个PMOS管(101a、101b、101c)。PMOS管101a和101b为一对镜像电流源，同时101b与101c也为一对镜像电流源。三个PMOS管的源极连接移动终端的电压源，栅极均相互连接。PMOS管101a、101b漏极分别连接第二组电流镜电路中的一对镜像电流源，101c的漏极作为PTAT电流源电路10的输出端，连接基准电压电路20。第二组电流镜电路包括两个NMOS管102a和102b。其中NMOS管102a和102b栅极相互连接，同时分别与PMOS管101a、NMOS管102a的漏极连接。NMOS管102b的漏极与PMOS管101b的漏极连接。NMOS管102a的源极则通过两个NPN异质结双极的晶体管(103a、104a)的串联通路接地。其中，两个晶体管103a、104a的基极分别与各自的集电极连接，晶体管103a的发射极连接104a的集电极。晶体管104a的发射极接地。NMOS管102的源极通过电阻R1、两个NPN异质结双极晶体管103b、104b的串联通路接地。其中，两个晶体管103b、104b的基极与各自的集电极连接，晶体管103b的发射极连接104b的集电极。晶体管104b的发射极接地。
基准电压电路20根据PTAT电流源电路10的PTAT电流，产生与PTAT电流和温度成比例的基准电压Vref。为了保持Vref与隔离稳压电路30、Vbias电压产生电路的相应结点电位基本吻合，基准电压Vref的产生采用NPN异质结双极晶体管202及203的BE结实现。
在本发明的一个实施例中，基准电压电路20包括晶体管202、203和电阻R2。其中电阻R2的连接PTAT电流源电路10和隔离稳压电路30，另一端连接晶体管202的集电极和基极。晶体管202的发射极和晶体管203的集电极和基极相连接，晶体管203的发射极接地。下面结合具体计算过程对基准电压Vref的生成进行说明。
在本发明的一个实施例中，PTAT电流源电路10晶体管103a与104a的发射结面积需相等，设为S1；晶体管103b与104b的发射结面积均相等，且设为S2，则需满足S1>S2。
假设，晶体管103a与104a的BE结电压之和VBE1，则可得：
VBE1＝VBE103a+VBE104a
同理，晶体管103b与104b的BE结电压之和VBE2，则可得：
VBE2＝VBE103b+VBE104b
BE结电压VBE1、VBE2与电阻R1上的电压VR1之间有如下关系，即：
ΔVBE＝VR1＝VBE1-VBE2
根据带隙基准源的定义以及NPN晶体管的温度特性可以知道，具有正温度系数，也即
Figure PCTCN2016070729-appb-000001
为了得到具有零温度系数的基准电压Vref，基准电压电路20必须包含具有负温度系数的组成部分，而NPN的晶体管恰好具有此特性，也即
Figure PCTCN2016070729-appb-000002
因此，将ΔVBE与VBE做合适的加权，即可得到具有零温度系数的基准电压Vref。在本发明的一个实施例中，通过选择合适的R1、R2电阻值，即可得到具有零温度系数的基准电压：
Figure PCTCN2016070729-appb-000003
在本发明的一个实施例中，隔离稳压电路30用于实现基准电压电路20与偏置电压电路40的有效隔离，避免基准电压电路20免受负载变化的干扰之外，还可以通过负反馈环路保证输出电压的稳定性。图3中的第一级功率放大管的隔离稳压电路30包括两个NPN异质结双极晶体管301、302和两个电阻R3、R4。其中，电阻R3与晶体管301的集电极同时连接到基准电压电路20的输出端。电阻R3的另一端则作为隔离稳压电路30的输出，同时还分别与晶体管301的基极以及晶体管302的集电极相连接。晶体管301的发射极一方面晶体管302的基 极连接，另一方面通过电阻R4端接地。晶体管302的发射极直接接地。而第二级隔离稳压电路中晶体管通过电阻接地。具体地，元件的设置需根据实际需求而定。下面对隔离稳压电路30的稳压原理进行详细说明。
随着输出功率的增加与减小，功率放大器芯片的温度会随之上升或者下降。该种情况反映在偏置电路中，即隔离稳压电路30输出电压Vb的上升或者下降。为了阐述隔离稳压电路30的负反馈原理，这里假设Vb受到工作环境温度的变化而有所上升，即：
ΔVb＞0
也就是晶体管301的BE结电位VBE301和集电极电流ICC301上升，即：
ΔVBE301＞0
ΔICC301＞0
因此意味着电阻R4上的电压降ΔVR4上升，即：
ΔVR4＝ΔICC301*R4＞0
则必然导致晶体管302的BE结电压上升、晶体管302的集电极电流上升、电阻R3的电压降上升，
ΔVBE302＞0
ΔICC302＞0
ΔVR3＝ΔICC302*R3＞0
而电阻R3的电压降上升必然导致Vb电位的下降，
ΔVb＜0
通过电阻R3反馈支路致使Vb向原来相反趋势变化，使得输出电压Vb逐渐趋于稳定。反之，Vb向相反趋势的变化，经过负反馈环路也能够逐渐调节并使之趋于稳定，具体这里不在进行赘述。综上分析，隔离稳压电路30通过引入负反馈环路，可以维持Vb的电位处于稳定状态，实现基准电压电路20与负载的有效隔离。
在本发明的一个实施例中，偏置电压电路40同时连接隔离稳压电路30输出端和设备电压源Vbat，用于产生用来偏置功率放大管Q1的电压Vbias。本实施例中的偏置电压电路40不仅可以实现偏置电压，同时还引入了补偿机制。通过补偿的作用，使功率放大管始终处于较为稳定的偏置状态。图3所示，第一级功率放大管的偏置电压电路40包括NPN异质结双极晶体管401、以及PN结二极管402。其中，晶体管401的基极与隔离稳压电路30的输出端相连接，同时二极管402的阴极，集电极与设备电压源Vbat连接，发射极作为输出端，直接连接至功率放大管Q1的基极。本实施例中第二级功率放大管的偏置电压电路40中，晶体管401的发射极通过电阻连接功率放大管Q2的基极。二极管402的阳极接地。本实施例中采用多个二极管的并联通路，这里二极管采用的个数不做具体限定。
下面对偏置电压电路40的补偿机制进行说明。功率放大管Q1在温度升高时，BE结开启电压降低，进而导致偏置电流上升。三极管401和二极管并联通路402的具体作用是通过补偿使得功率放大管Q1的BE结开启电压下降的同时，BE结电压也下降，则功率放大管Q1就可以始终处于稳定的偏置状态。图4所示为图3中二极管402的等效电路图。反向连接的二极管402可以等效为可变电容C1与电阻R1的并联网络。如图5所示，电容C1和R1的存在，使得晶体管401基极向左的电路部分，其在射频点处的特征阻抗R降低，也即：
Figure PCTCN2016070729-appb-000004
在射频功率点，特征阻抗值R的降低导致射频功率由反偏的二极管402泄露到地。而泄露的功率在晶体管401的BE结产生补偿电流。随着功率增加，经二极管402泄露到地的功率增加。芯片的温度上升，功率放大管Q1的开启电压下降。而此时补偿电流持续上升，晶体管 401的BE结得到的偏置电压在下降，集电极电流不会持续增大以至于烧毁管子，从而使功率放大管Q1始终处于较稳定的偏置状态。
在本发明的一个实施例中，偏置电路还增加了自热补偿电路50。该电路根据芯片内部的温度，可以自动补偿射频功率放大管Q1的增益。截至目前，工业界已经提出的克服芯片自热效应的方法，有些过度依赖于新工艺降低热阻，有些会导致功率的损失或者芯片面积大幅增加。而本实施例中的自热补偿电路50占用很少的芯片面积，采用常规工艺即可实现，具体参见图3。自热补偿电路50包括NPN异质结双极晶体管501和电阻R5。其中，晶体管501的基极分别连接基准电压电路20输出端和功率放大管Q1的基极，发射极连接到功率放大管Q1的集电极，集电极则通过电阻R5接地。补偿电路50中的晶体管501作为补偿通路的开关，选择合适大小的电阻R5可以控制开关打开的时间，同时决定补偿量的大小。
根据异质结双极型晶体管的温度特性可知，芯片内部晶体管结温上升会导致晶体管功率增益下降。尤其是大功率工作状态下，集电极和发射极之间的电压VCE增大会进一步降低增益。具体表现为手机发烫、输出功率降低、信号质量变差等。参见图6，自热补偿电路50可以等效为一个将功率放大管Q1基极到地的可变电阻，而通路中开关受控于功率管Q1电压VCE。其中可变电阻值控制补偿电流值，开关决定补偿通路打开或者关闭。输入信号较小时，功率管Q1的增益下滑并不明显，开关处于开路状态，不产生补偿电流。而随着输入信号的增大，补偿通路开关导通，产生补偿电流IB1。由于功率放大管Q1工作在恒定电流驱动的状态，为了维持整体电流IB不变，功率放大管Q1的集电极与发射极之间的电压VCE上升，基极与发射极之间的VBE降低，同时补偿电流IB1降低，而进入功率管Q1的电流IB-IB1会增加。虽然结温上升会导致功率管的增益下降，通过本发明自热补偿电路50产生的补偿电流维持功率管的集电极电流并未降低，使功率放大管总体表现出恒定的功率增益。
需要说明的是，上面主要介绍了第一级功率放大管Q1的偏置电路组成。由于第二级功率放大管Q2与第一级功率放大管Q1的工作状态并非完全相同，包括工作温度、发射极面积、偏置种类(A类、AB类 或者B类)等都不相同。因此当功率放大器包含多级的功率放大管时，各级的偏置电压电路、自热补偿电路的原理图与第一级功率放大管的原理图均类似，但具体并联二极管的数量、补偿电阻值有所不同，需要根据具体功率放大器设计需求而定。
本发明还公开了一种移动终端，该移动终端的功率放大器采用上述的有源偏置电路。这里所说的通信终端指可以在移动环境中使用、支持Wi-Fi、GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括但不限于3G/4G移动电话、笔记本电脑、平板电脑、车载电脑等。此外，该有源偏置电路也适用于其他功率放大器应用的场合，例如兼容多种通信制式的通信基站等。
综上所述，本发明所提供的有源偏置电路中，PTAT电流源电路和基准电压电路可以产生与温度成比例的电流和电压，隔离稳压电路同时通过负反馈环路保证偏置电路的稳定输出，在一定程度上抑制温度漂移导致的偏置状态漂移，为芯片提供稳定的偏置状态。同时偏置电压电路和自热补偿电路，通过补偿原理克服大功率输出状态下温度升高所导致的线性度恶化，有效提高射频功率放大器的线性度。
以上对本发明所提供的用于功率放大器的有源偏置电路及移动终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质精神的前提下对它所做的任何显而易见的改动，都将构成对本发明专利权的侵犯，将承担相应的法律责任。

Claims (10)

  1. 一种用于功率放大器的有源偏置电路，其特征在于包括PTAT电流源电路、基准电压电路、隔离稳压电路以及偏置电压电路；其中，
    所述PTAT电流源电路输入端连接到电压源，输出端连接基准电压电路，用于产生与所述电压源和温度成比例的电流；
    所述基准电压电路产生与所述电流和温度成比例的基准电压；
    所述隔离稳压电路隔离所述基准电压电路和所述偏置电压电路，通过负反馈的环路为所述偏置电压电路提供稳定电压；
    所述偏置电压电路接收所述隔离电压电路的电压，同时连接所述电压源，用于产生功率放大管的偏置电压。
  2. 如权利要求1所述的有源偏置电路，其特征在于所述PTAT电流源电路包括两组电流镜电路、多个三极管和电阻；其中，
    第一组电流镜电路包括三个PMOS管；各所述PMOS管的源极连接所述电压源，栅极对接；第一PMOS管的漏极连接第一NMOS管的漏极；第二PMOS管的漏极连接第二NMOS管的漏极；第三PMOS管的漏极连接所述基准电压电路；
    第二组电流镜电路包括所述第一NMOS管和所述第二NMOS管；所述第一NMOS管的栅极连接漏极和所述第二NMOS管的栅极，源极连接第一三极管；所述第二NMOS管的源极连接第一电阻；
    所述第一三极管与第二三极管串联后接地，
    所述第一电阻、第三三极管和第四三极管串联后接地。
  3. 如权利要求2所述的有源偏置电路，其特征在于：
    所述第一三极管和第二三极管的发射结面积相等，所述第三三极管和所述第四三极管的发射结面积相等，且所述第一三极管的发射结面积需大于所述第三三极管的发射结面积。
  4. 如权利要求1所述的有源偏置电路，其特征在于所述基准电压电路包括三极管和一个电阻；其中，
    第二电阻的一端分别连接所述PTAT电流源电路和所述隔离稳压电路；
    所述第二电阻的另一端连接第五三极管的集电极和基极；所述第 五三极管的发射极连接第六三极管的集电极和基极；所述第六三极管的发射极接地。
  5. 如权利要求1所述的有源偏置电路，其特征在于所述隔离稳压电路包括多个电阻和三极管；其中，
    第七三极管的集电极连接所述基准电压电路的输出端和第三电阻的一端，基极连接所述第三电阻的另一端与第八三极管的集电极，发射极连接第四电阻和所述第八三极管的基极；
    所述第八三极管的发射极和所述第四电阻的另一端分别接地；
    所述第七三极管、所述第三电阻和所述第八三极管的连接点连接所述偏置电压电路。
  6. 如权利要求5所述的有源偏置电路，其特征在于：
    所述第八三极管的发射极通过电阻接地。
  7. 如权利要求1所述的有源偏置电路，其特征在于所述偏置电压电路为三极管；其中，
    第九三极管的集电极连接所述电压源，基极接收所述隔离稳压电路提供的电压，发射极连接所述功率放大管的基极。
  8. 如权利要求7所述的有源偏置电路，其特征在于所述偏置电压电路还包括多个并联的二极管；其中，
    各所述二极管的阳极接地，阴极连接所述第九三极管的集电极。
  9. 如权利要求1所述的有源偏置电路，其特征在于：
    所述有源偏置电路还包括自热补偿电路：
    所述自热补偿电路包括三极管和电阻；第十三极管的基极与所述功率放大管的基极相连接，集电极通过第五电阻接地，发射极连接所述功率放大管的集电极。
  10. 一种移动终端，其特征在于所述移动终端的功率放大器采用权利要求1～9中任意一项所述的有源偏置电路。
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