WO2018233659A1 - 氮化镓半导体器件及其制备方法 - Google Patents

氮化镓半导体器件及其制备方法 Download PDF

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Publication number
WO2018233659A1
WO2018233659A1 PCT/CN2018/092140 CN2018092140W WO2018233659A1 WO 2018233659 A1 WO2018233659 A1 WO 2018233659A1 CN 2018092140 W CN2018092140 W CN 2018092140W WO 2018233659 A1 WO2018233659 A1 WO 2018233659A1
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layer
gallium nitride
gate
dielectric layer
contact hole
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PCT/CN2018/092140
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English (en)
French (fr)
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刘美华
林信南
刘岩军
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深圳市晶相技术有限公司
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Publication of WO2018233659A1 publication Critical patent/WO2018233659A1/zh

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    • H01L29/0611—
    • H01L29/0638—
    • H01L29/402—
    • H01L29/42356—
    • H01L29/475—
    • H01L29/66462—
    • H01L29/7783—

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  • the present application relates to the field of semiconductor processes, and in particular, to a gallium nitride semiconductor device and a method of fabricating the same.
  • Gallium nitride has the advantages of large forbidden band width, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, so that a semiconductor material can be fabricated using gallium nitride to obtain a gallium nitride semiconductor device.
  • a gallium nitride semiconductor device is prepared by forming a silicon nitride layer on a surface of a gallium nitride epitaxial layer, and etching a source contact hole and a drain contact hole on the silicon nitride layer.
  • Metal is deposited in the contact hole and the drain contact hole to form a source and a drain; and the silicon nitride layer and the aluminum gallium nitride layer in the gallium nitride epitaxial layer are etched to form a groove in the groove A dielectric layer and a metal layer are deposited to form a gate electrode; then a silicon dioxide layer and a field plate metal layer are deposited to form a gallium nitride semiconductor device.
  • attention has been paid to how to increase the on current and reduce the on-resistance.
  • the present application provides a gallium nitride semiconductor device including: a gallium nitride epitaxial layer; and a composite dielectric layer disposed on the gallium nitride epitaxial layer, the composite dielectric layer is nitrided Silicon and plasma enhanced orthosilicate; a source, a drain and a gate disposed on the composite dielectric layer, the source and the drain respectively extending through the composite dielectric layer and the gallium nitride epitaxial a layer connection; wherein the gate includes a first gate portion and a second gate portion connected to each other, the first gate portion and the second gate portion both penetrating through the composite dielectric layer and passing through the first gate portion a gate dielectric layer under the bottom of the bottom and the second gate is connected to the gallium nitride epitaxial layer; an insulating layer disposed on the source, the drain and the gate, and the composite dielectric layer, the insulating layer
  • the material is silicon dioxide; a field plate metal layer
  • the present application further provides a gallium nitride semiconductor device, comprising: a gallium nitride epitaxial layer; and a composite dielectric layer disposed on the gallium nitride epitaxial layer; a source and a drain disposed on the composite dielectric layer a gate and a gate, wherein the source and the drain are respectively connected to the gallium nitride epitaxial layer through the composite dielectric layer; wherein the gate includes a first gate portion and a second gate portion connected to each other The first gate portion and the second gate portion both penetrate the composite dielectric layer and are connected to the gallium nitride epitaxial layer through a gate dielectric layer located under the bottom of the first gate portion and the bottom portion of the second gate portion; An insulating layer on the source, the drain and the gate, and the composite dielectric layer; a field plate metal layer disposed on the insulating layer, the field plate metal layer penetrating the insulating layer and the source a pole connection; and a plurality of floating
  • the present application also provides a method for fabricating such a gallium nitride semiconductor device, comprising: providing a gallium nitride epitaxial layer, wherein the gallium nitride epitaxial layer comprises a silicon substrate layer and a gallium nitride layer disposed in order from bottom to top And an aluminum gallium nitride layer; depositing silicon nitride and plasma-enhanced orthosilicate on the surface of the gallium nitride epitaxial layer to form a composite dielectric layer; etching the composite dielectric layer to form a drain contact hole, and Depositing a first metal in the drain contact hole and on a surface of the composite dielectric layer; etching the composite dielectric layer to form a source contact hole and a plurality of floating field plate contact holes, and Depositing the first metal in a source contact hole and a surface of the plurality of floating field plate contact holes on the surface of the composite dielectric layer; performing photolithography and etching on the first metal to form
  • the present application applies a novel material through a composite dielectric layer on the surface of a gallium nitride epitaxial layer, and also performs a high temperature annealing treatment by depositing a first metal to pass the etched first metal and aluminum gallium nitride layer in contact with each other. An alloy is formed after the reaction to reduce the contact resistance of the etched first metal to the aluminum gallium nitride layer.
  • the depletion region of the power device is expanded, and the electric field strength of the metal-insulator-semiconductor (MIS) structure is reduced, thereby improving the withstand voltage of the device.
  • MIS metal-insulator-semiconductor
  • FIG. 1a is a schematic structural view of a gallium nitride semiconductor device according to still another embodiment of the present application.
  • FIG. 1b is a schematic diagram of a gate structure of a gallium nitride semiconductor device according to still another embodiment of the present application.
  • FIG. 1c is a schematic diagram of a preparation process of a gallium nitride semiconductor device according to still another embodiment of the present application.
  • FIG. 2a is a schematic structural view of a gallium nitride semiconductor device according to still another embodiment of the present application.
  • FIG. 2b is a schematic diagram of a preparation process of a gallium nitride semiconductor device according to still another embodiment of the present application.
  • 3a is a schematic structural view of a gallium nitride semiconductor device according to another embodiment of the present application.
  • FIG. 3b is a schematic diagram of a gate structure of a gallium nitride semiconductor device according to another embodiment of the present application.
  • FIG. 3c is a schematic diagram of a preparation process of a gallium nitride semiconductor device according to another embodiment of the present application.
  • a gallium nitride semiconductor device which includes a gallium nitride epitaxial layer 310, a composite dielectric layer 320, a source 331 and a drain 332, and a gate from bottom to top. 333.
  • the gallium nitride epitaxial layer 310 is composed of a silicon (Si) substrate 312, a gallium nitride (GaN) layer 313, and an aluminum gallium nitride (AlGaN) layer 314, wherein the silicon substrate 312, the gallium nitride layer 313, and The aluminum gallium nitride layer 314 is disposed in order from bottom to top.
  • the composite dielectric layer 320 is disposed on the gallium nitride epitaxial layer 310.
  • the composite dielectric layer 320 of the present embodiment may be, for example, silicon nitride and plasma enhanced orthosilicate (PETEOS).
  • PETEOS plasma enhanced orthosilicate
  • the silicon nitride and plasma enhanced orthosilicate are a high-k dielectric.
  • a source 331 , a drain 332 , and a gate 333 are disposed on the composite dielectric layer 320 .
  • the source 331 , the drain 332 and the gate 333 are partially inserted into the composite dielectric layer 320 like a “nail”, and the source 331 and the drain 332 respectively penetrate the composite dielectric layer 320 and the gallium nitride epitaxial layer.
  • 310 is connected; and a portion protrudes from the top of the composite dielectric layer 320.
  • the gate 333 extends through the composite dielectric layer 320 and is connected to the gallium nitride epitaxial layer 310 through a gate dielectric layer 360 located underneath its bottom portion; and a portion protrudes from the top of the composite dielectric layer 320.
  • the source 331 and/or the drain 332 are composed of a first metal.
  • the first metal includes, for example, a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer disposed in order from bottom to top, wherein the first titanium metal layer may have a thickness of, for example, 200 angstroms, aluminum metal.
  • the thickness of the layer may be, for example, 1200 angstroms
  • the thickness of the second titanium metal layer may be, for example, 200 angstroms
  • the thickness of the titanium nitride layer may be, for example, 200 angstroms.
  • the source 331 and the drain 332 formed by using the first metal material can react with the aluminum gallium nitride layer 314 in the gallium nitride epitaxial layer 310 during high-temperature annealing of the device to form an alloy, thereby making the source 331
  • the contact between the drain 332 and the contact surface of the aluminum gallium nitride layer is good, and the contact resistance between the source 331 and the drain 332 and the aluminum gallium nitride layer can be effectively reduced; leakage of the gallium nitride semiconductor device and soft blow are avoided. Wear the problem.
  • the gate 333 of the present embodiment includes two portions connected in parallel: a longer one is a reinforced first gate portion 333a and a shorter one is a depletion second gate portion 333b.
  • the first gate portion 333a is connected to the surface of the aluminum gallium nitride layer 314 through a gate dielectric layer 360 located under the bottom portion thereof, and protrudes into the aluminum gallium nitride layer 314; the second gate portion 333b
  • the surface of the aluminum gallium nitride layer 314 is connected by a gate dielectric layer 360 located underneath its bottom.
  • the gate formed by the two lengths is distinguished from the existing gate and presents a "profile".
  • the width D1 of the first gate portion 333a is, for example, not smaller than the width D2 of the second gate portion 333b.
  • the left and right positions of the first gate portion 333a and the second gate portion 333b may also be interchanged.
  • the gate 333a may extend downward into the aluminum gallium nitride layer 314, and the distance from the bottom end of the gate dielectric layer 360 under the gate 333a to the bottom of the aluminum gallium nitride layer 314 H is, for example, half of the entire aluminum gallium nitride layer 314.
  • the entire gate 333 is composed of a second metal which is Ni, an Au alloy.
  • the material of the gate dielectric layer 360 is, for example, a high-k (high dielectric) material such as silicon nitride, silicon oxide or hafnium oxide.
  • the insulating layer 340 is disposed over the drain 332, the gate 333 and a portion of the source 331 and the exposed composite dielectric layer 320.
  • the insulating layer 340 is made of silicon dioxide. Among them, the insulating layer 340 is uniformly deposited on the entire surface of the device, and the thickness of the precipitate is the same everywhere. Due to the presence of the source 331 , the drain 332 , and the gate 333 , the insulating layer 340 between the source 331 and the gate 333 and the insulating layer 340 between the gate 33 and the drain 332 are recessed downward. It can be smoothed by subsequent smoothing steps.
  • a field plate metal layer 350 may also be included, for example, disposed on the insulating layer 340.
  • the field plate metal layer 350 is connected to the source electrode 331 through the insulating layer 340.
  • the material of the field plate metal layer 350 is an aluminum silicon copper metal layer.
  • the present application also provides a method of preparing the above gallium nitride semiconductor device. As shown in Figure 1c, the specific steps include:
  • Step 301 sequentially depositing a gallium nitride layer 313 and an aluminum gallium nitride layer 314 on the silicon substrate 312 to form a gallium nitride epitaxial layer 310.
  • Gallium nitride is the third generation of wide bandgap semiconductor materials with large band gap, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, and high voltage, high frequency, High temperature, high power and anti-irradiation environment have strong advantages, so it is the best material for studying short-wave optoelectronic devices and high-voltage high-frequency high-power devices; among them, the large forbidden band width is 3.4 eV, high electron saturation rate At 2e7 cm per second, the high breakdown electric field is 1e10 to ⁇ 3e10 volts per centimeter.
  • a layer of silicon nitride and plasma enhanced orthosilicate (PETEOS) may then be deposited on the surface of the gallium nitride epitaxial layer 310 using a plasma enhanced chemical vapor deposition method to form a composite dielectric layer 120.
  • PETEOS plasma enhanced orthosilicate
  • the thickness of silicon nitride and plasma-enhanced orthosilicate may be, for example, 2000 angstroms.
  • Step 302 dry etching the composite dielectric layer 320 to form a source contact hole 321 and a drain contact hole 322 which are oppositely disposed.
  • a impurity removing step is also included.
  • the method of “DHF (diluted hydrofluoric acid) + chemical cleaning agent SC ⁇ 1+ chemical cleaning agent SC ⁇ 2” may be used first, for example, The device is treated with a diluted hydrofluoric acid solution, and then the device is treated with an alkaline mixed solution of hydrogen peroxide and ammonium hydroxide, and the device is treated with an acidic mixed solution of hydrogen peroxide and hydrogen chloride, thereby removing the surface of the entire device. Impurities.
  • Step 303 in the present embodiment, depositing a first metal in the source contact hole 321 and the drain contact hole 322, and on the surface of the composite dielectric layer 120.
  • a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and the like may be sequentially deposited on the surface of the source contact hole and the drain contact hole and the surface of the composite dielectric layer by a magnetron sputtering coating process.
  • a titanium nitride layer to form a first metal wherein the first titanium metal layer may have a thickness of, for example, 200 angstroms, the aluminum metal layer may have a thickness of, for example, 1200 angstroms, and the second titanium metal layer may have a thickness of, for example, 200 angstroms.
  • the thickness of the titanium nitride layer may be, for example, 200 angstroms.
  • the first metal is photolithographically and etched to form an ohmic contact electrode window 319.
  • the first metal is photolithographically and etched, wherein the photolithographic process includes gluing, exposing, and developing to form an ohmic contact electrode window 319; through the ohmic contact electrode window 319, the composite dielectric layer 320 is visible. Part of the surface.
  • the first metal on the source contact hole 121 constitutes the source 331 of the device
  • the first metal on the drain contact hole 322 constitutes the drain 332 of the device.
  • the device obtained at this time is named as the first component.
  • Step 304 performing a high temperature annealing treatment on the entire first component to form an alloy by reacting the etched first metal and the aluminum gallium nitride layer 314 in contact with each other.
  • a nitrogen gas is introduced into the reaction furnace, and the entire first assembly is subjected to a high temperature annealing treatment for 30 seconds in an environment of 840 to 850 ° C, so that the first metal after etching becomes an alloy.
  • an alloy may also be formed on the contact surface thereof, so that contact between the first metal and the aluminum gallium nitride layer 314 can be reduced. resistance. That is, the contact resistance between the source electrode 331, the drain 332, and the aluminum gallium nitride layer 314 is lowered.
  • Step 305 dry etching the composite dielectric layer 320 and the aluminum gallium nitride layer 314 through the ohmic contact electrode window 319 to form a gate contact hole 323, wherein the bottom of the gate contact hole 323 and the aluminum gallium nitride layer The bottom of 314 has a preset distance.
  • the composite dielectric layer 320 and a portion of the aluminum gallium nitride layer 314 are dry etched through the ohmic contact electrode window 319 by a dry etching method to form a first device.
  • the first etching only the portion of the composite dielectric layer 320 is performed to obtain a shallow second contact hole 323b; and the second contact obtained by the first etching during the second dry etching
  • the hole 323b is biased to one side and etched through the entire composite dielectric layer 320 and then deep into the partial aluminum gallium nitride layer 314 to form a deeper first contact hole 323a; thus obtaining the entire gate contact hole 323 .
  • the proportional relationship between the width D1 of the first gate portion and the width D2 of the second gate portion is controlled by controlling the etching process parameter to adjust the width of the gate contact hole 323b.
  • a gate dielectric layer 360 is then deposited on the bottom of the gate contact hole 323a and the gate contact hole 323b.
  • Step 306 then depositing Ni/Au in the gate contact hole 323a, the gate contact hole 323b, and a part of the composite dielectric layer 320, the metal thickness is 0.01-0.04 ⁇ m/0.08-0.4 ⁇ m; obtaining the gate 333 . It can be seen that the preparation of the first gate portion 333a and the second gate portion 333b is also integrally formed by the two gate contact holes actually communicating with each other.
  • the first contact hole 323a completely penetrates the composite dielectric layer 320 and passes through a portion of the aluminum gallium nitride layer 314 such that the bottom of the first contact hole 323a is spaced from the bottom of the aluminum gallium nitride layer 314.
  • H may be, for example, one half of the aluminum gallium nitride layer 314.
  • impurities such as impurities, particles, and ions may be present in the gate contact hole 323, so that the gate contact hole 320 may be cleaned with a hydrochloric acid solution, and the gate contact hole 320 may be removed. The impurities inside are removed.
  • the impurity on the device is removed by using DHF+SC1+SC2; and after the gate contact hole 323 is formed, the gate is made with a hydrochloric acid solution.
  • the impurities in the contact hole 323 are removed. Therefore, the surface of the composite dielectric layer and the cleaning in the gate contact hole 323 can be effectively ensured, thereby ensuring the performance of the gallium nitride semiconductor device.
  • the device obtained at this time is named as the second component.
  • Step 307 depositing an insulating layer 340 on the surface of the entire second component.
  • a layer of silicon oxide (SiO 2 ) is deposited on the surface of the entire second component, and the thickness may be, for example, 5000 ⁇ , and a silicon dioxide layer is formed as an insulating layer 340.
  • the silicon dioxide is uniformly deposited on the surface of the entire device, and the thickness is the same everywhere. Due to the presence of the source electrode 331, the drain electrode 332 and the gate electrode 333, the insulating layer 340 between the source electrode 331 and the gate electrode 333, The insulating layer 340 between the gate 333 and the drain 332 is recessed downward and can be flattened by a smoothing process.
  • Step 308 after dry etching the insulating layer 340 above the source contact hole 331, forming an opening 341.
  • the source 331 has a protrusion protruding from the outside of the source contact hole 321 , and the width of the opening 341 is smaller than the width of the protrusion of the source 331 .
  • Step 309 depositing a field plate metal 350 in the opening 341 and on the insulating layer 340 extending from above the source contact hole 321 to above the gate contact hole 323 to form the field plate metal layer 350.
  • a magnetron sputtering coating process may be employed, in the opening 341, and the first metal from the outer edge of the source contact hole 321 to the first edge of the gate contact hole 323.
  • a field plate metal is deposited on the composite dielectric layer 320 over the metal to a thickness of, for example, 10,000 angstroms to form the field plate metal layer 350.
  • the thickness of the field plate metal layer 350 is uniform, and the field plate metal layer 350 is recessed downward at the position of the opening 341 and at the position between the source contact hole 321 and the gate contact hole 323.
  • the smoothing process in the subsequent steps smoothes it.
  • the gallium nitride semiconductor device of the present embodiment employs a hybrid gate structure including a long first gate portion 333a belonging to the enhancement type and a second second gate portion 333b belonging to the depletion type.
  • the first gate portion 333a is turned off, and the second gate portion 333b can lock the channel potential at the drain voltage to provide a high blocking capability; in the on state, the enhanced channel and the depletion state
  • the type channel provides low channel resistance, ensuring high on-current and low on-resistance.
  • the gallium nitride semiconductor device obtained in this embodiment can be applied to technical fields such as power electronic components, filters, and radio communication components, and has a good application prospect.
  • an embodiment of the present application provides a gallium nitride semiconductor device, which includes a gallium nitride epitaxial layer 510, a composite dielectric layer 520, a source 531 and a drain 532, and a gate 533 from bottom to top.
  • the gallium nitride epitaxial layer 510 is composed of a silicon (Si) substrate 512, a gallium nitride (GaN) layer 513, and an aluminum gallium nitride (AlGaN) layer 514, wherein the silicon substrate 512, the gallium nitride layer 513, and The aluminum gallium nitride layer 514 is disposed in order from bottom to top.
  • the composite dielectric layer 520 is disposed on the gallium nitride epitaxial layer 510.
  • the composite dielectric layer 520 of the embodiment may be, for example, silicon nitride and plasma enhanced orthosilicate (PETEOS).
  • PETEOS plasma enhanced orthosilicate
  • the silicon nitride and plasma enhanced orthosilicate are a high-k dielectric.
  • a source 531, a drain 532, and a gate 533 are disposed on the composite dielectric layer 520. Specifically, the source 520, the drain 532, and the gate 533 are partially inserted into the composite dielectric layer 520 like a "nail", and the source 531 and the drain 532 respectively penetrate the composite dielectric layer 520 and the The gallium nitride epitaxial layer 510 is connected; and a portion protrudes from the top of the composite dielectric layer 520.
  • the gate 533 extends through the composite dielectric layer 520 and is connected to the gallium nitride epitaxial layer 510 through a gate dielectric layer 560 located below the bottom thereof; and a portion protrudes from the top of the composite dielectric layer 520.
  • the source 531 and/or the drain 532 are composed of a first metal.
  • the composition of the first metal is as shown in the above embodiment.
  • the source 531 and the drain 532 formed by using the first metal material can react with the aluminum gallium nitride layer 514 in the gallium nitride epitaxial layer 510 during high-temperature annealing of the device to form an alloy, thereby making the source 531
  • the contact between the drain 532 and the contact surface of the aluminum gallium nitride layer is good, and the contact resistance between the source 531, the drain 532 and the aluminum gallium nitride layer can be effectively reduced; the leakage of the gallium nitride semiconductor device and the soft blow are avoided. Wear the problem.
  • the gate 533 extends downward into the aluminum gallium nitride layer 514, and the distance from the bottom end of the gate 533 to the bottom of the aluminum gallium nitride layer 514 is, for example, the entire aluminum nitride.
  • the gate electrode 533 is composed of a second metal which is Ni, an Au alloy.
  • the material of the gate dielectric layer 560 is, for example, a high-k (high dielectric) material such as silicon nitride, silicon oxide or hafnium oxide.
  • a plurality of floating field plates 535 disposed on the composite dielectric layer 520 are further disposed, and the floating field plate 535 is connected to the gallium nitride epitaxial layer 510 through the composite dielectric layer 520, and The floating field plate 535 is independently disposed between the source and the drain and has an annular shape.
  • each floating field plate 535 can be, for example, 0.25 to 6 microns.
  • the insulating layer 540 is disposed on the drain 532, the gate 533 and a portion of the source 531, and the exposed composite dielectric layer 520.
  • the insulating layer 540 is made of silicon dioxide. Among them, the insulating layer 540 is uniformly deposited on the entire surface of the device, and the thickness of the precipitate is the same everywhere. Due to the presence of the source 531, the drain 532, and the gate 533, the insulating layer 540 between the source 531 and the gate 533 and the insulating layer 540 between the gate 533 and the drain 532 are recessed downward. It can be smoothed by the smoothing process.
  • a field plate metal layer 550 may also be included, for example, disposed on the insulating layer 540.
  • the field plate metal layer 550 is connected to the source electrode 531 through the insulating layer 540.
  • the material of the field plate metal layer 550 is an aluminum silicon copper metal layer.
  • the present application also provides a method of preparing the above gallium nitride semiconductor device. As shown in Figure 2b, the specific steps include:
  • Step 501 depositing a gallium nitride layer 513 and an aluminum gallium nitride layer 514 on the silicon substrate 512 to form a gallium nitride epitaxial layer 510.
  • Gallium nitride is the third generation of wide bandgap semiconductor materials with large band gap, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, and high voltage, high frequency, High temperature, high power and anti-irradiation environment have strong advantages, so it is the best material for studying short-wave optoelectronic devices and high-voltage high-frequency high-power devices; among them, the large forbidden band width is 3.4 eV, high electron saturation rate At 2e7 cm per second, the high breakdown electric field is 1e10 to ⁇ 3e10 volts per centimeter.
  • a layer of silicon nitride and plasma enhanced orthosilicate (PETEOS) may then be deposited on the surface of the gallium nitride epitaxial layer 510 using a plasma enhanced chemical vapor deposition method to form a composite dielectric layer 520.
  • PETEOS plasma enhanced orthosilicate
  • the thickness of silicon nitride and plasma-enhanced orthosilicate may be, for example, 2000 angstroms.
  • Step 502 dry etching the composite dielectric layer 520 to form a drain contact hole 522, and depositing a first metal in the drain contact hole 522 to form a corresponding electrode.
  • a drain contact hole 522 is first formed on the composite dielectric layer 520; then, a first titanium metal layer and an aluminum metal are sequentially deposited on the surface of the drain contact hole and the surface of the composite dielectric layer by a magnetron sputtering coating process.
  • a layer, a second titanium metal layer and a titanium nitride layer to form a first metal wherein the first titanium metal layer may have a thickness of, for example, 200 angstroms, and the aluminum metal layer may have a thickness of, for example, 1200 angstroms, the second titanium metal layer
  • the thickness may be, for example, 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms.
  • a drain is formed.
  • Step 503 dry etching the composite dielectric layer 520 to form a source contact hole 521 and a plurality of floating field plate contact holes 525, and further a source contact hole 521 and a plurality of floating field plate contact holes 525.
  • a first metal is deposited on the surface of the composite dielectric layer 520.
  • a first titanium metal layer and an aluminum metal layer may be sequentially deposited on the surface of the source contact hole 521 and the plurality of floating field plate contact holes 525 and a portion of the composite dielectric layer 520 by using a magnetron sputtering coating process.
  • a second titanium metal layer and a titanium nitride layer to form a first metal wherein the thickness of the first titanium metal layer may be, for example, 200 angstroms, and the thickness of the aluminum metal layer may be, for example, 1200 angstroms, the thickness of the second titanium metal layer For example, it may be 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms.
  • each floating field plate 535 may be, for example, 0.25 to 6 micrometers.
  • a impurity removing step is also included.
  • the method of “DHF (diluted hydrofluoric acid) + chemical cleaning agent SC ⁇ 1+ chemical cleaning agent SC ⁇ 2” may be used first, for example, The device is treated with a diluted hydrofluoric acid solution, and then the device is treated with an alkaline mixed solution of hydrogen peroxide and ammonium hydroxide, and the device is treated with an acidic mixed solution of hydrogen peroxide and hydrogen chloride, thereby removing the surface of the entire device. Impurities.
  • the first metal is photolithographically and etched to form a plurality of ohmic contact electrode windows 519.
  • the first metal is photolithographically and etched, wherein the lithographic process includes gluing, exposing, and developing to form an ohmic contact electrode window 519; through the ohmic contact electrode window 519, the composite dielectric layer 520 can be seen. Part of the surface.
  • the first metal on the source contact hole 521 constitutes the source 531 of the device
  • the first metal on the drain contact hole 522 constitutes the drain 532 of the device.
  • the device obtained at this time is named as the first component.
  • Step 504 the entire first component is subjected to a high temperature annealing treatment to form an alloy by reacting the etched first metal and the aluminum gallium nitride layer 514 in contact with each other.
  • a nitrogen gas is introduced into the reaction furnace, and the entire first assembly is subjected to a high temperature annealing treatment for 30 seconds in an environment of 840 to 850 ° C, so that the first metal after etching becomes an alloy.
  • the etched first metal in contact with each other and the aluminum gallium nitride layer 514 may also form an alloy on the contact surface thereof, thereby reducing the contact between the first metal and the aluminum gallium nitride layer 514. resistance. That is, the contact resistance between the source 531, the drain 532, and the aluminum gallium nitride layer 514 is lowered.
  • Step 505 dry etching the composite dielectric layer 520 and the aluminum gallium nitride layer 514 through the ohmic contact electrode window 519 to form a gate contact hole 523, wherein the bottom of the gate contact hole 523 and the aluminum gallium nitride layer The bottom of the 514 has a preset distance.
  • the composite dielectric layer 520 and a portion of the aluminum gallium nitride layer 514 are dry etched through the ohmic contact electrode window 519 by dry etching, thereby forming a first device.
  • the gate contact hole 523 completely penetrates the composite dielectric layer 520 and passes through a portion of the aluminum gallium nitride layer 514 such that the distance between the bottom of the gate contact hole 523 and the bottom of the aluminum gallium nitride layer 514 is, for example, One half of the aluminum gallium nitride layer 514.
  • impurities such as impurities, particles, and ions are present in the gate contact hole 523, so that the gate contact hole 520 can be cleaned with a hydrochloric acid solution, and the gate contact hole 520 can be cleaned.
  • the impurities inside are removed.
  • the impurities on the device are removed by the method of DHF+SC1+SC2; and after the gate contact hole 523 is formed, the gate contact hole 523 is treated with a hydrochloric acid solution. The impurities inside are removed. Therefore, the surface of the composite dielectric layer and the cleaning in the gate contact hole 523 can be effectively ensured, thereby ensuring the performance of the gallium nitride semiconductor device.
  • a gate dielectric layer 560 is then deposited on the bottom of the gate contact hole 523.
  • Step 506 in this embodiment, specifically, using a magnetron sputtering coating process, depositing Ni/Au as a second metal in the gate contact hole 523 and a portion of the composite dielectric layer 520, and the metal thickness is 0.01 to 0.04. Mm/0.08 to 0.4 ⁇ m; thereby constituting the gate electrode 533.
  • the device obtained at this time is named as the second component.
  • Step 507 depositing an insulating layer 540 on the surface of the entire second component.
  • a layer of silicon oxide (SiO 2 ) is deposited on the surface of the entire second component, and the thickness may be, for example, 5,000 angstroms, and a silicon dioxide layer is formed as an insulating layer 540.
  • the silicon dioxide is uniformly deposited on the surface of the entire device, and the thickness is the same everywhere. Due to the presence of the source electrode 531, the drain electrode 532 and the gate electrode 533, the insulating layer 540 between the source electrode 531 and the gate electrode 533, The insulating layer 540 between the gate 533 and the drain 532 is recessed downward and can be flattened by a smoothing process.
  • Step 508 after dry etching the insulating layer 540 over the source contact hole 531, forming an opening 541.
  • the source 531 has a protrusion protruding from the outside of the source contact hole 521, and the width of the opening 541 is smaller than the width of the protrusion of the source 531.
  • Step 509 depositing a field plate metal 550 in the opening 541 and on the insulating layer 540 extending from above the source contact hole 521 to above the gate contact hole 523 to form a field plate metal layer 550.
  • a magnetron sputtering coating process may be employed, in the opening 541, and the first metal from the outer edge of the source contact hole 521 to the first edge of the gate contact hole 523.
  • a field plate metal is deposited on the composite dielectric layer 520 over the metal to a thickness of, for example, 10,000 angstroms to form a field plate metal layer 550.
  • the thickness of the field plate metal layer 550 is uniform, and the field plate metal layer 550 is recessed downward at the position of the opening 541 and at the position between the source contact hole 521 and the gate contact hole 523. This condition can be leveled in a subsequent leveling process.
  • the depletion region of the power device in combination with the floating field plate, is expanded by the floating field plate, and the electric field strength of the MIS structure is reduced, thereby improving the withstand voltage of the device.
  • the gallium nitride semiconductor device obtained in this embodiment can be applied to technical fields such as power electronic components, filters, and radio communication components, and has a good application prospect.
  • an embodiment of the present application provides a gallium nitride semiconductor device including a gallium nitride epitaxial layer 810, a composite dielectric layer 820, a source 831 and a drain 832, a gate 833, and an insulation from bottom to top.
  • Layer 840 and gate dielectric layer 860 are examples of a gallium nitride semiconductor device.
  • the gallium nitride epitaxial layer 810 is composed of a silicon (Si) substrate 812, a gallium nitride (GaN) layer 813, and an aluminum gallium nitride (AlGaN) layer 814, wherein the silicon substrate 812, the gallium nitride layer 813, and The aluminum gallium nitride layer 814 is disposed in order from bottom to top.
  • the composite dielectric layer 820 is disposed on the gallium nitride epitaxial layer 810; the composite dielectric layer 820 of the embodiment may be, for example, silicon nitride and plasma enhanced orthosilicate (PETEOS).
  • PETEOS plasma enhanced orthosilicate
  • the silicon nitride and plasma enhanced orthosilicate are a high-k dielectric.
  • a source 831, a drain 832, and a gate 833 are disposed on the composite dielectric layer 820. Specifically, the source 831, the drain 832, and the gate 833 are partially inserted into the composite dielectric layer 820 like a "nail" portion, and the source 831 and the drain 832 respectively penetrate the composite dielectric layer 820 and the The gallium nitride epitaxial layer 810 is connected; and a portion protrudes from the top of the composite dielectric layer 820.
  • a gate electrode 833 extends through the composite dielectric layer 820 and is connected to the gallium nitride epitaxial layer 810 through a gate dielectric layer 860 located below its bottom portion; and a portion protrudes from the top of the composite dielectric layer 820.
  • the source 831 and/or the drain 832 are composed of a first metal as shown in the above embodiment.
  • the source 831 and the drain 832 formed by using the first metal material can react with the aluminum gallium nitride layer 814 in the gallium nitride epitaxial layer 810 during high-temperature annealing of the device to form an alloy, thereby making the source 831
  • the contact between the drain 832 and the contact surface of the aluminum gallium nitride layer is good, and the contact resistance between the source 831, the drain 832 and the aluminum gallium nitride layer can be effectively reduced; the leakage of the gallium nitride semiconductor device and the soft blow are avoided. Wear the problem.
  • the gate electrode 833 of the present embodiment includes two portions connected in parallel: a longer one is a reinforced first gate portion 833a and a shorter one is a depletion second gate portion 833b.
  • the first gate portion 833a is connected to the surface of the aluminum gallium nitride layer 814 through a gate dielectric layer 860 located under the bottom portion thereof, and the second gate portion 833b extends into the aluminum gallium nitride layer 814, and
  • the surface of the aluminum gallium nitride layer 814 is connected by a gate dielectric layer 860 located under the bottom of the second gate portion 833b.
  • the gate formed by the two lengths is distinguished from the existing gate and presents a "profile".
  • width D1 of the first gate portion 833a is, for example, not smaller than the width D2 of the second gate portion 833b.
  • the left and right positions of the first gate portion 833a and the second gate portion 833b may also be interchanged.
  • the gate 833a may extend downward into the aluminum gallium nitride layer 314, and the distance from the bottom end of the gate dielectric layer 860 under the gate 833a to the bottom of the aluminum gallium nitride layer 814 H is, for example, half of the entire aluminum gallium nitride layer 814.
  • the entire gate 833 is composed of a second metal which is Ni, an Au alloy.
  • the material of the gate dielectric layer 860 is, for example, a high-k (high dielectric) material such as silicon nitride, silicon oxide or hafnium oxide.
  • a plurality of floating field plates 835 disposed on the composite dielectric layer 820 are further disposed, and the floating field plate 835 is connected to the gallium nitride epitaxial layer 810 through the composite dielectric layer 820, and The floating field plate 835 is independently disposed between the source 831 and the drain 832 and has an annular shape.
  • each floating field plate 835 can be, for example, 0.25 to 6 microns.
  • the insulating layer 840 is disposed over the drain 832, the gate 833 and a portion of the source 831, and the exposed composite dielectric layer 820.
  • the insulating layer 840 is made of silicon dioxide. Among them, the insulating layer 840 is uniformly deposited on the entire surface of the device, and the thickness of the precipitate is the same everywhere. Due to the presence of the source 831, the drain 832, and the gate 833, the insulating layer 840 between the source 831 and the gate 833 and the insulating layer 840 between the gate 833 and the drain 832 are recessed downward. It can be smoothed by the smoothing process.
  • a field plate metal layer 850 may also be included, for example, disposed on the insulating layer 840.
  • the field plate metal layer 850 is connected to the source electrode 831 through the insulating layer 840.
  • the material of the field plate metal layer 850 is an aluminum silicon copper metal layer.
  • the gallium nitride semiconductor device of the present embodiment employs a hybrid gate structure including a long first gate portion belonging to the enhancement type and a short second gate portion belonging to the depletion type.
  • the first gate is turned off, and the second gate can lock the channel potential at the drain voltage to provide high blocking capability; in the on state, the enhanced channel and the depletion trench
  • the channel provides low channel resistance, ensuring high on-current and low on-resistance.
  • the present application also provides a method of preparing the above gallium nitride semiconductor device. As shown in Figure 3c, the specific steps include:
  • Step 801 depositing a gallium nitride layer 813 and an aluminum gallium nitride layer 814 on the silicon substrate 812 to form a gallium nitride epitaxial layer 810.
  • Gallium nitride is the third generation of wide bandgap semiconductor materials with large band gap, high electron saturation rate, high breakdown electric field, high thermal conductivity, corrosion resistance and radiation resistance, and high voltage, high frequency, High temperature, high power and anti-irradiation environment have strong advantages, so it is the best material for studying short-wave optoelectronic devices and high-voltage high-frequency high-power devices; among them, the large forbidden band width is 3.4 eV, high electron saturation rate At 2e7 cm per second, the high breakdown electric field is 1e10 to ⁇ 3e10 volts per centimeter.
  • a layer of silicon nitride and plasma enhanced orthosilicate (PETEOS) may then be deposited on the surface of the gallium nitride epitaxial layer 810 using a plasma enhanced chemical vapor deposition method to form a composite dielectric layer 820.
  • PETEOS plasma enhanced orthosilicate
  • the thickness of silicon nitride and plasma-enhanced orthosilicate may be, for example, 2000 angstroms.
  • Step 802 dry etching the composite dielectric layer 820 to form a drain contact hole 822; and depositing a first metal on the surface of the drain contact hole 822 and the surface of the composite dielectric layer 820 to form a corresponding drain electrode.
  • a drain contact hole 822 is first formed on the composite dielectric layer 820; then, a first titanium metal layer and an aluminum metal are sequentially deposited on the surface of the drain contact hole and the surface of the composite dielectric layer by a magnetron sputtering coating process.
  • a layer, a second titanium metal layer and a titanium nitride layer to form a first metal wherein the first titanium metal layer may have a thickness of, for example, 200 angstroms, and the aluminum metal layer may have a thickness of, for example, 1200 angstroms, the second titanium metal layer
  • the thickness may be, for example, 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms.
  • a drain is formed.
  • Step 803 dry etching the composite dielectric layer 820 to form a source contact hole 821 and a plurality of floating field plate contact holes; and further a source contact hole 821 and a plurality of floating field plate contact holes 825, A first metal is deposited on the surface of the composite dielectric layer 820 to form a source and a plurality of floating field plates.
  • a first titanium metal layer and an aluminum metal layer may be sequentially deposited on the surface of the source contact hole 821 and the plurality of floating field plate contact holes 825 and the partial composite dielectric layer 820 by using a magnetron sputtering coating process.
  • a second titanium metal layer and a titanium nitride layer to form a first metal wherein the thickness of the first titanium metal layer may be, for example, 200 angstroms, and the thickness of the aluminum metal layer may be, for example, 1200 angstroms, the thickness of the second titanium metal layer For example, it may be 200 angstroms, and the thickness of the titanium nitride layer may be, for example, 200 angstroms.
  • each floating field plate 835 can be, for example, 0.25 to 6 microns.
  • a impurity removing step is also included.
  • the method of “DHF (diluted hydrofluoric acid) + chemical cleaning agent SC ⁇ 1+ chemical cleaning agent SC ⁇ 2” may be used first, for example, The device is treated with a diluted hydrofluoric acid solution, and then the device is treated with an alkaline mixed solution of hydrogen peroxide and ammonium hydroxide, and the device is treated with an acidic mixed solution of hydrogen peroxide and hydrogen chloride, thereby removing the surface of the entire device. Impurities.
  • the first metal is photolithographically and etched to form a plurality of ohmic contact electrode windows 819.
  • the first metal is photolithographically and etched, wherein the lithographic process includes gluing, exposing, and developing to form an ohmic contact electrode window 819; through the ohmic contact electrode window 819, the composite dielectric layer 820 can be seen. Part of the surface.
  • the first metal on the source contact hole 821 constitutes the source 831 of the device
  • the first metal on the drain contact hole 822 constitutes the drain 832 of the device.
  • the device obtained at this time is named as the first component.
  • Step 804 performing a high temperature annealing treatment on the entire first component to form an alloy by reacting the etched first metal and the aluminum gallium nitride layer 814 in contact with each other.
  • a nitrogen gas is introduced into the reaction furnace, and the entire first assembly is subjected to a high temperature annealing treatment for 30 seconds in an environment of 840 to 850 ° C, so that the first metal after etching becomes an alloy.
  • the etched first metal in contact with each other and the aluminum gallium nitride layer 814 may also form an alloy on the contact surface thereof, thereby reducing the contact between the first metal and the aluminum gallium nitride layer 814. resistance. That is, the contact resistance between the source electrode 831, the drain electrode 832, and the aluminum gallium nitride layer 14 is lowered.
  • Step 805 dry etching the composite dielectric layer 820 and the aluminum gallium nitride layer 814 through the ohmic contact electrode window 819 to form a gate contact hole 823, wherein the bottom of the gate contact hole 823 and the aluminum gallium nitride layer The bottom of 814 has a preset distance.
  • the composite dielectric layer 820 and a portion of the aluminum gallium nitride layer 814 are dry etched through the ohmic contact electrode window 819 by dry etching, thereby forming a first device.
  • Gate contact hole 823 completely penetrates the composite dielectric layer 820 and passes through a portion of the aluminum gallium nitride layer 814 such that the distance H between the bottom of the gate contact hole 823 and the bottom of the aluminum gallium nitride layer 814 is, for example. It is half of the aluminum gallium nitride layer 814.
  • the gate contact hole 823 is made to have an upper width and a lower, inverted trapezoidal shape.
  • impurities such as impurities, particles, and ions may be present in the gate contact hole 823, so that the gate contact hole 820 can be cleaned with a hydrochloric acid solution, and the gate contact hole 820 can be cleaned. The impurities inside are removed.
  • the impurity on the device is removed by using DHF+SC1+SC2; and after the gate contact hole 823 is formed, the gate contact hole 823 is formed with a hydrochloric acid solution.
  • the impurities inside are removed. Therefore, the surface of the composite dielectric layer and the cleaning in the gate contact hole 823 can be effectively ensured, thereby ensuring the performance of the gallium nitride semiconductor device.
  • a gate dielectric layer 860 is then deposited on the bottom of the gate contact hole 823.
  • Step 806 in this embodiment, specifically, using a magnetron sputtering coating process, depositing Ni/Au as a second metal in the gate contact hole 823 and a portion of the composite dielectric layer 820, the metal thickness is 0.01-0.04 Mm/0.08 to 0.4 ⁇ m; thus constituting the gate electrode 833.
  • the device obtained at this time is named as the second component.
  • Step 807 depositing an insulating layer 840 over the surface of the entire second component.
  • a layer of silicon dioxide (SiO 2 ) is deposited on the surface of the entire second component, and the thickness may be, for example, 5000 angstroms, and a silicon dioxide layer is formed as an insulating layer 840.
  • the silicon dioxide is uniformly deposited on the surface of the entire device, and the thickness is the same everywhere. Due to the presence of the source electrode 831, the drain electrode 832 and the gate electrode 833, the insulating layer 840 between the source electrode 831 and the gate electrode 833, The insulating layer 840 between the gate 833 and the drain 832 is recessed downward and can be flattened by a smoothing process.
  • Step 808 after dry etching the insulating layer 840 above the source contact hole 831, an opening 841 is formed.
  • the source electrode 831 has a protrusion protruding from the outside of the source contact hole 821, and the width of the opening 841 is smaller than the width of the protrusion of the source electrode 831.
  • Step 809 depositing a field plate metal 850 over the opening 841 and over the insulating layer 840 extending over the source contact hole 821 over the gate contact hole 823 to form a field plate metal layer 850.
  • a magnetron sputtering coating process may be employed, in the opening 841, and the first metal from the outer edge of the source contact hole 821 to the first edge of the gate contact hole 823.
  • a field plate metal is deposited on the composite dielectric layer 820 over the metal to a thickness of, for example, 10,000 angstroms to form a field plate metal layer 850.
  • the thickness of the field plate metal layer 850 is uniform, and the field plate metal layer 850 is recessed downward at the position of the opening 841 and at the position between the source contact hole 821 and the gate contact hole 823.
  • the smoothing process of the subsequent steps makes it smooth.
  • the gallium nitride semiconductor device of the present embodiment employs a hybrid gate structure including a long first gate portion belonging to the enhancement type and a short second gate portion belonging to the depletion type.
  • the first gate is turned off, and the second gate can lock the channel potential at the drain voltage to provide high blocking capability; in the on state, the enhanced channel and the depletion trench
  • the channel provides low channel resistance, ensuring high on-current and low on-resistance.
  • the floating metal ring expands the depletion region of the power device, reducing the electric field strength of the MIS structure, thereby improving the withstand voltage of the device.
  • the gallium nitride semiconductor device obtained in this embodiment can be applied to technical fields such as power electronic components, filters, and radio communication components, and has a good application prospect.

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Abstract

一种氮化镓半导体器件，包括：氮化镓外延层（810）；设置于所述氮化镓外延层（810）上的氮化硅和等离子体增强正硅酸乙脂复合介质层（820）；设置于所述复合介质层（820）上的源极（831）、漏极（832）和栅极（833），所述源极（831）和所述漏极（832）分别贯穿所述复合介质层（820）与所述氮化镓外延层（810）连接，所述栅极（833）通过位于所述栅极（833）底部下方的栅极介质层（860）与所述氮化镓外延层（810）连接；设置于所述源极（831）、漏极（832）和栅极（833）以及所述复合介质层（820）上的绝缘层（840），以及设置于所述绝缘层（840）上的场板金属层（850）。

Description

氮化镓半导体器件及其制备方法 技术领域
本申请涉及半导体工艺领域，尤其涉及一种氮化镓半导体器件及其制备方法。
背景技术
氮化镓具有大禁带宽度、高电子饱和速率、高击穿电场、较高热导率、耐腐蚀以及抗辐射性能等优点，从而可以采用氮化镓制作半导体材料，而得到氮化镓半导体器件。现有技术中，氮化镓半导体器件的制备方法为：在氮化镓外延层的表面上形成氮化硅层，在氮化硅层上刻蚀出源极接触孔和漏极接触孔，源极接触孔和漏极接触孔内沉积金属，从而形成源极和漏极；再刻蚀氮化硅层以及氮化镓外延层中的氮化铝镓层，形成一个凹槽，在凹槽中沉积介质层和金属层，从而形成栅极；然后沉积二氧化硅层以及场板金属层，从而形成氮化镓半导体器件。然而现有技术中，人们关注如何提高导通电流和降低导通电阻的问题。
发明内容
为解决上述问题，本申请提供一种氮化镓半导体器件，包括：氮化镓外延层；以及，设置于所述氮化镓外延层上的复合介质层，所述复合介质层材质为氮化硅和等离子体增强正硅酸乙脂；设置于所述复合介质层上的源极、漏极和栅极，所述源极、漏极分别贯穿所述复合介质层与所述氮化镓外延层连接；其中，所述栅极包括相互连接的第一栅部和第二栅部，所述第一栅部、第二栅部均贯穿所述复合介质层且通过位于所述第一栅部底部和第二栅部底部下方的栅极介质层与所述氮化镓外延层连接；设置于所述源极、漏极和栅极以及所述复合介质层上的绝缘层，所述绝缘层的材质为二氧化硅；设置于所述绝缘层上的场板金属层，所述场板金属层贯穿所述绝缘层与所述源极连接；以及设置在所述复合介质层上的若干个浮空场板，所述浮空场板贯穿所述复合介质层与所述氮化镓外延层连接；其中，所述氮化镓外延层包括硅衬底，以及设置于所述硅衬底表面的氮化镓层和设置于所述氮化镓层表面的氮化铝镓层；所述第一栅部往下延伸入所述氮化铝镓层中；位于所述第一栅部底部的所述栅极介质层的底端到所述氮化铝镓层底部的距离为整个所述氮化铝镓层的一半。
本申请还提供一种氮化镓半导体器件，包括：氮化镓外延层；以及，设置于所述氮化镓外延层上的复合介质层；设置于所述复合介质层上的源极、漏极和栅极，所述源极、漏极分别贯穿所述复合介质层与所述氮化镓外延层连接；其中，所述栅极包括相互连接的第一栅部和第二栅部，所述第一栅部、第二栅部均贯穿所述复合介质层且通过位于所述第一栅部底部和第二栅部底部下方的栅极介质层与所述氮化镓外延层连接；设置于所述源极、漏极和栅极以及所述复合介质层上的绝缘层；设置于所述绝缘层上的场板金属层，所述场板金属层贯穿所述绝缘层与所述源极连接；以及设置在所述复合介质层上的若干个浮空场板，所述浮空场板贯穿所述复合介质层与所述氮化镓外延层连接。
本申请还提供这种氮化镓半导体器件的制备方法，包括：提供一氮化镓外延层，其中，所述氮化镓外延层包括由下而上依次设置的硅衬底层、氮化镓层和氮 化铝镓层；在所述氮化镓外延层表面沉积氮化硅和等离子体增强正硅酸乙脂，形成复合介质层；刻蚀所述复合介质层以形成漏极接触孔，并在所述漏极接触孔内、以及所述复合介质层的表面上沉积第一金属；刻蚀所述复合介质层以形成源极接触孔以及若干个浮空场板接触孔，并在所述源极接触孔内及所述若干个浮空场板接触孔内、所述复合介质层的表面上沉积所述第一金属；对所述第一金属进行光刻和刻蚀，形成多个欧姆接触电极窗口以获得漏极、源极和若干个浮空场板；进行高温退火处理，以通过相互接触的刻蚀后的所述第一金属与所述氮化铝镓层进行反应之后形成合金；通过所述多个欧姆接触电极窗口对所述复合介质层和所述氮化铝镓层进行刻蚀，形成第一栅极接触孔和第二栅极接触孔；在所述第一栅极接触孔和所述第二栅极接触孔的底部沉积一层栅极介质层；在所述第一栅极接触孔和所述第二栅极接触孔内、以及部分所述复合介质层上沉积第二金属以形成栅极；沉积一层绝缘层；对所述源极接触孔上方的所述绝缘层进行刻蚀以形成开孔；在所述开孔内、以及从所述源极接触孔上方延伸至所述栅极接触孔上方的所述绝缘层上沉积场板金属以形成场板金属层。
本申请通过在氮化镓外延层的表面的复合介质层应用了新颖材料，还通过沉积第一金属在进行高温退火处理，以通过相互接触的刻蚀后的第一金属与氮化铝镓层进行反应之后形成合金，以降低刻蚀后的第一金属与氮化铝镓层的接触电阻。通过引入混合栅结构，包括长的属于增强型的第一栅部和短的属于耗尽型的第二栅部，可以提供高的阻断能力、保证高的导通电流和低的导通电阻。通过结合浮空场板，扩展了功率器件的耗尽区，减小了金属-绝缘体-半导体(MIS)结构的电场强度，从而改善器件耐压。从而有效的保护了氮化镓半导体器件，增强了氮化镓半导体器件的可靠性。
附图说明
图1a为本申请又一实施例的氮化镓半导体器件的结构示意图。
图1b为本申请又一实施例的氮化镓半导体器件的栅极结构示意图。
图1c为本申请又一实施例的氮化镓半导体器件的制备流程示意图。
图2a为本申请又一实施例的氮化镓半导体器件的结构示意图。
图2b为本申请又一实施例的氮化镓半导体器件的制备流程示意图。
图3a为本申请另一实施例的氮化镓半导体器件的结构示意图。
图3b为本申请另一实施例的氮化镓半导体器件的栅极结构示意图。
图3c为本申请另一实施例的氮化镓半导体器件的制备流程示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参考图1a所示，在本申请实施例中提供一种氮化镓半导体器件，其从下 至上包括：氮化镓外延层310、复合介质层320、源极331和漏极332、栅极333、绝缘层340、场板金属层350、栅极介质层360。
其中，氮化镓外延层310由硅(Si)衬底312、氮化镓(GaN)层313和氮化铝镓(AlGaN)层314构成，其中，硅衬底312、氮化镓层313和氮化铝镓层314由下而上依次设置。
复合介质层320设置于所述氮化镓外延层310上；本实施例的所述复合介质层320材质可例如为氮化硅和等离子体增强正硅酸乙脂(PETEOS)。该氮化硅和等离子体增强正硅酸乙脂属于一种高介电常数(high‐k)介质。
源极331、漏极332和栅极333设置于所述复合介质层320上。具体地，源极331、漏极332和栅极333外形像“钉子”般一部分插入至所述复合介质层320中，源极331和漏极332分别贯穿复合介质层320与氮化镓外延层310连接；而一部分突出于所述复合介质层320顶部。栅极333贯穿复合介质层320并通过位于其底部下方的栅极介质层360与氮化镓外延层310连接；而一部分突出于复合介质层320顶部。所述源极331和/或漏极332由第一金属组成。其中第一金属例如包括从下至上依次设置的第一钛金属层、铝金属层、第二钛金属层和氮化钛层，其中，第一钛金属层的厚度可例如为200埃，铝金属层的厚度可例如为1200埃，第二钛金属层的厚度可例如为200埃，氮化钛层的厚度可例如为200埃。采用第一金属材质形成的源极331、漏极332，能够在器件高温退火过程中与所述氮化镓外延层310中的氮化镓铝层314发生反应，生成合金，从而使得源极331、漏极332与氮化铝镓层的接触面的接触良好，可以有效的降低源极331、漏极332与氮化铝镓层的接触电阻；避免出现氮化镓半导体器件的漏电以及软击穿的问题。
可选地，结合图1b所示，本实施例的栅极333包括并列相连的两个部分：较长的为增强型第一栅部333a、较短的为耗尽型第二栅部333b。所述第一栅部333a通过位于其底部下方的栅极介质层360与所述氮化铝镓层314表面连接，并伸入所述氮化铝镓层314中；所述第二栅部333b通过位于其底部下方的栅极介质层360与所述氮化铝镓层314表面连接。这种长短两个部分构成的栅极区别于现有的栅极，而呈现“异型”。
进一步地，所述第一栅部333a的宽度D1例如不小于第二栅部333b的宽度D2。当然，在其他实施例中，第一栅部333a和第二栅部333b的左右位置也可以互换。
所述栅极333a可以往下延伸入所述氮化铝镓层314中，位于所述栅极333a下的所述栅极介质层360的底端到所述氮化铝镓层314底部的距离H例如为整个所述氮化铝镓层314的一半。整个栅极333由第二金属组成，所述第二金属为Ni、Au合金。栅极介质层360的材质例如为氮化硅、氧化硅或氧化铪等high‐k(高介电)材料。
绝缘层340设置于漏极332、栅极333和一部分源极331上方，以及裸露出来的全部复合介质层320上，所述绝缘层340的材质为二氧化硅。其中，绝缘层340在整个器件的表面进行均匀沉积，各处沉淀的厚度相同。由于源极331、漏 极332、栅极333的存在，从而在源极331与栅极333之间的绝缘层340、在栅极33与漏极332之间的绝缘层340是向下凹陷的，可通过后续的磨平步骤使之平整。
还可例如包括有场板金属层350，其设置于所述绝缘层340上。所述场板金属层350贯穿所述绝缘层340与所述源极331连接。可选地，所述场板金属层350的材质为铝硅铜金属层。
本申请还提供上述氮化镓半导体器件的制备方法。如图1c所示，具体步骤包括：
步骤301：在硅衬底312上依次沉积氮化镓层313和氮化铝镓层314，形成氮化镓外延层310。氮化镓是第三代宽禁带半导体材料，具有大禁带宽度、高电子饱和速率、高击穿电场、较高热导率、耐腐蚀和抗辐射性能等特性、并且在高压、高频、高温、大功率和抗辐照环境条件下具有较强的优势，从而是研究短波光电子器件和高压高频率大功率器件的最佳材料；其中，大禁带宽度为3.4电子伏特，高电子饱和速率为2e7厘米每秒，高击穿电场为1e10～‐3e10伏特每厘米。
然后可以采用等离子体增强化学气相电积方法，在氮化镓外延层310的表面上沉积一层氮化硅和等离子体增强正硅酸乙脂(PETEOS)，形成复合介质层120。其中，氮化硅和等离子体增强正硅酸乙脂的厚度例如可为2000埃。
步骤302，对所述复合介质层320进行干法刻蚀，形成相对设置的源极接触孔321和漏极接触孔322。
为了使得所述源极接触孔321、漏极接触孔322清洁少杂质，还包括除杂步骤。具体的，在对复合介质层320进行干法刻蚀之后，可以先采用“DHF(稀的氢氟酸)+化学清洗剂SC‐1+化学清洗剂SC‐2”的方法，例如，可以先采用稀释后的氢氟酸溶液处理器件，然后采用过氧化氢与氢氧化氨的碱性混合溶液处理器件，再采用过氧化氢与氯化氢的酸性混合溶液处理器件，进而可以去除整个器件的表面上的杂质物。
步骤303，在本实施例中，在源极接触孔321和漏极接触孔322内、以及复合介质层120的表面上沉积第一金属。
具体地，可以采用磁控溅射镀膜工艺，在源极接触孔和漏极接触孔内、以及复合介质层的表面上，依次沉积第一钛金属层、铝金属层、第二钛金属层和氮化钛层，以形成第一金属；其中，第一钛金属层的厚度可例如为200埃，铝金属层的厚度可例如为1200埃，第二钛金属层的厚度可例如为200埃，氮化钛层的厚度可例如为200埃。
对第一金属进行光刻和刻蚀，形成欧姆接触电极窗口319。
对第一金属进行光刻和刻蚀，其中光刻的程序包括了涂胶、曝光和显影，从而可以形成一个欧姆接触电极窗口319；透过欧姆接触电极窗口319，可以看到复合介质层320的部分表面。如此，源极接触孔121上的第一金属构成了器件的源极331，漏极接触孔322上的第一金属构成了器件的漏极332。此时，为了能清楚表达本申请过程，命名此时获得的器件为第一组件。
步骤304，对整个第一组件进行高温退火处理，以通过相互接触的刻蚀后的第一金属与氮化铝镓层314进行反应之后形成合金。
在本实施例中，具体的，在反应炉中通入氮气气体，在840～850℃的环境下对整个第一组件进行30秒的高温退火处理，从而刻蚀后的第一金属会成为合金，并且相互接触的刻蚀后的第一金属与氮化铝镓层314进行反应之后也可以在其接触面上也形成合金，从而可以降低第一金属与氮化铝镓层314之间的接触电阻。即，降低源极331、漏极332与氮化铝镓层314之间的接触电阻。
步骤305，通过欧姆接触电极窗口319，对复合介质层320和氮化铝镓层314进行干法刻蚀，形成栅极接触孔323，其中，栅极接触孔323的底部与氮化铝镓层314的底部具有预设距离。
在本实施例中，采用干法刻蚀的方法，通过欧姆接触电极窗口319，对复合介质层320以及部分的氮化铝镓层314，进行干法刻蚀，进而在第一器件上形成一个栅极接触孔323。
其中，第一次刻蚀时，只在所述复合介质层320部分进行，获得较浅的第二接触孔323b；第二次干法刻蚀时在第一次刻蚀所获得的第二接触孔323b之中偏向一侧进行，并刻蚀贯穿整个复合介质层320后再深入至部分氮化铝镓层314中进行，形成更深的第一接触孔323a；如此获得整体的栅极接触孔323。通过控制刻蚀工艺参数调节栅极接触孔323b的宽度，来控制第一栅部的宽度D1、第二栅部的宽度D2的比例关系。
之后在所述栅极接触孔323a和栅极接触孔323b的底部沉积一层栅极介质层360。
步骤306，然后在所述栅极接触孔323a内、栅极接触孔323b内、以及部分复合介质层320上沉积Ni/Au，金属厚度为0.01～0.04μm/0.08～0.4μm；获得栅极333。由此可知，两个栅极接触孔之间实际上相互连通的，第一栅部333a、第二栅部333b的制备也是一体成型的。
可选地，第一接触孔323a完全的穿透了复合介质层320，并穿过部分的氮化铝镓层314，使得第一接触孔323a的底部与氮化铝镓层314的底部的距离H例如可以为氮化铝镓层314的一半。
在本实施例中，形成一个栅极接触孔323之后，栅极接触孔323内会存在杂质、颗粒以及离子等杂质物，从而可以采用盐酸溶液清洗栅极接触孔320，将栅极接触孔320内的杂质物去除掉。
具体地，本实施例通过在对复合介质层320进行干法刻蚀之后，采用DHF+SC1+SC2的方法去除器件上的杂质物；并形成栅极接触孔323之后，采用盐酸溶液将栅极接触孔323内的杂质物去除掉。从而可以有效的保证了复合介质层的表面以及栅极接触孔323内的清洁，进而保证了氮化镓半导体器件的性能。
此时，为了更清楚表达本申请内容，命名此时获得的器件为第二组件。
步骤307，在整个第二组件的表面沉积一层绝缘层340。
在本实施例中，具体的，在整个第二组件的表面沉积一层二氧化硅(SiO 2)， 厚度可例如为5000埃，形成二氧化硅层作为一层绝缘层340。其中，二氧化硅在整个器件的表面进行均匀沉积，各处厚度相同，由于源极331、漏极332和栅极333的存在，从而在源极331与栅极333之间的绝缘层340、在栅极333与漏极332之间的绝缘层340是向下凹陷的，可利用磨平工艺使之平整。
步骤308，对源极接触孔331上方的绝缘层340进行干法刻蚀之后，形成开孔341。所述源极331具有凸出于所述源极接触孔321外的凸出部，所述开孔341的宽度小于所述源极331的所述凸出部的宽度。
步骤309，在开孔341内、以及从源极接触孔321上方延伸至栅极接触孔323上方的绝缘层340上沉积场板金属350，形成场板金属层350。
在本实施例中，具体的，可以采用磁控溅射镀膜工艺，在开孔341内、以及从源极接触孔321的外边缘的第一金属直至栅极接触孔323的外边缘的第一金属上方的复合介质层320上沉积场板金属，厚度可例如为10000埃，从而形成场板金属层350。场板金属层350的厚度是均匀的，场板金属层350在开孔341的位置处、以及源极接触孔321与栅极接触孔323之间的位置处的是向下凹陷的，可通过后续步骤中的磨平工艺使之平整。
本实施例的氮化镓半导体器件采用混合栅结构，包括长的属于增强型的第一栅部333a和短的属于耗尽型的第二栅部333b。在关态条件下，第一栅部333a关断，而第二栅部333b可以在漏极电压下锁住沟道电势，提供高的阻断能力；开态时，增强型沟道和耗尽型沟道提供低的沟道电阻，保证高的导通电流和低的导通电阻。本实施例获得的氮化镓半导体器件可应用于电力电子元件、滤波器、无线电通信元件等技术领域中，具有良好的应用前景。
请参考图2a所示，本申请实施例提供一种氮化镓半导体器件，其从下至上包括：氮化镓外延层510、复合介质层520、源极531和漏极532、栅极533、绝缘层540、场板金属层550和栅极介质层560。
其中，氮化镓外延层510由硅(Si)衬底512、氮化镓(GaN)层513和氮化铝镓(AlGaN)层514构成，其中，硅衬底512、氮化镓层513和氮化铝镓层514由下而上依次设置。
复合介质层520设置于所述氮化镓外延层510上；本实施例的所述复合介质层520材质可例如为氮化硅和等离子体增强正硅酸乙脂(PETEOS)。该氮化硅和等离子体增强正硅酸乙脂属于一种高介电常数(high‐k)介质。
源极531、漏极532和栅极533设置于所述复合介质层520上。具体地，源极520、漏极532和栅极533外形像“钉子”般部分插入至所述复合介质层520中，所述源极531和漏极532分别贯穿所述复合介质层520与所述氮化镓外延层510连接；而一部分突出于所述复合介质层520顶部。所述栅极533贯穿所述复合介质层520并通过位于其底部下方的栅极介质层560与所述氮化镓外延层510连接；而一部分突出于所述复合介质层520顶部。所述源极531和/或漏极532由第一金属组成。第一金属的组分结构如上述实施例所示。采用第一金属材质形成的源极531、漏极532，能够在器件高温退火过程中与所述氮化镓外延层510 中的氮化镓铝层514发生反应，生成合金，从而使得源极531、漏极532与氮化铝镓层的接触面的接触良好，可以有效的降低源极531、漏极532与氮化铝镓层的接触电阻；避免出现氮化镓半导体器件的漏电以及软击穿的问题。
可选地，所述栅极533往下延伸入所述氮化铝镓层514中，所述栅极533底端到所述氮化铝镓层514底部的距离例如为整个所述氮化铝镓层514的一半与所述栅极介质层560的厚度之和。栅极533由第二金属组成，所述第二金属为Ni、Au合金。栅极介质层560的材质例如为氮化硅、氧化硅或氧化铪等high‐k(高介电)材料。
可选地，还包括设置在所述复合介质层520上的若干个浮空场板535，所述浮空场板535贯穿所述复合介质层520与所述氮化镓外延层510连接，且所述浮空场板535独立设置于所述源极、漏极之间并呈现环状。
每个浮空场板535的高度可例如为0.25～6微米。
绝缘层540设置于漏极532、栅极533和一部分源极531上方，以及裸露出来的全部复合介质层520上，所述绝缘层540的材质为二氧化硅。其中，绝缘层540在整个器件的表面进行均匀沉积，各处沉淀的厚度相同。由于源极531、漏极532、栅极533的存在，从而在源极531与栅极533之间的绝缘层540、在栅极533与漏极532之间的绝缘层540是向下凹陷的，可利用磨平工艺使之平整。
还可例如包括有场板金属层550，其设置于所述绝缘层540上。所述场板金属层550贯穿所述绝缘层540与所述源极531连接。可选地，所述场板金属层550的材质为铝硅铜金属层。
本申请还提供上述氮化镓半导体器件的制备方法。如图2b所示，具体步骤包括：
步骤501：在硅衬底512上依次沉积氮化镓层513和氮化铝镓层514，形成氮化镓外延层510。氮化镓是第三代宽禁带半导体材料，具有大禁带宽度、高电子饱和速率、高击穿电场、较高热导率、耐腐蚀和抗辐射性能等特性、并且在高压、高频、高温、大功率和抗辐照环境条件下具有较强的优势，从而是研究短波光电子器件和高压高频率大功率器件的最佳材料；其中，大禁带宽度为3.4电子伏特，高电子饱和速率为2e7厘米每秒，高击穿电场为1e10～‐3e10伏特每厘米。
然后可以采用等离子体增强化学气相电积方法，在氮化镓外延层510的表面上沉积一层氮化硅和等离子体增强正硅酸乙脂(PETEOS)，形成复合介质层520。其中，氮化硅和等离子体增强正硅酸乙脂的厚度例如可为2000埃。
步骤502，对所述复合介质层520进行干法刻蚀，形成漏极接触孔522，再在所述漏极接触孔522内沉积第一金属形成相应的电极。
首先，先在复合介质层520上开设漏极接触孔522；然后可以采用磁控溅射镀膜工艺，在漏极接触孔内以及复合介质层的表面上，依次沉积第一钛金属层、铝金属层、第二钛金属层和氮化钛层，以形成第一金属；其中，第一钛金属层的厚度可例如为200埃，铝金属层的厚度可例如为1200埃，第二钛金属层的厚度可例如为200埃，氮化钛层的厚度可例如为200埃。形成漏极。
步骤503，对所述复合介质层520进行干法刻蚀，形成源极接触孔521和多个浮空场板接触孔525，再在源极接触孔521以及多个浮空场板接触孔525和复合介质层520的表面上沉积第一金属。
类似地，可以采用磁控溅射镀膜工艺，在源极接触孔521以及多个浮空场板接触孔525、部分复合介质层520的表面上，依次沉积第一钛金属层、铝金属层、第二钛金属层和氮化钛层，以形成第一金属；其中，第一钛金属层的厚度可例如为200埃，铝金属层的厚度可例如为1200埃，第二钛金属层的厚度可例如为200埃，氮化钛层的厚度可例如为200埃。由此，获得源极531和浮空场板535。
其中，每个浮空场板535的长度可例如为0.25～6微米。
为了使得所述源极接触孔521、漏极接触孔522、多个浮空场板接触孔525清洁少杂质，还包括除杂步骤。具体的，在对复合介质层520进行干法刻蚀之后，可以先采用“DHF(稀的氢氟酸)+化学清洗剂SC‐1+化学清洗剂SC‐2”的方法，例如，可以先采用稀释后的氢氟酸溶液处理器件，然后采用过氧化氢与氢氧化氨的碱性混合溶液处理器件，再采用过氧化氢与氯化氢的酸性混合溶液处理器件，进而可以去除整个器件的表面上的杂质物。
对第一金属进行光刻和刻蚀，形成多个欧姆接触电极窗口519。
对第一金属进行光刻和刻蚀，其中光刻的程序包括了涂胶、曝光和显影，从而可以形成一个欧姆接触电极窗口519；透过欧姆接触电极窗口519，可以看到复合介质层520的部分表面。如此，源极接触孔521上的第一金属构成了器件的源极531，漏极接触孔522上的第一金属构成了器件的漏极532。此时，为了能清楚表达本申请过程，命名此时获得的器件为第一组件。
步骤504，对整个第一组件进行高温退火处理，以通过相互接触的刻蚀后的第一金属与氮化铝镓层514进行反应之后形成合金。
在本实施例中，具体的，在反应炉中通入氮气气体，在840～850℃的环境下对整个第一组件进行30秒的高温退火处理，从而刻蚀后的第一金属会成为合金，并且相互接触的刻蚀后的第一金属与氮化铝镓层514进行反应之后也可以在其接触面上也形成合金，从而可以降低第一金属与氮化铝镓层514之间的接触电阻。即，降低源极531、漏极532与氮化铝镓层514之间的接触电阻。
步骤505，通过欧姆接触电极窗口519，对复合介质层520和氮化铝镓层514进行干法刻蚀，形成栅极接触孔523，其中，栅极接触孔523的底部与氮化铝镓层514的底部具有预设距离。
在本实施例中，采用干法刻蚀的方法，通过欧姆接触电极窗口519，对复合介质层520以及部分的氮化铝镓层514，进行干法刻蚀，进而在第一器件上形成一个栅极接触孔523。其中，栅极接触孔523完全的穿透了复合介质层520，并穿过部分的氮化铝镓层514，使得栅极接触孔523的底部与氮化铝镓层514的底部的距离例如为氮化铝镓层514的一半。
在本实施例中，形成一个栅极接触孔523之后，栅极接触孔523内会存在杂质、颗粒以及离子等杂质物，从而可以采用盐酸溶液清洗栅极接触孔520，将栅 极接触孔520内的杂质物去除掉。
本实施例通过在对复合介质层520进行干法刻蚀之后，采用DHF+SC1+SC2的方法去除器件上的杂质物；并形成栅极接触孔523之后，采用盐酸溶液将栅极接触孔523内的杂质物去除掉。从而可以有效的保证了复合介质层的表面以及栅极接触孔523内的清洁，进而保证了氮化镓半导体器件的性能。
之后在所述栅极接触孔523的底部沉积一层栅极介质层560。
步骤506，在本实施例中，具体的，采用磁控溅射镀膜工艺，在栅极接触孔523内、以及部分复合介质层520上沉积Ni/Au作为第二金属，金属厚度为0.01～0.04μm/0.08～0.4μm；从而构成了栅极533。此时，为了更清楚表达本申请内容，命名此时获得的器件为第二组件。
步骤507，在整个第二组件的表面沉积一层绝缘层540。
在本实施例中，具体的，在整个第二组件的表面沉积一层二氧化硅(SiO 2)，厚度可例如为5000埃，形成二氧化硅层作为一层绝缘层540。其中，二氧化硅在整个器件的表面进行均匀沉积，各处厚度相同，由于源极531、漏极532和栅极533的存在，从而在源极531与栅极533之间的绝缘层540、在栅极533与漏极532之间的绝缘层540是向下凹陷的，可利用磨平工艺使之平整。
步骤508，对源极接触孔531上方的绝缘层540进行干法刻蚀之后，形成开孔541。所述源极531具有凸出于所述源极接触孔521外的凸出部，所述开孔541的宽度小于所述源极531的所述凸出部的宽度。
步骤509，在开孔541内、以及从源极接触孔521上方延伸至栅极接触孔523上方的绝缘层540上沉积场板金属550，形成场板金属层550。
在本实施例中，具体的，可以采用磁控溅射镀膜工艺，在开孔541内、以及从源极接触孔521的外边缘的第一金属直至栅极接触孔523的外边缘的第一金属上方的复合介质层520上沉积场板金属，厚度可例如为10000埃，从而形成场板金属层550。场板金属层550的厚度是均匀的，场板金属层550在开孔541的位置处、以及源极接触孔521与栅极接触孔523之间的位置处的是向下凹陷的。该状况可以在后续磨平工艺中处理平整。
本实施例结合浮空场板，通过这个浮空场板，扩展了功率器件的耗尽区，减小了MIS结构的电场强度，从而改善器件耐压。本实施例获得的氮化镓半导体器件可应用于电力电子元件、滤波器、无线电通信元件等技术领域中，具有良好的应用前景。
如图3a所示，本申请实施例提供一种氮化镓半导体器件，其从下至上包括：氮化镓外延层810、复合介质层820、源极831和漏极832、栅极833、绝缘层840和栅极介质层860。
其中，氮化镓外延层810由硅(Si)衬底812、氮化镓(GaN)层813和氮化铝镓(AlGaN)层814构成，其中，硅衬底812、氮化镓层813和氮化铝镓层814由下而上依次设置。
复合介质层820设置于所述氮化镓外延层810上；本实施例的所述复合介质 层820材质可例如为氮化硅和等离子体增强正硅酸乙脂(PETEOS)。该氮化硅和等离子体增强正硅酸乙脂属于一种高介电常数(high‐k)介质。
源极831、漏极832和栅极833设置于所述复合介质层820上。具体地，源极831、漏极832和栅极833外形像“钉子”般部分插入至所述复合介质层820中，所述源极831和漏极832分别贯穿所述复合介质层820与所述氮化镓外延层810连接；而一部分突出于所述复合介质层820顶部。栅极833贯穿所述复合介质层820并通过位于其底部下方的栅极介质层860与所述氮化镓外延层810连接；而一部分突出于所述复合介质层820顶部。所述源极831和/或漏极832由第一金属组成与上述实施例所示。采用第一金属材质形成的源极831、漏极832，能够在器件高温退火过程中与所述氮化镓外延层810中的氮化镓铝层814发生反应，生成合金，从而使得源极831、漏极832与氮化铝镓层的接触面的接触良好，可以有效的降低源极831、漏极832与氮化铝镓层的接触电阻；避免出现氮化镓半导体器件的漏电以及软击穿的问题。
可选地，结合图3b所示，本实施例的栅极833包括并列相连的两个部分：较长的为增强型第一栅部833a、较短的为耗尽型第二栅部833b。所述第一栅部833a通过位于其底部下方的栅极介质层860与所述氮化铝镓层814表面连接，所述第二栅部833b伸入所述氮化铝镓层814中、并通过位于第二栅部833b的底部下方的栅极介质层860与所述氮化铝镓层814表面连接。这种长短两个部分构成的栅极区别于现有的栅极，而呈现“异型”。
进一步地，所述第一栅部833a的宽度D1例如不小于第二栅部833b的宽度D2。当然，在其他实施例中，第一栅部833a和第二栅部833b的左右位置也可以互换。
所述栅极833a可以往下延伸入所述氮化铝镓层314中，位于所述栅极833a下的所述栅极介质层860的底端到所述氮化铝镓层814底部的距离H例如为整个所述氮化铝镓层814的一半。整个栅极833由第二金属组成，所述第二金属为Ni、Au合金。栅极介质层860的材质例如为氮化硅、氧化硅或氧化铪等high‐k(高介电)材料。
进一步地，还包括设置在所述复合介质层820上的若干个浮空场板835，所述浮空场板835贯穿所述复合介质层820与所述氮化镓外延层810连接，且所述浮空场板835独立设置于所述源极831、漏极832之间并呈现环状。
每个浮空场板835的高度可例如为0.25～6微米。
绝缘层840设置于漏极832、栅极833和一部分源极831上方，以及裸露出来的全部复合介质层820上，所述绝缘层840的材质为二氧化硅。其中，绝缘层840在整个器件的表面进行均匀沉积，各处沉淀的厚度相同。由于源极831、漏极832、栅极833的存在，从而在源极831与栅极833之间的绝缘层840、在栅极833与漏极832之间的绝缘层840是向下凹陷的，可利用磨平工艺使之平整。
还可例如包括有场板金属层850，其设置于所述绝缘层840上。所述场板金属层850贯穿所述绝缘层840与所述源极831连接。可选地，所述场板金属层 850的材质为铝硅铜金属层。
本实施例的氮化镓半导体器件采用混合栅结构，包括长的属于增强型的第一栅部和短的属于耗尽型的第二栅部。在关态条件下，第一栅部关断，而第二栅部可以在漏极电压下锁住沟道电势，提供高的阻断能力；开态时，增强型沟道和耗尽型沟道提供低的沟道电阻，保证高的导通电流和低的导通电阻。
本申请还提供上述氮化镓半导体器件的制备方法。如图3c所示，具体步骤包括：
步骤801：在硅衬底812上依次沉积氮化镓层813和氮化铝镓层814，形成氮化镓外延层810。氮化镓是第三代宽禁带半导体材料，具有大禁带宽度、高电子饱和速率、高击穿电场、较高热导率、耐腐蚀和抗辐射性能等特性、并且在高压、高频、高温、大功率和抗辐照环境条件下具有较强的优势，从而是研究短波光电子器件和高压高频率大功率器件的最佳材料；其中，大禁带宽度为3.4电子伏特，高电子饱和速率为2e7厘米每秒，高击穿电场为1e10～‐3e10伏特每厘米。
然后可以采用等离子体增强化学气相电积方法，在氮化镓外延层810的表面上沉积一层氮化硅和等离子体增强正硅酸乙脂(PETEOS)，形成复合介质层820。其中，氮化硅和等离子体增强正硅酸乙脂的厚度例如可为2000埃。
步骤802，对所述复合介质层820进行干法刻蚀，形成漏极接触孔822；再在所述漏极接触孔822内以及复合介质层820的表面上沉积第一金属形成相应的漏极电极。
首先，先在复合介质层820上开设漏极接触孔822；然后可以采用磁控溅射镀膜工艺，在漏极接触孔内以及复合介质层的表面上，依次沉积第一钛金属层、铝金属层、第二钛金属层和氮化钛层，以形成第一金属；其中，第一钛金属层的厚度可例如为200埃，铝金属层的厚度可例如为1200埃，第二钛金属层的厚度可例如为200埃，氮化钛层的厚度可例如为200埃。形成漏极。
步骤803，对所述复合介质层820进行干法刻蚀，形成源极接触孔821以及多个浮空场板接触孔；再在源极接触孔821以及多个浮空场板接触孔825、复合介质层820的表面上沉积第一金属以形成源极和多个浮空场板。
类似地，可以采用磁控溅射镀膜工艺，在源极接触孔821以及多个浮空场板接触孔825、部分复合介质层820的表面上，依次沉积第一钛金属层、铝金属层、第二钛金属层和氮化钛层，以形成第一金属；其中，第一钛金属层的厚度可例如为200埃，铝金属层的厚度可例如为1200埃，第二钛金属层的厚度可例如为200埃，氮化钛层的厚度可例如为200埃。由此，获得源极831和浮空场板835。
其中，每个浮空场板835的长度可例如为0.25～6微米。
为了使得所述源极接触孔821、漏极接触孔822、多个浮空场板接触孔825清洁少杂质，还包括除杂步骤。具体的，在对复合介质层820进行干法刻蚀之后，可以先采用“DHF(稀的氢氟酸)+化学清洗剂SC‐1+化学清洗剂SC‐2”的方法，例如，可以先采用稀释后的氢氟酸溶液处理器件，然后采用过氧化氢与氢氧化氨的碱性混合溶液处理器件，再采用过氧化氢与氯化氢的酸性混合溶液处理器件， 进而可以去除整个器件的表面上的杂质物。
对第一金属进行光刻和刻蚀，形成多个欧姆接触电极窗口819。
对第一金属进行光刻和刻蚀，其中光刻的程序包括了涂胶、曝光和显影，从而可以形成一个欧姆接触电极窗口819；透过欧姆接触电极窗口819，可以看到复合介质层820的部分表面。如此，源极接触孔821上的第一金属构成了器件的源极831，漏极接触孔822上的第一金属构成了器件的漏极832。此时，为了能清楚表达本申请过程，命名此时获得的器件为第一组件。
步骤804，对整个第一组件进行高温退火处理，以通过相互接触的刻蚀后的第一金属与氮化铝镓层814进行反应之后形成合金。
在本实施例中，具体的，在反应炉中通入氮气气体，在840～850℃的环境下对整个第一组件进行30秒的高温退火处理，从而刻蚀后的第一金属会成为合金，并且相互接触的刻蚀后的第一金属与氮化铝镓层814进行反应之后也可以在其接触面上也形成合金，从而可以降低第一金属与氮化铝镓层814之间的接触电阻。即，降低源极831、漏极832与氮化铝镓层14之间的接触电阻。
步骤805，通过欧姆接触电极窗口819，对复合介质层820和氮化铝镓层814进行干法刻蚀，形成栅极接触孔823，其中，栅极接触孔823的底部与氮化铝镓层814的底部具有预设距离。
在本实施例中，采用干法刻蚀的方法，通过欧姆接触电极窗口819，对复合介质层820以及部分的氮化铝镓层814，进行干法刻蚀，进而在第一器件上形成一个栅极接触孔823。其中，栅极接触孔823完全的穿透了复合介质层820，并穿过部分的氮化铝镓层814，使得栅极接触孔823的底部与氮化铝镓层814的底部的距离H例如为氮化铝镓层814的一半。进一步地，刻蚀时使得栅极接触孔823呈现一上宽下窄的、倒置的梯形。在本实施例中，形成一个栅极接触孔823之后，栅极接触孔823内会存在杂质、颗粒以及离子等杂质物，从而可以采用盐酸溶液清洗栅极接触孔820，将栅极接触孔820内的杂质物去除掉。
本实施例通过在对复合介质层820进行干法刻蚀之后，采用DHF+SC1+SC2的方法去除器件上的杂质物；并形成栅极接触孔823之后，采用盐酸溶液将栅极接触孔823内的杂质物去除掉。从而可以有效的保证了复合介质层的表面以及栅极接触孔823内的清洁，进而保证了氮化镓半导体器件的性能。
之后在所述栅极接触孔823的底部沉积一层栅极介质层860。
步骤806，在本实施例中，具体的，采用磁控溅射镀膜工艺，在栅极接触孔823内、以及部分复合介质层820上沉积Ni/Au作为第二金属，金属厚度为0.01～0.04μm/0.08～0.4μm；从而构成了栅极833。此时，为了更清楚表达本申请内容，命名此时获得的器件为第二组件。
步骤807，在整个第二组件的表面沉积一层绝缘层840。
在本实施例中，具体的，在整个第二组件的表面沉积一层二氧化硅(SiO 2)，厚度可例如为5000埃，形成二氧化硅层作为一层绝缘层840。其中，二氧化硅在整个器件的表面进行均匀沉积，各处厚度相同，由于源极831、漏极832和栅极 833的存在，从而在源极831与栅极833之间的绝缘层840、在栅极833与漏极832之间的绝缘层840是向下凹陷的，可利用磨平工艺使之平整。
步骤808，对源极接触孔831上方的绝缘层840进行干法刻蚀之后，形成开孔841。所述源极831具有凸出于所述源极接触孔821外的凸出部，所述开孔841的宽度小于所述源极831的所述凸出部的宽度。
步骤809，在开孔841内、以及从源极接触孔821上方延伸至栅极接触孔823上方的绝缘层840上沉积场板金属850，形成场板金属层850。
在本实施例中，具体的，可以采用磁控溅射镀膜工艺，在开孔841内、以及从源极接触孔821的外边缘的第一金属直至栅极接触孔823的外边缘的第一金属上方的复合介质层820上沉积场板金属，厚度可例如为10000埃，从而形成场板金属层850。场板金属层850的厚度是均匀的，场板金属层850在开孔841的位置处、以及源极接触孔821与栅极接触孔823之间的位置处的是向下凹陷的，通过在后续步骤的磨平工艺可使之平整。
本实施例的氮化镓半导体器件采用混合栅结构，包括长的属于增强型的第一栅部和短的属于耗尽型的第二栅部。在关态条件下，第一栅部关断，而第二栅部可以在漏极电压下锁住沟道电势，提供高的阻断能力；开态时，增强型沟道和耗尽型沟道提供低的沟道电阻，保证高的导通电流和低的导通电阻。结合浮空的金属环，通过这个浮空的金属环，扩展了功率器件的耗尽区，减小了MIS结构的电场强度，从而改善器件耐压。本实施例获得的氮化镓半导体器件可应用于电力电子元件、滤波器、无线电通信元件等技术领域中，具有良好的应用前景。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (20)

  1. 一种氮化镓半导体器件，包括：
    氮化镓外延层；以及，
    设置于所述氮化镓外延层上的复合介质层，所述复合介质层材质为氮化硅和等离子体增强正硅酸乙脂；
    设置于所述复合介质层上的源极、漏极和栅极，所述源极、漏极分别贯穿所述复合介质层与所述氮化镓外延层连接；其中，所述栅极包括相互连接的第一栅部和第二栅部，所述第一栅部、第二栅部均贯穿所述复合介质层且通过位于所述第一栅部底部和第二栅部底部下方的栅极介质层与所述氮化镓外延层连接；
    设置于所述源极、漏极和栅极以及所述复合介质层上的绝缘层，所述绝缘层的材质为二氧化硅；
    设置于所述绝缘层上的场板金属层，所述场板金属层贯穿所述绝缘层与所述源极连接；以及
    设置在所述复合介质层上的若干个浮空场板，所述浮空场板贯穿所述复合介质层与所述氮化镓外延层连接；
    其中，所述氮化镓外延层包括硅衬底，以及设置于所述硅衬底表面的氮化镓层和设置于所述氮化镓层表面的氮化铝镓层；
    所述第一栅部往下延伸入所述氮化铝镓层中；
    位于所述第一栅部底部的所述栅极介质层的底端到所述氮化铝镓层底部的距离为整个所述氮化铝镓层的一半。
  2. 一种氮化镓半导体器件，包括：
    氮化镓外延层；以及，
    设置于所述氮化镓外延层上的复合介质层；
    设置于所述复合介质层上的源极、漏极和栅极，所述源极、漏极分别贯穿所述复合介质层与所述氮化镓外延层连接；其中，所述栅极包括相互连接的第一栅部和第二栅部，所述第一栅部、第二栅部均贯穿所述复合介质层且通过位于所述第一栅部底部和第二栅部底部下方的栅极介质层与所述氮化镓外延层连接；
    设置于所述源极、漏极和栅极以及所述复合介质层上的绝缘层；
    设置于所述绝缘层上的场板金属层，所述场板金属层贯穿所述绝缘层与所述源极连接；以及
    设置在所述复合介质层上的若干个浮空场板，所述浮空场板贯穿所述复合介质层与所述氮化镓外延层连接。
  3. 根据权利要求2所述的氮化镓半导体器件，其中，所述氮化镓外延层包括硅衬底，以及设置于所述硅衬底表面的氮化镓层和设置于所述氮化镓层表面的氮化铝镓层。
  4. 根据权利要求2所述的氮化镓半导体器件，其中，所述第一栅部往下延伸入所述氮化铝镓层中。
  5. 根据权利要求4所述的氮化镓半导体器件，其中，位于所述第一栅部底部的所述栅极介质层的底端到所述氮化铝镓层底部的距离为整个所述氮化铝镓 层的一半。
  6. 根据权利要求2所述的氮化镓半导体器件，其中，所述源极和/或所述漏极由第一金属组成，所述第一金属从下至上依次包括第一钛金属层、铝金属层、第二钛金属层和氮化钛层。
  7. 根据权利要求2所述的氮化镓半导体器件，其中，所述栅极由第二金属组成，所述第二金属为镍铜合金。
  8. 根据权利要求2所述的氮化镓半导体器件，其中，所述栅极介质层的材质例如为氮化硅、氧化硅或氧化铪。
  9. 根据权利要求2所述的氮化镓半导体器件，其中，所述复合介质层的厚度为2000埃。
  10. 根据权利要求2所述的氮化镓半导体器件，其中，每个所述浮空场板呈现环状。
  11. 根据权利要求2所述的氮化镓半导体器件，其中，每个浮空场板的高度为0.25～6微米。
  12. 一种氮化镓半导体器件的制备方法，包括：
    提供一氮化镓外延层，其中，所述氮化镓外延层包括由下而上依次设置的硅衬底层、氮化镓层和氮化铝镓层；
    在所述氮化镓外延层表面沉积氮化硅和等离子体增强正硅酸乙脂，形成复合介质层；
    刻蚀所述复合介质层以形成漏极接触孔，并在所述漏极接触孔内、以及所述复合介质层的表面上沉积第一金属；
    刻蚀所述复合介质层以形成源极接触孔以及若干个浮空场板接触孔，并在所述源极接触孔内及所述若干个浮空场板接触孔内、所述复合介质层的表面上沉积所述第一金属；
    对所述第一金属进行光刻和刻蚀，形成多个欧姆接触电极窗口以获得漏极、源极和若干个浮空场板；
    进行高温退火处理，以通过相互接触的刻蚀后的所述第一金属与所述氮化铝镓层进行反应之后形成合金；
    通过所述多个欧姆接触电极窗口对所述复合介质层和所述氮化铝镓层进行刻蚀，形成第一栅极接触孔和第二栅极接触孔；
    在所述第一栅极接触孔和所述第二栅极接触孔的底部沉积一层栅极介质层；
    在所述第一栅极接触孔和所述第二栅极接触孔内、以及部分所述复合介质层上沉积第二金属以形成栅极；
    沉积一层绝缘层；
    对所述源极接触孔上方的所述绝缘层进行刻蚀以形成开孔；
    在所述开孔内、以及从所述源极接触孔上方延伸至所述栅极接触孔上方的所述绝缘层上沉积场板金属以形成场板金属层。
  13. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述源极、 漏极、所述若干个浮空场板分别贯穿所述复合介质层与所述氮化镓外延层连接。
  14. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述栅极贯穿所述复合介质层并通过位于所述栅极底部下方的所述栅极介质层与所述氮化镓外延层连接。
  15. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述源极具有凸出于所述源极接触孔外的凸出部，所述开孔的宽度小于所述源极的所述凸出部的宽度。
  16. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述高温退火处理步骤为：在保护氛围下，在840～850℃的温度下保持30～60秒。
  17. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述第一栅极接触孔和所述第二栅极接触孔分别贯穿所述复合介质层，且所述第一栅极接触孔伸入所述氮化铝镓层。
  18. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述第一栅极接触孔的底部与所述氮化铝镓层的底部之间的距离为所述氮化铝镓层的厚度的至少一半。
  19. 根据权利要求12所述氮化镓半导体器件的制备方法，其中，所述场板金属层的投影至少覆盖所述开孔、以及从所述源极接触孔至所述栅极接触孔之间的区域。
  20. 根据权利要求12所述氮化镓半导体器件的制备方法，还包括：清洗所述第一栅极接触孔和所述第二栅极接触孔。
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