WO2018227655A1 - 一种低寄生电感功率模块及双面散热低寄生电感功率模块 - Google Patents

一种低寄生电感功率模块及双面散热低寄生电感功率模块 Download PDF

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Publication number
WO2018227655A1
WO2018227655A1 PCT/CN2017/090248 CN2017090248W WO2018227655A1 WO 2018227655 A1 WO2018227655 A1 WO 2018227655A1 CN 2017090248 W CN2017090248 W CN 2017090248W WO 2018227655 A1 WO2018227655 A1 WO 2018227655A1
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Prior art keywords
half bridge
chip
insulating substrate
upper half
metal layer
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PCT/CN2017/090248
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English (en)
French (fr)
Inventor
牛利刚
王玉林
滕鹤松
徐文辉
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扬州国扬电子有限公司
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Application filed by 扬州国扬电子有限公司 filed Critical 扬州国扬电子有限公司
Priority to US16/621,700 priority Critical patent/US11139278B2/en
Priority to EP17913814.4A priority patent/EP3621106A4/en
Publication of WO2018227655A1 publication Critical patent/WO2018227655A1/zh

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Definitions

  • the invention relates to a power electronic power module, in particular to a low parasitic inductance power module and a double-sided heat dissipation low parasitic inductance power module.
  • Power electronics technology plays a very important role in today's fast-growing industrial field.
  • power electronic power modules have been widely used in electric vehicles, photovoltaic power generation, wind power generation, industrial frequency conversion and other industries. With the rise of China's industry, power electronic power modules have a broader market prospect.
  • the existing power electronic power module package is bulky and heavy, and does not meet the requirements of high power density and light weight in the fields of electric vehicles, aerospace and the like. Larger power electronic power modules often have large parasitic inductances, which cause large overshoot voltages and increased losses, and also limit applications in high switching frequency applications. SiC power electronic devices have high-frequency, high-temperature, and high-efficiency characteristics, but the parasitic inductance of existing power modules is large, which limits the performance of SiC. In addition, as the power density of the application end is continuously upgraded, the package structure of the existing power module has hindered the further improvement of the power density, and a more efficient heat dissipation structure must be developed to meet the increasing power density requirements.
  • the existing double-sided heat dissipation power module such as CN105161477A
  • the current commutation loop area is still large, and the parasitic inductance is also relatively large, and the single layer of the chip is set, so that the volume of the power module is relatively large, and
  • the power terminal and the control terminal are only connected to the first lining plate, the setting is not flexible enough, the lining area cannot be further reduced, and the loss is increased due to the long current path.
  • the present invention aims to provide a low parasitic inductance power module and a double-sided heat dissipation low parasitic inductance power module which are small in size, light in weight and small in parasitic inductance.
  • a low parasitic inductance power module comprising an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic casing, wherein the input power terminal comprises a positive power terminal, a negative power terminal, and a top metal insulation
  • the substrate and the bottom metal insulating substrate are stacked, and the top metal insulating substrate and the bottom metal insulating substrate are sintered with chips on opposite sides thereof, and the positive power terminal, the negative power terminal and the output power terminal are electrically connected to the chip;
  • the output power terminal includes a soldering portion and a connecting portion outside the plastic sealing housing, the soldering portion being located between the top metal insulating substrate and the bottom metal insulating substrate.
  • an upper half bridge switch chip and an upper half bridge diode chip are sintered on the bottom metal insulating substrate, and a lower half bridge switch chip and a lower half bridge diode chip are sintered on the top metal insulating substrate; the upper half bridge is opened The off chip and the lower half bridge diode chip are stacked, and the lower half bridge switch chip and the upper half bridge diode chip are stacked.
  • the positive power terminal is sintered on the bottom metal insulating substrate, and the negative power terminal is sintered on the top metal insulating substrate; the soldering portion is located between the sintered chip on the top metal insulating substrate and the sintered chip on the bottom metal insulating substrate.
  • the positive power terminal is sintered on the bottom metal insulating substrate
  • the negative power terminal is sintered on the top metal insulating substrate
  • the bottom metal insulating substrate or the top metal insulating substrate is provided with an output partial metal layer
  • the output power terminal passes through the output partial metal layer.
  • a chip connection block is connected, and the chip connection block is electrically connected to the chip on the bottom metal insulated substrate and the chip on the top metal insulating substrate.
  • the sintered chip on the top metal insulating substrate is a lower half bridge diode chip and an upper half bridge diode chip
  • the sintered chip on the bottom metal insulating substrate is a lower half bridge switch chip and an upper half bridge switch chip, wherein the lower half bridge The diode chip is stacked with the lower half bridge switch chip, and the upper half bridge diode chip and the upper half bridge switch chip are stacked.
  • both the positive power terminal and the negative power terminal are sintered on the top metal insulating substrate, and at least one input power terminal is connected to the bottom metal insulating substrate through a metal connecting column; or both the positive power terminal and the negative power terminal are sintered at the bottom metal On the insulating substrate, and connected to the top metal insulating substrate through a metal connecting column; or, the positive power terminal and the negative power terminal are sintered with the top metal insulating substrate and the bottom metal insulating substrate; the soldering portion is sintered on the top metal insulating substrate Between the chip and the sintered chip on the bottom metal-insulated substrate.
  • soldering portion is sintered on the side facing the bottom metal insulating substrate with the upper half bridge switch chip and the upper half bridge diode chip, and is sintered on the side facing the top metal insulating substrate with the lower half bridge switch chip and the lower half bridge diode chip.
  • the bottom metal insulated substrate is provided with a metal layer on the bottom surface of the metal insulated substrate, and the upper half bridge switch chip and the upper half bridge diode chip are sintered on the metal layer on the bottom surface of the bottom metal insulating substrate, when the upper half bridge switch chip is an IGBT
  • the positive power terminal is electrically connected to the collector of the upper half bridge switch chip and the negative pole of the upper half bridge diode chip.
  • the upper half bridge switch chip is a MOSFET, the positive power terminal and the upper half bridge switch chip are leaked.
  • the pole and the negative pole of the upper half bridge diode chip are electrically connected;
  • the top metal insulated substrate is provided with a top metal insulating substrate surface metal layer, a first upper half bridge driving partial metal layer and a second upper half bridge driving partial metal layer, and the top metal insulating substrate surface is sintered on the metal layer
  • the half bridge switch chip and the lower half bridge diode chip, the first upper half bridge drive partial metal layer and the second upper half bridge drive local metal layer respectively have an upper half bridge drive terminal, and the upper half bridge switch chip gate and the gate
  • the first upper half bridge drives the partial metal layer electrical connection, and the output power terminal is electrically connected to the second upper half bridge driving the local metal layer;
  • the top metal insulated substrate is further provided with a lower half bridge driving a partial metal layer, the lower half bridge driving the local metal layer is connected with the gate of the lower half bridge switch chip, and the lower half bridge driving the other end of the partial metal layer is connected A lower half bridge driving terminal, and a metal layer on the surface of the top metal insulating substrate is also connected with a lower half bridge driving terminal.
  • the chip connection block is sintered on the side facing the bottom metal insulating substrate with the upper half bridge switch chip and the upper half bridge diode chip, and sintered on the side facing the top metal insulating substrate with the lower half bridge switch chip and the lower half bridge diode chip.
  • the chip connection block is divided into a first chip connection block and a second chip connection block, and the first chip connection block and the second chip connection block are both sintered with the output partial metal layer;
  • the first chip connection block is facing the top metal insulating substrate One side is sintered with the lower half bridge diode chip, and the upper half bridge switch chip is sintered on the side facing the bottom metal insulating substrate;
  • the second chip connecting block is sintered on the side facing the top metal insulating substrate and the lower half bridge switch chip, facing the bottom One side of the metal insulating substrate is sintered with the upper half bridge diode chip.
  • the bottom metal insulating substrate is provided with an upper half bridge surface metal layer and an output partial metal layer, and the upper half bridge surface metal layer is sintered with an upper half bridge switch chip and an upper half bridge diode chip, when the upper half bridge switch When the chip is an IGBT, the positive power terminal is electrically connected to the collector of the upper half bridge switch chip and the negative pole of the upper half bridge diode chip, and when the upper half bridge switch chip is a MOSFET, the positive power terminal and the upper half bridge switch The drain of the chip and the cathode of the upper half bridge diode chip are electrically connected;
  • the top metal insulating substrate is provided with a lower half bridge surface metal layer, a lower half bridge driving partial metal layer, a first upper half bridge driving partial metal layer and a second upper half bridge driving partial metal layer, and a lower half bridge surface metal layer
  • the lower half bridge switch chip and the lower half bridge diode chip are sintered, the lower half bridge surface metal layer and the lower half bridge drive local metal layer are respectively connected with a lower half bridge drive terminal, and the first upper half bridge drives the partial metal layer and the first The upper half of the bridge drives the partial metal layer to be respectively connected with an upper half bridge driving terminal;
  • the metal layer on the lower half of the bridge is connected to the emitter of the IGBT chip; when the lower half-bridge switch chip is a MOSFET, the metal layer on the lower half of the bridge is connected to the source of the MOSFET chip, and the lower half bridge is driven.
  • the local metal layer is connected to the gate of the lower half bridge switch chip, the first upper half bridge drives the local metal layer to be connected to the gate of the upper half bridge switch chip, and the second upper half bridge drives the solder portion of the local metal layer and the output power terminal. Connected.
  • the top metal insulating substrate comprises a top metal insulating substrate positive metal layer electrically connected to the positive power terminal, a top metal insulating substrate negative metal layer electrically connected to the negative power terminal, and an output power terminal and an upper half bridge driving terminal. Connected upper half bridge switch chip emitter/source local metal layer, and upper half bridge switch chip gate local metal layer electrically connected to another upper half bridge drive terminal;
  • the surface of the positive metal layer of the top metal insulating substrate is sintered with an upper half bridge diode chip, and the surface of the negative metal layer of the top metal insulating substrate is sintered with a lower half bridge diode chip, the upper half bridge switch chip gate partial metal layer and the upper half bridge switch chip Gate electrical connection;
  • the bottom metal insulated substrate comprises a bottom metal insulated substrate positive metal layer electrically connected to the positive power terminal, a bottom metal insulated substrate negative metal layer electrically connected to the negative power terminal and a lower half bridge driving terminal, and the other lower half a partial local metal layer of a lower half bridge switch chip electrically connected to the bridge drive terminal;
  • the surface of the positive metal layer of the bottom metal insulating substrate is sintered with an upper half bridge switch chip, and the bottom metal insulating substrate has a lower half bridge switch chip sintered on the surface of the negative metal layer; the lower half bridge switch chip gate partial metal layer and the lower half bridge switch chip The door is electrically connected.
  • the output power terminal further includes an upper half bridge lead end, and the soldering portion is connected to an emitter or a source of the upper half bridge switch chip, to a collector or a drain of the lower half bridge switch chip, and to the upper half bridge
  • the positive electrode of the diode chip is connected to the negative electrode of the lower half bridge diode chip; the upper half bridge terminal is connected to the upper half bridge switch chip emitter/source partial metal layer of the top metal insulating substrate.
  • soldering portion of the output power terminal is a base at a position in contact with the chip, a three-layer structure at a position not in contact with the chip, a middle layer in the middle layer, and a filler body on the upper and lower sides.
  • a stress buffer layer is filled between the soldering portion of the output power terminal and the chip.
  • the plastic-clad outer casing is formed by the transfer mold integrated molding process, and the middle portion of the upper surface of the metal layer on the back side of the top metal-insulated substrate and the middle portion of the lower surface of the metal layer on the back side of the bottom metal-insulated substrate are exposed outside the plastic-clad casing, and are higher Plastic enclosure.
  • a double-sided heat dissipation low parasitic inductance power module includes the low parasitic inductance power module as described above, and the lower surface of the low parasitic inductance power module is provided with a heat dissipation device, and the upper surface is provided with a plurality of heat pipes, and the heat dissipation device
  • the heat pipe insertion port is provided, and the heat pipe includes an evaporation section, and the evaporation section is bent downward at the edge of the power module to form a connection section, and the connection section is inserted into the heat pipe insertion port of the heat dissipation device and fixed.
  • a driving terminal is further included, and the driving terminal is connected with a driving board, and a heat pipe is disposed between the driving board and the power module.
  • the evaporation section of the heat pipe is sintered on the top metal insulating substrate; the evaporation section is wrapped in the plastic enclosure; or the evaporation section is exposed outside the plastic enclosure, and the plastic enclosure is in the middle of the upper surface of the top metal insulation substrate The intermediate portion of the lower surface of the portion and the bottom metal insulating substrate is exposed.
  • a lower surface of the bottom metal insulated substrate is provided with a spoiler structure
  • an upper surface of the heat dissipating device is provided with a spoiler hole
  • the spoiler structure protrudes into the heat dissipating device through the spoiler hole and is sealed at the spoiler hole
  • a heat exchange passage that constitutes a heat dissipating medium inside the heat sink.
  • the top metal insulated substrate of the present invention is laminated with the bottom metal insulating substrate, and the chips are sintered on the opposite faces, and the soldering portions of the output power terminals are also disposed on the top metal insulating substrate and the bottom metal insulating substrate.
  • the stacking of the chip and the electrode can greatly reduce the parasitic inductance of the loop, reduce the volume of the power module, save the cost, reduce the weight, and is especially suitable for the packaging of the SiC power chip; meanwhile, the power end of the internal chip of the power module All use large-area sintered structure, greatly reduced The risk of module failure caused by the failure of the bonding wire when using the bonding wire is reduced, the overcurrent capability is fully improved, and the reliability of the module is improved.
  • the heat sink can be disposed on both sides of the power module, the thermal resistance of the power module can be reduced, or a heat sink can be disposed at the bottom, and the heat pipe is connected to the heat sink at the top for double-sided heat dissipation, which can ensure the heat dissipation efficiency of the power module.
  • the structure of the heat sink and the volume of the heat sink are further simplified.
  • Embodiment 1 is a view showing the overall appearance of Embodiment 1;
  • Figure 2 is a front view and a partial enlarged view of Embodiment 1;
  • Figure 3 is a schematic view of the interior of the embodiment 1;
  • Figure 4 is a front elevational view and a partial enlarged view of the first embodiment
  • FIG. 5 is a schematic view of a bottom metal insulated substrate assembly of Embodiment 1;
  • FIG. 6 is a schematic view of a top metal insulated substrate assembly of Embodiment 1;
  • Figure 7 is a schematic exploded view of Embodiment 1;
  • FIG. 8 is a schematic diagram of a conventional half-bridge power module topology and a commutation loop
  • FIG. 9 is a schematic diagram of a topology structure and a commutation loop of a half bridge power module of Embodiment 1;
  • FIG. 10 is a schematic diagram of a heat dissipation scheme of a three-phase bridge power module
  • Figure 11 is an exploded view of the installation of a three-phase bridge power module
  • FIG. 12 is a schematic overall structural view of a three-phase bridge power module
  • Figure 13 is a topological diagram of a three-phase bridge power module
  • Figure 14 is a schematic structural view of Embodiment 2.
  • Figure 15 is a schematic structural view of Embodiment 3.
  • Figure 16 is a schematic internal view of Embodiment 4.
  • FIG. 17 is a schematic view of a bottom metal insulated substrate assembly of Embodiment 4.
  • FIG. 18 is a schematic view of a top metal insulated substrate assembly of Embodiment 4.
  • Figure 19 is a schematic exploded view of Embodiment 4.
  • Figure 20 is a schematic exploded view of Embodiment 5.
  • FIG. 21 is a schematic structural view of a top metal insulated substrate of Embodiment 5.
  • FIG. 22 is a schematic structural view of a bottom metal insulated substrate of Embodiment 5;
  • Figure 24 is a schematic view showing the bottom metal insulated substrate assembly of Embodiment 6;
  • Figure 25 is a schematic view showing the top metal insulated substrate assembly of Embodiment 6;
  • Figure 26 is a schematic exploded view of Embodiment 6;
  • Figure 27 is a schematic structural view of Embodiment 7.
  • Figure 28 is a schematic view of a heat sink of Embodiment 7.
  • FIG. 29 is a schematic diagram of a heat dissipation mode of Embodiment 7.
  • Figure 33 is a schematic structural view of Embodiment 8.
  • Figure 34 is a rear view of the power module of Embodiment 9;
  • Figure 35 is a rear perspective view showing the spoiler structure of Embodiment 9;
  • Figure 36 is a schematic view showing the direction of the fluid of Embodiment 9;
  • FIG. 37 is a schematic view of a heat sink of Embodiment 9.
  • the invention stacks the switch chip and the freewheeling diode chip of the opposite bridge arm, so that the path of the commutation loop is the shortest, thereby greatly reducing the parasitic inductance of the loop; and the heat dissipation path is provided on both sides of the stacking chip to achieve the purpose of double-sided heat dissipation. , further reducing the thermal resistance of the power module.
  • a low parasitic inductance double-sided heat dissipation power module includes a positive power terminal 1 , a negative power terminal 2 , an output power terminal 3 , a bottom metal insulated substrate 5 connected to the positive power terminal 1 , and a negative power terminal.
  • the positive power terminal 1 in this embodiment is sintered on the bottom metal insulating substrate 5
  • the negative power terminal 2 is sintered on the top metal insulating substrate 4, and both power terminals can be sintered on the same substrate, and then connected to another substrate through a metal connecting block or other connection manner to realize the positive power terminal 1 and the bottom metal.
  • the chip on the insulating substrate 5 is electrically connected, and the negative power terminal 2 is electrically connected to the chip on the top metal insulating substrate 4; and the metal insulating substrate used in the top metal insulating substrate 4 and the bottom metal insulating substrate 5 in this embodiment are both
  • the DBC that is, the top metal insulating substrate 4 includes an insulating substrate and a metal layer on both sides of the substrate, and is mounted on one side of the bottom metal insulating substrate 5
  • the chip, the other side of the chip is not the metal back surface of the top metal insulating substrate 41.
  • the bottom metal insulating substrate 5 has the same structure, and the chip side is the bottom metal insulating substrate back metal layer 51; the person skilled in the art
  • the DBC structure may not be used, and the aluminum substrate may be coated on both sides of the insulating substrate, or the metal coated on one side of the copper side may be covered with a metal such as aluminum on both sides of the insulating medium;
  • the plastic sealing shell 15 is formed by the transfer molding process.
  • the molten thermosetting plastic is injected into the cavity by means of a plastic sealing press, and the sintered power module semi-finished product is placed in the cavity, and the melted thermosetting plastic is rapidly solidified after reaching the curing temperature, forming the design scheme of the present invention.
  • the outer casing 15 is molded.
  • the intermediate portion of the upper surface of the back metal layer 41 of the top metal insulating substrate and the intermediate portion of the lower surface of the back metal layer 51 of the bottom metal insulating substrate are exposed outside the molded case 15, and are higher than the molded case 15, as shown in FIG.
  • the structure can make the metal layer on the back side of the metal insulating substrate better contact with the heat dissipating device, and can achieve better heat dissipation effect.
  • the top metal insulating substrate 4 and the bottom metal insulating substrate 5 are stacked and arranged in parallel, and the metal insulating substrate connected to the negative power terminal 2 in this embodiment is a top metal insulating substrate. 4.
  • the metal-insulated substrate connected to the positive power terminal 1 is the bottom metal-insulated substrate 5. The position of the top metal-insulated substrate 4 and the bottom metal-insulated substrate 5 may be reversed, without affecting the effect of the design.
  • the top metal insulating substrate 4 and the bottom metal insulating substrate 5 are sintered with chips on opposite sides thereof;
  • the output power terminal 3 includes a soldering portion 31 and a connecting portion 32 located outside the molded casing 15, the connection in this embodiment
  • the portion 32 is provided with a mounting hole;
  • the soldering portion 31 is located between the chip sintered on the top metal insulating substrate 4 and the chip sintered on the bottom metal insulating substrate 5;
  • the soldering portion 31 in this embodiment is a planar structure, and the soldering portion 31 One end is bent and extended upward to form a connecting portion having a mounting hole.
  • the flat plate structure can be formed without bending according to actual needs.
  • the layout of the internal chip of the power module is as shown in FIG. 4, and the arrangement of the chip is a stacked structure.
  • the bottom metal insulating substrate 5 is sintered with the upper half bridge switch chip 6 and the upper half bridge on one side facing the top metal insulating substrate 4.
  • the diode chip 7, the top metal insulating substrate 4 is sintered with a lower half bridge switch chip 8 and a lower half bridge diode chip 9 on one side facing the bottom metal insulating substrate 5.
  • the bottom metal insulated substrate 5 is provided with an upper half bridge switch chip, the soldering portion 31 of the output power terminal 3 is sintered on the upper surface of the upper half bridge power chip, and the lower half bridge diode chip 9 is sintered on the output power terminal 3.
  • the upper half bridge switch chip and the lower half bridge diode chip 9 are stacked, the lower half bridge diode chip 9 is located above the upper half bridge switch chip, and the upper half surface of the lower half bridge diode is sintered with the top metal insulating substrate 4; similarly,
  • the bottom metal insulated substrate 5 is further provided with an upper half bridge diode chip 7, and the soldering portion 31 of the output power terminal 3 is sintered on the side facing the bottom metal insulating substrate 5 with the upper half bridge switch chip 6 and the upper half bridge diode chip 7, One side facing the top metal insulating substrate 4 is sintered with the lower half bridge switch chip 8 and the lower half bridge diode chip 9.
  • the soldering portion 31 of the output power terminal 3 is sintered on the upper surface of the upper half bridge diode chip 7, and the lower half bridge switch chip, the lower half bridge switch chip 8 and the upper half bridge diode chip are also sintered on the output power terminal 3.
  • the lower half-bridge switch chip 8 is located above the upper half-bridge diode chip 7, and the upper surface of the lower-half bridge switch chip 8 is also sintered with the top metal-insulated substrate 4.
  • the structures of the upper half-bridge metal-insulated substrate assembly and the lower-half bridge metal-insulated substrate assembly are respectively described, as shown in FIG. 5 and FIG.
  • the positive power terminal 1 is sintered on the surface of the metal layer of the bottom metal insulating substrate 5
  • the bottom metal insulating substrate 5 is provided with the bottom metal insulating substrate surface metal layer 52
  • the bottom metal insulating substrate surface metal layer 52 is sintered with the upper half bridge.
  • the positive power terminal 1 is electrically connected to the collector of the upper half bridge switch chip 6 and the negative pole of the upper half bridge diode chip 7, when the upper half
  • the bridge switch chip 6 is a MOSFET
  • the positive power terminal 1 is electrically connected to the drain of the upper half bridge switch chip 6 and the negative electrode of the upper half bridge diode chip 7.
  • the negative power terminal 2 is sintered on the surface of the metal layer of the top metal insulating substrate 4, and the top metal insulating substrate 4 is provided with a top metal insulating substrate surface metal layer 42, a first upper half bridge driving partial metal layer 421, and a second upper surface.
  • the half bridge drives the partial metal layer 422.
  • the top metal insulating substrate surface metal layer 42 is sintered with a lower half bridge switch chip 8 and a lower half bridge diode chip 9.
  • the first upper half bridge drives the partial metal layer 421 and the second upper half.
  • the bridge driving partial metal layer 422 is respectively connected with an upper half bridge driving terminal 10, and the gate of the upper half bridge switching chip 6 is electrically connected to the first upper half bridge driving partial metal layer 421 through a metal connecting block, and the output power terminal 3 is output.
  • the metal connection block provided thereon is electrically connected to the second upper half bridge driving partial metal layer 422.
  • the top metal insulated substrate 4 is further provided with a lower half bridge driving partial metal layer 423, the lower half bridge driving partial metal layer 423 is connected to the gate of the lower half bridge switch chip 8, and the lower half bridge drives the partial metal layer 423.
  • the other end is connected to a lower half bridge drive terminal 11, and the top metal insulated substrate surface metal layer 42 is also connected to a lower half bridge drive terminal 11.
  • Figure 7 shows the relationship between the various layers inside the power module.
  • the sintering described in this embodiment is specifically sintered by the solder layer 16, because the upper and lower surfaces of the switch chip are plated or sputtered or evaporated with titanium-nickel-silver metal.
  • the structure may be such that the solder layer 16 may be a solder layer 16 formed by sintering a solder such as tin-lead or a solder layer 16 formed by sintering a silver paste.
  • a metal connection block is used between the gate of the upper half bridge switch chip 6 and the first upper half bridge drive partial metal layer 421, the output power terminal 3 and the second upper half bridge drive local metal layer 422.
  • the metal block may be selected from a metal material such as molybdenum, tungsten copper or the like which is matched with the thermal expansion coefficient of the chip. If the connection mode of the metal connection block is not used, the bonding wire may also be used for connection.
  • FIG. 8 and FIG. 9 respectively show a conventional half-bridge topology and a half-bridge topology of the present invention.
  • a collector or a drain of a switch chip is connected to a metal layer on a surface of a metal-insulated substrate through a solder layer 16, and the switch chip is The emitter or the source is connected to the surface metal layer through the bonding wire, that is, the upper half bridge switch chip 6 and the lower half bridge diode chip 9 are connected by a bonding wire and a metal layer, and the thick line in the figure indicates the freewheeling circuit path.
  • the invention stacks the upper half bridge switch chip and the lower half bridge diode chip 9 , and saves the middle metal insulating substrate metal layer and the bonding wire, and the connection path is the shortest, so the commutation loop is also the shortest, so that the The amplitude reduces the parasitic inductance.
  • FIG. 10 and FIG. 11 are schematic diagrams showing the connection between the power module and the heat sink.
  • the top metal insulating substrate back metal layer 41 and the bottom metal insulating substrate back metal layer 51 are respectively provided with a first heat sink 12 and a second heat sink 13 respectively.
  • the back surface metal layer 41 of the insulating substrate is in contact with the first heat dissipating device 12 through a thermal grease or other heat conductive material, and the bottom metal insulating substrate back metal layer 51 is also in contact with the second heat dissipating device 13 through a thermal grease or other heat conducting material;
  • An insulating spacer 121 is mounted on both sides of the device 13, and the insulating spacer 121 is in contact with the positive/negative power terminals of the power module to facilitate mounting of the busbar.
  • the present invention can also be applied to a three-phase bridge structure, and three half-bridge power module structures described in the present invention are arranged in a word line and packaged inside the same plastic package to realize low parasitic power.
  • the three-phase bridge power module of the sense that is, one power module includes three positive power terminals 1, three negative power terminals 2 and three output power terminals 3, the topology of which is three half bridges, as shown in FIG.
  • Embodiment 2 As shown in FIG. 14, the structure of the embodiment is substantially the same as that of the embodiment 1, except that the soldering portion 31 of the output power terminal 3 in this embodiment is the base 311 at a position in contact with the chip. The position is not in contact with the chip, the middle layer is the base 311, the upper and lower sides are the filling body 312; the base 311 is metal molybdenum or tungsten copper having a small thermal expansion coefficient, and the filling body 312 is electrically conductive. Metallic silver.
  • the power chip is sintered on the molybdenum substrate 311 of the output electrode, and the portion where the output electrode is not in contact with the chip is grooved, and the groove is filled with silver.
  • the thermal expansion coefficient of metal molybdenum is generally one-third of that of copper, which is close to the chip.
  • the thermal stress of the solder layer 16 is small and the reliability is high, but the conductivity of molybdenum is only three points of copper. One, therefore, filling the silver structure in the portion of the output electrode can reduce the resistance of the output electrode.
  • Embodiment 3 As shown in FIG. 15, this embodiment is basically the same as the structure of Embodiment 1, except that the soldering portion 31 of the output power terminal 3 and the chip are filled with a stress buffer layer 14, the output power.
  • the welded portion 31 of the terminal 3 is metallic copper
  • the stress buffer layer 14 is metallic molybdenum or tungsten copper.
  • the output electrode is a pure copper material. Since the thermal expansion of the copper and the chip is greatly different, in order to improve the long-term reliability of the solder layer 16, the present embodiment adds a stress buffer layer 14 transition between the chip and the output electrode, that is, on the surface of the chip. Sintered metal molybdenum or tungsten copper, and then sintered molybdenum or tungsten copper on the output electrode.
  • Embodiment 4 As shown in FIG. 16-19, the structure of the embodiment is substantially the same as that of the embodiment 1. The difference is that, in FIG. 17, the bottom metal insulated substrate 5 is provided with a metal layer 52 on the bottom surface of the metal insulated substrate. a first partial metal layer 53 and a second partial metal layer 54, wherein the first partial metal layer 53 and the second partial metal layer 54 are respectively connected with an upper half bridge driving terminal 10, an output power terminal 3 and a second partial metal layer 54 electrical connection, thereby achieving control of the upper half bridge switch chip.
  • the positive power terminal 1 is electrically connected to the collector of the upper half bridge switch chip 6 and the negative pole of the upper half bridge diode chip 7, and the gate of the upper half bridge switch chip 6 passes through
  • the root bonding wire is electrically connected to the first partial metal layer 53.
  • the positive power terminal 1 is electrically connected to the drain of the upper half bridge switch chip 6 and the negative pole of the upper half bridge diode chip 7, and the gate of the upper half bridge switch chip 6
  • the first partial metal layer 53 is electrically connected by a bonding wire.
  • a top metal insulating substrate surface metal layer 42 and a third partial metal layer 43 are disposed on the top metal insulating substrate 4, and a lower half bridge driving terminal 11 is connected to the other end of the third partial metal layer 43.
  • Metal insulating substrate surface metal layer 42 is also connected to a lower half bridge driving terminal 11;
  • the negative power terminal 2 is electrically connected to the emitter of the lower half bridge switch chip 8 and the anode of the lower half bridge diode chip 9, and the gate of the lower half bridge switch chip 8
  • the third partial metal layer 43 is connected;
  • the negative power terminal 2 is electrically connected to the source of the lower half bridge switch chip 8 and the anode of the lower half bridge diode chip 9, and the gate of the lower half bridge switch chip 8
  • the third partial metal layer 43 is connected.
  • the present invention can be used as a basis for forming a semiconductor chip, and a silicon substrate can also be used, and a germanium substrate or a III-V semiconductor material such as GaN or SiC can also be used; in addition, for packaging, molding or packaging, plastic can be used. Materials or ceramic materials, etc.
  • This embodiment is basically the same as the structure of Embodiment 1, except that
  • the positive power terminal 1 and the negative power terminal 2 are both sintered on the top metal insulating substrate 4, and at least one input power terminal is connected to the bottom metal insulating substrate 5 through a metal connecting post;
  • both the positive power terminal 1 and the negative power terminal 2 are sintered on the bottom metal insulating substrate 5 and connected to the top metal insulating substrate 4 through a metal connecting post;
  • the positive power terminal 1 and the negative power terminal 2 are sintered with both the top metal insulating substrate 4 and the bottom metal insulating substrate 5.
  • the molded case 15 is provided with heat sinks on both sides of the top metal insulating substrate back metal layer 41 and the bottom metal insulating substrate back metal layer 51.
  • the chip sintered on the top metal insulating substrate 4 is a lower half bridge diode chip 9 and an upper half bridge diode chip 7, and the chip sintered on the bottom metal insulating substrate 5 is a lower half bridge switch chip 8 and an upper half bridge.
  • the switch chip 6 is in which the lower half bridge diode chip 9 and the lower half bridge switch chip 8 are stacked, and the upper half bridge diode chip 7 and the upper half bridge switch chip 6 are stacked.
  • the top metal insulating substrate 4 includes a top metal insulating substrate positive metal layer 451 electrically connected to the positive power terminal 1 by sintering, and a top metal insulating electrically connected to the negative power terminal 2 by sintering. a substrate negative electrode metal layer 452, an upper half bridge switch chip 6 electrically connected to the output power terminal 3 and an upper half bridge drive terminal, an upper half switch chip emitter/source partial metal layer 453, and another upper half bridge drive The upper half bridge switch chip 6 electrically connected to the terminal half bridge switch chip 6 gate partial metal layer 454;
  • the surface of the top metal insulating substrate positive electrode metal layer 451 is sintered with the upper half bridge diode chip 7, and opposite to the negative electrode of the upper half bridge diode chip 7, the surface of the top metal insulating substrate negative electrode metal layer 452 is sintered with the lower half bridge diode chip 9, And opposite to the positive pole of the lower half bridge diode chip 9, the gate partial metal layer 454 of the upper half bridge switch chip 6 is electrically connected to the gate of the upper half bridge switch chip 6.
  • the bottom metal insulating substrate 5 includes a bottom metal insulating substrate positive metal layer 551 electrically connected to the positive power terminal 1 by sintering or ultrasonic metal welding, a negative power terminal 2, and a lower half bridge driving terminal.
  • the bottom metal insulated substrate negative metal layer 552 electrically connected, and the lower half bridge switch chip gate partial metal layer 553 electrically connected to the other lower half bridge driving terminal; the positive power terminal 1 and the negative power terminal 2 may be sintered or
  • the ultrasonic metal welding is respectively connected to the bottom metal insulating substrate positive metal layer 551 and the bottom metal insulating substrate negative metal layer 552;
  • the surface of the bottom metal insulating substrate positive electrode metal layer 551 is sintered with the upper half bridge switch chip 6 and is opposite to the collector or the drain of the upper half bridge switch chip 6, and the bottom metal insulated substrate negative electrode metal layer 552 is sintered with the lower half bridge.
  • the switch chip 8 is opposite to the emitter of the lower half bridge switch chip 8; the lower half bridge switch chip gate partial metal layer 553 is electrically connected to the gate of the lower half bridge switch chip 8 by sintering.
  • the output power terminal 3 includes a connection portion 32 provided with a connection hole, a solder portion 31 for connection to the chip, and an upper half bridge output terminal 33, and the solder portion 31 and the upper half bridge switch chip 6
  • the emitter or source is sintered.
  • the upper half bridge switch chip 6 is an IGBT, it is an emitter.
  • the upper half bridge switch chip 6 is a MOSFET, it is a source, and the collector or drain of the lower half bridge switch chip 8 is sintered.
  • the lower half bridge switch chip 8 When the lower half bridge switch chip 8 is an IGBT, it is a collector, and when the lower half bridge switch chip 8 is a MOSFET, it is a drain, is sintered with the positive electrode of the upper half bridge diode chip 7, and is sintered with the negative electrode of the lower half bridge diode chip 9;
  • a metal stress buffer layer is disposed between the soldering portion 31 and the chip, and is connected by the metal stress buffer layer.
  • This embodiment is basically the same as the structure of Embodiment 1, except that
  • the bottom metal insulated substrate 5 is provided with an upper half bridge surface metal layer 561 and an output partial metal layer 562.
  • the upper half bridge surface metal layer 561 is sintered with an upper half bridge switch chip 6 and an upper half bridge diode chip. 7;
  • the top metal insulating substrate 4 is provided with a lower half bridge surface metal layer 461, a lower half bridge driving partial metal layer 462, a first upper half bridge driving partial metal layer 463, and a second upper half bridge driving local metal.
  • Layer 464, the lower half bridge surface metal layer 461 is sintered with a lower half bridge switch chip 8 and a lower half bridge diode chip 9, and the lower half bridge surface metal layer 461 and the lower half bridge drive partial metal layer 462 are respectively connected with a lower half bridge.
  • a driving terminal, a first upper half bridge driving partial metal layer 463 and a second upper half bridge driving partial metal layer 464 respectively connected to an upper half bridge driving terminal;
  • the lower half bridge surface metal layer 461 is connected to the emitter of the IGBT chip; when the lower half bridge switch chip 8 is a MOSFET, the lower half bridge surface metal layer 461 is connected to the source of the MOSFET chip.
  • the lower half bridge driving partial metal layer 462 is connected to the gate of the lower half bridge switch chip 8.
  • the first upper half bridge drives the local metal layer 463 to be connected to the gate of the upper half bridge switch chip 6, and the second upper half bridge drives the local metal.
  • the layer 464 is connected to the welded portion 31 of the output power terminal 3.
  • the output power terminal 3 includes a soldering portion 31 and a connecting portion 32 provided with a mounting hole, and the soldering portion 31 is located between the bottom metal insulating substrate 5 and the top metal insulating substrate 4.
  • An output partial metal layer 562 is disposed on the bottom metal insulating substrate 5 or the top metal insulating substrate 4, and the output power terminal 3 is connected to the chip connecting block through the output partial metal layer 562, the chip connecting block and the chip on the bottom metal insulating substrate 5.
  • the chips on the top metal insulating substrate 4 are electrically connected.
  • the welded portion 31 in this embodiment is a planar structure, and one end of the welded portion 31 is bent and extended upward to form a connecting portion 32 having a mounting hole. In specific applications, the bent portion may be bent without forming a whole piece according to actual needs. Flat structure.
  • the soldering portion 31 is provided with an upper half bridge driving connection end, the upper half bridge driving connecting end is connected with the second upper half bridge driving partial metal layer 464 of the top metal insulating substrate 4, and the second upper half bridge drives the other end of the partial metal layer 464. Connect an upper half bridge drive terminal.
  • the upper half bridge drive connection end in this embodiment may be a single metal connection block, or may be integrated with the output power terminal 3, the upper half bridge switch chip 6 gate and the first upper half bridge of the top metal insulated substrate 4
  • the driving partial metal layer 463 is electrically connected by a metal connecting block, and the metal connecting block is made of a conductive material; the chip connecting block may be selected from a metal material such as molybdenum, tungsten copper or the like which is matched with the thermal expansion coefficient of the chip, and the thermal expansion coefficient of the chip connecting block is preferably a range.
  • the metal material between 2 and 8 ppm/° C. can reduce the thermal stress of the sintered layer between the chip and the chip connecting block, avoid premature cracking failure of the sintered layer, and improve reliability.
  • the first upper half bridge driving partial metal layer 463 may also be disposed on the bottom metal insulating substrate 5, and the gate of the upper half bridge switch chip 6 and the first upper half bridge driving partial metal layer 463 may use bonding wires. Make a connection.
  • the chip connection block may be an integral part or may be split according to the number of chips.
  • the chip connection block is divided into a first chip connection block 361 and a second chip connection block 362, and the first chip connection block 361 and the second chip.
  • the connection block 362 is sintered with the output partial metal layer 562; the first chip connection block 361 is sintered on the side facing the top metal-insulated substrate 4 and the lower half-bridge diode chip 9, on the side facing the bottom metal-insulated substrate 5 and the upper half-bridge switch
  • the chip 6 is sintered; the second chip connection block 362 is sintered on the side facing the top metal insulating substrate 4 and the lower half bridge switch chip 8, and is sintered on the side facing the bottom metal insulating substrate 5 and the upper half bridge diode chip 7.
  • the structure of the embodiment is substantially the same as that of the embodiment 1-6, except that, as shown in FIG. 27, the heat dissipation device 18 is disposed on the lower surface of the power module of the embodiment 1-6 and is disposed on the upper surface of the power module.
  • the heat sink 18 is provided with a heat pipe insertion port 181.
  • the heat pipe 19 includes an evaporation section 191.
  • the beginning of the evaporation section 191 is connected to the power module.
  • the plurality of evaporation sections 191 are on the upper surface of the power module.
  • the staggered arrangement, the evaporation section 191 is bent downward at the edge of the power module to form a connecting section 192, and the connecting section 192 is inserted into the heat pipe insertion opening 181 of the heat sink 18 and fixed.
  • the connecting section 192 is provided.
  • the extending portion of the condensation section is inserted into the heat pipe insertion opening 181 of the heat sink 18 and fixed; the plurality of evaporation sections 191 can also be parallel but not staggered, that is, the starting end is not connected to the power module, and the main body is sintered.
  • both ends of the heat pipe 19 are bent downward at the edge of the power module to form a connecting section 192, and the connecting section 192 is inserted into the heat pipe insertion opening 181 of the heat sink 18 and fixed.
  • the heat sink 18 and the cold end of the heat pipe 19 may be connected by soldering, or connected by other media, or connected by an interference fit.
  • the cold end of the heat pipe 19 can be directly in contact with the liquid heat dissipating medium, and the sealing of the connecting hole of the heat sink and the heat pipe 19 is required.
  • the heat sink 18 can be water-cooled, air-cooled, or other heat-dissipating methods commonly used in the art.
  • the heat sink 18 in this embodiment is an air-cooling heat sink, and the cold end of the heat pipe 19 is inserted into the air-cooled heat sink.
  • the assembly process of the power module and the heat pipe 19 in this embodiment is performed by soldering one end of the heat pipe 19 to the outer surface of the top metal insulating substrate 4 inside the power module;
  • the injection molding package is performed, and the heat pipe 19 outside the injection molding module is bent in the direction of the bottom metal insulating substrate 5.
  • the evaporation section 191 of the heat pipe 19 is wrapped in the plastic casing 15 at this time, for convenience and power.
  • the heat dissipating device at the bottom of the module contacts the heat dissipating, and the plastic encapsulating casing 15 exposes the intermediate portion of the lower surface of the bottom metal insulating substrate 5, and the upper surface of the top metal insulating substrate 4 which is in contact with the heat dissipating device, together with the heat pipe evaporation portion 191, is encapsulated in the plastic seal.
  • the heat of the power chip is conducted to the evaporation section 191 of the heat pipe 19 through the top metal insulating substrate 4.
  • the filling medium inside the heat pipe 19 changes from the liquid phase to the vapor phase, and the vapor phase heat dissipation medium reaches the cold end of the heat pipe 19 and then changes again. It is a liquid phase and reaches the evaporation section 191 under the action of capillary siphoning, and continuously circulates, thereby achieving the purpose of conducting heat from the top of the module to the cold end.
  • the evaporation section 191 is soldered to the top metal of the power module by soldering.
  • the arrangement of the heat pipes 19 is divided into staggered bidirectional arrangements.
  • the drive board 17 of the power module also generate a large amount of heat during operation. If the heat is not dissipated in time, there is also a risk of component burnout.
  • the driving plate 17 since the heat pipe 19 having high heat conduction is disposed on the top metal insulating substrate 4, the driving plate 17 can be in contact with the heat pipe 19 through the heat dissipating medium, and the heat of the driving plate 17 can also be conducted to the heat sink through the heat pipe 19, further Improve the reliability of the system.
  • This embodiment is basically the same as the structure of Embodiment 7, except that:
  • the upper surface of the top metal insulating substrate 4 is sintered with staggered heat pipes 19, and the cold outer end is bent in the direction of the bottom metal insulating substrate 5, and is inserted into the heat sink 18.
  • the driving board 17 is connected to the driving terminal, and is fixed on the other surface of the heat pipe 19 by a high thermal conductive bonding material to achieve the purpose of dissipating heat of the driving chip.
  • the plastic case 15 will be in the middle of the upper surface of the top metal insulating substrate 4.
  • the intermediate portion of the lower surface of the portion and the bottom metal insulating substrate 5 is exposed, and the intermediate portion of the upper surface of the top metal insulating substrate 4 and the intermediate portion of the lower surface of the bottom metal insulating substrate 5 are both higher than the plastic sealing case 15 for facilitating contact with the heat sink 18.
  • the evaporation section 191 of the heat pipe 19 is sintered on the top metal insulating substrate 4, and the evaporation section 191 is exposed outside the plastic casing 15.
  • a spoiler 53 is sintered in the middle portion of the lower surface of the bottom metal insulating substrate 5, and the fluid directly contacts the spoiler 53 to achieve a better heat dissipation effect.
  • the spoiler structure 53 in this embodiment is a cylindrical pin-fin of a fork row, and is sintered on the lower surface of the bottom metal insulating substrate 5 by solder, and the pin-fin of the fluid flow direction is arranged in a crosswise manner, thereby increasing the disturbance of the fluid. Sexuality enhances the heat transfer between the fluid and the pin-fin.
  • the upper surface of the heat sink 18 is provided with a spoiler hole 182.
  • the spoiler structure 53 extends into the heat sink 18 through the spoiler hole 182 and is sealed at the port of the spoiler hole 182.
  • the heat exchange channel that constitutes the heat dissipation medium inside.
  • the spoiler structure 53 is not limited to a cylindrical pin-fin, and the cross section may be in the form of a rhombic, a square, or a rib-like structure.
  • the pin-fin material is generally copper and is plated with other metals on the surface.
  • the solder paste is printed on the lower surface of the bottom metal insulating substrate 5, and the pin-fin is sintered under the bottom metal insulating substrate 5 by using a fixture.
  • the heat generated inside the power module is conducted to the pin-fin through the bottom metal insulating substrate 5, and the pin-fin is directly in contact with the fluid, and the thermal grease of the metal layer flat structure on the lower surface of the bottom metal insulating substrate 5 is removed, thereby increasing the power.
  • the heat dissipation area of the module reduces the thermal resistance of the power module.

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Abstract

一种低寄生电感功率模块，包括输入功率端子、输出功率端子（3）、顶部金属绝缘基板（4）、底部金属绝缘基板（5）和塑封外壳（15），输入功率端子包括正极功率端子（1）、负极功率端子（2），顶部金属绝缘基板（4）与底部金属绝缘基板（5）叠层设置，顶部金属绝缘基板（4）与底部金属绝缘基板（5）在二者相对的面上均烧结有芯片，正极功率端子（1）、负极功率端子（2）以及输出功率端子（3）均与芯片电连接；输出功率端子（3）包括焊接部（31）和位于塑封外壳（15）外部的连接部（32），焊接部（31）位于顶部金属绝缘基板（4）与底部金属绝缘基板（5）之间。该功率模块大大降低了回路寄生电感，减小了功率模块的体积，节约了成本，减轻了重量，尤其适合SiC功率芯片的封装，充分提高了过流能力，提高了模块的可靠性。

Description

一种低寄生电感功率模块及双面散热低寄生电感功率模块 技术领域
本发明涉及电力电子功率模块，尤其是一种低寄生电感功率模块及双面散热低寄生电感功率模块。
背景技术
电力电子技术在当今快速发展的工业领域占有非常重要的地位，电力电子功率模块作为电力电子技术的代表，已广泛应用于电动汽车，光伏发电，风力发电，工业变频等行业。随着我国工业的崛起，电力电子功率模块有着更加广阔的市场前景。
现有电力电子功率模块封装体积大，重量重，不符合电动汽车、航空航天等领域的高功率密度、轻量化的要求。体积较大的电力电子功率模块，其寄生电感往往也比较大，这会造成过冲电压较大、损耗增加，而且也限制了在高开关频率场合的应用。SiC电力电子器件具有高频、高温、高效的特性，但现有功率模块的寄生电感较大，限制了SiC性能的发挥。另外，随着应用端功率密度的不断升级，现有功率模块的封装结构已经阻碍了功率密度的进一步提升，必须开发出更加有效的散热结构才能满足功率密度日益增长的需求
现有的双面散热功率模块如CN105161477A，由于芯片单层设置，电流的换流回路面积仍然较大，往往寄生电感也比较大，而且芯片单层设置，使得功率模块的体积相对较大，另外功率端子与控制端子只与第一衬板连接，设置不够灵活、衬板面积无法进一步减小，还会由于电流路径较长造成损耗增加。
发明内容
发明目的：针对上述现有技术存在的缺陷，本发明旨在提供一种体积小、重量轻、寄生电感小的一种低寄生电感功率模块及双面散热低寄生电感功率模块。
技术方案：一种低寄生电感功率模块，包括输入功率端子、输出功率端子、顶部金属绝缘基板、底部金属绝缘基板和塑封外壳，所述输入功率端子包括正极功率端子、负极功率端子，顶部金属绝缘基板与底部金属绝缘基板叠层设置，顶部金属绝缘基板与底部金属绝缘基板在二者相对的面上均烧结有芯片，正极功率端子、负极功率端子以及与输出功率端子均与芯片电连接；所述输出功率端子包括焊接部和位于塑封外壳外部的连接部，所述焊接部位于顶部金属绝缘基板与底部金属绝缘基板之间。
进一步的，底部金属绝缘基板上烧结有上半桥开关芯片和上半桥二极管芯片，顶部金属绝缘基板上烧结有下半桥开关芯片和下半桥二极管芯片；所述上半桥开 关芯片与下半桥二极管芯片叠层设置，下半桥开关芯片与上半桥二极管芯片叠层设置。
进一步的，正极功率端子烧结在底部金属绝缘基板上，负极功率端子烧结在顶部金属绝缘基板上；焊接部位于顶部金属绝缘基板上烧结的芯片和底部金属绝缘基板上烧结的芯片之间。
进一步的，正极功率端子烧结在底部金属绝缘基板上，负极功率端子烧结在顶部金属绝缘基板上，底部金属绝缘基板或顶部金属绝缘基板上设有输出局部金属层，输出功率端子通过输出局部金属层连接有芯片连接块，芯片连接块与底部金属绝缘基板上的芯片和顶部金属绝缘基板上的芯片电连接。
进一步的，顶部金属绝缘基板上烧结的芯片为下半桥二极管芯片和上半桥二极管芯片，底部金属绝缘基板上烧结的芯片为下半桥开关芯片和上半桥开关芯片，其中，下半桥二极管芯片与下半桥开关芯片叠层设置，上半桥二极管芯片与上半桥开关芯片叠层设置。
进一步的，正极功率端子和负极功率端子均烧结在顶部金属绝缘基板上，并且至少一个输入功率端子与底部金属绝缘基板通过金属连接柱相连；或者，正极功率端子和负极功率端子均烧结在底部金属绝缘基板上，并与顶部金属绝缘基板通过金属连接柱相连；或者，正极功率端子和负极功率端子与顶部金属绝缘基板和底部金属绝缘基板均烧结；所述焊接部位于顶部金属绝缘基板上烧结的芯片和底部金属绝缘基板上烧结的芯片之间。
进一步的，焊接部在面向底部金属绝缘基板的一面与上半桥开关芯片和上半桥二极管芯片烧结，在面向顶部金属绝缘基板的一面与下半桥开关芯片和下半桥二极管芯片烧结。
进一步的，底部金属绝缘基板上设有底部金属绝缘基板表面金属层，底部金属绝缘基板表面金属层上烧结有上半桥开关芯片和上半桥二极管芯片，当所述上半桥开关芯片为IGBT时，正极功率端子与上半桥开关芯片的集电极以及上半桥二极管芯片的负极电连接，当所述上半桥开关芯片为MOSFET时，所述正极功率端子与上半桥开关芯片的漏极以及上半桥二极管芯片的负极电连接；
所述顶部金属绝缘基板上设有顶部金属绝缘基板表面金属层、第一上半桥驱动局部金属层和第二上半桥驱动局部金属层，所述顶部金属绝缘基板表面金属层上烧结有下半桥开关芯片和下半桥二极管芯片，第一上半桥驱动局部金属层和第二上半桥驱动局部金属层分别连有一个上半桥驱动端子，上半桥开关芯片的门极与所述第一上半桥驱动局部金属层电连接，输出功率端子与第二上半桥驱动局部金属层电连接；
所述顶部金属绝缘基板上还设有下半桥驱动局部金属层，下半桥驱动局部金属层与所述下半桥开关芯片的门极相连，下半桥驱动局部金属层的另一端连接有一个下半桥驱动端子，所述顶部金属绝缘基板表面金属层也连接有一个下半桥驱动端子。
进一步的，芯片连接块在面向底部金属绝缘基板的一面与上半桥开关芯片和上半桥二极管芯片烧结，在面向顶部金属绝缘基板的一面与下半桥开关芯片和下半桥二极管芯片烧结。
进一步的，芯片连接块分为第一芯片连接块和第二芯片连接块，第一芯片连接块与第二芯片连接块均与输出局部金属层烧结；第一芯片连接块在面向顶部金属绝缘基板的一面与下半桥二极管芯片烧结，在面向底部金属绝缘基板的一面与上半桥开关芯片烧结；第二芯片连接块在面向顶部金属绝缘基板的一面与下半桥开关芯片烧结，在面向底部金属绝缘基板的一面与上半桥二极管芯片烧结。
进一步的，底部金属绝缘基板上设有上半桥表面金属层和输出局部金属层，上半桥表面金属层上烧结有上半桥开关芯片和上半桥二极管芯片，当所述上半桥开关芯片为IGBT时，正极功率端子与上半桥开关芯片的集电极以及上半桥二极管芯片的负极电连接，当所述上半桥开关芯片为MOSFET时，所述正极功率端子与上半桥开关芯片的漏极以及上半桥二极管芯片的负极电连接；
所述顶部金属绝缘基板上设有下半桥表面金属层、下半桥驱动局部金属层、第一上半桥驱动局部金属层和第二上半桥驱动局部金属层，下半桥表面金属层上烧结有下半桥开关芯片和下半桥二极管芯片，下半桥表面金属层和下半桥驱动局部金属层分别连有一个下半桥驱动端子，第一上半桥驱动局部金属层和第二上半桥驱动局部金属层分别连有一个上半桥驱动端子；
当下半桥开关芯片为IGBT时，下半桥表面金属层与IGBT芯片的发射极相连；当下半桥开关芯片为MOSFET时，下半桥表面金属层与MOSFET芯片的源极相连，下半桥驱动局部金属层与下半桥开关芯片的门极相连，第一上半桥驱动局部金属层与上半桥开关芯片的门极相连，第二上半桥驱动局部金属层与输出功率端子的焊接部相连。
进一步的，顶部金属绝缘基板包括与正极功率端子电连接的顶部金属绝缘基板正极金属层、与负极功率端子电连接的顶部金属绝缘基板负极金属层、与输出功率端子和一个上半桥驱动端子电连接的上半桥开关芯片发射极/源极局部金属层，以及与另一个上半桥驱动端子电连接的上半桥开关芯片门极局部金属层；
顶部金属绝缘基板正极金属层的表面烧结有上半桥二极管芯片，顶部金属绝缘基板负极金属层的表面烧结有下半桥二极管芯片，上半桥开关芯片门极局部金属层与上半桥开关芯片的门极电连接；
所述底部金属绝缘基板包括与正极功率端子电连接的底部金属绝缘基板正极金属层、与负极功率端子及一个下半桥驱动端子电连接的底部金属绝缘基板负极金属层，以及与另一个下半桥驱动端子电连接的下半桥开关芯片门极局部金属层；
底部金属绝缘基板正极金属层的表面烧结有上半桥开关芯片，底部金属绝缘基板负极金属层表面烧结有下半桥开关芯片；下半桥开关芯片门极局部金属层与下半桥开关芯片的门极电连接。
进一步的，输出功率端子还包括上半桥引出端，所述焊接部与上半桥开关芯片的发射极或源极连接、与下半桥开关芯片的集电极或漏极连接、与上半桥二极管芯片的正极连接、与下半桥二极管芯片的负极连接；上半桥引出端与顶部金属绝缘基板的上半桥开关芯片发射极/源极局部金属层连接。
进一步的，输出功率端子的焊接部在与芯片接触的位置为基体，在不与芯片接触的位置为三层结构，中间一层为基体，上下两侧为填充体。
进一步的，输出功率端子的焊接部与芯片之间填充有应力缓冲层。
进一步的，塑封外壳为传递模一体化成型工艺制作，顶部金属绝缘基板背面金属层上表面的中间部分以及底部金属绝缘基板背面金属层下表面的中间部分均露出在塑封外壳的外部，并且高出塑封外壳。
一种双面散热低寄生电感功率模块，包括如前所述的低寄生电感功率模块，且所述低寄生电感功率模块的下表面设有散热装置，上表面设有多个热管，散热装置上设有热管插入口，热管包括蒸发段，蒸发段在功率模块的边缘处向下折弯形成连接段，连接段插入散热装置的热管插入口并固定。
进一步的，还包括驱动端子，驱动端子连接有驱动板，所述驱动板和功率模块之间设有热管。
进一步的，热管的蒸发段烧结在顶部金属绝缘基板上；所述蒸发段被包裹在塑封外壳内；或者，所述蒸发段露在塑封外壳外部，且塑封外壳将顶部金属绝缘基板上表面的中间部分和底部金属绝缘基板下表面的中间部分裸露在外。
进一步的，底部金属绝缘基板下表面设有扰流结构，所述散热装置的上表面设有扰流孔，所述扰流结构通过扰流孔伸入散热装置内部并在扰流孔口处密封，在散热装置内部构成散热介质的换热通道。
有益效果：本发明的顶部金属绝缘基板与底部金属绝缘基板叠层设置，且在二者相对的面上均烧结有芯片，输出功率端子的焊接部也设置在顶部金属绝缘基板与底部金属绝缘基板之间，如此芯片及电极的堆叠设置可以大大降低回路寄生电感，减小了功率模块的体积，节约了成本，减轻了重量，尤其适合SiC功率芯片的封装；同时，功率模块内部芯片的功率端全部采用大面积烧结结构，大大降 低了使用键合线时因键合线失效造成的模块故障风险，充分提高了过流能力，提高了模块的可靠性。并且，功率模块的两侧均可设置热沉，可以减小功率模块的热阻，或在底部设置散热装置，顶部采用热管连接至散热装置进行双面散热，能够在保证功率模块散热效率的同时进一步简化散热装置结构、压缩散热装置体积。
附图说明
图1是实施例1整体外观结构图；
图2是实施例1主视图及局部放大图；
图3是实施例1内部示意图；
图4是实施例1内部主视图及局部放大图；
图5是实施例1底部金属绝缘基板组件示意图；
图6是实施例1顶部金属绝缘基板组件示意图；
图7是实施例1爆炸示意图；
图8是传统半桥功率模块拓扑结构及换流回路示意图；
图9是实施例1半桥功率模块拓扑结构及换流回路示意图；
图10是三相桥功率模块散热方案示意图；
图11是三相桥功率模块安装爆炸图；
图12是三相桥功率模块整体结构示意图；
图13是三相桥功率模块拓扑图；
图14是实施例2的结构示意图；
图15是实施例3的结构示意图；
图16是实施例4的内部示意图；
图17是实施例4的底部金属绝缘基板组件示意图；
图18是实施例4的顶部金属绝缘基板组件示意图；
图19是实施例4的爆炸示意图；
图20是实施例5的爆炸示意图；
图21是实施例5的顶部金属绝缘基板结构示意图；
图22是实施例5的底部金属绝缘基板结构示意图；
图23是实施例5的输出功率端子结构示意图；
图24是实施例6的底部金属绝缘基板组件示意图；
图25是实施例6的顶部金属绝缘基板组件示意图；
图26是实施例6的爆炸示意图；
图27是实施例7的结构示意图；
图28是实施例7的散热装置示意图；
图29是实施例7的一种散热方式示意图；
图30、31、32是实施例7的装配过程示意图；
图33是实施例8的结构示意图；
图34是实施例9的功率模块背面示意图；
图35是实施例9的设置有扰流结构的背面示意图；
图36是实施例9的流体方向示意图；
图37是实施例9的散热装置示意图。
具体实施方式
下面通过实施例并结合附图对本技术方案进行详细说明。
实施例1：
本发明通过将开关芯片与相对桥臂的续流二极管芯片堆叠设置，使得换流回路路径最短，从而大大减少回路寄生电感；通过在堆叠设置芯片的两侧设置散热通路，达到双面散热的目的，进一步降低功率模块的热阻。
如图1所示，一种低寄生电感双面散热功率模块，包括正极功率端子1、负极功率端子2、输出功率端子3、与正极功率端子1相连的底部金属绝缘基板5、与负极功率端子2相连的顶部金属绝缘基板4、上半桥驱动端子10、下半桥驱动端子11以及用于包封的塑封外壳15，本实施例中的正极功率端子1烧结在底部金属绝缘基板5上，负极功率端子2烧结在顶部金属绝缘基板4上，也可以将两个功率端子均烧结在同一基板上，再通过金属连接块或其他连接方式连接到另一基板，实现正极功率端子1与底部金属绝缘基板5上的芯片电连接，负极功率端子2与顶部金属绝缘基板4上的芯片电连接；并且，本实施例中顶部金属绝缘基板4与底部金属绝缘基板5所采用的金属绝缘基板均为DBC，即顶部金属绝缘基板4包括绝缘基板和基板两侧的金属层，面向底部金属绝缘基板5的一面上安装了芯片，未安装芯片的另一面则为顶部金属绝缘基板背面金属层41，同理，底部金属绝缘基板5也有相同的结构，未安装芯片一面为底部金属绝缘基板背面金属层51；本领域技术人员在实施时也可不采用DBC结构，也可以采用绝缘基板两侧覆铝，或者一侧覆铜一侧覆铝等金属覆盖在绝缘介质两侧的结构；塑封外壳15为传递模一体化成型工艺制作，即借助塑封压机将融化的热固性塑料注入到模腔内，模腔内放置有经过烧结的功率模块半成品，融化的热固性塑料达到固化温度后会快速固化成型，形成本发明设计方案所示的塑封外壳15。顶部金属绝缘基板背面金属层41上表面的中间部分以及底部金属绝缘基板背面金属层51下表面的中间部分均露出在塑封外壳15的外部，并且高出塑封外壳15，如图2所示，这种结构可以使金属绝缘基板背面金属层更好地与散热装置接触，可以实现更好的散热效果。
如图3所示，功率模块内部，顶部金属绝缘基板4与底部金属绝缘基板5叠层设置，为平行正对结构，本实施例中与负极功率端子2相连的金属绝缘基板为顶部金属绝缘基板4，与正极功率端子1相连的金属绝缘基板为底部金属绝缘基板5，也可以将顶部金属绝缘基板4组件与底部金属绝缘基板5组件位置对换，不影响本设计方案的效果。顶部金属绝缘基板4与底部金属绝缘基板5在二者相对的面上均烧结有芯片；所述输出功率端子3包括焊接部31和位于塑封外壳15外部的连接部32，本实施例中的连接部32设有安装孔；所述焊接部31位于顶部金属绝缘基板4上烧结的芯片与底部金属绝缘基板5上烧结的芯片之间；本实施例中的焊接部31是平面结构，焊接部31的一端弯折并向上延伸形成具有安装孔的连接部，具体应用时也可根据实际需要不进行弯折而是做成一整块平板结构。
功率模块内部芯片的布局如图4所示，芯片的布置为堆叠结构，本实施例中底部金属绝缘基板5在面向顶部金属绝缘基板4的一面上烧结有上半桥开关芯片6和上半桥二极管芯片7，顶部金属绝缘基板4在面向底部金属绝缘基板5的一面上烧结有下半桥开关芯片8和下半桥二极管芯片9。具体的：底部金属绝缘基板5上设置有上半桥开关芯片，输出功率端子3的焊接部31烧结在上半桥功率芯片的上表面，在输出功率端子3上烧结有下半桥二极管芯片9，上半桥开关芯片与下半桥二极管芯片9叠层设置，下半桥二极管芯片9位于上半桥开关芯片的上方，下半桥二极管的上表面烧结有顶部金属绝缘基板4；同理，底部金属绝缘基板5上还设置有上半桥二极管芯片7，输出功率端子3的焊接部31在面向底部金属绝缘基板5的一面与上半桥开关芯片6和上半桥二极管芯片7烧结，在面向顶部金属绝缘基板4的一面与下半桥开关芯片8和下半桥二极管芯片9烧结。具体的，输出功率端子3的焊接部31烧结在上半桥二极管芯片7的上表面，在输出功率端子3上还烧结有下半桥开关芯片，下半桥开关芯片8与上半桥二极管芯片7叠层设置，下半桥开关芯片8位于上半桥二极管芯片7的上方，下半桥开关芯片8的上表面也烧结有顶部金属绝缘基板4。
为了进一步说明芯片的位置及连接结构，对上半桥金属绝缘基板组件、下半桥金属绝缘基板组件的结构分别给予说明，如图5、图6所示。图5中，正极功率端子1烧结在底部金属绝缘基板5金属层表面，底部金属绝缘基板5上设有底部金属绝缘基板表面金属层52，底部金属绝缘基板表面金属层52上烧结有上半桥开关芯片6和上半桥二极管芯片7，当上半桥开关芯片为IGBT时，正极功率端子1与上半桥开关芯片6的集电极以及上半桥二极管芯片7的负极电连接，当上半桥开关芯片6为MOSFET时，所述正极功率端子1与上半桥开关芯片6的漏极以及上半桥二极管芯片7的负极电连接。
图6中，负极功率端子2烧结在顶部金属绝缘基板4金属层表面，顶部金属绝缘基板4上设有顶部金属绝缘基板表面金属层42、第一上半桥驱动局部金属层421和第二上半桥驱动局部金属层422，所述顶部金属绝缘基板表面金属层42上烧结有下半桥开关芯片8和下半桥二极管芯片9，第一上半桥驱动局部金属层421和第二上半桥驱动局部金属层422分别连有一个上半桥驱动端子10，上半桥开关芯片6的门极通过金属连接块与所述第一上半桥驱动局部金属层421电连接，输出功率端子3上设有的金属连接块与第二上半桥驱动局部金属层422电连接。
所述顶部金属绝缘基板4上还设有下半桥驱动局部金属层423，下半桥驱动局部金属层423与所述下半桥开关芯片8的门极相连，下半桥驱动局部金属层423的另一端连接有一个下半桥驱动端子11，所述顶部金属绝缘基板表面金属层42也连接有一个下半桥驱动端子11。
图7给出了功率模块内部各层的关系，本实施例中所述的烧结具体为通过焊接层16烧结，由于开关芯片的上、下表面通过电镀或者溅射或者蒸发有钛镍银的金属结构，因此焊接层16可以是锡铅等钎焊料通过烧结形成的焊接层16，也可以是银浆通过烧结形成的焊接层16。此外，图中上半桥开关芯片6的门极与第一上半桥驱动局部金属层421之间、输出功率端子3与第二上半桥驱动局部金属层422之间均采用了金属连接块实现电气连接，该金属块可以选用钼、钨铜等与芯片的热膨胀系数比较匹配的金属材料，若不采用金属连接块的连接方式，也可以使用键合线进行连接。
图8、图9分别为传统半桥拓扑结构及本发明半桥拓扑结构，传统的功率模块内部，开关芯片的集电极或漏极通过焊接层16与金属绝缘基板表面金属层连接，开关芯片的发射极或源极通过键合线与表面金属层相连，即上半桥开关芯片6与下半桥二极管芯片9之间通过键合线、金属层连接，图中的粗线表示续流回路路径；本发明将上半桥开关芯片与下半桥二极管芯片9叠层设置，省掉了中间的金属绝缘基板金属层与键合线，其连接路径最短，因此其换流回路也最短，从而大幅度降低了寄生电感。
图10、图11为功率模块与散热装置的连接示意图，顶部金属绝缘基板背面金属层41与底部金属绝缘基板背面金属层51上分别设有第一散热装置12和第二散热装置13，顶部金属绝缘基板背面金属层41与第一散热装置12通过导热硅脂或其它导热材料接触，底部金属绝缘基板背面金属层51也通过导热硅脂或其它导热材料与第二散热装置13接触；第二散热装置13的两侧安装有绝缘垫块121，绝缘垫块121与功率模块的正/负功率端子接触，便于安装母排。
如图12所示，本发明还可以应用在三相桥结构中，将三个本发明中记载的半桥功率模块结构一字排布，并封装在同一塑封外壳内部，便可以实现低寄生电 感的三相桥功率模块，即一个功率模块包括三个正极功率端子1、三个负极功率端子2和三个输出功率端子3，其拓扑结构为三个半桥，如图13所示。
实施例2：如图14所示，本实施例与实施例1的结构基本相同，不同之处在于，本实施例中的输出功率端子3的焊接部31在与芯片接触的位置为基体311，在不与芯片接触的位置为三层结构，中间一层为基体311，上下两侧为填充体312；基体311为热膨胀系数较小的金属钼或钨铜，填充体312为导电性较好的金属银。
本实施例中功率芯片烧结在输出电极的钼基体311上，输出电极不与芯片接触的部位加工有槽，槽内填充有银。金属钼的热膨胀系数一般为铜的三分之一，与芯片比较接近，功率模块工作过程中，焊接层16的热应力较小，可靠性较高，但钼的电导率仅有铜的三分之一，因此在输出电极的局部做填充银结构能够减小输出电极的电阻。
实施例3：如图15所示，本实施例与实施例1的结构基本相同，不同之处在于，输出功率端子3的焊接部31与芯片之间填充有应力缓冲层14，所述输出功率端子3的焊接部31为金属铜，应力缓冲层14为金属钼或钨铜。
输出电极为纯铜材料，由于铜与芯片的热膨胀相差较大，为了提高焊接层16的长期可靠性，本实施例在芯片与输出电极之间增加了应力缓冲层14过渡，即在芯片的表面烧结金属钼或钨铜，然后再将钼或钨铜烧结在输出电极上。
实施例4：如图16-19所示，本实施例与实施例1的结构基本相同，不同之处在于，图17中，底部金属绝缘基板5上设有底部金属绝缘基板表面金属层52、第一局部金属层53和第二局部金属层54，所述第一局部金属层53和第二局部金属层54分别连有一个上半桥驱动端子10，输出功率端子3与第二局部金属层54电连接，从而实现对上半桥开关芯片的控制。
当所述上半桥开关芯片6为IGBT时，正极功率端子1与上半桥开关芯片6的集电极以及上半桥二极管芯片7的负极电连接，上半桥开关芯片6的门极通过一根键合线与第一局部金属层53电连接。
当所述上半桥开关芯片6为MOSFET时，所述正极功率端子1与上半桥开关芯片6的漏极以及上半桥二极管芯片7的负极电连接，上半桥开关芯片6的门极通过一根键合线与第一局部金属层53电连接。
图18中，顶部金属绝缘基板4上设有顶部金属绝缘基板表面金属层42和第三局部金属层43，第三局部金属层43的另一端连接有一个下半桥驱动端子11，所述顶部金属绝缘基板表面金属层42也连接有一个下半桥驱动端子11；
当所述下半桥开关芯片8为IGBT时，负极功率端子2与下半桥开关芯片8的发射极以及下半桥二极管芯片9的正极的电连接，下半桥开关芯片8的门极与第三局部金属层43相连；
当所述下半桥开关芯片8为MOSFET时，负极功率端子2与下半桥开关芯片8的源极以及下半桥二极管芯片9的正极的电连接，下半桥开关芯片8的门极与第三局部金属层43相连。
本发明作为形成半导体芯片的基础，可以使用硅衬底，可也以使用锗衬底或者III-V半导体材料，例如，GaN或SiC；另外，对于包装、模塑或封装而言，可以使用塑料材料或陶瓷材料等。
实施例5：
本实施例与实施例1的结构基本相同，不同之处在于，
正极功率端子1和负极功率端子2均烧结在顶部金属绝缘基板4上，并且至少一个输入功率端子与底部金属绝缘基板5通过金属连接柱相连；
或者，正极功率端子1和负极功率端子2均烧结在底部金属绝缘基板5上，并与顶部金属绝缘基板4通过金属连接柱相连；
或者，正极功率端子1和负极功率端子2与顶部金属绝缘基板4和底部金属绝缘基板5均烧结。
塑封外壳15在顶部金属绝缘基板背面金属层41和底部金属绝缘基板背面金属层51的两侧均设有热沉。
如图20所示，顶部金属绝缘基板4上烧结的芯片为下半桥二极管芯片9和上半桥二极管芯片7，底部金属绝缘基板5上烧结的芯片为下半桥开关芯片8和上半桥开关芯片6，其中，下半桥二极管芯片9与下半桥开关芯片8叠层设置，上半桥二极管芯片7与上半桥开关芯片6叠层设置。
如图21所示，顶部金属绝缘基板4包括与正极功率端子1通过烧结的方式实现电连接的顶部金属绝缘基板正极金属层451、与负极功率端子2通过烧结的方式实现电连接的顶部金属绝缘基板负极金属层452、与输出功率端子3和一个上半桥驱动端子电连接的上半桥开关芯片6上半桥开关芯片发射极/源极局部金属层453，以及与另一个上半桥驱动端子电连接的上半桥开关芯片6上半桥开关芯片6门极局部金属层454；
顶部金属绝缘基板正极金属层451的表面烧结有上半桥二极管芯片7，并且与上半桥二极管芯片7的负极相对，顶部金属绝缘基板负极金属层452的表面烧结有下半桥二极管芯片9，并且与下半桥二极管芯片9的正极相对，上半桥开关芯片6门极局部金属层454与上半桥开关芯片6的门极电连接。
如图22所示，底部金属绝缘基板5包括与正极功率端子1通过烧结或超声波金属焊接的方式实现电连接的底部金属绝缘基板正极金属层551、与负极功率端子2及一个下半桥驱动端子电连接的底部金属绝缘基板负极金属层552，以及与另一个下半桥驱动端子电连接的下半桥开关芯片门极局部金属层553；正极功率端子1、负极功率端子2均可通过烧结或超声波金属焊接的方式分别连接至底部金属绝缘基板正极金属层551和底部金属绝缘基板负极金属层552；
底部金属绝缘基板正极金属层551的表面烧结有上半桥开关芯片6，并与上半桥开关芯片6的集电极或漏极正对，底部金属绝缘基板负极金属层552表面烧结有下半桥开关芯片8，并与下半桥开关芯片8的发射极正对；下半桥开关芯片门极局部金属层553通过烧结的方式与下半桥开关芯片8的门极电连接。
如图23所示，输出功率端子3包括设有连接孔的连接部32、用于与芯片连接的焊接部31，以及上半桥引出端33，所述焊接部31与上半桥开关芯片6的发射极或源极烧结，当上半桥开关芯片6为IGBT时为发射极，当上半桥开关芯片6为MOSFET时为源极、与下半桥开关芯片8的集电极或漏极烧结，当下半桥开关芯片8为IGBT时为集电极，当下半桥开关芯片8为MOSFET时为漏极、与上半桥二极管芯片7的正极烧结、与下半桥二极管芯片9的负极烧结；所述焊接部31与芯片之间均设有金属应力缓冲层，并通过该金属应力缓冲层连接。
实施例6：
本实施例与实施例1的结构基本相同，不同之处在于，
如图24所示，底部金属绝缘基板5上设有上半桥表面金属层561和输出局部金属层562，上半桥表面金属层561上烧结有上半桥开关芯片6和上半桥二极管芯片7；
如图25所示，顶部金属绝缘基板4上设有下半桥表面金属层461、下半桥驱动局部金属层462、第一上半桥驱动局部金属层463和第二上半桥驱动局部金属层464，下半桥表面金属层461上烧结有下半桥开关芯片8和下半桥二极管芯片9，下半桥表面金属层461和下半桥驱动局部金属层462分别连有一个下半桥驱动端子，第一上半桥驱动局部金属层463和第二上半桥驱动局部金属层464分别连有一个上半桥驱动端子；
当下半桥开关芯片8为IGBT时，下半桥表面金属层461与IGBT芯片的发射极相连；当下半桥开关芯片8为MOSFET时，下半桥表面金属层461与MOSFET芯片的源极相连，下半桥驱动局部金属层462与下半桥开关芯片8的门极相连，第一上半桥驱动局部金属层463与上半桥开关芯片6的门极相连，第二上半桥驱动局部金属层464与输出功率端子3的焊接部31相连。
结合图24、图25，如图26所示，输出功率端子3包括焊接部31和设有安装孔的连接部32，所述焊接部31位于底部金属绝缘基板5与顶部金属绝缘基板4之间，底部金属绝缘基板5或顶部金属绝缘基板4上设有输出局部金属层562，输出功率端子3通过输出局部金属层562连接有芯片连接块，芯片连接块与底部金属绝缘基板5上的芯片和顶部金属绝缘基板4上的芯片电连接。本实施例中的焊接部31是平面结构，焊接部31的一端弯折并向上延伸形成具有安装孔的连接部32，具体应用时也可根据实际需要不进行弯折而是做成一整块平板结构。
焊接部31上设有上半桥驱动连接端，上半桥驱动连接端与顶部金属绝缘基板4的第二上半桥驱动局部金属层464相连，第二上半桥驱动局部金属层464另一端连接一个上半桥驱动端子。本实施例中的上半桥驱动连接端可以采用单独的金属连接块，也可以与输出功率端子3为一体结构，上半桥开关芯片6门极与顶部金属绝缘基板4的第一上半桥驱动局部金属层463采用金属连接块实现电气连接，金属连接块选用导电类材料；芯片连接块可以选用钼、钨铜等与芯片的热膨胀系数比较匹配的金属材料，芯片连接块的热膨胀系数优选范围在2～8ppm/℃之间的金属材料，如此能够降低芯片与芯片连接块之间烧结层的热应力，避免烧结层过早开裂失效，提高了可靠性。另外，第一上半桥驱动局部金属层463也可以设置在底部金属绝缘基板5上，此时上半桥开关芯片6的门极与第一上半桥驱动局部金属层463可以使用键合线进行连接。
芯片连接块可以为一块整体，也可以根据芯片数量进行拆分，本实施例中芯片连接块分为第一芯片连接块361和第二芯片连接块362，第一芯片连接块361与第二芯片连接块362均与输出局部金属层562烧结；第一芯片连接块361在面向顶部金属绝缘基板4的一面与下半桥二极管芯片9烧结，在面向底部金属绝缘基板5的一面与上半桥开关芯片6烧结；第二芯片连接块362在面向顶部金属绝缘基板4的一面与下半桥开关芯片8烧结，在面向底部金属绝缘基板5的一面与上半桥二极管芯片7烧结。
实施例7：
本实施例与实施例1-6的结构基本相同，不同之处在于，如图27所示，本实施例在实施例1-6的功率模块下表面设置散热装置18并在功率模块上表面设置多个热管19。
如图28所示，散热装置18上设有热管插入口181，热管19包括蒸发段191，蒸发段191的始端连接在功率模块上，本实施例中多个蒸发段191在功率模块的上表面交错排布，蒸发段191在功率模块的边缘处向下折弯形成连接段192，连接段192插入散热装置18的热管插入口181并固定，本实施例中连接段192包 括其延伸出的冷凝段，冷凝段插入散热装置18的热管插入口181并固定；多个蒸发段191也可以采用平行但不交错的方式，即始端不连接在功率模块上，其主体烧结在功率模块的上表面，热管19的两端均在功率模块的边缘处向下折弯形成连接段192，连接段192插入散热装置18的热管插入口181并固定。
散热装置18与热管19冷端可以通过软钎焊进行连接，或者通过其它介质进行连接，或者通过过盈配合进行连接。热管19冷端可以直接与液体散热介质接触，此时需做好散热器与热管19连接孔的密封。
如图29所示，散热装置18可以采用水冷、风冷或其他本领域常用的散热方式，本实施例中的散热装置18为风冷散热装置，热管19的冷端插入风冷散热器中。
如图30-32所示是本实施例中功率模块与热管19的装配部分流程，通过软钎焊的方式将热管19的一端焊接在功率模块内部顶部金属绝缘基板4的外表面；然后对模块进行注塑封装，再将完成注塑模块外部的热管19向底部金属绝缘基板5的方向进行折弯，本实施例中热管19的蒸发段191被包裹在塑封外壳15内，此时，为了方便与功率模块底部的散热装置接触散热，塑封外壳15将底部金属绝缘基板5下表面的中间部分裸露在外，而不需要与散热装置接触的顶部金属绝缘基板4上表面连同热管蒸发段191一起包封在塑封外壳15内部。
此时，功率芯片的热量通过顶部金属绝缘基板4传导到热管19的蒸发段191，热管19内部的填充介质由液相变为汽相，汽相散热介质到达热管19冷端后，又重新变为液相，并在毛细管虹吸的作用下到达蒸发段191，不断循环，实现了将模块顶部的热量传导至冷端的目的。为了减小热管19蒸发段191与顶部金属绝缘基板4的热阻，将蒸发段191通过软钎焊焊接在功率模块顶部金属上。为进一步优化散热效果，热管19的排列分为交错双向排列。
功率模块的驱动板17上有些元件在工作过程中也会产生大量热量，如果不及时散热，同样存在元件烧毁的风险。本发明功率模块由于在顶部金属绝缘基板4上布置有高导热的热管19，驱动板17可以通过散热介质与热管19接触，此时驱动板17的热量也可以通过热管19传导至散热器，进一步提高了系统的可靠性。
实施例8：
本实施例与实施例7的结构基本相同，不同之处在于：
如图33所示，顶部金属绝缘基板4的上表面烧结有交错排布的热管19，热外的冷端向底部金属绝缘基板5的方向折弯，并插入散热装置18内部。驱动板17与驱动端子连接，并通过高热导的粘结材料固定在热管19的另一表面，达到驱动芯片散热的目的。此时，塑封外壳15将顶部金属绝缘基板4上表面的中间 部分和底部金属绝缘基板5下表面的中间部分裸露在外，顶部金属绝缘基板4上表面的中间部分和底部金属绝缘基板5下表面的中间部分均高出塑封外壳15，便于与散热装置18的接触；热管19的蒸发段191烧结在顶部金属绝缘基板4上，蒸发段191露在塑封外壳15外部。
实施例9：
本实施例与实施例7、实施例8的结构基本相同，不同之处在于：
如图34-36所示，本实施例在底部金属绝缘基板5下表面的中间部分烧结有扰流结构53，流体直接与扰流结构53接触，达到更好的散热效果。本实施例中的扰流结构53为叉排的圆柱状pin-fin，通过焊料烧结在底部金属绝缘基板5的下表面，流体流动向方向的pin-fin呈交叉排布，增加了流体的扰动性，增强了流体与pin-fin的换热效果。
如图37所示，散热装置18的上表面设有扰流孔182，所述扰流结构53通过扰流孔182伸入散热装置18内部并在扰流孔182口处密封，在散热装置18内部构成散热介质的换热通道。
扰流结构53不限于圆柱状pin-fin，横截面可也以是菱性、方形，或者是肋条状结构等形式。pin-fin的材料一般为铜材，并在表面镀有其它金属，通过在底部金属绝缘基板5的下表面印刷焊膏，并利用工装夹具，将pin-fin烧结在底部金属绝缘基板5的下表面，功率模块内部产生的热量通过底部金属绝缘基板5传导至pin-fin，而pin-fin直接与流体接触，去除了底部金属绝缘基板5下表面金属层平板结构的导热硅脂，增加了功率模块的散热面积，减小了功率模块的热阻。
以上仅是本发明的优选实施方式，应当指出：对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种低寄生电感功率模块，其特征在于，包括输入功率端子、输出功率端子(3)、顶部金属绝缘基板(4)、底部金属绝缘基板(5)和塑封外壳(15)，所述输入功率端子包括正极功率端子(1)、负极功率端子(2)，顶部金属绝缘基板(4)与底部金属绝缘基板(5)叠层设置，顶部金属绝缘基板(4)与底部金属绝缘基板(5)在二者相对的面上均烧结有芯片，正极功率端子(1)、负极功率端子(2)以及与输出功率端子(3)均与芯片电连接；所述输出功率端子(3)包括焊接部(31)和位于塑封外壳(15)外部的连接部(32)，所述焊接部(31)位于顶部金属绝缘基板(4)与底部金属绝缘基板(5)之间。
  2. 根据权利要求1所述的一种低寄生电感功率模块，其特征在于，所述底部金属绝缘基板(5)上烧结有上半桥开关芯片(6)和上半桥二极管芯片(7)，顶部金属绝缘基板(4)上烧结有下半桥开关芯片(8)和下半桥二极管芯片(9)；所述上半桥开关芯片(6)与下半桥二极管芯片(9)叠层设置，下半桥开关芯片(8)与上半桥二极管芯片(7)叠层设置。
  3. 根据权利要求2所述的一种低寄生电感功率模块，其特征在于，所述正极功率端子(1)烧结在底部金属绝缘基板(5)上，负极功率端子(2)烧结在顶部金属绝缘基板(4)上；焊接部(31)位于顶部金属绝缘基板(4)上烧结的芯片和底部金属绝缘基板(5)上烧结的芯片之间。
  4. 根据权利要求2所述的一种低寄生电感功率模块，其特征在于，所述正极功率端子(1)烧结在底部金属绝缘基板(5)上，负极功率端子(2)烧结在顶部金属绝缘基板(4)上，底部金属绝缘基板(5)或顶部金属绝缘基板(4)上设有输出局部金属层(562)，输出功率端子(3)通过输出局部金属层(562)连接有芯片连接块，芯片连接块与底部金属绝缘基板(5)上的芯片和顶部金属绝缘基板(4)上的芯片电连接。
  5. 根据权利要求1所述的一种低寄生电感功率模块，其特征在于，所述顶部金属绝缘基板(4)上烧结的芯片为下半桥二极管芯片(9)和上半桥二极管芯片(7)，底部金属绝缘基板(5)上烧结的芯片为下半桥开关芯片(8)和上半桥开关芯片(6)，其中，下半桥二极管芯片(9)与下半桥开关芯片(8)叠层设置，上半桥二极管芯片(7)与上半桥开关芯片(6)叠层设置。
  6. 根据权利要求2或5所述的一种低寄生电感功率模块，其特征在于，所述正极功率端子(1)和负极功率端子(2)均烧结在顶部金属绝缘基板(4)上，并且至少一个输入功率端子与底部金属绝缘基板(5)通过金属连接柱相连；或者，正极功率端子(1)和负极功率端子(2)均烧结在底部金属绝缘基板(5) 上，并与顶部金属绝缘基板(4)通过金属连接柱相连；或者，正极功率端子(1)和负极功率端子(2)与顶部金属绝缘基板(4)和底部金属绝缘基板(5)均烧结；所述焊接部(31)位于顶部金属绝缘基板(4)上烧结的芯片和底部金属绝缘基板(5)上烧结的芯片之间。
  7. 根据权利要求3所述的一种低寄生电感功率模块，其特征在于，所述焊接部(31)在面向底部金属绝缘基板(5)的一面与上半桥开关芯片(6)和上半桥二极管芯片(7)烧结，在面向顶部金属绝缘基板(4)的一面与下半桥开关芯片(8)和下半桥二极管芯片(9)烧结。
  8. 根据权利要求3所述的一种低寄生电感功率模块，其特征在于，所述底部金属绝缘基板(5)上设有底部金属绝缘基板表面金属层(52)，底部金属绝缘基板表面金属层(52)上烧结有上半桥开关芯片(6)和上半桥二极管芯片(7)，当所述上半桥开关芯片为IGBT时，正极功率端子(1)与上半桥开关芯片(6)的集电极以及上半桥二极管芯片的负极电连接，当所述上半桥开关芯片(6)为MOSFET时，所述正极功率端子(1)与上半桥开关芯片(6)的漏极以及上半桥二极管芯片的负极电连接；
    所述顶部金属绝缘基板(4)上设有顶部金属绝缘基板表面金属层(42)、第一上半桥驱动局部金属层(421)和第二上半桥驱动局部金属层(422)，所述顶部金属绝缘基板表面金属层(42)上烧结有下半桥开关芯片(8)和下半桥二极管芯片(9)，第一上半桥驱动局部金属层(421)和第二上半桥驱动局部金属层(422)分别连有一个上半桥驱动端子(10)，上半桥开关芯片(6)的门极与所述第一上半桥驱动局部金属层(421)电连接，输出功率端子(3)与第二上半桥驱动局部金属层(422)电连接；
    所述顶部金属绝缘基板(4)上还设有下半桥驱动局部金属层(423)，下半桥驱动局部金属层(423)与所述下半桥开关芯片(8)的门极相连，下半桥驱动局部金属层(423)的另一端连接有一个下半桥驱动端子(11)，所述顶部金属绝缘基板表面金属层(42)也连接有一个下半桥驱动端子(11)。
  9. 根据权利要求4所述的一种低寄生电感功率模块，其特征在于，所述芯片连接块在面向底部金属绝缘基板(5)的一面与上半桥开关芯片(6)和上半桥二极管芯片(7)烧结，在面向顶部金属绝缘基板(4)的一面与下半桥开关芯片(8)和下半桥二极管芯片(9)烧结。
  10. 根据权利要求4所述的一种低寄生电感功率模块，其特征在于，所述芯片连接块分为第一芯片连接块(361)和第二芯片连接块(362)，第一芯片连接 块(361)与第二芯片连接块(362)均与输出局部金属层(562)烧结；第一芯片连接块(361)在面向顶部金属绝缘基板(4)的一面与下半桥二极管芯片(9)烧结，在面向底部金属绝缘基板(5)的一面与上半桥开关芯片(6)烧结；第二芯片连接块(362)在面向顶部金属绝缘基板(4)的一面与下半桥开关芯片(8)烧结，在面向底部金属绝缘基板(5)的一面与上半桥二极管芯片(7)烧结。
  11. 根据权利要求4所述的一种低寄生电感功率模块，其特征在于，所述底部金属绝缘基板(5)上设有上半桥表面金属层(561)和输出局部金属层(562)，上半桥表面金属层(561)上烧结有上半桥开关芯片(6)和上半桥二极管芯片(7)，当所述上半桥开关芯片(6)为IGBT时，正极功率端子(1)与上半桥开关芯片(6)的集电极以及上半桥二极管芯片(7)的负极电连接，当所述上半桥开关芯片(6)为MOSFET时，所述正极功率端子(1)与上半桥开关芯片(6)的漏极以及上半桥二极管芯片(7)的负极电连接；
    所述顶部金属绝缘基板(4)上设有下半桥表面金属层(461)、下半桥驱动局部金属层(462)、第一上半桥驱动局部金属层(463)和第二上半桥驱动局部金属层(464)，下半桥表面金属层(461)上烧结有下半桥开关芯片(8)和下半桥二极管芯片(9)，下半桥表面金属层(461)和下半桥驱动局部金属层(462)分别连有一个下半桥驱动端子，第一上半桥驱动局部金属层(463)和第二上半桥驱动局部金属层(464)分别连有一个上半桥驱动端子；
    当下半桥开关芯片(8)为IGBT时，下半桥表面金属层(461)与IGBT芯片的发射极相连；当下半桥开关芯片(8)为MOSFET时，下半桥表面金属层(461)与MOSFET芯片的源极相连，下半桥驱动局部金属层(462)与下半桥开关芯片(8)的门极相连，第一上半桥驱动局部金属层(463)与上半桥开关芯片(6)的门极相连，第二上半桥驱动局部金属层(464)与输出功率端子(3)的焊接部(31)相连。
  12. 根据权利要求6所述的一种低寄生电感功率模块，其特征在于，所述顶部金属绝缘基板(4)包括与正极功率端子(1)电连接的顶部金属绝缘基板正极金属层(451)、与负极功率端子(2)电连接的顶部金属绝缘基板负极金属层(452)、与输出功率端子(3)和一个上半桥驱动端子电连接的上半桥开关芯片发射极/源极局部金属层(453)，以及与另一个上半桥驱动端子(10)电连接的上半桥开关芯片门极局部金属层(454)；
    顶部金属绝缘基板正极金属层(451)的表面烧结有上半桥二极管芯片(7)，顶部金属绝缘基板负极金属层(452)的表面烧结有下半桥二极管芯片(9)，上半桥开关芯片门极局部金属层(454)与上半桥开关芯片(6)的门极电连接；
    所述底部金属绝缘基板(5)包括与正极功率端子(1)电连接的底部金属绝缘基板正极金属层(551)、与负极功率端子(2)及一个下半桥驱动端子(11)电连接的底部金属绝缘基板负极金属层(552)，以及与另一个下半桥驱动端子电连接的下半桥开关芯片门极局部金属层(553)；
    底部金属绝缘基板正极金属层(551)的表面烧结有上半桥开关芯片(6)，底部金属绝缘基板负极金属层(552)表面烧结有下半桥开关芯片(8)；下半桥开关芯片门极局部金属层(553)与下半桥开关芯片(8)的门极电连接。
  13. 根据权利要求6所述的一种低寄生电感功率模块，其特征在于，所述输出功率端子(3)还包括上半桥引出端(33)，所述焊接部(31)与上半桥开关芯片(6)的发射极或源极连接、与下半桥开关芯片(8)的集电极或漏极连接、与上半桥二极管芯片(7)的正极连接、与下半桥二极管芯片(9)的负极连接；上半桥引出端(33)与顶部金属绝缘基板(4)的上半桥开关芯片发射极/源极局部金属层(453)连接。
  14. 根据权利要求1所述的一种低寄生电感功率模块，其特征在于，所述输出功率端子(3)的焊接部(31)在与芯片接触的位置为基体(311)，在不与芯片接触的位置为三层结构，中间一层为基体(311)，上下两侧为填充体(312)。
  15. 根据权利要求1所述的一种低寄生电感功率模块，其特征在于，所述输出功率端子(3)的焊接部(31)与芯片之间填充有应力缓冲层(14)。
  16. 根据权利要求1所述的一种低寄生电感功率模块，其特征在于，所述塑封外壳(15)为传递模一体化成型工艺制作，顶部金属绝缘基板背面金属层(41)上表面的中间部分以及底部金属绝缘基板背面金属层(51)下表面的中间部分均露出在塑封外壳(15)的外部，并且高出塑封外壳(15)。
  17. 一种双面散热低寄生电感功率模块，其特征在于，包括如权利要求1-16任一项所述的低寄生电感功率模块，且所述低寄生电感功率模块的下表面设有散热装置(18)，上表面设有多个热管(19)，散热装置(18)上设有热管插入口(181)，热管(19)包括蒸发段(191)，蒸发段(191)在功率模块的边缘处向下折弯形成连接段(192)，连接段(192)插入散热装置(18)的热管插入口(181)并固定。
  18. 根据权利要求17所述的一种双面散热低寄生电感功率模块，其特征在于，还包括驱动端子，驱动端子连接有驱动板(17)，所述驱动板(17)和功率模块之间设有热管(19)。
  19. 根据权利要求17所述的一种双面散热低寄生电感功率模块，其特征在于，所述热管(19)的蒸发段(191)烧结在顶部金属绝缘基板(4)上；所述蒸发段(191)被包裹在塑封外壳(15)内；或者，所述蒸发段(191)露在塑封外壳(15)外部，且塑封外壳(15)将顶部金属绝缘基板(4)上表面的中间部分和底部金属绝缘基板(5)下表面的中间部分裸露在外。
  20. 根据权利要求17所述的一种低寄生电感功率模块，其特征在于，所述底部金属绝缘基板(5)下表面设有扰流结构(53)，所述散热装置(18)的上表面设有扰流孔(182)，所述扰流结构(53)通过扰流孔(182)伸入散热装置(18)内部并在扰流孔(182)口处密封，在散热装置(18)内部构成散热介质的换热通道。
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