WO2018225393A1 - Dispositif de conversion d'énergie, circuit de détection de défaillance et circuit d'attaque - Google Patents

Dispositif de conversion d'énergie, circuit de détection de défaillance et circuit d'attaque Download PDF

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Publication number
WO2018225393A1
WO2018225393A1 PCT/JP2018/016082 JP2018016082W WO2018225393A1 WO 2018225393 A1 WO2018225393 A1 WO 2018225393A1 JP 2018016082 W JP2018016082 W JP 2018016082W WO 2018225393 A1 WO2018225393 A1 WO 2018225393A1
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Prior art keywords
circuit
signal
switching element
arm side
pair
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PCT/JP2018/016082
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English (en)
Japanese (ja)
Inventor
遼一 稲田
広津　鉄平
龍太郎 中里
宣信 船崎
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日立オートモティブシステムズ株式会社
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Priority to JP2019523380A priority Critical patent/JP6778324B2/ja
Publication of WO2018225393A1 publication Critical patent/WO2018225393A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage

Definitions

  • the present invention relates to a power converter, a failure detection circuit and a drive circuit used in the power converter.
  • a direct current supplied from a battery is changed to an alternating current by switching a motor configured to generate a driving force of the vehicle and a switching element using a power semiconductor or the like.
  • An inverter device power conversion device
  • Such an inverter device is equipped with a failure detection circuit that detects a failure when a failure occurs in an internal circuit.
  • the failure detection circuit includes, for example, an overcurrent detection circuit that detects that a large current has flowed through the power semiconductor due to a failure, and an overheat detection circuit that detects that the power semiconductor has abnormally generated heat due to a failure.
  • Patent Document 1 discloses an overcurrent limiting circuit provided in a high voltage power IC including a high side output switch element and a low side output switch element.
  • This overcurrent limiting circuit includes a voltage comparison circuit that detects when the voltage at the midpoint terminal becomes a voltage corresponding to the overcurrent of the high-side output switch element, and before the drive control signal is input to the high-side output switch element.
  • a logical product of the first delay circuit that delays the edge by the first delay time, the second delay circuit that delays the output signal of the voltage comparison circuit by the second delay time, and the output signal of each delay circuit is obtained.
  • an AND circuit for detecting an overcurrent and outputting an overcurrent detection signal.
  • the main object of the present invention is to provide a technique for identifying a short-circuit fault location when a short-circuit fault occurs in any of the switching elements in a power conversion device having a plurality of switching elements.
  • a power converter includes a pair of switching elements in which a switching element on the upper arm side and a switching element on the lower arm side are connected in series, and drive signals for controlling the pair of switching elements, respectively.
  • a control circuit that outputs a signal, a driver circuit that drives each of the pair of switching elements based on the drive signal, and an overcurrent detection that detects an overcurrent flowing through each of the pair of switching elements and outputs an overcurrent detection signal
  • a failure detection circuit that outputs a failure detection signal when each of the pair of switching elements is short-circuited, and the failure detection circuit is based on the drive signal for each of the pair of switching elements.
  • the failure detection signal is output, and at least one of the delay signal change from on to off and the change from off to on of one of the pair of switching elements, and the other switching element At least one of the change from OFF to ON and the change from ON to OFF of the drive signal is synchronized with each other.
  • the power conversion device includes, for a plurality of phases, a switching circuit having a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series, A control circuit that outputs a drive signal for controlling the pair of switching elements of a plurality of phases; a driver circuit that drives the pair of switching elements of the plurality of phases based on the drive signal; An overcurrent detection circuit that detects an overcurrent that flows through each of the pair of switching elements of the phase and outputs an overcurrent detection signal, and the overcurrent detection circuit for any one of the plurality of phases When the overcurrent detection signal is output to one of the pair of switching elements, the control circuit
  • the drive signal for the upper arm side switching element is on, or the drive signal for the upper arm side switching element and the drive signal for the lower arm side switching element of the phase are both off.
  • the drive signal for the switching element on the upper arm side of the phase is in the on state immediately before, the switching element on the upper arm side is turned off for all of the plurality of phases.
  • the drive signal is output so that the switching element on the upper arm side is controlled to be on and the switching element on the lower arm side is controlled to be off.
  • the failure detection circuit outputs a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series, and a drive signal for controlling the pair of switching elements.
  • a delay circuit that outputs a delay signal based on the drive signal for each of the pair of switching elements, and the pair of switching elements has an overcurrent.
  • the drive circuit includes a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series, and a control for outputting a drive signal for controlling the pair of switching elements.
  • a driver circuit that drives each of the pair of switching elements based on the drive signal, and detects an overcurrent that flows through each of the pair of switching elements.
  • An overcurrent detection circuit that outputs an overcurrent detection signal; and a failure detection circuit that outputs a failure detection signal when each of the pair of switching elements is short-circuited, and the failure detection circuit includes the pair of switching elements.
  • a delay circuit that outputs a delay signal based on the drive signal for each of the switching elements; The failure detection signal is output based on the overcurrent detection signal and the delay signal, and the change of the delay signal from ON to OFF and the change from OFF to ON of one of the pair of switching elements is changed. At least one and at least one of the change from OFF to ON and the change from ON to OFF of the drive signal for the other switching element are synchronized with each other.
  • the short-circuit failure location can be specified.
  • FIG. 1 is a diagram illustrating a configuration of a power conversion device 3 and peripheral circuits according to an embodiment of the present invention.
  • a power conversion device 3 shown in FIG. 1 is connected between an external power source 1 and a load 2 and exchanges power input and output between them.
  • the external power source 1 is a DC power source for driving the load 2 and corresponds to, for example, an in-vehicle battery.
  • the load 2 is a target load to be driven by the power conversion device 3, and examples thereof include a motor, a solenoid, and a transformer for transformation.
  • a three-phase AC motor that is mounted on an electric vehicle such as a hybrid vehicle or an electric vehicle and generates a driving force of the vehicle is used as the load 2 will be described. The same applies to.
  • the power conversion device 3 includes a control circuit 4, a current sensor 5, and an inverter circuit 6.
  • the inverter circuit 6 includes six power semiconductors 6au, 6bu, 6av, 6bv, 6aw, and 6bw that operate as switching elements, and six drive circuits 7au, 7bu, 7av, 7bv, and 7aw that drive each power semiconductor. , 7 bw.
  • the same symbols (au to bw) are added to the end of the reference numerals for power semiconductors and drive circuits that have a corresponding relationship. This also applies to various signals such as drive signals and failure detection signals described later.
  • the power conversion device 3 includes the power semiconductor and the drive circuit for three phases (6) each of the U phase, the V phase, and the W phase as described above.
  • the power semiconductors 6au, 6av, 6aw disposed on the upper side, that is, the high potential side are referred to as upper arm side power semiconductors
  • the power semiconductors 6bu disposed on the lower side, that is, the low potential side, 6bv and 6bw are referred to as lower arm side power semiconductors.
  • the drive circuits 7au, 7av, and 7aw arranged on the upper side, that is, on the high potential side are referred to as upper arm side drive circuits
  • the drive circuits 7bu, 7bv, and 7bw arranged on the lower side, that is, on the low potential side are referred to. This is referred to as a lower arm side drive circuit.
  • the control circuit 4 is a circuit that performs drive control of the load 2 using the inverter circuit 6, and includes a CPU, a RAM, a ROM, a communication circuit (all not shown), and the like.
  • the ROM mounted on the control circuit 4 may be an electrically rewritable ROM, such as an EEPROM (Electrically Erasable Programmable ROM) or a flash ROM.
  • the control circuit 4 communicates with an electronic control device (not shown) connected to the outside of the power conversion device 3 and receives a drive command for the load 2. Based on this drive command and the current value obtained from the current sensor 5, drive control of the load 2 is performed.
  • the drive control of the load 2 is performed by outputting drive signals 8au to 8bw from the control circuit 4 to the drive circuits 7au to 7bw of the inverter circuit 6, respectively. That is, the control circuit 4 receives the drive command from the outside, and the upper arm side power semiconductors 6au, 6av, 6aw and the lower arm side which are switching elements provided for each of the U phase, the V phase, and the W phase.
  • Drive signals 8au to 8bw for controlling each of the power semiconductors 6bu, 6bv and 6bw are output.
  • the control circuit 4 receives the failure detection signals 19au to 19bw output from the drive circuits 7au to 7bw, respectively, and specifies a failure occurrence point based on the failure detection signals 19au to 19bw. Specifically, when any of the failure detection signals 19au to 19bw changes from low indicating normal state to high indicating short-circuit failure, it is determined that a short-circuit failure has occurred in the power semiconductor corresponding to the failure detection signal. . Then, in order to control the inverter circuit 6 corresponding to the specified failure location, the state of the drive signals 8au to 8bw is switched from the normal state. A specific operation at this time will be described later. Further, at this time, the control circuit 4 outputs a failure notification signal to the failure notification device 30 connected to the outside of the power conversion device 3.
  • the current sensor 5 is a sensor for measuring the current flowing through the load 2.
  • a three-phase AC motor is used as the load 2 as described above. Therefore, the current sensor 5 individually measures the current value of each phase and outputs the measured value to the control circuit 4.
  • the power semiconductors 6au to 6bw function as switching elements by being driven to be switched by the drive circuits 7au to 7bw, respectively.
  • the power semiconductors 6 au to 6 bw are switched in response to a drive command, whereby the direct current supplied from the external power supply 1 is converted into a three-phase alternating current and output to the load 2.
  • a power MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • each of the power semiconductors 6au to 6bw has a sense terminal. From this sense terminal, a constant ratio of the current flowing between the drain and source of the power semiconductor, for example, 1 / 100th or 1 / 1000th of current is output.
  • the driving circuits 7 au to 7 bw receive the driving signals 8 au to 8 bw output from the control circuit 4, respectively, and switch on / off the corresponding power semiconductors 6 au to 6 bw.
  • the drive circuits 7 au to 7 bw have a failure detection circuit for detecting a short-circuit failure of the corresponding power semiconductors 6 au to 6 bw. When the failure of the power semiconductor is detected, the drive circuits 7 au to 7 bw Failure detection signals 19au to 19bw are output respectively. The details of the drive circuits 7au to 7bw will be described later with reference to FIG.
  • the failure notification device 30 receives a failure notification signal from the control circuit 4 and notifies the vehicle occupant of the occurrence of the failure.
  • Examples of the failure notification method include a method of lighting a lamp, generating a warning sound, and notifying by voice.
  • FIG. 2 is a diagram showing a configuration of a drive circuit and its peripheral circuits in the power conversion device 3 according to the first embodiment of the present invention.
  • FIG. 2 among the power semiconductors 6 au to 6 bw and the drive circuits 7 au to 7 bw for the three phases shown in FIG. 1, the configuration related to the power semiconductors 6 au and 6 bu for one phase (U phase) and the drive circuits 7 au and 7 bu Only a representative example is shown.
  • the configurations of the other two-phase (V-phase, W-phase) power semiconductors 6av, 6bv, 6aw, 6bw and drive circuits 7av, 7bv, 7aw, 7bw are the same as those shown in FIG. Description of is omitted.
  • the drive circuits 7au and 7bu each have a driver circuit 10, an overcurrent detection circuit 11, and a failure detection circuit 16 therein.
  • the driver circuit 10 controls the gate signal output to the corresponding power semiconductor based on the drive signal output from the control circuit 4. Thereby, on / off of the power semiconductor is switched.
  • the driver circuit 10 inside the drive circuit 7au receives the drive signal 8au from the control circuit 4, controls the gate signal 9au, and switches on / off the target power semiconductor 6au.
  • the driver circuit 10 in the drive circuit 7bu receives the drive signal 8bu from the control circuit 4, controls the gate signal 9bu, and switches on / off the target power semiconductor 6bu. In this way, in the drive circuits 7au and 7bu, the driver circuit 10 drives the pair of upper arm side power semiconductors 6au and lower arm side power semiconductors 6bu based on the drive signals 8au and 8bu, respectively.
  • the overcurrent detection circuit 11 is a circuit that detects an overcurrent flowing through a corresponding power semiconductor and outputs an overcurrent detection signal.
  • the overcurrent detection circuit 11 includes a resistor 12, a reference voltage source 13, and a comparator 14 inside.
  • the overcurrent detection circuit 11 converts the sense current output from the corresponding power semiconductor into a voltage by the resistor 12.
  • the converted voltage and the voltage of the reference voltage source 13 are compared by the comparator 14.
  • the overcurrent detection signal is not output.
  • the overcurrent detection circuit 11 detects the occurrence of an overcurrent and outputs an overcurrent detection signal.
  • the overcurrent detection circuit 11 inside the drive circuit 7au notifies whether or not an overcurrent flows through the target power semiconductor 6au by an overcurrent detection signal 15au.
  • the overcurrent detection circuit 11 in the drive circuit 7bu notifies whether or not an overcurrent is flowing through the target power semiconductor 6bu by an overcurrent detection signal 15bu.
  • the overcurrent detection circuit 11 detects the overcurrents flowing through the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu, respectively, and overcurrent detection signals 15au and 15bu. Is output.
  • the failure detection circuit 16 has a delay circuit 17 inside.
  • the delay circuit 17 receives a drive signal output to a corresponding power semiconductor and a drive signal output to a power semiconductor paired with the power semiconductor, and outputs a delay signal based on these drive signals. Details of the method of generating the delay signal will be described later.
  • the failure detection circuit 16 fails when the corresponding power semiconductor is short-circuited based on the delay signal generated by the delay circuit 17 and the overcurrent detection signal output from the overcurrent detection circuit 11 described above. Is detected and a failure detection signal is generated. Specifically, when the delay signal is in a low (off) state and the overcurrent detection signal is high (overcurrent state), it is determined that the corresponding power semiconductor is short-circuited and a failure is detected. Set the signal high (failed state). Then, the failure detection circuit 16 outputs the generated failure detection signal to the control circuit 4.
  • the failure detection circuit 16 simulates the original on / off state of the corresponding power semiconductor by the delay signal.
  • an overcurrent detection signal is output from the overcurrent detection circuit 11 when the delay signal is in a low (off) state, that is, when the power semiconductor is supposed to be in an off state
  • the power semiconductor is Estimated that there is a short circuit failure.
  • the overcurrent detection signal is output, the pair of upper arm side power semiconductors and the lower arm side power semiconductors are both turned on. Therefore, the fact that the overcurrent detection signal is output even though the delay signal is off means that the target power semiconductor must be off, but it is erroneously turned on due to a short circuit fault. That's what it means. Therefore, in such a case, it can be determined that the target power semiconductor is short-circuited.
  • the failure detection circuit 16 inside the drive circuit 7au is driven by the internal delay circuit 17 to drive the drive signal 8au corresponding to the corresponding upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu which forms a pair therewith. Based on the signal 8bu, the value of the delay signal 18au is determined. Then, using the delay signal 18au and the overcurrent detection signal 15au, the value of the failure detection signal 19au is switched and output to the control circuit 4. Further, the failure detection circuit 16 inside the drive circuit 7bu is provided with a drive signal 8bu for the corresponding lower arm side power semiconductor 6bu and a drive signal 8au for the upper arm side power semiconductor 6au paired therewith by an internal delay circuit 17. Based on the above, the value of the delay signal 18bu is determined.
  • the failure detection circuit 16 delays the delay signals 18au and 18bu based on the drive signals 8au and 8bu for each of the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu.
  • the circuit 17 outputs the failure detection signals 19au and 19bu based on the delay signals 18au and 18bu and the overcurrent detection signals 15au and 15bu.
  • FIGS. 3 and 4 are diagrams respectively showing examples of timing charts of respective signals when the power conversion device 3 according to the first embodiment of the present invention is normal and when a short circuit failure occurs.
  • FIGS. 3 and 4 only timing charts of signals in the power semiconductors 6au and 6bu and the drive circuits 7au and 7bu for one phase (U phase) shown in FIG. 2 are shown as representative examples.
  • the signal change is the same as in FIGS.
  • the drive signals 8au and 8bu are switched between high (on state) and low (off state) at regular intervals.
  • the drive signals 8au and 8bu both have a dead time tdd which is a low (off state) time zone.
  • the power semiconductors 6au and 6bu are delayed from the change of the drive signals 8au and 8bu by a delay time tdr, respectively.
  • Change When the state of the drive signals 8au and 8bu changes from high (on state) to low (off state), the power semiconductors 6au and 6bu are delayed from the change of the drive signals 8au and 8bu by a delay time tdf, respectively. Turn off. As shown in the example of FIG. 3, the delay time tdf is set to be shorter than the dead time tdd in order to avoid the power semiconductors 6au and 6bu being simultaneously turned on.
  • the failure detection circuit 16 in the drive circuit 7au outputs the delay signal 18au related to the upper arm side power semiconductor 6au at the timing shown in FIG. 3 based on the drive signals 8au and 8bu by the delay circuit 17. Specifically, the change of the delay signal 18au from low (off state) to high (on state) is caused by the low (off) state of the drive signal 8au output to the upper arm side power semiconductor 6au corresponding to the drive circuit 7au. State) to high (on state). Further, the change of the delay signal 18au from high (on state) to low (off state) indicates that the drive signal 8bu output to the lower arm side power semiconductor 6bu paired with the upper arm side power semiconductor 6au is low ( Synchronize with the change from off to high. In the delay circuit 17 included in the failure detection circuit 16 in the drive circuit 7au, the change timing of the delay signal 18au is determined and output in this way.
  • the failure detection circuit 16 in the drive circuit 7bu outputs a delay signal 18bu related to the lower arm side power semiconductor 6bu at the timing shown in FIG. 3 based on the drive signals 8au and 8bu by the delay circuit 17.
  • the change of the delay signal 18bu from low (off state) to high (on state) indicates that the drive signal 8bu output to the lower arm side power semiconductor 6bu corresponding to the drive circuit 7bu is low (off). State) to high (on state).
  • the change of the delay signal 18bu from high (on state) to low (off state) is caused by the low (in the drive signal 8au output to the upper arm side power semiconductor 6au paired with the lower arm side power semiconductor 6bu ( Synchronize with the change from off to high.
  • the delay circuit 17 included in the failure detection circuit 16 in the drive circuit 7bu the change timing of the delay signal 18bu is determined and output in this way.
  • the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu are both in a normal state. Therefore, the overcurrent detection signals 15au and 15bu remain low indicating that both are not in an overcurrent state. Therefore, the failure detection signals 19au and 19bu output from the failure detection circuit 16 of the drive circuits 7au and 7bu, respectively, remain low indicating that no short-circuit failure has occurred. That is, in the case of FIG. 3, the failure detection signal indicating the occurrence of a short-circuit failure is not output from the failure detection circuit 16 in any of the drive circuits 7 au and 7 bu.
  • the delay signals 18 au and 18 bu output from the delay circuit 17 by the failure detection circuit 16 in the drive circuits 7 au and 7 bu indicate the on / off states of the corresponding power semiconductors 6 au and 6 bu as described above. It is a simulation. Therefore, originally, it is desirable that the delay signals 18au and 18bu accurately simulate the delay times tdr and tdf from the change of the drive signals 8au and 8bu to the change of the states of the power semiconductors 6au and 6bu, respectively. However, in order to accurately simulate the delay times tdr and tdf, it is necessary to provide a plurality of timers inside the delay circuit 17.
  • the change of the delay signals 18au and 18bu from off to on is shifted from the timing at which the target power semiconductors 6au and 6bu actually change from off to on.
  • the delay signal 18au related to the power semiconductor 6au on the upper arm side the drive signal output to the drive circuit 7au corresponding to the power semiconductor 6au at the timing when the delay signal 18au changes from off to on. It is synchronized with the timing when 8 au changes from off to on.
  • the delay signal 18bu related to the power semiconductor 6bu on the lower arm side the drive signal 8bu output to the drive circuit 7bu corresponding to the power semiconductor 6bu indicates the timing at which the delay signal 18bu changes from off to on. It is synchronized with the timing when it changes from off to on.
  • the change of the delay signals 18au and 18bu from on to off is also shifted from the timing at which the target power semiconductors 6au and 6bu actually change from on to off.
  • the timing at which the delay signal 18au changes from on to off corresponds to the power semiconductor 6bu on the lower arm side paired with the power semiconductor 6au.
  • the drive signal 8bu output to the drive circuit 7bu is synchronized with the timing when it changes from on to off.
  • the delay signal 18bu related to the power semiconductor 6bu on the lower arm side the drive circuit corresponding to the power semiconductor 6au on the upper arm side that is paired with the power semiconductor 6bu at the timing when the delay signal 18bu changes from on to off.
  • the drive signal 8au output to 7au is synchronized with the timing when it changes from on to off.
  • the change in the delay signal simulating the switching state of the pair of power semiconductors on the upper arm side and the lower arm side is compared with the change in the drive signal of the arm.
  • Each is synchronized with a change in the arm drive signal.
  • the timer in the delay circuit 17 can be deleted, and the delay circuit 17 can be configured only by a simple combination of logic circuits.
  • the delay circuit 17 in the drive circuit 7 au corresponding to the upper arm side power semiconductor 6 au can be realized by using an RS flip-flop having the drive signal 8 au as an S input and the drive signal 8 bu as an R input.
  • the delay circuit 17 in the drive circuit 7bu corresponding to the lower arm side power semiconductor 6bu can be realized by using an RS flip-flop having the drive signal 8bu as an S input and the drive signal 8au as an R input.
  • the scale and area of the delay circuit 17 can be reduced, and the configuration of the power conversion device 3 of the present embodiment can be realized at a lower cost.
  • the change from OFF to ON and the change from ON to OFF of the delay signals 18au and 18bu are both synchronized with the drive signal 8au or 8bu. However, only one of the timings is selected. May be synchronized with the drive signal 8au or 8bu. When only the change of the delay signal from OFF to ON is synchronized with the drive signal, the timer for simulating the delay time tdr can be reduced. Similarly, when only the change of the delay signal from on to off is synchronized with the drive signal, the timer for simulating the delay time tdf can be reduced.
  • a power conversion device to which the present invention is applied can be realized by synchronizing at least one of a change from OFF to ON of a signal and a change from ON to OFF with each other.
  • FIG. 4 shows an example of a timing chart when the power semiconductor 6au has a short circuit failure at the timing of time t1.
  • both the power semiconductors 6au and 6bu are turned on at time t2 when the power semiconductor 6bu is turned on, and a large current flows through them.
  • the overcurrent detection signals 15au and 15bu both become high (overcurrent state).
  • the delay signal 18au is in an off state and the delay signal 18bu is in an on state. Therefore, the failure detection signal 19au becomes high (failure state) at time t2, and the failure detection signal 19bu remains low (normal state).
  • the failure of the power semiconductor 6au is notified to the control circuit 4 by the failure detection signal 19au.
  • FIG. 5 shows a flowchart of the failure detection process executed by the control circuit 4. This process is performed in the control circuit 4 when any of the failure detection signals 19au to 19bw becomes high (failure state).
  • step S100 the control circuit 4 determines whether any of the failure detection signals 19au, 19av, 19aw related to the upper arm side power semiconductors 6au, 6av, 6aw is high (failure state). If any one is high (failure state), the control circuit 4 determines that any one of the upper arm side power semiconductors 6au, 6av, 6aw has a short-circuit fault, and proceeds to the processing of step S101. On the other hand, when all of the failure detection signals 19au, 19av, 19aw are low (normal state), the control circuit 4 proceeds to the process of step S102.
  • step S101 the control circuit 4 controls all the upper arm side power semiconductors 6au, 6av, 6aw to the on state, and controls all the paired lower arm side power semiconductors 6bu, 6bv, 6bw to the off state.
  • the drive signals 8au to 8bw are output to the drive circuits 7au to 7bw, respectively.
  • the drive signals 8au, 8av, 8aw are all set to high (on state), and the lower arm side
  • the drive signals 8au, 8av, 8aw are set to high (on state)
  • the lower arm side For the drive circuits 7bu, 7bv, 7bw corresponding to the power semiconductors 6bu, 6bv, 6bw, all the drive signals 8bu, 8bv, 8bw are set to low (off state).
  • the upper arm side power semiconductors 6au, 6av, 6aw are all turned on, and the lower arm side power semiconductors 6bu, 6bv, 6bw are all turned off.
  • step S101 the control circuit 4 proceeds to the process of step S104.
  • step S102 the control circuit 4 determines whether one of the failure detection signals 19bu, 19bv, 19bw related to the lower arm side power semiconductors 6bu, 6bv, 6bw is high (failure state). If any one is high (failure state), the control circuit 4 determines that any one of the lower arm side power semiconductors 6bu, 6bv, 6bw has a short-circuit failure, and proceeds to the process of step S103. On the other hand, when all of the failure detection signals 19bu, 19bv, 19bw are low (normal state), the control circuit 4 ends the failure detection process shown in FIG.
  • step S103 the control circuit 4 controls all the upper arm side power semiconductors 6au, 6av, 6aw to the off state, and controls all the paired lower arm side power semiconductors 6bu, 6bv, 6bw to the on state.
  • the drive signals 8au to 8bw are output to the drive circuits 7au to 7bw, respectively.
  • the drive signals 8au, 8av, 8aw are all set to low (off state), and the lower arm side
  • the drive signals 8au, 8av, 8aw are all set to low (off state)
  • the lower arm side For the drive circuits 7bu, 7bv, and 7bw corresponding to the power semiconductors 6bu, 6bv, and 6bw, all the drive signals 8bu, 8bv, and 8bw are set to high (on state).
  • the upper arm side power semiconductors 6au, 6av, 6aw are all turned off, and the lower arm side power semiconductors 6bu, 6bv, 6bw are all turned on.
  • step S104 Similar to the state described in step S101, in this state, the three-phase motor connected to the power conversion device 3 as the load 2 is in a state where neither power running nor regeneration is performed, and torque output is lost. Sudden acceleration and sudden deceleration can be prevented.
  • step S103 the control circuit 4 proceeds to the process of step S104.
  • step S104 the control circuit 4 outputs a failure notification signal to the failure notification device 30.
  • additional information for example, information on the location of the power semiconductor in which a short circuit has failed may be transmitted to the failure notification device 30.
  • the control circuit 4 can switch the U-phase, V-phase, and W-phase switching circuits, that is, the upper arm side power semiconductors 6au, 6av, 6aw and the lower arm side power.
  • the overcurrent detection circuit 11 outputs an overcurrent detection signal to any one of the power semiconductors 6au to 6bw for any phase. Then, the following control is performed.
  • the drive signal for the upper arm side power semiconductor of the phase is on, or the drive signal for the upper arm side power semiconductor of the phase and the drive signal for the lower arm side power semiconductor are both off.
  • the upper arm side power semiconductors 6au, 6av, 6aw are controlled to be in the off state for all three phases, and the lower arm side Drive signals 8au to 8bw are output so as to control the power semiconductors 6bu, 6bv, and 6bw to the on state.
  • the drive signal for the lower arm side power semiconductor of the phase is on, or the drive signal for the upper arm side power semiconductor of the phase and the drive signal for the lower arm side power semiconductor are both off, And when the drive signal for the lower arm side power semiconductor of the phase has been turned on immediately before, the upper arm side power semiconductors 6au, 6av, 6aw are controlled to be turned on and the lower arm side for all three phases.
  • Drive signals 8au to 8bw are output so as to control the power semiconductors 6bu, 6bv, and 6bw to an off state.
  • a delay signal is generated using a drive signal, and a short-circuit fault location of a pair of power semiconductors provided in each phase is specified from the delay signal and an overcurrent detection signal.
  • the change of the delay signal from OFF to ON is synchronized with the change of the drive signal for the target power semiconductor from OFF to ON, and the change of the delay signal from OFF to ON is the change of the drive signal for the paired power semiconductor. Synchronize with changes from off to on.
  • the delay circuit can be configured on a small scale, and a short-circuit fault location can be determined at a lower cost.
  • the power semiconductors 6au, 6av, 6aw which are switching elements on the upper arm side and the power semiconductors 6bu, 6bv, 6bw which are switching elements on the lower arm side are respectively connected in series.
  • Inverter circuit 6, control circuit 4 that outputs drive signals 8 au to 8 bw for controlling these power semiconductors 6 au to 6 bw, and power semiconductors 6 au to 6 bw are driven based on the drive signals 8 au to 8 bw, respectively.
  • Driver circuit 10 overcurrent detection circuit 11 for detecting overcurrent flowing through power semiconductors 6au to 6bw and outputting an overcurrent detection signal, and failure detection signal when power semiconductors 6au to 6bw are short-circuited, respectively.
  • a failure detection circuit 16 that outputs.
  • the failure detection circuit 16 includes a delay circuit 17 that outputs a delay signal based on the drive signals 8au to 8bw for each of the power semiconductors 6au to 6bw, and outputs a failure detection signal based on the overcurrent detection signal and the delay signal.
  • At least one and at least one of the change from OFF to ON and the change from ON to OFF of the drive signal 8bu or 8au for the other power semiconductor are synchronized with each other as described with reference to FIG. Since it did in this way, when a short circuit failure generate
  • the failure detection circuit 16 outputs the overcurrent detection signal 15au or 15bu for one power semiconductor of the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu, and the one power semiconductor.
  • the delay signal 18au or 18bu is in the off state
  • the failure detection signal 19au or 19bu is output for one power semiconductor. Since it did in this way, when a short circuit fault occurs in any power semiconductor, this can be detected reliably and a failure detection signal can be outputted.
  • the control circuit 4 Based on the failure detection signals 19au to 19bw output from the failure detection circuit 16, the control circuit 4 identifies which of the power semiconductors 6au to 6bw has a short circuit failure. Since it did in this way, a short circuit fault location can be specified reliably.
  • the power conversion device 3 has a plurality of combinations of the upper arm side power semiconductor and the lower arm side power semiconductor.
  • the control circuit 4 specifies that the power semiconductor on the upper arm side is short-circuited in any of the combinations of power semiconductors, the upper arm side power semiconductors 6au, 6av, 6aw are used for all the power semiconductor combinations.
  • Drive signals 8au to 8bw are output so that the lower arm side power semiconductors 6bu, 6bv and 6bw are controlled to be turned off.
  • the upper arm side power semiconductors 6au, 6av, 6aw are turned off for all the power semiconductor combinations.
  • the drive signals 8au to 8bw are output so that the lower arm side power semiconductors 6bu, 6bv and 6bw are controlled to be in the ON state. Since it did in this way, when a three-phase motor is connected to the power converter device 3 as the load 2, it is possible to prevent sudden acceleration and sudden deceleration of the three-phase motor due to a short circuit failure.
  • FIG. 6 is a diagram showing a configuration of a drive circuit and its peripheral circuits in the power conversion device according to the second embodiment of the present invention.
  • symbol is provided to the component same as Example 1, and those description is abbreviate
  • the drive circuits 7au and 7bu in FIG. 6 each have a failure detection circuit 16a having a configuration different from that of the failure detection circuit 16 described in the first embodiment.
  • the failure detection circuit 16 a includes a latch circuit 20 in addition to the configuration of the failure detection circuit 16, and the condition for setting the failure detection signal to high (failure state) is different from that of the failure detection circuit 16.
  • the failure detection circuit 16a in the drive circuit 7au corresponding to the upper arm side power semiconductor 6au is in a state where the delay signal 18au output from the delay circuit 17 is low (off), and overcurrent detection is performed.
  • the target failure detection signal 19au is set to high (failure state).
  • the delay signal 18bu output from the delay circuit 17 is in the low (off) state, and the overcurrent detection signal 15bu.
  • the failure detection signal 19bu is set to high (failure state).
  • the latch circuit 20 has a role of maintaining high (failure state) when the failure detection signals 19au and 19bu once become high (failure state).
  • the latch circuit 20 outputs a failure detection signal 19au that is output when a reset signal (not shown) from the control circuit 4 is input. , 19bu are changed from high (failure state) to low (normal state).
  • the failure detection circuit 16a outputs the failure detection signal 19au or 19bu for one of the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu, the failure detection signal 19bu for the other power semiconductor.
  • the failure detection signal 19bu for the other power semiconductor.
  • the output of the failure detection signal 19au or 19bu is held for one of the power semiconductors.
  • FIG. 7 is a diagram illustrating an example of a timing chart of each signal when a short circuit fault occurs in the power conversion device according to the second embodiment of the present invention.
  • FIG. 7 also shows an example of a timing chart when the power semiconductor 6au is short-circuited at the timing of time t1, similarly to FIG. 4 described in the first embodiment.
  • the overcurrent detection signals 15au and 15bu become high (overcurrent state) and the failure detection signal 19au changes to high (failure state) at time t2
  • the change in the drive signals 8au and 8bu thereafter occurs.
  • the failure detection signal 19au is maintained high (failure state), and the failure detection signal 19bu is maintained low (normal state).
  • the control circuit 4 can perform the failure detection process at an arbitrary timing. For example, as in the first embodiment, it may be performed at the timing when any of the failure detection signals 19au to 19bw becomes high (failure state), or may be performed periodically at regular intervals. good. Since the failure detection process of the control circuit 4 in this embodiment is the same as the content described in the first embodiment, the description thereof is omitted.
  • the drive signals 8au and 8bu are turned on / off.
  • the failure detection signals 19au and 19bu alternately change between high (failure state) and low (normal state). Therefore, in order to correctly determine which one of the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu is short-circuited, the control circuit 4 correctly receives the first of the failure detection signals 19au and 19bu that is output. There is a need.
  • the time during which the failure detection signal corresponding to the correct failure occurrence location is high may be short. Therefore, if the time until the control circuit 4 receives the failure detection signal after the failure detection signal is output becomes longer due to the time taken for other control processing or the like, the failure detection signal output first is correctly received. Otherwise, the control circuit 4 may erroneously determine the failure location. The same applies to the other phases.
  • the control circuit 4 can perform the failure detection process at an arbitrary timing, and can prevent the determination error of the failure location.
  • the failure detection circuit 16a outputs the failure detection signal 19au or 19bu for one power semiconductor of the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu. If the failure detection signal 19bu or 19au is not output for the other power semiconductor when it is output, the output of the failure detection signal 19au or 19bu is held for the one power semiconductor. Since it did in this way, it is possible to specify a short circuit failure location without error at arbitrary timings.
  • the failure detection circuits 16 and 16a are provided inside the drive circuits 7au to 7bw, respectively, but are provided outside the drive circuits 7au to 7bw. Also good. Further, the failure detection circuits 16 and 16a may be realized by processing executed by the control circuit 4, or may be incorporated in the control circuit 4 as hardware. Further, the overcurrent detection circuit 11 may also be provided outside the drive circuits 7au to 7bw, or may be realized as processing of the control circuit 4 or an internal element.
  • the present invention is not limited to the above-described embodiments, and includes various modifications.
  • the correspondence between the high / low state of a signal and the state represented by the signal may be opposite to the example described in the embodiment. good.
  • the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.
  • Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.
  • Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor.
  • Information such as programs, tables, and files that realize each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un dispositif de conversion d'énergie dans lequel, lorsqu'une défaillance de court-circuit se produit dans l'un quelconque d'une pluralité d'éléments de commutation, l'emplacement de la défaillance de court-circuit est spécifié. Des circuits de détection de défaillance (16) dans les circuits d'attaque (7au, 7bu) possèdent des circuits à retard (17), respectivement, qui émettent des signaux retardés (18au, 18bu) sur la base de signaux d'attaque (8au, 8bu) destinés à des semi-conducteurs de puissance (6au, 6bu), et émettent des signaux de détection de défaillance (19au, 19bu), respectivement, sur la base de signaux de détection de surintensité (15au, 15bu) et des signaux retardés (18au, 18bu). Un changement de MARCHE à ARRÊT et/ou d'ARRÊT à MARCHE dans le signal retardé (18au ou 18bu) associé à un semi-conducteur de la paire de semi-conducteurs de puissance (6au, 6bu), et un changement d'ARRÊT à MARCHE et/ou de MARCHE à ARRÊT dans le signal d'attaque (8bu ou 8au) de l'autre semi-conducteur de puissance sont synchronisés entre eux.
PCT/JP2018/016082 2017-06-05 2018-04-19 Dispositif de conversion d'énergie, circuit de détection de défaillance et circuit d'attaque WO2018225393A1 (fr)

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
WO2020241366A1 (fr) * 2019-05-24 2020-12-03 日立オートモティブシステムズ株式会社 Dispositif de conversion d'énergie et procédé de commande de dispositif de conversion d'énergie

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JPH0723998U (ja) * 1993-09-30 1995-05-02 日新電機株式会社 インバータの短絡検出回路
JP2008220045A (ja) * 2007-03-05 2008-09-18 Honda Motor Co Ltd 電動機の制御装置および車両
JP2013169102A (ja) * 2012-02-16 2013-08-29 Denso Corp ゲート駆動回路
JP2016111858A (ja) * 2014-12-09 2016-06-20 株式会社デンソー 電力変換装置
JP2017022678A (ja) * 2015-07-15 2017-01-26 ルネサスエレクトロニクス株式会社 半導体装置および電力制御装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0723998U (ja) * 1993-09-30 1995-05-02 日新電機株式会社 インバータの短絡検出回路
JP2008220045A (ja) * 2007-03-05 2008-09-18 Honda Motor Co Ltd 電動機の制御装置および車両
JP2013169102A (ja) * 2012-02-16 2013-08-29 Denso Corp ゲート駆動回路
JP2016111858A (ja) * 2014-12-09 2016-06-20 株式会社デンソー 電力変換装置
JP2017022678A (ja) * 2015-07-15 2017-01-26 ルネサスエレクトロニクス株式会社 半導体装置および電力制御装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020241366A1 (fr) * 2019-05-24 2020-12-03 日立オートモティブシステムズ株式会社 Dispositif de conversion d'énergie et procédé de commande de dispositif de conversion d'énergie
JPWO2020241366A1 (fr) * 2019-05-24 2020-12-03
JP7124218B2 (ja) 2019-05-24 2022-08-23 日立Astemo株式会社 電力変換装置、および電力変換装置の制御方法

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