WO2018225393A1

WO2018225393A1 - Power conversion device, failure detection circuit, and driving circuit

Info

Publication number: WO2018225393A1
Application number: PCT/JP2018/016082
Authority: WO
Inventors: 遼一稲田; 広津　鉄平; 龍太郎中里; 宣信船崎
Original assignee: 日立オートモティブシステムズ株式会社
Priority date: 2017-06-05
Filing date: 2018-04-19
Publication date: 2018-12-13
Also published as: JPWO2018225393A1; JP6778324B2

Abstract

Provided is a power conversion device in which when a short-circuit failure occurs in any of a plurality of switching elements, the location of the short-circuit failure is specified. Failure detection circuits 16 inside driving circuits 7au, 7bu have delay circuits 17, respectively, which output delayed signals 18au, 18bu on the basis of drive signals 8au, 8bu for power semiconductors 6au, 6bu and output failure detection signals 19au, 19bu, respectively, on the basis of overcurrent detection signals 15au, 15bu and the delayed signals 18au, 18bu. At least one of the changes from ON to OFF and from OFF to ON in the delayed signal 18au or 18bu associated with one of the pair of power semiconductors 6au, 6bu and at least one of the changes from OFF to ON and from ON to OFF in the drive signal 8bu or 8au for the other of the power semiconductors are synchronized with each other.

Description

Power converter, failure detection circuit, drive circuit

The present invention relates to a power converter, a failure detection circuit and a drive circuit used in the power converter.

In an electric vehicle such as a hybrid vehicle or an electric vehicle, a direct current supplied from a battery is changed to an alternating current by switching a motor configured to generate a driving force of the vehicle and a switching element using a power semiconductor or the like. An inverter device (power conversion device) that converts and supplies the motor is mounted. Generally, such an inverter device is equipped with a failure detection circuit that detects a failure when a failure occurs in an internal circuit. The failure detection circuit includes, for example, an overcurrent detection circuit that detects that a large current has flowed through the power semiconductor due to a failure, and an overheat detection circuit that detects that the power semiconductor has abnormally generated heat due to a failure.

The technology described in Patent Document 1 is known as background technology in this technical field. Patent Document 1 discloses an overcurrent limiting circuit provided in a high voltage power IC including a high side output switch element and a low side output switch element. This overcurrent limiting circuit includes a voltage comparison circuit that detects when the voltage at the midpoint terminal becomes a voltage corresponding to the overcurrent of the high-side output switch element, and before the drive control signal is input to the high-side output switch element. A logical product of the first delay circuit that delays the edge by the first delay time, the second delay circuit that delays the output signal of the voltage comparison circuit by the second delay time, and the output signal of each delay circuit is obtained. And an AND circuit for detecting an overcurrent and outputting an overcurrent detection signal.

JP-A-9-172358

When a failure occurs in the inverter device, it is preferable to specify the failure location using the above-described failure detection circuit and perform control according to the location. However, in the technique described in Patent Document 1, it is possible to detect an overcurrent due to a short-circuit fault, but a method of specifying which of the high-side output switch element and the low-side output switch element has a short-circuit fault Is not specified.

Therefore, the main object of the present invention is to provide a technique for identifying a short-circuit fault location when a short-circuit fault occurs in any of the switching elements in a power conversion device having a plurality of switching elements.

A power converter according to an aspect of the present invention includes a pair of switching elements in which a switching element on the upper arm side and a switching element on the lower arm side are connected in series, and drive signals for controlling the pair of switching elements, respectively. A control circuit that outputs a signal, a driver circuit that drives each of the pair of switching elements based on the drive signal, and an overcurrent detection that detects an overcurrent flowing through each of the pair of switching elements and outputs an overcurrent detection signal A failure detection circuit that outputs a failure detection signal when each of the pair of switching elements is short-circuited, and the failure detection circuit is based on the drive signal for each of the pair of switching elements. A delay circuit for outputting a delay signal, based on the overcurrent detection signal and the delay signal; The failure detection signal is output, and at least one of the delay signal change from on to off and the change from off to on of one of the pair of switching elements, and the other switching element At least one of the change from OFF to ON and the change from ON to OFF of the drive signal is synchronized with each other.
The power conversion device according to another aspect of the present invention includes, for a plurality of phases, a switching circuit having a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series, A control circuit that outputs a drive signal for controlling the pair of switching elements of a plurality of phases; a driver circuit that drives the pair of switching elements of the plurality of phases based on the drive signal; An overcurrent detection circuit that detects an overcurrent that flows through each of the pair of switching elements of the phase and outputs an overcurrent detection signal, and the overcurrent detection circuit for any one of the plurality of phases When the overcurrent detection signal is output to one of the pair of switching elements, the control circuit The drive signal for the upper arm side switching element is on, or the drive signal for the upper arm side switching element and the drive signal for the lower arm side switching element of the phase are both off. And when the drive signal for the switching element on the upper arm side of the phase is in the on state immediately before, the switching element on the upper arm side is turned off for all of the plurality of phases. Output the drive signal so as to control the switching element on the lower arm side to the on state, and the driving signal for the switching element on the lower arm side in the phase is on, or The drive signal for the upper arm side switching element and the lower arm side switch of the phase. When both of the drive signals for the switching element are in an off state and the drive signal for the switching element on the lower arm side of the phase is in the on state immediately before, for all of the plurality of phases, The drive signal is output so that the switching element on the upper arm side is controlled to be on and the switching element on the lower arm side is controlled to be off.
The failure detection circuit according to the present invention outputs a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series, and a drive signal for controlling the pair of switching elements. A delay circuit that outputs a delay signal based on the drive signal for each of the pair of switching elements, and the pair of switching elements has an overcurrent. Is detected, based on the delay signal, it is determined which one of the pair of switching elements has a short-circuit fault, and a failure detection signal is output, and one of the pair of switching elements At least one of a change from on to off and a change from off to on of the delayed signal, and the other The at least one change to the off from the change and on from OFF to ON of the drive signal for the switching element, are synchronized with each other.
The drive circuit according to the present invention includes a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series, and a control for outputting a drive signal for controlling the pair of switching elements. A driver circuit that drives each of the pair of switching elements based on the drive signal, and detects an overcurrent that flows through each of the pair of switching elements. An overcurrent detection circuit that outputs an overcurrent detection signal; and a failure detection circuit that outputs a failure detection signal when each of the pair of switching elements is short-circuited, and the failure detection circuit includes the pair of switching elements. A delay circuit that outputs a delay signal based on the drive signal for each of the switching elements; The failure detection signal is output based on the overcurrent detection signal and the delay signal, and the change of the delay signal from ON to OFF and the change from OFF to ON of one of the pair of switching elements is changed. At least one and at least one of the change from OFF to ON and the change from ON to OFF of the drive signal for the other switching element are synchronized with each other.

According to the present invention, when a short-circuit failure occurs in any of the plurality of switching elements, the short-circuit failure location can be specified.

It is the figure which showed the structure of the power converter device and peripheral circuit which concern on one Embodiment of this invention. It is the figure which showed the structure of the drive circuit and its peripheral circuit in the power converter device which concerns on the 1st Embodiment of this invention. It is a figure showing the example of the timing chart of each signal at the time of normal in the power converter device which concerns on the 1st Embodiment of this invention. It is a figure showing the example of the timing chart of each signal at the time of the occurrence of the short circuit fault in the power converter device which concerns on the 1st Embodiment of this invention. It is the figure which showed the flowchart of a failure detection process. It is the figure which showed the structure of the drive circuit and its peripheral circuit in the power converter device which concerns on the 2nd Embodiment of this invention. It is a figure showing the example of the timing chart of each signal at the time of the occurrence of the short circuit fault in the power converter device which concerns on the 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment described below, when a power semiconductor that is a switching element is connected in series by an upper arm and a lower arm, when one of the power semiconductors is short-circuited, the failure location can be specified. The example of a structure is shown.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of a power conversion device 3 and peripheral circuits according to an embodiment of the present invention. A power conversion device 3 shown in FIG. 1 is connected between an external power source 1 and a load 2 and exchanges power input and output between them.

The external power source 1 is a DC power source for driving the load 2 and corresponds to, for example, an in-vehicle battery. The load 2 is a target load to be driven by the power conversion device 3, and examples thereof include a motor, a solenoid, and a transformer for transformation. In the following description, an example in which a three-phase AC motor that is mounted on an electric vehicle such as a hybrid vehicle or an electric vehicle and generates a driving force of the vehicle is used as the load 2 will be described. The same applies to.

The power conversion device 3 includes a control circuit 4, a current sensor 5, and an inverter circuit 6. The inverter circuit 6 includes six power semiconductors 6au, 6bu, 6av, 6bv, 6aw, and 6bw that operate as switching elements, and six drive circuits 7au, 7bu, 7av, 7bv, and 7aw that drive each power semiconductor. , 7 bw. In the present embodiment, the same symbols (au to bw) are added to the end of the reference numerals for power semiconductors and drive circuits that have a corresponding relationship. This also applies to various signals such as drive signals and failure detection signals described later.

In this embodiment, a three-phase AC motor is used as the load 2 as described above. For this reason, the power conversion device 3 includes the power semiconductor and the drive circuit for three phases (6) each of the U phase, the V phase, and the W phase as described above. In the present embodiment, the power semiconductors 6au, 6av, 6aw disposed on the upper side, that is, the high potential side are referred to as upper arm side power semiconductors, and the power semiconductors 6bu disposed on the lower side, that is, the low potential side, 6bv and 6bw are referred to as lower arm side power semiconductors. Similarly, the drive circuits 7au, 7av, and 7aw arranged on the upper side, that is, on the high potential side are referred to as upper arm side drive circuits, and the drive circuits 7bu, 7bv, and 7bw arranged on the lower side, that is, on the low potential side are referred to. This is referred to as a lower arm side drive circuit.

The control circuit 4 is a circuit that performs drive control of the load 2 using the inverter circuit 6, and includes a CPU, a RAM, a ROM, a communication circuit (all not shown), and the like. The ROM mounted on the control circuit 4 may be an electrically rewritable ROM, such as an EEPROM (Electrically Erasable Programmable ROM) or a flash ROM.

The control circuit 4 communicates with an electronic control device (not shown) connected to the outside of the power conversion device 3 and receives a drive command for the load 2. Based on this drive command and the current value obtained from the current sensor 5, drive control of the load 2 is performed. The drive control of the load 2 is performed by outputting drive signals 8au to 8bw from the control circuit 4 to the drive circuits 7au to 7bw of the inverter circuit 6, respectively. That is, the control circuit 4 receives the drive command from the outside, and the upper arm side power semiconductors 6au, 6av, 6aw and the lower arm side which are switching elements provided for each of the U phase, the V phase, and the W phase. Drive signals 8au to 8bw for controlling each of the power semiconductors 6bu, 6bv and 6bw are output.

Further, the control circuit 4 receives the failure detection signals 19au to 19bw output from the drive circuits 7au to 7bw, respectively, and specifies a failure occurrence point based on the failure detection signals 19au to 19bw. Specifically, when any of the failure detection signals 19au to 19bw changes from low indicating normal state to high indicating short-circuit failure, it is determined that a short-circuit failure has occurred in the power semiconductor corresponding to the failure detection signal. . Then, in order to control the inverter circuit 6 corresponding to the specified failure location, the state of the drive signals 8au to 8bw is switched from the normal state. A specific operation at this time will be described later. Further, at this time, the control circuit 4 outputs a failure notification signal to the failure notification device 30 connected to the outside of the power conversion device 3.

The current sensor 5 is a sensor for measuring the current flowing through the load 2. In the present embodiment, a three-phase AC motor is used as the load 2 as described above. Therefore, the current sensor 5 individually measures the current value of each phase and outputs the measured value to the control circuit 4.

The power semiconductors 6au to 6bw function as switching elements by being driven to be switched by the drive circuits 7au to 7bw, respectively. In the inverter circuit 6, the power semiconductors 6 au to 6 bw are switched in response to a drive command, whereby the direct current supplied from the external power supply 1 is converted into a three-phase alternating current and output to the load 2. As the power semiconductors 6au to 6bw, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is used.

Moreover, each of the power semiconductors 6au to 6bw has a sense terminal. From this sense terminal, a constant ratio of the current flowing between the drain and source of the power semiconductor, for example, 1 / 100th or 1 / 1000th of current is output.

The driving circuits 7 au to 7 bw receive the driving signals 8 au to 8 bw output from the control circuit 4, respectively, and switch on / off the corresponding power semiconductors 6 au to 6 bw. The drive circuits 7 au to 7 bw have a failure detection circuit for detecting a short-circuit failure of the corresponding power semiconductors 6 au to 6 bw. When the failure of the power semiconductor is detected, the drive circuits 7 au to 7 bw Failure detection signals 19au to 19bw are output respectively. The details of the drive circuits 7au to 7bw will be described later with reference to FIG.

The failure notification device 30 receives a failure notification signal from the control circuit 4 and notifies the vehicle occupant of the occurrence of the failure. Examples of the failure notification method include a method of lighting a lamp, generating a warning sound, and notifying by voice.

FIG. 2 is a diagram showing a configuration of a drive circuit and its peripheral circuits in the power conversion device 3 according to the first embodiment of the present invention. In FIG. 2, among the power semiconductors 6 au to 6 bw and the drive circuits 7 au to 7 bw for the three phases shown in FIG. 1, the configuration related to the power semiconductors 6 au and 6 bu for one phase (U phase) and the drive circuits 7 au and 7 bu Only a representative example is shown. The configurations of the other two-phase (V-phase, W-phase) power semiconductors 6av, 6bv, 6aw, 6bw and drive circuits 7av, 7bv, 7aw, 7bw are the same as those shown in FIG. Description of is omitted.

As shown in FIG. 2, the drive circuits 7au and 7bu each have a driver circuit 10, an overcurrent detection circuit 11, and a failure detection circuit 16 therein.

The driver circuit 10 controls the gate signal output to the corresponding power semiconductor based on the drive signal output from the control circuit 4. Thereby, on / off of the power semiconductor is switched. In the case of FIG. 2, the driver circuit 10 inside the drive circuit 7au receives the drive signal 8au from the control circuit 4, controls the gate signal 9au, and switches on / off the target power semiconductor 6au. The driver circuit 10 in the drive circuit 7bu receives the drive signal 8bu from the control circuit 4, controls the gate signal 9bu, and switches on / off the target power semiconductor 6bu. In this way, in the drive circuits 7au and 7bu, the driver circuit 10 drives the pair of upper arm side power semiconductors 6au and lower arm side power semiconductors 6bu based on the drive signals 8au and 8bu, respectively.

The overcurrent detection circuit 11 is a circuit that detects an overcurrent flowing through a corresponding power semiconductor and outputs an overcurrent detection signal. The overcurrent detection circuit 11 includes a resistor 12, a reference voltage source 13, and a comparator 14 inside. The overcurrent detection circuit 11 converts the sense current output from the corresponding power semiconductor into a voltage by the resistor 12. The converted voltage and the voltage of the reference voltage source 13 are compared by the comparator 14. As a result, when a large current does not flow through the corresponding power semiconductor, the voltage after conversion by the resistor 12 is lower than the voltage of the reference voltage source 13, and the output of the comparator 14 is low (normal state). At this time, the overcurrent detection signal is not output. On the other hand, when a large current flows through the corresponding power semiconductor and the voltage after conversion by the resistor 12 becomes higher than the voltage of the reference voltage source 13, the overcurrent detection signal output from the comparator 14 becomes high (overcurrent state). Become. As a result, the overcurrent detection circuit 11 detects the occurrence of an overcurrent and outputs an overcurrent detection signal.

In the case of FIG. 2, the overcurrent detection circuit 11 inside the drive circuit 7au notifies whether or not an overcurrent flows through the target power semiconductor 6au by an overcurrent detection signal 15au. The overcurrent detection circuit 11 in the drive circuit 7bu notifies whether or not an overcurrent is flowing through the target power semiconductor 6bu by an overcurrent detection signal 15bu. In this way, in the drive circuits 7au and 7bu, the overcurrent detection circuit 11 detects the overcurrents flowing through the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu, respectively, and overcurrent detection signals 15au and 15bu. Is output.

The failure detection circuit 16 has a delay circuit 17 inside. The delay circuit 17 receives a drive signal output to a corresponding power semiconductor and a drive signal output to a power semiconductor paired with the power semiconductor, and outputs a delay signal based on these drive signals. Details of the method of generating the delay signal will be described later. The failure detection circuit 16 fails when the corresponding power semiconductor is short-circuited based on the delay signal generated by the delay circuit 17 and the overcurrent detection signal output from the overcurrent detection circuit 11 described above. Is detected and a failure detection signal is generated. Specifically, when the delay signal is in a low (off) state and the overcurrent detection signal is high (overcurrent state), it is determined that the corresponding power semiconductor is short-circuited and a failure is detected. Set the signal high (failed state). Then, the failure detection circuit 16 outputs the generated failure detection signal to the control circuit 4.

In the above operation, the failure detection circuit 16 simulates the original on / off state of the corresponding power semiconductor by the delay signal. When an overcurrent detection signal is output from the overcurrent detection circuit 11 when the delay signal is in a low (off) state, that is, when the power semiconductor is supposed to be in an off state, the power semiconductor is Estimated that there is a short circuit failure. Here, when the overcurrent detection signal is output, the pair of upper arm side power semiconductors and the lower arm side power semiconductors are both turned on. Therefore, the fact that the overcurrent detection signal is output even though the delay signal is off means that the target power semiconductor must be off, but it is erroneously turned on due to a short circuit fault. That's what it means. Therefore, in such a case, it can be determined that the target power semiconductor is short-circuited.

In the case of FIG. 2, the failure detection circuit 16 inside the drive circuit 7au is driven by the internal delay circuit 17 to drive the drive signal 8au corresponding to the corresponding upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu which forms a pair therewith. Based on the signal 8bu, the value of the delay signal 18au is determined. Then, using the delay signal 18au and the overcurrent detection signal 15au, the value of the failure detection signal 19au is switched and output to the control circuit 4. Further, the failure detection circuit 16 inside the drive circuit 7bu is provided with a drive signal 8bu for the corresponding lower arm side power semiconductor 6bu and a drive signal 8au for the upper arm side power semiconductor 6au paired therewith by an internal delay circuit 17. Based on the above, the value of the delay signal 18bu is determined. Then, using the delay signal 18bu and the overcurrent detection signal 15bu, the value of the failure detection signal 19bu is switched and output to the control circuit 4. Thus, in the drive circuits 7au and 7bu, the failure detection circuit 16 delays the delay signals 18au and 18bu based on the drive signals 8au and 8bu for each of the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu. The circuit 17 outputs the failure detection signals 19au and 19bu based on the delay signals 18au and 18bu and the overcurrent detection signals 15au and 15bu.

Next, the operation of the power conversion device 3 according to the first embodiment of the present invention will be described with reference to the timing charts of FIGS. 3 and 4 are diagrams respectively showing examples of timing charts of respective signals when the power conversion device 3 according to the first embodiment of the present invention is normal and when a short circuit failure occurs. In FIGS. 3 and 4, only timing charts of signals in the power semiconductors 6au and 6bu and the drive circuits 7au and 7bu for one phase (U phase) shown in FIG. 2 are shown as representative examples. With respect to the other two phases (V phase and W phase), the signal change is the same as in FIGS.

As shown in FIG. 3, for example, the drive signals 8au and 8bu are switched between high (on state) and low (off state) at regular intervals. However, the drive signals 8au and 8bu both have a dead time tdd which is a low (off state) time zone.

When the state of the drive signals 8au and 8bu changes from low (off state) to high (on state), the power semiconductors 6au and 6bu are delayed from the change of the drive signals 8au and 8bu by a delay time tdr, respectively. Change. When the state of the drive signals 8au and 8bu changes from high (on state) to low (off state), the power semiconductors 6au and 6bu are delayed from the change of the drive signals 8au and 8bu by a delay time tdf, respectively. Turn off. As shown in the example of FIG. 3, the delay time tdf is set to be shorter than the dead time tdd in order to avoid the power semiconductors 6au and 6bu being simultaneously turned on.

In this embodiment, the failure detection circuit 16 in the drive circuit 7au outputs the delay signal 18au related to the upper arm side power semiconductor 6au at the timing shown in FIG. 3 based on the drive signals 8au and 8bu by the delay circuit 17. Specifically, the change of the delay signal 18au from low (off state) to high (on state) is caused by the low (off) state of the drive signal 8au output to the upper arm side power semiconductor 6au corresponding to the drive circuit 7au. State) to high (on state). Further, the change of the delay signal 18au from high (on state) to low (off state) indicates that the drive signal 8bu output to the lower arm side power semiconductor 6bu paired with the upper arm side power semiconductor 6au is low ( Synchronize with the change from off to high. In the delay circuit 17 included in the failure detection circuit 16 in the drive circuit 7au, the change timing of the delay signal 18au is determined and output in this way.

Similarly, the failure detection circuit 16 in the drive circuit 7bu outputs a delay signal 18bu related to the lower arm side power semiconductor 6bu at the timing shown in FIG. 3 based on the drive signals 8au and 8bu by the delay circuit 17. Specifically, the change of the delay signal 18bu from low (off state) to high (on state) indicates that the drive signal 8bu output to the lower arm side power semiconductor 6bu corresponding to the drive circuit 7bu is low (off). State) to high (on state). Further, the change of the delay signal 18bu from high (on state) to low (off state) is caused by the low (in the drive signal 8au output to the upper arm side power semiconductor 6au paired with the lower arm side power semiconductor 6bu ( Synchronize with the change from off to high. In the delay circuit 17 included in the failure detection circuit 16 in the drive circuit 7bu, the change timing of the delay signal 18bu is determined and output in this way.

In the case of FIG. 3, the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu are both in a normal state. Therefore, the overcurrent detection signals 15au and 15bu remain low indicating that both are not in an overcurrent state. Therefore, the failure detection signals 19au and 19bu output from the failure detection circuit 16 of the drive circuits 7au and 7bu, respectively, remain low indicating that no short-circuit failure has occurred. That is, in the case of FIG. 3, the failure detection signal indicating the occurrence of a short-circuit failure is not output from the failure detection circuit 16 in any of the drive circuits 7 au and 7 bu.

In this embodiment, the delay signals 18 au and 18 bu output from the delay circuit 17 by the failure detection circuit 16 in the drive circuits 7 au and 7 bu indicate the on / off states of the corresponding power semiconductors 6 au and 6 bu as described above. It is a simulation. Therefore, originally, it is desirable that the delay signals 18au and 18bu accurately simulate the delay times tdr and tdf from the change of the drive signals 8au and 8bu to the change of the states of the power semiconductors 6au and 6bu, respectively. However, in order to accurately simulate the delay times tdr and tdf, it is necessary to provide a plurality of timers inside the delay circuit 17. Further, in a time zone where both the power semiconductors 6au and 6bu are off (period of toff in FIG. 3), even if one of the power semiconductors 6au and 6bu is short-circuited, the other power semiconductor is in the off state. The overcurrent does not flow through the power semiconductors 6au and 6bu, and the overcurrent detection signals 15au and 15bu are not output. Therefore, within the period of toff, even if there is a difference between the timing at which the states of the power semiconductors 6au and 6bu actually change and the timing at which the delay signals 18au and 18bu change, there is an output from the failure detection circuit 16. The timing at which the failure detection signals 19au and 19bu change from low (normal state) to high (failure state) does not change, and the failure location can be specified.

Therefore, in the present embodiment, by utilizing the above, the change of the delay signals 18au and 18bu from off to on is shifted from the timing at which the target power semiconductors 6au and 6bu actually change from off to on. Specifically, for the delay signal 18au related to the power semiconductor 6au on the upper arm side, the drive signal output to the drive circuit 7au corresponding to the power semiconductor 6au at the timing when the delay signal 18au changes from off to on. It is synchronized with the timing when 8 au changes from off to on. Similarly, for the delay signal 18bu related to the power semiconductor 6bu on the lower arm side, the drive signal 8bu output to the drive circuit 7bu corresponding to the power semiconductor 6bu indicates the timing at which the delay signal 18bu changes from off to on. It is synchronized with the timing when it changes from off to on.

Furthermore, the change of the delay signals 18au and 18bu from on to off is also shifted from the timing at which the target power semiconductors 6au and 6bu actually change from on to off. Specifically, for the delay signal 18au related to the power semiconductor 6au on the upper arm side, the timing at which the delay signal 18au changes from on to off corresponds to the power semiconductor 6bu on the lower arm side paired with the power semiconductor 6au. The drive signal 8bu output to the drive circuit 7bu is synchronized with the timing when it changes from on to off. Similarly, for the delay signal 18bu related to the power semiconductor 6bu on the lower arm side, the drive circuit corresponding to the power semiconductor 6au on the upper arm side that is paired with the power semiconductor 6bu at the timing when the delay signal 18bu changes from on to off. The drive signal 8au output to 7au is synchronized with the timing when it changes from on to off.

As described above, in the power conversion device 3 of the present embodiment, the change in the delay signal simulating the switching state of the pair of power semiconductors on the upper arm side and the lower arm side is compared with the change in the drive signal of the arm. Each is synchronized with a change in the arm drive signal. Thereby, the timer in the delay circuit 17 can be deleted, and the delay circuit 17 can be configured only by a simple combination of logic circuits. For example, the delay circuit 17 in the drive circuit 7 au corresponding to the upper arm side power semiconductor 6 au can be realized by using an RS flip-flop having the drive signal 8 au as an S input and the drive signal 8 bu as an R input. Similarly, the delay circuit 17 in the drive circuit 7bu corresponding to the lower arm side power semiconductor 6bu can be realized by using an RS flip-flop having the drive signal 8bu as an S input and the drive signal 8au as an R input. As a result, the scale and area of the delay circuit 17 can be reduced, and the configuration of the power conversion device 3 of the present embodiment can be realized at a lower cost.

In the embodiment described above, the change from OFF to ON and the change from ON to OFF of the delay signals 18au and 18bu are both synchronized with the drive signal 8au or 8bu. However, only one of the timings is selected. May be synchronized with the drive signal 8au or 8bu. When only the change of the delay signal from OFF to ON is synchronized with the drive signal, the timer for simulating the delay time tdr can be reduced. Similarly, when only the change of the delay signal from on to off is synchronized with the drive signal, the timer for simulating the delay time tdf can be reduced. That is, at least one of the change from ON to OFF and the change from OFF to ON of the delay signal for one of the pair of power semiconductors on the upper arm side and the lower arm side, and driving for the other power semiconductor A power conversion device to which the present invention is applied can be realized by synchronizing at least one of a change from OFF to ON of a signal and a change from ON to OFF with each other.

FIG. 4 shows an example of a timing chart when the power semiconductor 6au has a short circuit failure at the timing of time t1. When a short circuit failure occurs in the power semiconductor 6au, both the power semiconductors 6au and 6bu are turned on at time t2 when the power semiconductor 6bu is turned on, and a large current flows through them. As a result, as shown in FIG. 4, the overcurrent detection signals 15au and 15bu both become high (overcurrent state). On the other hand, at time t2, the delay signal 18au is in an off state and the delay signal 18bu is in an on state. Therefore, the failure detection signal 19au becomes high (failure state) at time t2, and the failure detection signal 19bu remains low (normal state). As a result, the failure of the power semiconductor 6au is notified to the control circuit 4 by the failure detection signal 19au.

FIG. 5 shows a flowchart of the failure detection process executed by the control circuit 4. This process is performed in the control circuit 4 when any of the failure detection signals 19au to 19bw becomes high (failure state).

In step S100, the control circuit 4 determines whether any of the failure detection signals 19au, 19av, 19aw related to the upper arm side power semiconductors 6au, 6av, 6aw is high (failure state). If any one is high (failure state), the control circuit 4 determines that any one of the upper arm side power semiconductors 6au, 6av, 6aw has a short-circuit fault, and proceeds to the processing of step S101. On the other hand, when all of the failure detection signals 19au, 19av, 19aw are low (normal state), the control circuit 4 proceeds to the process of step S102.

In step S101, the control circuit 4 controls all the upper arm side power semiconductors 6au, 6av, 6aw to the on state, and controls all the paired lower arm side power semiconductors 6bu, 6bv, 6bw to the off state. The drive signals 8au to 8bw are output to the drive circuits 7au to 7bw, respectively. Specifically, for the drive circuits 7au, 7av, 7aw corresponding to the upper arm side power semiconductors 6au, 6av, 6aw, respectively, the drive signals 8au, 8av, 8aw are all set to high (on state), and the lower arm side For the drive circuits 7bu, 7bv, 7bw corresponding to the power semiconductors 6bu, 6bv, 6bw, all the drive signals 8bu, 8bv, 8bw are set to low (off state). As a result, the upper arm side power semiconductors 6au, 6av, 6aw are all turned on, and the lower arm side power semiconductors 6bu, 6bv, 6bw are all turned off. In this state, the current flowing through the three-phase motor connected to the power conversion device 3 as the load 2 circulates inside the three-phase motor via the upper arm side power semiconductors 6au, 6av, 6aw, so the external power source 1 and the load No power exchange between the two. As a result, the three-phase motor is in a state in which neither power running nor regeneration is performed, and torque output is lost. Therefore, sudden acceleration or sudden deceleration of the three-phase motor due to a short circuit failure can be prevented. After executing the process of step S101, the control circuit 4 proceeds to the process of step S104.

In step S102, the control circuit 4 determines whether one of the failure detection signals 19bu, 19bv, 19bw related to the lower arm side power semiconductors 6bu, 6bv, 6bw is high (failure state). If any one is high (failure state), the control circuit 4 determines that any one of the lower arm side power semiconductors 6bu, 6bv, 6bw has a short-circuit failure, and proceeds to the process of step S103. On the other hand, when all of the failure detection signals 19bu, 19bv, 19bw are low (normal state), the control circuit 4 ends the failure detection process shown in FIG.

In step S103, the control circuit 4 controls all the upper arm side power semiconductors 6au, 6av, 6aw to the off state, and controls all the paired lower arm side power semiconductors 6bu, 6bv, 6bw to the on state. The drive signals 8au to 8bw are output to the drive circuits 7au to 7bw, respectively. Specifically, for the drive circuits 7au, 7av, 7aw corresponding to the upper arm side power semiconductors 6au, 6av, 6aw, respectively, the drive signals 8au, 8av, 8aw are all set to low (off state), and the lower arm side For the drive circuits 7bu, 7bv, and 7bw corresponding to the power semiconductors 6bu, 6bv, and 6bw, all the drive signals 8bu, 8bv, and 8bw are set to high (on state). As a result, the upper arm side power semiconductors 6au, 6av, 6aw are all turned off, and the lower arm side power semiconductors 6bu, 6bv, 6bw are all turned on. Similar to the state described in step S101, in this state, the three-phase motor connected to the power conversion device 3 as the load 2 is in a state where neither power running nor regeneration is performed, and torque output is lost. Sudden acceleration and sudden deceleration can be prevented. After executing the process of step S103, the control circuit 4 proceeds to the process of step S104.

In step S104, the control circuit 4 outputs a failure notification signal to the failure notification device 30. At this time, additional information, for example, information on the location of the power semiconductor in which a short circuit has failed may be transmitted to the failure notification device 30. After the process of step S104 is completed, the control circuit 4 ends the failure detection process shown in FIG.

By executing the failure detection process of FIG. 5 described above, the control circuit 4 can switch the U-phase, V-phase, and W-phase switching circuits, that is, the upper arm side power semiconductors 6au, 6av, 6aw and the lower arm side power. In a circuit configuration in which the semiconductors 6bu, 6bv, 6bw are connected in series in pairs, the overcurrent detection circuit 11 outputs an overcurrent detection signal to any one of the power semiconductors 6au to 6bw for any phase. Then, the following control is performed. That is, the drive signal for the upper arm side power semiconductor of the phase is on, or the drive signal for the upper arm side power semiconductor of the phase and the drive signal for the lower arm side power semiconductor are both off, When the drive signal for the upper arm side power semiconductor of the phase is in the on state immediately before, the upper arm side power semiconductors 6au, 6av, 6aw are controlled to be in the off state for all three phases, and the lower arm side Drive signals 8au to 8bw are output so as to control the power semiconductors 6bu, 6bv, and 6bw to the on state. In addition, the drive signal for the lower arm side power semiconductor of the phase is on, or the drive signal for the upper arm side power semiconductor of the phase and the drive signal for the lower arm side power semiconductor are both off, And when the drive signal for the lower arm side power semiconductor of the phase has been turned on immediately before, the upper arm side power semiconductors 6au, 6av, 6aw are controlled to be turned on and the lower arm side for all three phases. Drive signals 8au to 8bw are output so as to control the power semiconductors 6bu, 6bv, and 6bw to an off state.

As described above, according to the present embodiment, a delay signal is generated using a drive signal, and a short-circuit fault location of a pair of power semiconductors provided in each phase is specified from the delay signal and an overcurrent detection signal. At this time, the change of the delay signal from OFF to ON is synchronized with the change of the drive signal for the target power semiconductor from OFF to ON, and the change of the delay signal from OFF to ON is the change of the drive signal for the paired power semiconductor. Synchronize with changes from off to on. As a result, the delay circuit can be configured on a small scale, and a short-circuit fault location can be determined at a lower cost.

According to the first embodiment of the present invention described above, the following operational effects are obtained.

(1) In the power converter 3, the power semiconductors 6au, 6av, 6aw which are switching elements on the upper arm side and the power semiconductors 6bu, 6bv, 6bw which are switching elements on the lower arm side are respectively connected in series. Inverter circuit 6, control circuit 4 that outputs drive signals 8 au to 8 bw for controlling these power semiconductors 6 au to 6 bw, and power semiconductors 6 au to 6 bw are driven based on the drive signals 8 au to 8 bw, respectively. Driver circuit 10, overcurrent detection circuit 11 for detecting overcurrent flowing through power semiconductors 6au to 6bw and outputting an overcurrent detection signal, and failure detection signal when power semiconductors 6au to 6bw are short-circuited, respectively. And a failure detection circuit 16 that outputs. The failure detection circuit 16 includes a delay circuit 17 that outputs a delay signal based on the drive signals 8au to 8bw for each of the power semiconductors 6au to 6bw, and outputs a failure detection signal based on the overcurrent detection signal and the delay signal. To do. In this power conversion device 3, the change of the delay signal 18 au or 18 bu from one of the pair of upper arm side power semiconductor 6 au and lower arm side power semiconductor 6 bu from on to off, and the change from off to on. At least one and at least one of the change from OFF to ON and the change from ON to OFF of the drive signal 8bu or 8au for the other power semiconductor are synchronized with each other as described with reference to FIG. Since it did in this way, when a short circuit failure generate | occur | produces in either of the power semiconductors 6au-6bw which are several switching elements, a short circuit failure location can be specified.

(2) The failure detection circuit 16 outputs the overcurrent detection signal 15au or 15bu for one power semiconductor of the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu, and the one power semiconductor. When the delay signal 18au or 18bu is in the off state, the failure detection signal 19au or 19bu is output for one power semiconductor. Since it did in this way, when a short circuit fault occurs in any power semiconductor, this can be detected reliably and a failure detection signal can be outputted.

(3) Based on the failure detection signals 19au to 19bw output from the failure detection circuit 16, the control circuit 4 identifies which of the power semiconductors 6au to 6bw has a short circuit failure. Since it did in this way, a short circuit fault location can be specified reliably.

(4) The power conversion device 3 has a plurality of combinations of the upper arm side power semiconductor and the lower arm side power semiconductor. When the control circuit 4 specifies that the power semiconductor on the upper arm side is short-circuited in any of the combinations of power semiconductors, the upper arm side power semiconductors 6au, 6av, 6aw are used for all the power semiconductor combinations. Drive signals 8au to 8bw are output so that the lower arm side power semiconductors 6bu, 6bv and 6bw are controlled to be turned off. In addition, when it is specified that the power semiconductor on the lower arm side is short-circuited in any of the power semiconductor combinations, the upper arm side power semiconductors 6au, 6av, 6aw are turned off for all the power semiconductor combinations. The drive signals 8au to 8bw are output so that the lower arm side power semiconductors 6bu, 6bv and 6bw are controlled to be in the ON state. Since it did in this way, when a three-phase motor is connected to the power converter device 3 as the load 2, it is possible to prevent sudden acceleration and sudden deceleration of the three-phase motor due to a short circuit failure.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the present embodiment, an example of a power conversion device capable of performing a failure detection process at an arbitrary timing is shown.

FIG. 6 is a diagram showing a configuration of a drive circuit and its peripheral circuits in the power conversion device according to the second embodiment of the present invention. In addition, the same code | symbol is provided to the component same as Example 1, and those description is abbreviate | omitted.

The drive circuits 7au and 7bu in FIG. 6 each have a failure detection circuit 16a having a configuration different from that of the failure detection circuit 16 described in the first embodiment. The failure detection circuit 16 a includes a latch circuit 20 in addition to the configuration of the failure detection circuit 16, and the condition for setting the failure detection signal to high (failure state) is different from that of the failure detection circuit 16. Specifically, the failure detection circuit 16a in the drive circuit 7au corresponding to the upper arm side power semiconductor 6au is in a state where the delay signal 18au output from the delay circuit 17 is low (off), and overcurrent detection is performed. When the signal 15au is high (overcurrent state) and when the failure detection signal 19bu from the drive circuit 7bu corresponding to the lower arm side power semiconductor 6bu paired with the upper arm side power semiconductor 6au is low (normal state) The target failure detection signal 19au is set to high (failure state). Similarly, in the failure detection circuit 16a in the drive circuit 7bu corresponding to the lower arm side power semiconductor 6bu, the delay signal 18bu output from the delay circuit 17 is in the low (off) state, and the overcurrent detection signal 15bu. When the failure detection signal 19au from the drive circuit 7au corresponding to the upper arm side power semiconductor 6au paired with the lower arm side power semiconductor 6bu is low (normal state) The failure detection signal 19bu is set to high (failure state). The latch circuit 20 has a role of maintaining high (failure state) when the failure detection signals 19au and 19bu once become high (failure state). The latch circuit 20 outputs a failure detection signal 19au that is output when a reset signal (not shown) from the control circuit 4 is input.
, 19bu are changed from high (failure state) to low (normal state). Thus, when the failure detection circuit 16a outputs the failure detection signal 19au or 19bu for one of the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu, the failure detection signal 19bu for the other power semiconductor. Alternatively, when 19au is not output, the output of the failure detection signal 19au or 19bu is held for one of the power semiconductors.

FIG. 7 is a diagram illustrating an example of a timing chart of each signal when a short circuit fault occurs in the power conversion device according to the second embodiment of the present invention. FIG. 7 also shows an example of a timing chart when the power semiconductor 6au is short-circuited at the timing of time t1, similarly to FIG. 4 described in the first embodiment. In FIG. 7, when both of the overcurrent detection signals 15au and 15bu become high (overcurrent state) and the failure detection signal 19au changes to high (failure state) at time t2, the change in the drive signals 8au and 8bu thereafter occurs. The failure detection signal 19au is maintained high (failure state), and the failure detection signal 19bu is maintained low (normal state).

In this embodiment, the control circuit 4 can perform the failure detection process at an arbitrary timing. For example, as in the first embodiment, it may be performed at the timing when any of the failure detection signals 19au to 19bw becomes high (failure state), or may be performed periodically at regular intervals. good. Since the failure detection process of the control circuit 4 in this embodiment is the same as the content described in the first embodiment, the description thereof is omitted.

In the first embodiment described above, as shown in the timing chart of FIG. 4, when one of the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu is short-circuited, the drive signals 8au and 8bu are turned on / off. With the change of OFF, the failure detection signals 19au and 19bu alternately change between high (failure state) and low (normal state). Therefore, in order to correctly determine which one of the upper arm side power semiconductor 6au and the lower arm side power semiconductor 6bu is short-circuited, the control circuit 4 correctly receives the first of the failure detection signals 19au and 19bu that is output. There is a need. However, depending on the occurrence timing of the short-circuit failure, the time during which the failure detection signal corresponding to the correct failure occurrence location is high (failure state) may be short. Therefore, if the time until the control circuit 4 receives the failure detection signal after the failure detection signal is output becomes longer due to the time taken for other control processing or the like, the failure detection signal output first is correctly received. Otherwise, the control circuit 4 may erroneously determine the failure location. The same applies to the other phases.

On the other hand, in the configuration of the second embodiment, as shown in the timing chart of FIG. 7, the failure detection signal that has previously been high (failure state) is retained, and the paired failure detection signal is high (failure state). ). Therefore, the control circuit 4 can perform the failure detection process at an arbitrary timing, and can prevent the determination error of the failure location.

According to the second embodiment of the present invention described above, the failure detection circuit 16a outputs the failure detection signal 19au or 19bu for one power semiconductor of the pair of upper arm side power semiconductor 6au and lower arm side power semiconductor 6bu. If the failure detection signal 19bu or 19au is not output for the other power semiconductor when it is output, the output of the failure detection signal 19au or 19bu is held for the one power semiconductor. Since it did in this way, it is possible to specify a short circuit failure location without error at arbitrary timings.

In each of the first and second embodiments described above, the

failure detection circuits

16 and 16a are provided inside the drive circuits 7au to 7bw, respectively, but are provided outside the drive circuits 7au to 7bw. Also good. Further, the

failure detection circuits

16 and 16a may be realized by processing executed by the control circuit 4, or may be incorporated in the control circuit 4 as hardware. Further, the overcurrent detection circuit 11 may also be provided outside the drive circuits 7au to 7bw, or may be realized as processing of the control circuit 4 or an internal element.

The present invention is not limited to the above-described embodiments, and includes various modifications. For example, the correspondence between the high / low state of a signal and the state represented by the signal (on state / off state, overcurrent state / normal state, failure state / normal state) may be opposite to the example described in the embodiment. good. The above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment. Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files that realize each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

Each embodiment and various modifications described above are merely examples, and the present invention is not limited to these contents as long as the features of the invention are not impaired. Moreover, although various embodiment and the modification were demonstrated above, this invention is not limited to these content. Other embodiments conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 3 ... Power converter device, 4 ... Control circuit, 6 ... Inverter circuit, 6au-6bw ... Power semiconductor, 7au-7bw ... Drive circuit, 8au-8bw ... Drive signal, 10 ... Driver circuit, 11 ... Overcurrent detection circuit, 15au, 15bu ... Overcurrent detection signal, 16, 16a ... Failure detection circuit, 17 ... Delay circuit, 18au, 18bu ... Delay Signal, 19au to 19bw ... Failure detection signal

Claims

A pair of switching elements in which a switching element on the upper arm side and a switching element on the lower arm side are connected in series;
A control circuit for outputting a drive signal for controlling the pair of switching elements, and
A driver circuit for driving each of the pair of switching elements based on the drive signal;
An overcurrent detection circuit that detects an overcurrent flowing through each of the pair of switching elements and outputs an overcurrent detection signal;
A failure detection circuit that outputs a failure detection signal when each of the pair of switching elements has a short-circuit failure, and
The failure detection circuit includes a delay circuit that outputs a delay signal based on the drive signal for each of the pair of switching elements, and outputs the failure detection signal based on the overcurrent detection signal and the delay signal. And
At least one of a change from ON to OFF of the delay signal for one switching element of the pair of switching elements and a change from OFF to ON, and the driving signal for the other switching element from OFF to ON. The power conversion device is synchronized with at least one of the change and the change from on to off.
The power conversion device according to claim 1,
The failure detection circuit detects the failure of the one switching element when the overcurrent detection signal is output for the one switching element and the delay signal is off for the one switching element. A power converter that outputs signals.
The power conversion device according to claim 2,
The failure detection circuit outputs the failure detection signal for the one switching element when the failure detection signal is not output for the other switching element when the failure detection signal is output for the other switching element. Power converter that holds the output of
In the power converter device as described in any one of Claim 1- Claim 3,
The said control circuit is a power converter device which specifies which switching element among the said pair of switching elements is a short circuit failure based on the said failure detection signal which the said failure detection circuit outputs.
The power conversion device according to claim 4,
A plurality of combinations of the pair of switching elements;
The control circuit includes:
When the switching element on the upper arm side is specified to be short-circuited in any of the combinations, the switching element on the upper arm side is controlled to be turned on for all the combinations, and the lower arm side switching element is controlled. Outputting the drive signal so as to control the switching element to an off state;
If it is specified that the switching element on the lower arm side is short-circuited in any of the combinations, the switching element on the upper arm side is controlled to be in an off state for all the combinations, and the lower arm side switching element is controlled. A power converter that outputs the drive signal so as to control the switching element to be in an ON state.
For a plurality of phases, a switching circuit having a pair of switching elements each having a switching element on the upper arm side and a switching element on the lower arm side connected in series,
A control circuit for outputting drive signals for controlling the pair of switching elements of the plurality of phases,
A driver circuit for driving each of the pair of switching elements of the plurality of phases based on the drive signal;
An overcurrent detection circuit that detects an overcurrent flowing through each of the pair of switching elements of the plurality of phases and outputs an overcurrent detection signal; and
For any one of the plurality of phases, when the overcurrent detection circuit outputs the overcurrent detection signal to any one of the pair of switching elements, the control circuit The drive signal for the arm-side switching element is on, or both the drive signal for the upper-arm switching element and the drive signal for the lower-arm switching element in the phase are off. And when the driving signal for the upper arm side switching element of the phase has been turned on immediately before, the upper arm side switching element is controlled to be turned off for all of the plurality of phases. And outputting the drive signal so as to control the switching element on the lower arm side to the on state,
The driving signal for the switching element on the lower arm side in the phase is in an ON state, or the driving signal for the switching element on the upper arm side in the phase and the driving signal for the switching element on the lower arm side are When both are in an off state and the drive signal for the switching element on the lower arm side of the phase is on state immediately before, the switching element on the upper arm side is turned on for all of the plurality of phases. A power converter that outputs the drive signal so that the lower arm side switching element is controlled to be turned off while being controlled to be turned on.
A power comprising: a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series; and a control circuit that outputs a drive signal for controlling the pair of switching elements. A failure detection circuit used in a converter,
A delay circuit that outputs a delay signal based on the drive signal for each of the pair of switching elements;
When an overcurrent flows through the pair of switching elements, based on the delay signal, it is determined which one of the pair of switching elements has a short circuit fault, and outputs a failure detection signal,
At least one of a change from ON to OFF of the delay signal for one switching element of the pair of switching elements and a change from OFF to ON, and the driving signal for the other switching element from OFF to ON. A fault detection circuit that is synchronized with each other with at least one of the change and the change from on to off.
A power comprising: a pair of switching elements in which an upper arm side switching element and a lower arm side switching element are connected in series; and a control circuit that outputs a drive signal for controlling the pair of switching elements. A drive circuit used in the conversion device,
A driver circuit for driving each of the pair of switching elements based on the drive signal;
An overcurrent detection circuit that detects an overcurrent flowing through each of the pair of switching elements and outputs an overcurrent detection signal;
A failure detection circuit that outputs a failure detection signal when each of the pair of switching elements has a short-circuit failure, and
The failure detection circuit includes a delay circuit that outputs a delay signal based on the drive signal for each of the pair of switching elements, and outputs the failure detection signal based on the overcurrent detection signal and the delay signal. And
At least one of a change from ON to OFF of the delay signal for one switching element of the pair of switching elements and a change from OFF to ON, and the driving signal for the other switching element from OFF to ON. A drive circuit that is synchronized with each other with at least one of the change and the change from on to off.