WO2018214142A1 - 阻变存储器及其制备方法 - Google Patents

阻变存储器及其制备方法 Download PDF

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WO2018214142A1
WO2018214142A1 PCT/CN2017/086084 CN2017086084W WO2018214142A1 WO 2018214142 A1 WO2018214142 A1 WO 2018214142A1 CN 2017086084 W CN2017086084 W CN 2017086084W WO 2018214142 A1 WO2018214142 A1 WO 2018214142A1
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lower electrode
layer
metal
oxide
oxide layer
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French (fr)
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吕杭炳
刘明
龙世兵
刘琦
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to the field of memory, and further relates to a resistive memory, and to a method for preparing a resistive memory.
  • Resistive memory is a new type of non-volatile memory technology.
  • the memory cell has a simple structure, fast operation, low power consumption and stable information. It has a wide range of applications in embedded applications and stand-alone applications.
  • RRAM uses the reversible conversion of material resistivity to achieve the storage of binary information.
  • reliability such as maintaining characteristics and yield, and further improvement is required, and the activation voltage needs to be further reduced.
  • the TaOx-based resistive memory has a programming process similar to the breakdown of a dielectric, and generates an oxygen vacancy chain (ie, a conductive path) inside the Ta 2 O 5 film, but the technique has a high activation voltage and a low switch. The problem.
  • a resistive memory comprising:
  • An oxide layer comprising a lower electrode metal, located above the lower electrode;
  • a resistance conversion layer located above the oxide layer containing the lower electrode metal, wherein the resistance conversion layer material is a nitrogen-containing cerium oxide;
  • intercalation layer over the resistance conversion layer, wherein the intercalation material is a metal or a semiconductor;
  • the upper electrode is located above the intercalation layer.
  • the lower electrode material is tungsten
  • the oxide layer material containing the lower electrode metal is WO x
  • x is between 1 and 3.
  • the oxide layer containing the lower electrode metal has a thickness of between 1 nm and 30 nm.
  • the nitrogen content of the nitrogen-containing niobium oxide is between 0.05% and 30%.
  • the resistance conversion layer has a thickness of between 1 nm and 20 nm.
  • intercalation material is one of the following types of intercalation materials:
  • Ta, TaN, Ti, TiN, Ru or Ir Ta, TaN, Ti, TiN, Ru and Ir two or more metals; metal oxides containing Ta, TaN, Ti, TiN, Ru or Ir; Ta An oxide of two or more metals of TaN, Ti, TiN, Ru and Ir; amorphous silicon; amorphous carbon; or graphene.
  • a method of fabricating a resistive memory memory includes: forming a lower electrode;
  • the resistance conversion layer material is a nitrogen-containing cerium oxide
  • the intercalation material is a metal or a semiconductor
  • An upper electrode is formed over the intercalation layer.
  • the oxide layer containing the lower electrode metal is formed by sputtering or thermal oxidation.
  • the resistance conversion layer is formed by reactive sputtering on a oxide layer containing a lower electrode metal to form a nitrogen-containing tantalum oxide layer; or by thermal oxidation in an oxygen-containing or oxygen plasma atmosphere Forming a nitrogen-containing tantalum oxide layer on the oxide layer containing the lower electrode metal; or forming a nitrogen-containing tantalum oxide on the oxide layer containing the lower electrode metal in an oxygen and nitrogen atmosphere by thermal oxidation Floor.
  • the intercalation material is Ta
  • the intercalation layer has a thickness between 0.1 nm and 10 nm.
  • an oxide layer containing the lower electrode metal By providing an oxide layer containing the lower electrode metal, it can be used as an oxygen storage layer to provide sufficient oxygen during the erasing operation of the memory cell to avoid oxygen depletion and improve device fatigue.
  • the characteristics can also be formed by thermal oxidation to eliminate the gap problem when the tungsten plug is formed by chemical mechanical polishing;
  • a nitrogen-containing niobium oxide resistance transition layer which has a lower activation voltage and a higher switching ratio than Ta 2 O 5 , it can also increase the ability of the oxygen vacancy to control the device resistance, and a small amount of oxygen vacancies.
  • the generation can cause a large change in the resistance of the device, and reduce the activation voltage while increasing the switching ratio;
  • oxygen ions generated during the operation can be preserved on the surface, and the fatigue characteristics of the device can be improved, and the selection of the upper electrode is not limited.
  • FIG. 1 is a schematic structural diagram of a resistive memory according to an embodiment of the present invention.
  • FIG. 2 is a process flow diagram of a method for fabricating a resistive memory according to an embodiment of the present invention.
  • Figure 3 is a schematic view of the structure of the process of Figure 2.
  • 4A and 4B are respectively an equivalent circuit diagram and a cross-sectional view of a memory cell including a resistive memory of an embodiment of the present invention.
  • Figure 5 is a graph of current-voltage of a Ta 2 O 5 based resistive memory.
  • Figure 6 is a graph showing current-voltage of a resistive memory using an embodiment of the present invention.
  • on top of include contact and non-contact with a single or multiple layers.
  • the layers are formed directly or disposed on another layer, and may also mean that one layer is formed indirectly or disposed on another layer, that is, other layers may exist between the two layers.
  • a resistive memory capable of reducing an activation voltage and increasing an activation voltage in a yttrium oxide dielectric layer on the basis of an original metal-dielectric layer-metal (MIM) structure. Switch ratio.
  • FIG. 1 is a schematic structural diagram of a resistive memory according to an embodiment of the present invention. As shown in FIG. 1 , an embodiment of the present invention provides a resistive memory, including:
  • An oxide layer 102 containing a lower electrode metal which is located above the lower electrode 101;
  • a resistance conversion layer 103 which is located on the oxide layer 102 containing the lower electrode metal, wherein the material of the resistance conversion layer 103 is a nitrogen-containing cerium oxide;
  • the intercalation layer 104 is located above the resistance conversion layer 103, wherein the intercalation material is a metal oxide or a conductive carbon material;
  • the upper electrode 105 is located above the intercalation layer 104.
  • the lower electrode 101 it may be formed on a substrate, the substrate may be a semiconductor or a compound semiconductor, the substrate may also be a MOS circuit, and the lower electrode 101 may be electrically connected to the MOS circuit through a plug.
  • the material of the lower electrode 101 includes a metal material, which may be a metal or a metal compound that is inert under an electric field, including but not limited to: tungsten, titanium, titanium nitride, tantalum, tantalum nitride, etc., preferably using tungsten in the embodiment of the present invention.
  • the thickness of the lower electrode 101 can be selected to be 1-100 nm.
  • the oxide layer 102 containing the lower electrode metal is formed on the lower electrode 101.
  • the oxide layer 102 containing the lower electrode metal functions as: an oxygen storage layer, which provides sufficient oxygen during the erasing operation of the memory cell, avoids oxygen depletion, improves fatigue characteristics of the device, and eliminates CMP formation.
  • W plug is the seam problem (ie the middle hole problem).
  • the oxide layer 102 containing the lower electrode metal is determined according to the material of the lower electrode 101. If the material of the electrode 101 is tungsten, the material of the oxide layer 102 containing the lower electrode metal is an oxide of tungsten, and the chemical formula of the oxide containing the tungsten WOx, which may be the chemical composition ratio of WOx completely WO 3, may be completely non-chemical composition ratio of between 1 and 3 x interposed.
  • the thickness of the oxide layer 102 containing the lower electrode metal is between 1 nm and 30 nm, and further preferably, the thickness is between 5 nm and 10 nm.
  • the resistance change layer 103 it is formed on the oxide layer 102 containing the lower electrode metal. It consists in improving the existing ruthenium-based resistance transition layer, and by adding other elements to the ruthenium oxide, it can have a lower activation voltage and a higher switching ratio than Ta 2 O 5 .
  • the embodiment of the present invention provides that the material of the resistance conversion layer 103 is a nitrogen-containing niobium oxide, and the purpose is to increase the activation energy of the O ion on the one hand, and increase the oxygen vacancy amount to the device resistance on the other hand. Regulatory ability.
  • the nitrogen-containing niobium oxide has an added content of nitrogen of 0.05% to 30%, and a further preferable addition content of between 1% and 10%.
  • the thickness of the resistance change layer 103 may be between 1 nm and 20 nm, and more preferably between 3 nm and 10 nm.
  • the intercalation 104 material may be a metal, including but not limited to Ta, TaN, Ti, TiN, Ir, Al or Ru, and may also be a semiconductor material including, but not limited to, metal oxide, amorphous silicon, amorphous carbon or graphite. Alkene.
  • it may be a Ta intercalation layer, and the Ta intercalation layer functions to preserve oxygen ions generated during the surface preservation operation, thereby improving the fatigue characteristics of the device while making the selection of the upper electrode unrestricted.
  • the thickness of the intercalation layer 104 may be between 0.1 nm and 10 nm, and more preferably between 0.5 nm and 5 nm.
  • FIG. 2 is a process flow diagram of a method for preparing a resistive memory according to an embodiment of the present invention. As shown in FIG. 2, in another aspect of the embodiments of the present invention, a method for preparing a resistive memory is further provided, including the steps of:
  • the step of forming a lower electrode may be further included, and the lower electrode may be formed on a substrate, the substrate may be a semiconductor or a compound semiconductor, the substrate may also be a MOS circuit, and the lower electrode may pass through the plug and the MOS The circuit is electrically connected.
  • Embodiments of the invention preferably employ tungsten as the lower electrode.
  • the thickness of the lower electrode can be selected to be 1-100 nm.
  • the lower electrode may be formed by atomic layer deposition, sputtering, vapor phase evaporation or chemical vapor deposition.
  • the material of the lower electrode includes a metal material, which may be a metal or a metal compound inert under an electric field, including but not limited to: tungsten, yttrium oxide, Platinum or gold.
  • FIG. 3 is a schematic structural view of the process of FIG. 2, and an oxide layer 302 containing a lower electrode metal is formed on the lower electrode 301.
  • the oxide layer 302 containing the lower electrode metal is determined according to the material of the lower electrode 301. If the material of the electrode 301 is tungsten, a tungsten oxide is formed on the tungsten of the lower electrode 301.
  • the oxide layer 302 containing the lower electrode metal may be formed by a reactive sputtering process, deposited on the lower electrode, such as WOx, x between 1 and 3, and the WOx may be a complete chemical composition ratio of WO3, or may be incomplete.
  • WOx of chemical composition ratio sputtered tungsten oxide can be sputtered by WO3 alloy target or W metal target reactive sputtering, and the chemical composition ratio can be controlled by adjusting the flow ratio of Ar/O 2 (different sputtering machine corresponding The flow ratio is different, and is not limited herein), the thickness of WOx is 1 nm to 50 nm; or the lower electrode 301 may be oxidized by thermal oxidation in an O-containing atmosphere or O plasma, as listed below.
  • the electrode 301 is made of tungsten as an example.
  • the oxidation temperature is 200 degrees Celsius to 500 degrees Celsius
  • the thickness of the formed WOx is 1 nm to 50 nm.
  • a resistance change layer 303 is formed on the oxide layer 302 containing the lower electrode metal.
  • the embodiment of the present invention provides that the material of the resistance conversion layer 103 is a nitrogen-containing niobium oxide, and the purpose is to increase the activation energy of the O ion on the one hand, and increase the oxygen vacancy amount to the device resistance on the other hand. Regulatory ability.
  • the nitrogen-containing niobium oxide has an added content of nitrogen of 0.05% to 30%, and a further preferable addition content of between 1% and 10%.
  • the thickness of the resistance change layer 303 is between 1 nm and 20 nm, and more preferably between 3 nm and 10 nm.
  • the resistance conversion layer 303 can be formed in the following manner:
  • a nitrogen-containing tantalum oxide layer is formed on the oxide layer 302 containing the lower electrode metal in an oxygen and nitrogen atmosphere by thermal oxidation.
  • TaON resistive material can be deposited on WOx by reactive sputtering.
  • the initial resistance state of the device can be adjusted by the amount of N.
  • the thickness of TaON is 1 nm to 20 nm, and the N/O is 0.01-10.
  • the TaN substrate can be formed by thermal oxidation in an O-containing atmosphere or O plasma, the oxidation temperature is 200 degrees Celsius to 500 degrees Celsius, and the thickness of the TaON is 1 nm to 20 nm;
  • an intercalation layer 304 is formed over the resistance change layer 303, wherein the intercalation material is a metal or a semiconductor.
  • the intercalation material may be a metal such as Ta, TaN, Ti, TiN, Ir, Al, Ru, etc., or may be a semiconductor material such as a metal oxide such as Ta, TaN, Ti, TiN, Ru or Ir. a metal oxide; or an oxide of two or more metals of Ta, TaN, Ti, TiN, Ru and Ir.
  • the intercalation material may also be amorphous silicon, amorphous C, graphene or the like.
  • the metal intercalation layer may have a thickness of 0.1 nm to 10 nm and may be formed by thermal evaporation, sputtering, chemical vapor deposition, pulsed laser deposition, physical transfer, or the like.
  • the oxygen ions generated during the operation can be preserved on the surface to improve the fatigue characteristics of the device, and the selection of the upper electrode is not limited.
  • the thickness of the intercalation layer 304 may be between 0.1 nm and 10 nm, and more preferably between 0.5 nm and 5 nm.
  • step S104 is not limited, and the processes known in the prior art and known materials can be selected for preparation.
  • FIG. 4A and 4B are respectively an equivalent circuit diagram and a cross-sectional view of a memory cell including a resistive memory of an embodiment of the present invention.
  • the memory cell of the resistive memory device prepared by the above method is as shown in FIG. 4B.
  • the structure of the dummy coil is a resistive memory structure, which includes, in order from the bottom, the lower electrode 401, and the metal containing the lower electrode.
  • the lower electrode is tungsten
  • the resistance conversion layer is a nitrogen-containing cerium oxide
  • the intercalation layer is yttrium for specific preparation and experimental testing.
  • the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, the specific embodiments provided are such that the invention will satisfy the applicable legal requirements.
  • Step 1 Forming tungsten oxide on tungsten.
  • the WOx may be a complete chemical composition ratio of WO 3 ; the sputtered tungsten oxide using the WO 3 alloy target sputtering chemical composition ratio can be controlled by adjusting the flow ratio of Ar/O 2 , the thickness is 1 nm to 50 nm;
  • Step 2 Forming a TaON resistance transition layer on the tungsten oxide.
  • the TaON resistive material is deposited on the WOx by reactive sputtering.
  • the initial resistance state of the device is adjusted by the N content.
  • the thickness of the TaON is 1 nm to 20 nm, and the N/O is 0.01-10.
  • Step 3 forming an intercalation material over the TaON resistance transition layer, the intercalation material being metal, Ta, formed by thermal evaporation;
  • Step 4 Forming an upper electrode on the intercalation material.
  • the TaON-based resistive memory prepared by the present invention has an operating voltage. Low, large switching ratio.

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Abstract

一种阻变存储器以及其制备方法，其中阻变存储器包括：下电极(101)；含下电极金属的氧化物层(102)，位于下电极(101)之上；电阻转变层(103)，位于含下电极金属的氧化物层(102)之上，其中，所述电阻转变层(103)材料为含氮的钽氧化物；插层(104)，位于电阻转变层(103)之上，其中所述插层(104)材料为金属或半导体；上电极(105)，位于插层(104)之上。通过设置含氮的钽氧化物电阻转变层(103)，其与Ta 2O 5相比，具有较低的激活电压，高开关比的特点，还可以增加氧空位数量对器件电阻的调控能力。

Description

阻变存储器及其制备方法 技术领域
本发明涉及存储器领域，进一步的涉及一种阻变存储器，还涉及一种阻变存储器的制备方法。
背景技术
阻变存储器(RRAM)是一种新型的不挥发存储器技术，存储单元结构简单、工作速度快、功耗低且信息保持稳定，在嵌入式应用和独立式应用里具有广泛的用途。RRAM利用材料电阻率的可逆转换实现二进制信息的存储。但目前主要在可靠性上还存在若干问题，如保持特性、良率还需进一步提高，而激活电压需要进一步降低。
现有技术中，TaOx基类阻变存储器，其编程过程类似于介质的击穿，在Ta2O5薄膜内部产生氧空位链(即导电通道)，但是该技术存在激活电压高以及开关比较低的问题。
发明内容
有鉴于此，本发明的目的在于提供一种阻变式存储器，以解决以上所述的至少一项技术问题。
根据本发明的一方面，提供一种阻变存储器，包括：
下电极；
含下电极金属的氧化物层，位于下电极之上；
电阻转变层，位于含下电极金属的氧化物层之上，其中，所述电阻转变层材料为含氮的钽氧化物；
插层，位于电阻转变层之上，其中所述插层材料为金属或半导体；
上电极，位于插层之上。
进一步的，所述下电极材料为钨，含下电极金属的氧化物层材料为WOx，x介于1和3之间。
进一步的，所述含下电极金属的氧化物层厚度介于1nm和30nm之间。
进一步的，所述含氮的钽氧化物中氮的原子含量介于0.05％和30％之间。
进一步的，所述电阻转变层厚度介于1nm和20nm之间。
进一步的，所述插层材料为插层材料为以下的一种类型：
Ta，TaN，Ti，TiN，Ru或Ir；Ta，TaN，Ti，TiN，Ru和Ir中两种或两种以上金属；含Ta，TaN，Ti，TiN，Ru或Ir的金属氧化物；Ta，TaN，Ti，TiN，Ru和Ir中两种或两种以上金属的氧化物；非晶硅；非晶碳；或者石墨烯。
根据本发明的另一方面，提供一种阻变存储器的制备方法，包括：形成下电极；
在下电极之上形成含下电极金属的氧化物层；
含下电极金属的氧化物层之上形成电阻转变层，其中，所述电阻转变层材料为含氮的钽氧化物；
在电阻转变层之上形成插层，其中所述插层材料为金属或半导体；
在插层之上形成上电极。
进一步的，通过溅射或者热氧化方式形成所述含下电极金属的氧化物层。
进一步的，所述电阻转变层的形成方式为：通过反应溅射于含下电极金属的氧化物层上形成含氮的钽氧化物层；或者，通过热氧化方式在含氧或氧等离子体氛围中在含下电极金属的氧化物层上形成含氮的钽氧化物层；或者，通过热氧化方式在含氧和氮氛围中于含下电极金属的氧化物层上形成含氮的钽氧化物层。
进一步的，所述插层材料为Ta，插层厚度介于0.1nm和10nm之间。
通过设置含下电极金属的氧化物层，可以作为蓄氧层，在存储单元做擦写操作的时候提供足够的氧，避免氧耗尽的情况，提高器件的疲劳 特性，还可以通过热氧化形成，消除经化学机械研磨形成钨塞时的缝隙问题；
通过设置含氮的钽氧化物电阻转变层，其与Ta2O5相比，具有较低的激活电压，高开关比的特点，还可以增加氧空位数量对器件电阻的调控能力，少量氧空位的产生即可导致器件电阻的大幅度变化，降低激活电压的同时，增加开关比；
通过设置插层，能够在表面保存操作过程中产生的氧离子，提高器件的疲劳特性，同时使上电极的选取不受限制。
附图说明
图1是本发明实施例的阻变存储器结构示意图。
图2是本发明实施例的阻变存储器的制备方法工艺流程图。
图3是图2的工艺过程中结构示意图。
图4A和图4B分别是含本发明实施例的阻变存储器的存储单元等效电路图和截面示意图。
图5是Ta2O5基阻变存储器电流-电压曲线图。
图6是采用本发明实施例的阻变存储器电流-电压曲线图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。在此说明所附附图简化过且做为例示用。附图中所示的各层数量、形状及尺寸可依据实际情况而进行修改，且组件的配置可能更为复杂。本发明中也可进行其他方面的实践或应用，且不偏离本发明所定义的精神及范畴的条件下，可进行各种变化以及调整。
本发明中，“位于…之上”、“在……上形成”、“于……上形成”和“设置在……上”包括与单一或多个层间的接触与非接触。可以表示一 层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还可以存在其它的层。
根据本发明的基本构思，提供一种阻变存储器，该阻变存储器在原有的金属-介质层-金属(MIM)结构基础上，在氧化钽介质层中加入氮元素，能够降低激活电压，提高开关比。
图1是本发明实施例的阻变存储器结构示意图。图1中所示，本发明实施例一方面，提供一种阻变存储器，包括：
下电极101；
含下电极金属的氧化物层102，其位于下电极101之上；
电阻转变层103，其位于含下电极金属的氧化物层102之上，其中，电阻转变层103材料为含氮的钽氧化物；
插层104，位于电阻转变层103之上，其中插层材料为金属氧化物、导电碳材料；
上电极105，位于插层104之上。
其中，对于下电极101，其可以形成于衬底上，衬底可以为半导体或者化合物半导体，衬底还可以为MOS电路，下电极101可以通过插塞与MOS电路电性连接。下电极101的材料包括金属材料，可以为在电场下惰性的金属或金属化合物，包括但不限于：钨、钛、氮化钛、钽、氮化钽、等，本发明实施例优选的采用钨作为下电极。下电极101的厚度可以选择为1-100nm。
其中，对于含下电极金属的氧化物层102，其形成于下电极101上。含下电极金属的氧化物层102作用在于：可以作为蓄氧层，在存储单元做擦写操作的时候提供足够的氧，避免氧耗尽的情况，提高器件的疲劳特性；还可以消除CMP形成W塞是的seam问题(即中间空洞问题)。
含下电极金属的氧化物层102依据下电极101材料确定，如下电极101材料为钨，则该含下电极金属的氧化物层102材料则为钨的氧化物，该含该钨的氧化物化学式WOx，其可以是完全化学组分比的WO3，也可以是非完全化学组分比的WOx，x介于1和3之间。含下电极金属的 氧化物层102的厚度介于1nm和30nm之间，进一步优选的，该厚度介于5nm和10nm之间。
其中，对于电阻转变层103，其形成于含下电极金属的氧化物层102上。其在于对已有的钽基电阻转变层进行改进，可以通过在钽氧化物中加入其它元素，能够相比于Ta2O5，具有较低的激活电压，高开关比的特性。本发明实施例提供所述电阻转变层103材料为含氮的钽氧化物，目的是由于N离子中心存在，一方面可以提高O离子的激活能，另一方面，可以增加氧空位数量对器件电阻的调控能力。
含氮的钽氧化物中，氮的添加含量0.05％～30％，进一步优选的添加含量介于1％～10％之间。
对于电阻转变层103的厚度，可以介于1nm至20nm之间，进一步优选的，介于3nm至10nm之间。
其中，对于插层104，其形成于电阻转变层之上。该插层104材料可以为金属，包括但不限于Ta、TaN、Ti、TiN、Ir、Al或Ru，也可以为半导体材料，包括但不限于金属氧化物，非晶硅，非晶碳或者石墨烯。优选的，可以为Ta插层，Ta插层的作用在于在表面保存操作过程中产生的氧离子，提高器件的疲劳特性，同时使上电极的选取不受限制。
对于插层104的厚度，可以介于0.1nm和10nm之间，进一步优选的，介于0.5nm和5nm之间。
图2是本发明实施例阻变存储器的制备方法工艺流程图。图2中所示，本发明实施例的另一方面，还提供一种阻变存储器的制备方法，包括步骤：
S201：在下电极之上形成含下电极金属的氧化物层；
S202：含下电极金属的氧化物层之上形成电阻转变层，其中，所述电阻转变层材料为含氮的钽氧化物；
S203：在电阻转变层之上形成插层，其中所述插层材料为金属或半导体；
S204：在插层之上形成上电极。
在步骤S201之前，还可包括形成下电极的步骤，而且下电极可以形成于一衬底上，衬底可以为半导体或者化合物半导体，衬底还可以为MOS电路，下电极可以通过插塞与MOS电路电性连接。本发明实施例优选的采用钨作为下电极。下电极的厚度可以选择为1-100nm。可以采用原子层沉积、溅射、气相蒸发或者化学气相沉积工艺形成下电极，下电极的材料包括金属材料，可以为在电场下惰性的金属或金属化合物，包括但不限于：钨、氧化钽、铂或者金。
对于步骤S201，如图2和图3所示，其中图3是图2的工艺过程中结构示意图，在下电极301之上形成含下电极金属的氧化物层302。含下电极金属的氧化物层302依据下电极301材料确定，如下电极301材料为钨，则在下电极301钨上形成钨氧化物。
含下电极金属的氧化物层302形成方式可以采用反应溅射工艺，在下电极上沉积，例如WOx，x介于1和3之间该WOx可以是完全化学组分比的WO3，也可以是非完全化学组分比的WOx；溅射氧化钨可以采用WO3合金靶溅射或者W金属靶反应溅射，化学组分比可以通过调节Ar/O2的流量比来控制(不同的溅射机台对应的流量比不同，此处不受限制)，WOx的厚度为1nm～50nm；或者也可以采用在含O氛围中，或O等离子体中，采用热氧化的方式将下电极301氧化形成，列举下电极301为钨作为实施例，例如氧化温度为200摄氏度～500摄氏度，形成的WOx厚度为1nm～50nm。
对于步骤S202，如图2和图3所示，电阻转变层303形成于含下电极金属的氧化物层302上。本发明实施例提供所述电阻转变层103材料为含氮的钽氧化物，目的是由于N离子中心存在，一方面可以提高O离子的激活能，另一方面，可以增加氧空位数量对器件电阻的调控能力。
含氮的钽氧化物中，氮的添加含量0.05％～30％，进一步优选的添加含量介于1％～10％之间。电阻转变层303的厚度为介于1nm至20nm之间，进一步优选的，介于3nm至10nm之间。
所述电阻转变层303的形成方式可以为：
A：通过反应溅射于含下电极金属的氧化物层302上形成含氮的钽氧化物层；或者，
B：通过热氧化方式在含氧或氧等离子体氛围中在含下电极金属的氧化物层302上形成含氮的钽氧化物层；或者，
C：通过热氧化方式在含氧和氮氛围中于含下电极金属的氧化物层302上形成含氮的钽氧化物层。
以下列举含氮的钨氧化物具体实施例进行说明电阻转变层的形成工艺：
例如，可以采用反应溅射的方式，在WOx上沉积TaON阻变材料，器件初始阻态的大小可以通过调节N含量的多少，TaON的厚度为1nm～20nm，N/O为0.01～10；也可以通过在含O氛围中，或O等离子体中，将TaN基体通过热氧化的方式形成，氧化温度为200摄氏度～500摄氏度，TaON的厚度为1nm～20nm；
还可以通过在含O和N的等离子体氛围中，通过加热的方式将TaN基体或Ta基体热氧化形成氧化温度为200度～500度，TaON的厚度为1nm～20nm。
对于步骤S203，参见图3和图2，在电阻转变层303之上形成插层304，其中插层材料为金属或半导体。
其中，插层材料可以为金属，如Ta、TaN、Ti、TiN、Ir、Al，Ru等，也可以为半导体材料，如金属氧化物，如含Ta，TaN，Ti，TiN，Ru或Ir的金属氧化物；或者是Ta，TaN，Ti，TiN，Ru和Ir中两种或两种以上金属的氧化物。插层材料还可以为非晶硅，非晶C，石墨烯等。
金属插层的厚度可以为0.1nm～10nm，可以通过热蒸发、溅射、化学气相沉积、脉冲激光沉积活着物理转移等方式形成。通过设置Ta插层，能表面保存操作过程中产生的氧离子，提高器件的疲劳特性，同时使上电极的选取不受限制。
对于插层304的厚度，可以介于0.1nm和10nm之间，进一步优选的，介于0.5nm和5nm之间。
由于插层的存在，对于步骤S104中上电极的选择可不受限制，可选择现有技术中已知工艺和已知材料进行制备。
图4A和图4B分别是含本发明实施例的阻变存储器的存储单元等效电路图和截面示意图。通过上述方法所制备的阻变存储器的存储单元如图4B所示，在电路整体结构中，虚线圈内的为阻变存储器结构，由下之上依次包括：下电极401；含下电极金属的氧化物层402，电阻转变层403，插层404，以及上电极105；阻变存储器的等效电路图参见图4A。
以下选取下电极为钨，电阻转变层为含氮的钽氧化物，插层为钽进行具体制备以及实验测试。实际上，本发明可以许多不同形式来实施而不应被解释为限制到下文中所阐述的实施例。相反地，所提供的具体实施例使得本发明将满足适用的法律需求。
实施例1：
制备工艺：
步骤1：在钨上形成钨氧化物。采用反应溅射的方式，该WOx可以是完全化学组分比的WO3；溅射氧化钨采用WO3合金靶溅射化学组分比可以通过调节Ar/O2的流量比来控制，厚度为1nm～50nm；
步骤2：在钨氧化物上形成TaON电阻转变层。采用反应溅射的方式，在WOx上沉积TaON阻变材料，器件初始阻态的大小通过调节N含量的多少，TaON的厚度为1nm～20nm，N/O为0.01～10；
步骤3：在TaON电阻转变层上方形成插层材料，插层材料为金属，Ta，通过热蒸发方式形成；
步骤4：在插层材料上形成上电极。
实验测试：
图6是采用本发明实施例的阻变存储器电流-电压曲线图，相比于图5的Ta2O5基阻变存储器电流-电压曲线，采用本发明制备的TaON基阻变存储器具有操作电压低、开关比大的特点。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种阻变存储器，其特征在于包括：
    下电极；
    含下电极金属的氧化物层，位于下电极之上；
    电阻转变层，位于含下电极金属的氧化物层之上，其中，所述电阻转变层材料为含氮的钽氧化物；
    插层，位于电阻转变层之上，其中所述插层材料为金属或半导体；
    上电极，位于插层之上。
  2. 根据权利要求1所述的阻变存储器，其特征在于，所述下电极材料为钨，含下电极金属的氧化物层材料为WOx，x介于1和3之间。
  3. 根据权利要求1所述的阻变存储器，其特征在于，所述含下电极金属的氧化物层厚度介于1nm和30nm之间。
  4. 根据权利要求1所述的阻变存储器，其特征在于，所述含氮的钽氧化物中氮的原子含量介于0.05％和30％之间。
  5. 根据权利要求1所述的阻变存储器，其特征在于，所述电阻转变层厚度介于1nm和20nm之间。
  6. 根据权利要求1所述的阻变存储器，其特征在于，所述插层材料为以下的一种类型：
    Ta，TaN，Ti，TiN，Ru或Ir；
    Ta，TaN，Ti，TiN，Ru和Ir中两种或两种以上金属；
    含Ta，TaN，Ti，TiN，Ru或Ir的金属氧化物；
    Ta，TaN，Ti，TiN，Ru和Ir中两种或两种以上金属的氧化物；
    非晶硅；
    非晶碳；或者
    石墨烯。
  7. 一种阻变存储器的制备方法，其特征在于，包括：
    形成下电极；
    在下电极之上形成含下电极金属的氧化物层；
    含下电极金属的氧化物层之上形成电阻转变层，其中，所述电阻转变层材料为含氮的钽氧化物；
    在电阻转变层之上形成插层，其中所述插层材料为金属或半导体；
    在插层之上形成上电极。
  8. 根据权利要求7所述的制备方法，其特征在于，通过溅射或者热氧化方式形成所述含下电极金属的氧化物层。
  9. 根据权利要求7所述的制备方法，其特征在于，所述电阻转变层的形成方式为：
    通过反应溅射于含下电极金属的氧化物层上形成含氮的钽氧化物层；
    或者，通过热氧化方式在含氧或氧等离子体氛围中在含下电极金属的氧化物层上形成含氮的钽氧化物层；
    或者，通过热氧化方式在含氧和氮氛围中于含下电极金属的氧化物层上形成含氮的钽氧化物层。
  10. 根据权利要求7所述的制备方法，其特征在于，所述插层材料为Ta，插层厚度介于0.1nm和10nm之间。
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