WO2018210086A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018210086A1
WO2018210086A1 PCT/CN2018/083313 CN2018083313W WO2018210086A1 WO 2018210086 A1 WO2018210086 A1 WO 2018210086A1 CN 2018083313 W CN2018083313 W CN 2018083313W WO 2018210086 A1 WO2018210086 A1 WO 2018210086A1
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Prior art keywords
voltage
node
power supply
circuit
compensation
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PCT/CN2018/083313
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English (en)
French (fr)
Inventor
吴昊
于洪俊
安娜
次刚
郭宝磊
王鑫
王灵国
刘颖
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/095,892 priority Critical patent/US10540926B2/en
Publication of WO2018210086A1 publication Critical patent/WO2018210086A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • Conventional organic light emitting diode displays often display anomalous images during the first frame period after power up. This can be caused by an unstable supply voltage. For example, the power supply voltage can climb from 0V to 4.6V after power-on, which will cause abnormal operation of the pixel circuit, thereby affecting the display effect.
  • a pixel circuit comprising: a light emitting device; a reset circuit configured to reset a first node and a second node in response to a signal on a first scan line being valid; a write circuit Configuring to write a data voltage on the data line to the first node and a transition voltage to the second node in response to the signal on the second scan line being valid, the transition voltage An instantaneous value of a power supply voltage received at a power supply terminal; a compensation circuit configured to selectively transmit an uncompensated reference voltage or a compensated reference voltage to a third node, the compensated reference voltage being Determining an uncompensated reference voltage and a compensation voltage, the compensation voltage being related to a nominal value of the power supply voltage; an illumination control circuit configured to: at a third node in response to a signal valid on the illumination control line a voltage is transmitted to the first node and provides a path through which a drive current flows from the first power supply end through the light emitting device to
  • the compensated reference voltage is equal to a sum of the uncompensated reference voltage and the compensation voltage, and the compensation voltage has a magnitude equal to a nominal value of the power supply voltage.
  • the compensation circuit includes: a first diode having a positive terminal connected to a reference voltage terminal for receiving the uncompensated reference voltage; and a negative electrode connected to the fourth node; a diode having a positive terminal connected to the fourth node and a negative electrode connected to the third node; and a first capacitor having a first end connected to the fourth node and connected to receive the The second end of the compensation voltage end of the compensation voltage.
  • the compensation circuit further includes a second capacitor having a first end coupled to the third node and a second end grounded.
  • the reset circuit includes: a first transistor having a gate connected to the first scan line, a first pole connected to the first power terminal, and being connected to the first a second pole of the node; and a second transistor having a gate connected to the first scan line, a first pole connected to the reset voltage terminal, and a second pole connected to the second node.
  • the driving circuit includes: a driving transistor having a gate connected to the second node, a source connected to the first power terminal, and a drain connected to the light emission control circuit And a third capacitor connected between the first node and the second node.
  • the transition voltage is equal to the instantaneous value of the supply voltage plus a threshold voltage of the drive transistor.
  • the write circuit includes: a third transistor having a gate connected to the second scan line, a first pole connected to the data line, and being connected to the first a second pole of the node; and a fourth transistor having a gate connected to the second scan line, a first pole connected to the drain of the drive transistor, and a second connection to the second node Two poles.
  • the illumination control circuit includes: a fifth transistor having a gate connected to the illumination control line, a first pole connected to the third node, and being connected to the first a second pole of the node; and a sixth transistor having a gate connected to the light emission control line, a first pole connected to the drain of the drive transistor, and a second pole connected to the light emitting device .
  • the light emitting device includes an organic light emitting diode having an anode connected to the second pole of the sixth transistor and a cathode connected to the second power terminal.
  • a method of driving a pixel circuit as described above comprising: resetting the first node and the second node by the reset circuit during a reset phase; a write phase, the write data is written by the write circuit to the first node and the transition voltage is written to the second node; and in the illumination phase, selectively selected by the illumination control circuit Transmitting the voltage at the third node to the first node, the light-emitting control circuit providing the drive current to flow from the first power supply terminal through the light-emitting device to the second The path of the power supply terminal, and the magnitude of the drive current is controlled by the drive circuit based on the voltage at the second node and the supply voltage.
  • a display device comprising: a plurality of scan lines for transmitting scan signals; a plurality of light emission control lines for transmitting light emission control signals; and a plurality of data lines for transmitting a data voltage; and a plurality of pixels arranged in the array.
  • the pixels disposed in the nth row and the mth column include: a light emitting device; a reset circuit configured to respond to the first node and in response to the scan signal on the nth scan line of the scan line being valid The second node performs a reset; the write circuit is configured to respond to the mth data line in the data line in response to the scan signal on the n+1th scan line in the scan line being valid Writing the data voltage to the first node and writing a transition voltage to the second node, the transition voltage being related to an instantaneous value of the power supply voltage received at the first power supply terminal; a compensation circuit, Configuring to selectively transmit an uncompensated reference voltage or a compensated reference voltage to a third node, the compensated reference voltage being determined by the uncompensated reference voltage and a compensation voltage, the compensation voltage Corresponding to a rating of the power supply voltage; an illumination control circuit configured to responsive to the illumination control signal on the nth illumination control line of the illumination control line to be active at the third node Transfer
  • the display device further includes a power source configured to supply the power supply voltage and the uncompensated reference voltage.
  • the power source is further configured to generate the compensation voltage based on the power supply voltage.
  • FIG. 1 is a block diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of an example circuit of the pixel circuit shown in FIG. 1;
  • FIG. 3 is an example timing diagram of an example pixel circuit shown in FIG. 2;
  • FIG. 4 is a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 5 is a block diagram of a power supply in the display device shown in FIG.
  • signal active as used herein in connection with a component of a circuit or circuit means that the signal causes the components of the circuit or circuit to be enabled under the control of the signal.
  • invalid signal means that the signal causes the components of the circuit or circuit to be disabled under the control of the signal. For example, for a P-type transistor, the active signal has a low level and the inactive signal has a high level.
  • FIG. 1 is a block diagram of a pixel circuit 100 in accordance with an embodiment of the present disclosure.
  • the pixel circuit 100 includes a reset circuit 110, a write circuit 120, a drive circuit 130, an illumination control circuit 140, a light emitting device 150, and a compensation circuit 160.
  • Light emitting device 150 is an electroluminescent device, examples of which include, but are not limited to, organic light emitting diodes.
  • the reset circuit 110 is configured to reset the first node P1 and the second node P2 in response to the signal on the first scan line S[n] (not shown in FIG. 1) being active.
  • the write circuit 120 is configured to transmit data on the data line D[m] (not shown in FIG. 1) in response to the signal on the second scan line S[n+1] (not shown in FIG. 1) being active.
  • the voltage V data is written to the first node P1 and the transition voltage V temp is written to the second node P2.
  • the transition voltage V temp is related to the instantaneous value V ELVDD(t) of the power supply voltage V ELVDD received at the first power supply terminal ELVDD (not shown in FIG. 1 ) .
  • the compensation circuit 160 is configured to selectively transmit the uncompensated reference voltage V ref or the compensated reference voltage V ref0 to the third node P3.
  • the compensated reference voltage V ref0 is determined by the uncompensated reference voltage V ref and the compensation voltage V 0 .
  • the compensation voltage V 0 is related to the rated value V ELVDD(t2) of the power supply voltage V ELVDD .
  • the compensation voltage V 0 may have a magnitude equal to the nominal value V ELVDD(t2) of the power supply voltage V ELVDD .
  • V p3 V ref or V ref0
  • the third point P3 of the voltage at the first node P1 to the transmission causes a change in the voltage V p2 of the second point P2.
  • the driving circuit 130 is configured to control the magnitude of the driving current I OLED based on the voltage V p2 at the second node P2 and the power supply voltage V ELVDD .
  • the instantaneous value of the supply voltage V ELVDD can climb from V ELVDD(t1) (eg, as low as 0V) to The nominal value is V ELVDD(t2) (for example, 4.6V).
  • V ELVDD(t1) eg, as low as 0V
  • V ELVDD(t2) for example, 4.6V
  • the voltage V p2 applied to the second node P2 can include the compensation voltage V 0 related to the nominal value V ELVDD(t2) of the power supply voltage V ELVDD .
  • this can eliminate or alleviate the adverse effect of the variation of the instantaneous value V ELVDD(t) of the power supply voltage V ELVDD (from V ELVDD(t1) to V ELVDD(t2) ) to the drive current I OLED .
  • V ELVDD(t1) to V ELVDD(t2) the power supply voltage V ELVDD
  • the compensation circuit 160 applies only the uncompensated reference voltage V ref to the third node P3. At this time, the voltage V p2 does not include the compensation voltage V 0 related to the rated value V ELVDD(t2) of the power supply voltage V ELVDD .
  • the compensation circuit 160 includes a first diode D1, a second diode D2, and a first capacitor C1.
  • the first diode D1 has a positive electrode connected to a reference voltage terminal REF for receiving the uncompensated reference voltage V ref and a negative electrode connected to the fourth node P4.
  • the second diode D2 has a positive electrode connected to the fourth node P4 and a negative electrode connected to the third node P3.
  • the first capacitor C1 has a first terminal connected to a second end connected to and to receive the compensation voltage compensating COMP terminal voltage V 0 of the fourth point P4.
  • the voltage Vp3 at the third node P3 can be controlled by controlling the voltage applied to the compensation voltage terminal COMP.
  • the nominal value V ELVDD(t2) of the supply voltage V ELVDD can be selectively introduced into the voltage V p2 at the second node P2 as will be further described below.
  • the compensation circuit 160 also optionally includes a second capacitor C2 having a first end coupled to the third node P3 and a second end grounded. The presence of the second capacitor C2 contributes to the stabilization of the voltage at the third node P3.
  • the reset circuit 110 includes a first transistor T1 and a second transistor T2.
  • the first transistor T1 has a gate connected to the first scan line S[n], a first pole connected to the first power supply terminal ELVDD, and a second pole connected to the first node P1.
  • the second transistor T2 has a gate connected to the first scan line S[n], a first pole connected to the reset voltage terminal INIT, and a second pole connected to the second node P2.
  • the first node P1 and the second node P2 are reset by the first transistor T1 and the second transistor T2 at respective reset voltages.
  • the drive circuit 130 includes a drive transistor T0 and a third capacitor C3.
  • the driving transistor T0 has a gate connected to the second node P2, a source connected to the first power terminal ELVDD, and a drain connected to the light emission control circuit 140.
  • a third capacitor C3 is connected between the first node P1 and the second node P2. Due to the bootstrap effect of the third capacitor C3, the change in the voltage V p1 of the first point P1 may cause a change in the voltage V p2 of the second point P2.
  • the drive transistor T0 controls the magnitude of the drive current I OLED .
  • the driving current I OLED can be calculated as
  • I OLED K(V gs -V th ) 2 (1)
  • Vgs is the gate-source voltage of the drive transistor T0
  • Vth is the threshold voltage of the drive transistor T0.
  • the write circuit 120 includes a third transistor T3 and a fourth transistor T4.
  • the third transistor T3 has a gate connected to the second scan line S[n+1], a first pole connected to the data line D[m], and a second connected to the first node P1 pole.
  • the fourth transistor T4 has a gate connected to the second scan line S[n+1], a first pole connected to the drain of the driving transistor T0, and a second node connected to the second node P2 The second pole. When the signal on the second scan line S[n+1] is valid, the fourth transistor T4 is turned on so that the driving transistor T0 is in a diode-connected state.
  • transition voltage V temp is written to the second node P2 which is equal to the instantaneous value V ELVDD(t) of the supply voltage V ELVDD plus the threshold voltage V th of the drive transistor.
  • the data voltage V data on the data line D[m] is written to the first node P1 through the third transistor T3.
  • the light emission control circuit 140 includes a fifth transistor T5 and a sixth transistor T6.
  • the fifth transistor T5 has a gate connected to the light emission control line EM[n], a first electrode connected to the third node P3, and a second electrode connected to the first node P1.
  • the sixth transistor T6 has a gate connected to the light emission control line EM[n], a first electrode connected to the drain of the driving transistor T0, and a second electrode connected to the light emitting device 150.
  • the emission control signal line EM [n] is valid, the voltage applied to the third point P3 through the fifth transistor T5 is transmitted to the first node P1, due to change in the voltage V p2 of the second point P2 .
  • the sixth transistor T6 is turned on to form a current path through which the driving current I OLED flows from the first power supply terminal ELVDD through the driving transistor T0 and the light emitting device 150 to the second power supply terminal ELVSS.
  • the light emitting device 150 is an organic light emitting diode (OLED) having an anode connected to the second pole of the sixth transistor T6 and connected to the second power terminal ELVSS Cathode.
  • OLED organic light emitting diode
  • FIG. 3 is an example timing diagram of the example pixel circuit 200 shown in FIG. 2. As shown, pixel circuit 200 undergoes a reset phase, a data write phase, and an illumination phase in one frame period.
  • the first power supply ELVDD at the end of the power supply voltage ELVDD instantaneous values V V ELVDD (t) is equal to the data writing stage at the entire V ELVDD (t1) (e.g., 0V) and climbing at the start of the emission phase To the rated value V ELVDD(t2) (for example, 4.6V).
  • the supply voltage V ELVDD can have a more gradual rising edge and can begin to climb after the illuminating phase begins. This does not affect the validity of the concepts of the present disclosure.
  • the signal on the first scan line S[n] is asserted such that the first transistor T1 and the second transistor T2 are turned on.
  • the first node P1 is reset at V ELVDD(t1) by the turned-on first transistor T1
  • the second node P2 is reset by the turned-on second transistor T2 at the reset voltage V init received via the reset voltage terminal INIT.
  • V p1 V ELVDD(t1)
  • V p2 V init .
  • the signal on the second scan line S[n+1] is active, so that the third transistor T3 and the fourth transistor T4 are turned on.
  • V p1 V data
  • V p2 V ELVDD(t1) +V th .
  • the instantaneous value V ELVDD(t) of the power supply voltage V ELVDD reaches the rated value V ELVDD(t2) , and the compensation voltage terminal COMP is applied with the compensation voltage V 0 equal to the rated value V ELVDD(t2) . Since the bootstrap effect of the first capacitor C1, the third node voltage V p3 P3 is changed to the compensated reference voltage V ref0, which is equal to V 0 + V ref. At the same time, since the signal on the light emission control line EM[n] is valid, the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the drive current I OLED is independent of the supply voltage V ELVDD and is therefore unaffected by the sudden change of the supply voltage V ELVDD . This makes it possible to avoid a splash phenomenon due to a sudden change in the power supply voltage V ELVDD .
  • first to sixth transistors T1 to T6 are illustrated and described as P-type transistors in the above embodiments, N-type transistors are possible.
  • the active signal has a high voltage level and the invalid signal has a low voltage level.
  • the transistors can be, for example, thin film transistors, which are typically fabricated such that their first and second poles can be used interchangeably.
  • FIG. 4 is a block diagram of a display device 400 in accordance with an embodiment of the present disclosure.
  • the display device 400 includes a pixel array 410, a timing controller 420, a first scan driver 430, a second scan driver 440, a data driver 450, and a power source 460.
  • display device 400 can be any product or component having a display function, such as a cell phone, tablet, television, display, notebook, digital photo frame, navigator, and the like.
  • the pixel array 410 includes n x m pixels P (n and m are natural numbers) arranged in the array.
  • the pixel array 410 is connected to n+1 first scan lines S1, S2, . . . , Sn and Sn+1 arranged in the row direction to transmit the first scan signal, n second lines arranged in the row direction to transmit the light emission control signal Scan lines EM1, EM2, ..., EMn, m data lines D1, D2, ..., Dm arranged in the column direction to transfer data voltages, and wires for supplying respective pixels P with the power supply voltage V ELVDD from the power source 460 (not shown).
  • Each of the pixels P may take the form of the pixel circuit 100 or 200 as described above.
  • the timing controller 420 is for controlling the first scan driver 430, the second scan driver 440, and the data driver 450.
  • the timing controller 420 receives input image data RGBD and an input control signal CONT from an external device (eg, a host).
  • the input image data RGBD may include input pixel data for the pixel P.
  • the input control signal CONT may include a main clock signal, a data enable signal, a vertical sync signal, a horizontal sync signal, and the like.
  • the timing controller 420 generates output image data RGBD', a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 based on the input image data RGBD and the input control signal CONT.
  • the output image data RGBD' is supplied to the data driver 450.
  • the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3 are supplied to the first scan driver 430, the second scan driver 440, and the data driver 450, respectively, and the first scan driver 430, the second scan driver 440, and The driving timing of the data driver 450 is controlled based on the first control signal CONT1, the second control signal CONT2, and the third control signal CONT3, respectively.
  • the first and second control signals CONT1 and CONT2 may include a vertical enable signal, a gate clock signal, and the like.
  • the third control signal CONT3 may include a horizontal enable signal, a data clock signal, a data load signal, and the like.
  • the implementation of timing controller 420 can be known.
  • the timing controller 420 can be implemented in a number of ways, such as with dedicated hardware, to perform the various functions discussed above.
  • a "processor” is an example of a timing controller 420 that employs one or more microprocessors that can be programmed using software (eg, microcode) to perform the various functions discussed above.
  • the timing controller 420 can be implemented with or without a processor, and can also be implemented as dedicated hardware that performs some functions and a processor that performs other functions (eg, one or more programmed microprocessors and associated The combination of circuits).
  • the first scan driver 430 generates a plurality of scan signals based on the first control signal CONT1.
  • the first scan driver 430 is connected to the scan lines S[1], S[2], . . . , S[n], S[n+1] to apply the generated scan signals to the pixel array 410.
  • the second scan driver 440 generates a plurality of illumination control signals based on the second control signal CONT2.
  • the second scan driver 440 is connected to the illumination control lines EM[1], EM[2], . . . , EM[n] to apply the generated illumination control signals to the pixel array 410.
  • the data driver 450 receives the third control signal CONT3 and the output image data RGBD' from the timing controller 420, and generates a plurality of data voltages based on the third control signal CONT3 and the output image data RGBD'.
  • the data driver 450 is connected to the data lines D[1], D[2], . . . , D[m] to apply data voltages to the pixel array 410.
  • the power source 460 supplies the pixel array 410 with a power supply voltage V ELVDD and a reference voltage V ref .
  • power supply 460 can also supply power to timing controller 420, first scan driver 430, second scan driver 440, and data driver 450.
  • Examples of power supply 460 include, but are not limited to, a DC/DC converter and a low dropout regulator (LDO).
  • FIG. 5 shows a block diagram of a power supply 460.
  • the power supply 460 in addition to generating the power supply voltage V ELVDD and the reference voltage V ref , the power supply 460 is further configured to generate the compensation voltage V 0 based on the power supply voltage V ELVDD .
  • the power supply 460 includes a voltage generator 462 and a voltage compensator 464.
  • a voltage generator 462 such as a DC/DC converter or LDO, generates a supply voltage V ELVDD and a reference voltage V ref from the input voltage V in .
  • the voltage compensator 464 receives the power supply voltage V ELVDD and generates the compensation voltage V 0 based on the power supply voltage V ELVDD .
  • the voltage compensator 464 includes a Schmitt trigger SCH and a multiplexer MUX.
  • the power supply voltage V ELVDD is supplied to the Schmitt trigger SCH as an input signal.
  • the Schmitt trigger SCH In the process of the instantaneous value V ELVDD(t) of the power supply voltage V ELVDD rising from V ELVDD(t1) to V ELVDD(t2) , when V ELVDD(t) is greater than the forward threshold voltage, the Schmitt trigger SCH
  • the output signal changes from a high level to a low level.
  • the multiplexer MUX In response to the output signal, the multiplexer MUX selectively couples its output terminal to the supply voltage VLVDD or ground.
  • the multiplexer MUX When the output signal of the Schmitt trigger SCH is high, the multiplexer MUX couples its output terminal to the ground voltage; when the output signal of the Schmitt trigger SCH is low, the multiplexer MUX will Its output terminal is coupled to the supply voltage V ELVDD , at which time a compensation voltage V 0 is output at the output terminal of the multiplexer MUX which is substantially equal to the nominal value V ELVDD(t2) of the supply voltage V ELVDD .
  • An output terminal of the multiplexer MUX can be coupled to each of the compensation voltage terminals COMP (FIG.
  • the compensation voltage V 0 is supplied from the output terminal of the multiplexer MUX to the desired pixel row in the pixel array 410 under the control of 420 (Fig. 4).
  • the timing controller 420 may also be further configured to restore the output terminal of the multiplexer MUX to be coupled to ground in response to the illumination control signal on the illumination control line EM connected to the desired pixel row changing from active to inactive. Voltage.
  • the control aspect of the timing controller 420 is beyond the scope of the present disclosure and will not be described in detail herein.
  • the voltage compensator 464 shown in Figure 5 is exemplary and the voltage compensator 464 can take other forms. Other embodiments are also contemplated.
  • the voltage compensator 464 may be a single voltage generator, and which may generate the compensation voltage V 0 provided under the control of the timing controller 420.

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Abstract

一种像素电路（100，200），包括：发光器件（150）、复位电路（110）、写入电路（120）、补偿电路（160）、发光控制电路（140）和驱动电路（130）。补偿电路（160）被配置成选择性地将未经补偿的参考电压或经补偿的参考电压传送到第三节点（P3），经补偿的参考电压由未经补偿的参考电压和补偿电压确定，补偿电压与电源电压的额定值有关。发光控制电路（140）被配置成将第三节点（P3）处的电压传送到第一节点（P1）以便引起第二节点（P2）处的电压的改变。驱动电路（130）被配置成基于第二节点（P2）处的电压和电源电压而控制流过发光器件（150）的驱动电流的量值。

Description

像素电路及其驱动方法、显示装置
相关申请的交叉引用
本申请要求2017年5月15日提交的中国专利申请No.201710338003.X的权益，其全部公开内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、显示装置。
背景技术
传统的有机发光二极管显示器在上电后的第一帧周期里常常显示异常图像。这可以由不稳定的电源电压引起。例如，电源电压可以在上电之后从0V爬升至4.6V，这将造成像素电路的异常工作，从而影响显示效果。
发明内容
根据本公开的一个方面，提供了一种像素电路，包括：发光器件；复位电路，被配置成响应于第一扫描线上的信号有效而对第一节点和第二节点进行复位；写入电路，被配置成响应于第二扫描线上的信号有效而将数据线上的数据电压写入到所述第一节点并且将过渡电压写入到所述第二节点，所述过渡电压与在第一电源端处接收的电源电压的瞬时值有关；补偿电路，被配置成选择性地将未经补偿的参考电压或经补偿的参考电压传送到第三节点，所述经补偿的参考电压由所述未经补偿的参考电压和补偿电压确定，所述补偿电压与所述电源电压的额定值有关；发光控制电路，被配置成响应于发光控制线上的信号有效而将所述第三节点处的电压传送到所述第一节点并且提供驱动电流经由其从所述第一电源端通过所述发光器件流动到第二电源端的路径，所述第三节点处的所述电压到所述第一节点的传送引起所述第二节点处的电压的改变；以及驱动电路，被配置成基于所述第二节点处的所述电压和所述电源电压而控制所述驱动电流的量值。
在一些示例性实施例中，所述经补偿的参考电压等于所述未经补 偿的参考电压与所述补偿电压之和，并且所述补偿电压具有等于所述电源电压的额定值的量值。
在一些示例性实施例中，所述补偿电路包括：第一二极管，具有连接到用以接收所述未经补偿的参考电压的参考电压端的正极以及连接到第四节点的负极；第二二极管，具有连接到所述第四节点的正极以及连接到所述第三节点的负极；和第一电容器，具有连接到所述第四节点的第一端以及连接到用以接收所述补偿电压的补偿电压端的第二端。
在一些示例性实施例中，所述补偿电路还包括第二电容器，其具有连接到所述第三节点的第一端以及被接地的第二端。
在一些示例性实施例中，所述复位电路包括：第一晶体管，具有连接到所述第一扫描线的栅极、连接到所述第一电源端的第一极、以及连接到所述第一节点的第二极；和第二晶体管，具有连接到所述第一扫描线的栅极、连接到复位电压端的第一极、以及连接到所述第二节点的第二极。
在一些示例性实施例中，所述驱动电路包括：驱动晶体管，具有连接到所述第二节点的栅极、连接到所述第一电源端的源极、以及连接到所述发光控制电路的漏极；和第三电容器，连接在所述第一节点和所述第二节点之间。
在一些示例性实施例中，所述过渡电压等于所述电源电压的所述瞬时值加上所述驱动晶体管的阈值电压。
在一些示例性实施例中，所述写入电路包括：第三晶体管，具有连接到所述第二扫描线的栅极、连接到所述数据线的第一极、以及连接到所述第一节点的第二极；和第四晶体管，具有连接到所述第二扫描线的栅极、连接到所述驱动晶体管的所述漏极的第一极、以及连接到所述第二节点的第二极。
在一些示例性实施例中，所述发光控制电路包括：第五晶体管，具有连接到所述发光控制线的栅极、连接到所述第三节点的第一极、以及连接到所述第一节点的第二极；和第六晶体管，具有连接到所述发光控制线的栅极、连接到所述驱动晶体管的所述漏极的第一极、以及连接到所述发光器件的第二极。
在一些示例性实施例中，所述发光器件包括有机发光二极管，其 具有连接到所述第六晶体管的所述第二极的阳极以及连接到所述第二电源端的阴极。
根据本公开的另一方面，提供了一种驱动如上所述的像素电路的方法，包括：在复位阶段，由所述复位电路对所述第一节点和所述第二节点进行复位；在数据写入阶段，由所述写入电路向所述第一节点写入所述数据电压以及向所述第二节点写入所述过渡电压；以及在发光阶段，由所述发光控制电路选择性地将所述第三节点处的所述电压传送到所述第一节点，由所述发光控制电路提供所述驱动电流经由其从所述第一电源端通过所述发光器件流动到所述第二电源端的所述路径，并且由所述驱动电路基于所述第二节点处的所述电压和所述电源电压而控制所述驱动电流的所述量值。
根据本公开的又另一方面，提供了一种显示装置，包括：多条扫描线，用于传送扫描信号；多条发光控制线，用于传送发光控制信号；多条数据线，用于传送数据电压；以及多个像素，布置在阵列中。布置在第n行和第m列的所述像素包括：发光器件；复位电路，被配置成响应于所述扫描线中的第n条扫描线上的所述扫描信号有效而对第一节点和第二节点进行复位；写入电路，被配置成响应于所述扫描线中的第n+1条扫描线上的所述扫描信号有效而将所述数据线中的第m条数据线上的所述数据电压写入到所述第一节点并且将过渡电压写入到所述第二节点，所述过渡电压与在第一电源端处接收的所述电源电压的瞬时值有关；补偿电路，被配置成选择性地将未经补偿的参考电压或经补偿的参考电压传送到第三节点，所述经补偿的参考电压由所述未经补偿的参考电压和补偿电压确定，所述补偿电压与所述电源电压的额定值有关；发光控制电路，被配置成响应于所述发光控制线中的第n条发光控制线上的所述发光控制信号有效而将所述第三节点处的电压传送到所述第一节点并且提供驱动电流经由其从所述第一电源端通过所述发光器件流动到第二电源端的路径，所述第三节点处的所述电压到所述第一节点的传送引起所述第二节点处的电压的改变；以及驱动电路，被配置成基于所述第二节点处的所述电压和所述电源电压而控制所述驱动电流的量值。n和m为正整数。
在一些示例性实施例中，所述显示装置还包括电源，其被配置成供应所述电源电压和所述未经补偿的参考电压。
在一些示例性实施例中，所述电源还被配置成基于所述电源电压生成所述补偿电压。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
图1为根据本公开实施例的一种像素电路的框图；
图2为图1中所示的像素电路的示例电路的示意图；
图3为图2中所示的示例像素电路的示例时序图；
图4为根据本公开实施例的一种显示装置的框图；并且
图5为图4中所示的显示装置中的电源的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件”或“直接耦合到另一个元件”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术 语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
如本文中结合电路或电路的部件使用的短语“信号有效”是指该信号使得该电路或电路的部件在该信号的控制下被启用。相反，短语“信号无效”是指该信号使得该电路或电路的部件在该信号的控制下被禁用。例如，对于P型晶体管，有效信号具有低电平，并且无效信号具有高电平。
为更好地理解本公开的技术方案，下面结合附图对本公开的实施例进行详细描述。
图1为根据本公开实施例的一种像素电路100的框图。如图1所示，该像素电路100包括复位电路110、写入电路120、驱动电路130、发光控制电路140、发光器件150和补偿电路160。
发光器件150为电致发光器件，其示例包括但不限于有机发光二极管。
复位电路110被配置成响应于第一扫描线S[n](图1中未示出)上的信号有效而对第一节点P1和第二节点P2进行复位。
写入电路120被配置成响应于第二扫描线S[n+1](图1中未示出)上的信号有效而将数据线D[m](图1中未示出)上的数据电压V data写入到所述第一节点P1并且将过渡电压V temp写入到所述第二节点P2。如稍后将描述的，所述过渡电压V temp与在第一电源端ELVDD(图1中未示出)处接收的电源电压V ELVDD的瞬时值V ELVDD(t)有关。
补偿电路160被配置成选择性地将未经补偿的参考电压V ref或经补偿的参考电压V ref0传送到第三节点P3。所述经补偿的参考电压V ref0由未经补偿的参考电压V ref和补偿电压V 0确定。所述补偿电压V 0与所述电源电压V ELVDD的额定值V ELVDD(t2)有关。具体地，所述补偿电压V 0可以具有等于所述电源电压V ELVDD的所述额定值V ELVDD(t2)的量值。
发光控制电路140被配置成响应于发光控制线EM[n](图1中未示出)上的信号有效而将所述第三节点P3处的电压V p3(＝V ref或V ref0)传送到所述第一节点P1并且提供驱动电流I OLED经由其从所述第一电 源端ELVDD通过所述发光器件150流动到第二电源端ELVSS(图1中未示出)的路径。如稍后将描述的，所述第三节点P3处的所述电压到所述第一节点P1的传送引起所述第二节点P2处的电压V p2的改变。
驱动电路130被配置成基于所述第二节点P2处的所述电压V p2和所述电源电压V ELVDD而控制所述驱动电流I OLED的量值。
在上电(或掉电并重新上电)之后的第一个帧周期中，电源电压V ELVDD的瞬时值V ELVDD(t)可以从V ELVDD(t1)(例如，低至0V)爬升到所述额定值V ELVDD(t2)(例如，4.6V)。这本来会引起像素电路100的异常工作，因为像素电路100的驱动电路130基于所述第二节点P2处的所述电压V p2和所述电源电压V ELVDD而操作。归因于补偿电路160，施加在第二节点P2的电压V p2能够包含与电源电压V ELVDD的额定值V ELVDD(t2)有关的补偿电压V 0。如稍后将详细描述的，这可以消除或缓解电源电压V ELVDD的瞬时值V ELVDD(t)的变动(从V ELVDD(t1)到V ELVDD(t2))对驱动电流I OLED的不利影响。结果，显示图像中存在的闪屏现象可以被避免。
在电源电压V ELVDD的瞬时值V ELVDD(t)爬升到额定值V ELVDD(t2)之后，经补偿的参考电压V ref0的提供不再必要。因此，所述补偿电路160向所述第三节点P3仅施加所述未经补偿的参考电压V ref。此时，电压V p2不包含与电源电压V ELVDD的额定值V ELVDD(t2)有关的补偿电压V 0。
图2为图1中所示的像素电路100的示例电路200的示意图。如图2所示，所述补偿电路160包括第一二极管D1、第二二极管D2和第一电容器C1。第一二极管D1具有连接到用以接收所述未经补偿的参考电压V ref的参考电压端REF的正极以及连接到第四节点P4的负极。第二二极管D2具有连接到所述第四节点P4的正极以及连接到所述第三节点P3的负极。第一电容器C1具有连接到所述第四节点P4的第一端以及连接到用以接收所述补偿电压V 0的补偿电压端COMP的第二端。借助于第一电容器C1的自举效应，第三节点P3处的电压V p3可以通过控制施加到补偿电压端COMP的电压进行控制。例如，当补偿电压端COMP被施加地电压(例如，0V)时，V p3基本上等于未经补偿的参考电压V ref(忽略二极管D1和D2的导通电压)，并且当补偿电压端COMP被施加补偿电压V 0(＝V ELVDD(t2))时，V p3将从未经补偿的参考电压V ref跳变到经补偿的参考电压V ref0＝V ref+V 0＝V ref+V ELVDD(t2)。这 样，电源电压V ELVDD的额定值V ELVDD(t2)可以被选择性地引入到第二节点P2处的电压V p2中，如下面将进一步描述的。在图2所示的示例中，补偿电路160还可选地包括第二电容器C2，其具有连接到所述第三节点P3的第一端以及被接地的第二端。第二电容器C2的存在有助于第三节点P3处的电压的稳定。
继续图2的示例，复位电路110包括第一晶体管T1和第二晶体管T2。第一晶体管T1具有连接到所述第一扫描线S[n]的栅极、连接到所述第一电源端ELVDD的第一极、以及连接到所述第一节点P1的第二极。第二晶体管T2具有连接到所述第一扫描线S[n]的栅极、连接到复位电压端INIT的第一极、以及连接到所述第二节点P2的第二极。当所述第一扫描线S[n]上的信号有效时，第一节点P1和第二节点P2分别通过第一晶体管T1和第二晶体管T2被复位处于各自的复位电压。
驱动电路130包括驱动晶体管T0和第三电容器C3。驱动晶体管T0具有连接到所述第二节点P2的栅极、连接到所述第一电源端ELVDD的源极、以及连接到所述发光控制电路140的漏极。第三电容器C3连接在所述第一节点P1和所述第二节点P2之间。归因于第三电容器C3的自举效应，第一节点P1处的电压V p1的变化可以引起第二节点P2处的电压V p2的变化。响应于其栅-源电压V gs(＝V p2-V ELVDD(t))，驱动晶体管T0控制驱动电流I OLED的量值。具体地，驱动电流I OLED可以计算为
I OLED＝K(V gs-V th) 2        (1)
其中K典型地可以视为常数，V gs为驱动晶体管T0的栅-源电压，并且V th为驱动晶体管T0的阈值电压。
写入电路120包括第三晶体管T3和第四晶体管T4。第三晶体管T3具有连接到所述第二扫描线S[n+1]的栅极、连接到所述数据线D[m]的第一极、以及连接到所述第一节点P1的第二极。第四晶体管T4具有连接到所述第二扫描线S[n+1]的栅极、连接到所述驱动晶体管T0的所述漏极的第一极、以及连接到所述第二节点P2的第二极。当所述第二扫描线S[n+1]上的信号有效时，第四晶体管T4被打开使得驱动晶体管T0处于二极管连接状态。这样，过渡电压V temp被写入到第二节点 P2，其等于所述电源电压V ELVDD的所述瞬时值V ELVDD(t)加上所述驱动晶体管的阈值电压V th。同时，数据线D[m]上的数据电压V data通过第三晶体管T3被写入到第一节点P1。
发光控制电路140包括第五晶体管T5和第六晶体管T6。第五晶体管T5具有连接到所述发光控制线EM[n]的栅极、连接到所述第三节点P3的第一极、以及连接到所述第一节点P1的第二极。第六晶体管T6具有连接到所述发光控制线EM[n]的栅极、连接到所述驱动晶体管T0的所述漏极的第一极、以及连接到所述发光器件150的第二极。当所述发光控制线EM[n]上的信号有效时，施加在第三节点P3处的电压通过第五晶体管T5被传送到第一节点P1，引起第二节点P2处的电压V p2的变化。而且，第六晶体管T6被打开，形成驱动电流I OLED经由其从第一电源端ELVDD通过驱动晶体管T0和发光器件150流到第二电源端ELVSS的电流路径。
在图2所示的示例中，所述发光器件150为有机发光二极管(OLED)，其具有连接到所述第六晶体管T6的所述第二极的阳极以及连接到所述第二电源端ELVSS的阴极。当驱动电流I OLED流过OLED时，OLED被驱动发光。
图3为图2中所示的示例像素电路200的示例时序图。如所示的，像素电路200在一个帧周期中经历复位阶段、数据写入阶段和发光阶段。不失一般性，假定第一电源端ELVDD处的电源电压V ELVDD的瞬时值V ELVDD(t)在整个数据写入阶段等于V ELVDD(t1)(例如，0V)并且在发光阶段的开始处爬升到额定值V ELVDD(t2)(例如，4.6V)。在实践中，电源电压V ELVDD可以具有更缓和的上升沿并且可以在发光阶段开始之后才开始爬升。这不影响本公开的概念的有效性。
下面通过结合图2和图3对像素电路200的操作进行详细描述。
在复位阶段，第一扫描线S[n]上的信号有效，使得第一晶体管T1和第二晶体管T2导通。第一节点P1通过导通的第一晶体管T1被复位处于V ELVDD(t1)，并且第二节点P2通过导通的第二晶体管T2被复位处于经由复位电压端INIT接收的复位电压V init。换言之，在复位阶段，V p1＝V ELVDD(t1)，并且V p2＝V init。
在数据写入阶段，第二扫描线S[n+1]上的信号有效，使得第三晶体管T3和第四晶体管T4导通。数据线D[m]的上数据电压V data通过导 通的第三晶体管T3被写入第一节点P1，并且过渡电压V temp(＝V ELVDD(t1)+V th)通过导通的第四晶体管T4写入第二节点P2。换言之，在数据写入阶段，V p1＝V data，并且V p2＝V ELVDD(t1)+V th。此外，施加在参考电压端REF的参考电压V ref通过第一和第二二极管D1和D2被传送到第三节点P3，使得第三节点P3处的电压V p3基本上等于参考电压V ref(忽略二极管D1和D2的导通电压)，即V p3＝V ref。
在发光阶段，电源电压V ELVDD的瞬时值V ELVDD(t)达到额定值V ELVDD(t2)，并且补偿电压端COMP被施加有等于额定值V ELVDD(t2)的补偿电压V 0。由于第一电容器C1的自举效应，第三节点P3处的电压V p3变为经补偿的参考电压V ref0，其等于V 0+V ref。同时，由于发光控制线EM[n]上的信号有效，第五晶体管T5和第六晶体管T6导通。第三节点P3处的电压V p3通过导通的第五晶体管T5被传送到第一节点P1，即第一节点P1处的电压V p1从V data变为V 0+V ref。由于第三电容C3的自举效应，第二节点P2处的电压V p2从V ELVDD(t1)+V th变为V ELVDD(t1)+V th+V 0+V ref-V data。此时，驱动晶体管T0的栅-源电压V gs＝V p2-V ELVDD(t2)＝V ELVDD(t1)+V th+V 0+V ref-V data-V ELVDD(t2)。考虑到V ELVDD(t1)＝0，并且V 0＝V ELVDD(t2)，从等式(1)可以推导出
I OLED＝K(V gs-V th) 2＝K(V ELVDD(t1)+V th+V 0+V ref-V data-V ELVDD(t2)-V th) 2＝K(V ELVDD(t1)+V th+V ELVDD(t2)+V ref-V data-V ELVDD(t2)-V th) 2＝K(V ref-V data) 2
可以看到，驱动电流I OLED与电源电压V ELVDD无关，并且因此不受电源电压V ELVDD的突变的影响。这使得避免由于电源电压V ELVDD的突变所致的闪屏现象成为可能。
在该实施例中，补偿电压V 0(＝V ELVDD(t2))可以贯穿发光阶段而被保持施加在补偿电压端COMP，使得驱动电流I OLED在整个发光阶段内不受电源电压V ELVDD的突变的影响。而后，由于电源电压V ELVDD的瞬时值V ELVDD(t1)被稳定在额定值V ELVDD(t2)，所以不再需要补偿电压V 0。因此，补偿电压端COMP在发光阶段结束之后恢复为施加地电压(例如，0V)。于是，在下一个帧周期中，施加到第三节点P3的电压将为 未经补偿的参考电压V ref，并且像素电路200正常地操作而不针对电源电压V ELVDD的突变进行补偿。
虽然在上面的实施例中第一到第六晶体管T1～T6被图示和描述为P型晶体管，但是N型晶体管是可能的。在N型晶体管的情况下，有效信号具有高电压水平，并且无效信号具有低电压水平。各晶体管可以例如为薄膜晶体管，其典型地被制作为使得它们的第一极和第二极能够可互换地使用。
图4为根据本公开实施例的一种显示装置400的框图。参考图4，该显示装置400包括像素阵列410、时序控制器420、第一扫描驱动器430、第二扫描驱动器440、数据驱动器450和电源460。作为示例而非限制，显示装置400可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
像素阵列410包括布置在阵列中的n×m个像素P(n和m是自然数)。像素阵列410连接到在行方向上布置以传送第一扫描信号的n+1条第一扫描线S1，S2，…，Sn和Sn+1、在行方向上布置以传送发光控制信号的n条第二扫描线EM1，EM2，…，EMn、在列方向上布置以传送数据电压的m条数据线D1，D2，…，Dm、以及用于向各个像素P供应来自电源460的电源电压V ELVDD的电线(未示出)。像素P中的每一个可以采取如上所述的像素电路100或200的形式。
时序控制器420用于控制第一扫描驱动器430、第二扫描驱动器440、和数据驱动器450。时序控制器420从外部设备(例如，主机)接收输入图像数据RGBD和输入控制信号CONT。输入图像数据RGBD可包括用于像素P的输入像素数据。输入控制信号CONT可包括主时钟信号、数据使能信号、垂直同步信号、水平同步信号等。时序控制器420基于输入图像数据RGBD和输入控制信号CONT生成输出图像数据RGBD’、第一控制信号CONT1、第二控制信号CONT2和第三控制信号CONT3。输出图像数据RGBD’被提供给数据驱动器450。第一控制信号CONT1、第二控制信号CONT2和第三控制信号CONT3被分别提供给第一扫描驱动器430、第二扫描驱动器440和数据驱动器450，并且第一扫描驱动器430、第二扫描驱动器440和数据驱动器450的驱动时序分别基于第一控制信号CONT1、第二控制信号CONT2和第三控制信号CONT3而被控制。第一和第二控制信号CONT1和CONT2 可包括垂直启动信号、栅极时钟信号等。第三控制信号CONT3可包括水平启动信号、数据时钟信号、数据负载信号等。时序控制器420的实现方式可以是已知的。时序控制器420可以以许多方式(诸如用专用硬件)实现以执行上面所讨论的各种功能。“处理器”是时序控制器420的一个示例，其采用可以使用软件(例如微代码)编程以执行上面所讨论的各种功能的一个或多个微处理器。时序控制器420可以在采用或不采用处理器的情况下来实现，并且也可以实现为执行一些功能的专用硬件和执行其它功能的处理器(例如，一个或多个编程的微处理器和相关联的电路)的组合。
第一扫描驱动器430基于第一控制信号CONT1生成多个扫描信号。第一扫描驱动器430连接至扫描线S[1]，S[2]，…，S[n]，S[n+1]以将生成的扫描信号施加至像素阵列410。
第二扫描驱动器440基于第二控制信号CONT2生成多个发光控制信号。第二扫描驱动器440连接至发光控制线EM[1]，EM[2]，...，EM[n]以将生成的发光控制信号施加至像素阵列410。
数据驱动器450从时序控制器420接收第三控制信号CONT3和输出图像数据RGBD’，并且基于第三控制信号CONT3和输出图像数据RGBD’生成多个数据电压。数据驱动器450连接至数据线D[1]，D[2]，...，D[m]以将数据电压施加至像素阵列410。
电源460向像素阵列410供应电源电压V ELVDD和参考电压V ref。在一些实施例中，电源460还可以向时序控制器420、第一扫描驱动器430、第二扫描驱动器440和数据驱动器450供应电力。电源460的示例包括但不限于DC/DC转换器和低压差稳压器(LDO)。
图5示出了电源460的框图。在该实施例中，除了生成电源电压V ELVDD和参考电压V ref之外，电源460还被配置成基于所述电源电压V ELVDD生成所述补偿电压V 0。参考图5，电源460包括电压生成器462和电压补偿器464。
电压生成器462，例如DC/DC转换器或LDO，从输入电压V in生成电源电压V ELVDD和参考电压V ref。
电压补偿器464接收电源电压V ELVDD，并且基于所述电源电压V ELVDD生成所述补偿电压V 0。具体地，电压补偿器464包括施密特触发器SCH和多路选择器MUX。电源电压V ELVDD被供应给施密特触发 器SCH作为输入信号。在电源电压V ELVDD的瞬时值V ELVDD(t)从V ELVDD(t1)爬升至V ELVDD(t2)的过程中，当V ELVDD(t)大于正向阈值电压时，施密特触发器SCH的输出信号而从高电平改变为低电平。响应于该输出信号，多路选择器MUX选择性地将其输出端子耦合到电源电压V ELVDD或者地电压。当施密特触发器SCH的输出信号为高电平时，多路选择器MUX将其输出端子耦合到地电压；当施密特触发器SCH的输出信号为低电平时，多路选择器MUX将其输出端子耦合到电源电压V ELVDD，此时在多路选择器MUX的输出端子处输出补偿电压V 0，其基本上等于电源电压V ELVDD的额定值V ELVDD(t2)。多路选择器MUX的输出端子可以通过开关网络(未示出)耦合到像素阵列410(图4)中的各行像素的各补偿电压端COMP(图2)，所述开关网络可以在时序控制器420(图4)的控制下将补偿电压V 0从多路选择器MUX的输出端子供应给像素阵列410中的期望的像素行。时序控制器420还可以还被配置成响应于连接到该期望的像素行的发光控制线EM上的发光控制信号从有效跳变为无效而将多路选择器MUX的输出端子恢复为耦合到地电压。时序控制器420的控制方面超出了本公开的范围，并且在此不进行详细描述。
图5中所示的电压补偿器464是示例性的，并且电压补偿器464可以采取其他形式。还设想了其他实施例。例如，电压补偿器464可以是一个单独的电压生成器，其可以在时序控制器420的控制下生成和提供所述补偿电压V 0。
可以理解的是，以上实施例仅仅是为了说明的目的而被公开，并且本公开并不局限于此。本领域内的普通技术人员可以对所公开的实施例做出各种变型和改进而不脱离本公开的范围。因此，这些变型和改进也落入本公开的保护范围。

Claims (17)

  1. 一种像素电路，包括：
    发光器件；
    复位电路，被配置成响应于第一扫描线上的信号有效而对第一节点和第二节点进行复位；
    写入电路，被配置成响应于第二扫描线上的信号有效而将数据线上的数据电压写入到所述第一节点并且将过渡电压写入到所述第二节点，所述过渡电压与在第一电源端处接收的电源电压的瞬时值有关；
    补偿电路，被配置成选择性地将未经补偿的参考电压或经补偿的参考电压传送到第三节点，所述经补偿的参考电压由所述未经补偿的参考电压和补偿电压确定，所述补偿电压与所述电源电压的额定值有关；
    发光控制电路，被配置成响应于发光控制线上的信号有效而将所述第三节点处的电压传送到所述第一节点并且提供驱动电流经由其从所述第一电源端通过所述发光器件流动到第二电源端的路径，所述第三节点处的所述电压到所述第一节点的传送引起所述第二节点处的电压的改变；以及
    驱动电路，被配置成基于所述第二节点处的所述电压和所述电源电压而控制所述驱动电流的量值。
  2. 根据权利要求1所述的像素电路，其中所述经补偿的参考电压等于所述未经补偿的参考电压与所述补偿电压之和，并且其中所述补偿电压具有等于所述电源电压的所述额定值的量值。
  3. 根据权利要求2所述的像素电路，其中所述补偿电路包括：
    第一二极管，具有连接到用以接收所述未经补偿的参考电压的参考电压端的正极以及连接到第四节点的负极；
    第二二极管，具有连接到所述第四节点的正极以及连接到所述第三节点的负极；和
    第一电容器，具有连接到所述第四节点的第一端以及连接到用以接收所述补偿电压的补偿电压端的第二端。
  4. 根据权利要求3所述的像素电路，其中所述补偿电路还包括第二电容器，其具有连接到所述第三节点的第一端以及被接地的第二端。
  5. 根据权利要求1所述的像素电路，其中所述复位电路包括：
    第一晶体管，具有连接到所述第一扫描线的栅极、连接到所述第一电源端的第一极、以及连接到所述第一节点的第二极；和
    第二晶体管，具有连接到所述第一扫描线的栅极、连接到复位电压端的第一极、以及连接到所述第二节点的第二极。
  6. 根据权利要求1所述的像素电路，其中所述驱动电路包括：
    驱动晶体管，具有连接到所述第二节点的栅极、连接到所述第一电源端的源极、以及连接到所述发光控制电路的漏极；和
    第三电容器，连接在所述第一节点和所述第二节点之间。
  7. 根据权利要求6所述的像素电路，其中所述过渡电压等于所述电源电压的所述瞬时值加上所述驱动晶体管的阈值电压。
  8. 根据权利要求6所述的像素电路，其中所述写入电路包括：
    第三晶体管，具有连接到所述第二扫描线的栅极、连接到所述数据线的第一极、以及连接到所述第一节点的第二极；和
    第四晶体管，具有连接到所述第二扫描线的栅极、连接到所述驱动晶体管的所述漏极的第一极、以及连接到所述第二节点的第二极。
  9. 根据权利要求6所述的像素电路，其中所述发光控制电路包括：
    第五晶体管，具有连接到所述发光控制线的栅极、连接到所述第三节点的第一极、以及连接到所述第一节点的第二极；和
    第六晶体管，具有连接到所述发光控制线的栅极、连接到所述驱动晶体管的所述漏极的第一极、以及连接到所述发光器件的第二极。
  10. 根据权利要求9所述的像素电路，其中所述发光器件包括有机发光二极管，其具有连接到所述第六晶体管的所述第二极的阳极以及连接到所述第二电源端的阴极。
  11. 一种驱动根据权利要求1至10中任一项所述的像素电路的方法，包括：
    在复位阶段，由所述复位电路对所述第一节点和所述第二节点进行复位；
    在数据写入阶段，由所述写入电路向所述第一节点写入所述数据电压以及向所述第二节点写入所述过渡电压；以及
    在发光阶段，由所述发光控制电路选择性地将所述第三节点处的所述电压传送到所述第一节点，由所述发光控制电路提供所述驱动电 流经由其从所述第一电源端通过所述发光器件流动到所述第二电源端的所述路径，并且由所述驱动电路基于所述第二节点处的所述电压和所述电源电压而控制所述驱动电流的所述量值。
  12. 一种显示装置，包括：
    多条扫描线，用于传送扫描信号；
    多条发光控制线，用于传送发光控制信号；
    多条数据线，用于传送数据电压；以及
    多个像素，布置在阵列中，其中布置在第n行和第m列的所述像素包括：
    发光器件；
    复位电路，被配置成响应于所述扫描线中的第n条扫描线上的所述扫描信号有效而对第一节点和第二节点进行复位；
    写入电路，被配置成响应于所述扫描线中的第n+1条扫描线上的所述扫描信号有效而将所述数据线中的第m条数据线上的所述数据电压写入到所述第一节点并且将过渡电压写入到所述第二节点，所述过渡电压与在第一电源端处接收的所述电源电压的瞬时值有关；
    补偿电路，被配置成选择性地将未经补偿的参考电压或经补偿的参考电压传送到第三节点，所述经补偿的参考电压由所述未经补偿的参考电压和补偿电压确定，所述补偿电压与所述电源电压的额定值有关；
    发光控制电路，被配置成响应于所述发光控制线中的第n条发光控制线上的所述发光控制信号有效而将所述第三节点处的电压传送到所述第一节点并且提供驱动电流经由其从所述第一电源端通过所述发光器件流动到第二电源端的路径，所述第三节点处的所述电压到所述第一节点的传送引起所述第二节点处的电压的改变；以及
    驱动电路，被配置成基于所述第二节点处的所述电压和所述电源电压而控制所述驱动电流的量值，并且
    其中，n和m为正整数。
  13. 根据权利要求12所述的显示装置，其中所述经补偿的参考电压等于所述未经补偿的参考电压与所述补偿电压之和，并且其中所述补偿电压具有等于所述电源电压的额定值的量值。
  14. 根据权利要求13所述的显示装置，其中所述补偿电路包括：
    第一二极管，具有连接到用以接收所述未经补偿的参考电压的参考电压端的正极以及连接到第四节点的负极；
    第二二极管，具有连接到所述第四节点的正极以及连接到所述第三节点的负极；和
    第一电容器，具有连接到所述第四节点的第一端以及连接到用以接收所述补偿电压的补偿电压端的第二端。
  15. 根据权利要求14所述的显示装置，其中所述补偿电路还包括第二电容器，其具有连接到所述第三节点的第一端以及被接地的第二端。
  16. 根据权利要求12所述的显示装置，还包括电源，其被配置成供应所述电源电压和所述未经补偿的参考电压。
  17. 根据权利要求16所述的显示装置，其中所述电源还被配置成基于所述电源电压生成所述补偿电压。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107103877B (zh) * 2017-05-15 2019-06-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN108538252B (zh) 2018-04-13 2020-03-27 京东方科技集团股份有限公司 一种电压补偿方法、装置、显示设备及计算可读存储介质
CN108766361A (zh) * 2018-05-31 2018-11-06 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN109636793A (zh) * 2018-12-14 2019-04-16 中航华东光电（上海）有限公司 显示器的检测系统及其检测方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150064544A (ko) * 2013-12-03 2015-06-11 엘지디스플레이 주식회사 유기 발광 다이오드 표시장치 및 그 구동 방법
US20150187270A1 (en) * 2013-12-27 2015-07-02 Samsung Display Co., Ltd. Display device and method for driving the same
CN104867448A (zh) * 2015-04-02 2015-08-26 友达光电股份有限公司 主动式有机发光二极管电路及其驱动方法
CN105976758A (zh) * 2014-06-04 2016-09-28 上海天马有机发光显示技术有限公司 一种有机发光显示器的像素补偿电路及方法
CN106448557A (zh) * 2016-12-26 2017-02-22 深圳市华星光电技术有限公司 发光驱动电路及有机发光显示器
CN106652903A (zh) * 2017-03-03 2017-05-10 京东方科技集团股份有限公司 一种oled像素电路及其驱动方法、显示装置
CN107103877A (zh) * 2017-05-15 2017-08-29 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011203388A (ja) * 2010-03-24 2011-10-13 Toshiba Mobile Display Co Ltd 有機ｅｌ表示装置及び有機ｅｌ表示方法
KR102006382B1 (ko) * 2013-04-17 2019-08-02 삼성디스플레이 주식회사 화소, 이를 포함하는 표시장치 및 그 구동 방법
KR102185361B1 (ko) * 2014-04-04 2020-12-02 삼성디스플레이 주식회사 화소 및 상기 화소를 포함하는 유기발광 표시장치
JP2016061936A (ja) * 2014-09-18 2016-04-25 株式会社ジャパンディスプレイ 表示装置、及びその駆動方法
CN105185304B (zh) * 2015-09-09 2017-09-22 京东方科技集团股份有限公司 一种像素电路、有机电致发光显示面板及显示装置
CN105405396B (zh) * 2016-01-11 2017-11-10 京东方科技集团股份有限公司 一种有机发光二极管的驱动方法、驱动电路和显示装置
CN105702211B (zh) * 2016-04-29 2018-04-06 京东方科技集团股份有限公司 像素电路及像素电路的驱动方法、显示装置
CN108305587A (zh) * 2017-01-11 2018-07-20 群创光电股份有限公司 显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150064544A (ko) * 2013-12-03 2015-06-11 엘지디스플레이 주식회사 유기 발광 다이오드 표시장치 및 그 구동 방법
US20150187270A1 (en) * 2013-12-27 2015-07-02 Samsung Display Co., Ltd. Display device and method for driving the same
CN105976758A (zh) * 2014-06-04 2016-09-28 上海天马有机发光显示技术有限公司 一种有机发光显示器的像素补偿电路及方法
CN104867448A (zh) * 2015-04-02 2015-08-26 友达光电股份有限公司 主动式有机发光二极管电路及其驱动方法
CN106448557A (zh) * 2016-12-26 2017-02-22 深圳市华星光电技术有限公司 发光驱动电路及有机发光显示器
CN106652903A (zh) * 2017-03-03 2017-05-10 京东方科技集团股份有限公司 一种oled像素电路及其驱动方法、显示装置
CN107103877A (zh) * 2017-05-15 2017-08-29 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置

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