WO2018205533A1 - 电路结构及其驱动方法、神经网络 - Google Patents

电路结构及其驱动方法、神经网络 Download PDF

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WO2018205533A1
WO2018205533A1 PCT/CN2017/110871 CN2017110871W WO2018205533A1 WO 2018205533 A1 WO2018205533 A1 WO 2018205533A1 CN 2017110871 W CN2017110871 W CN 2017110871W WO 2018205533 A1 WO2018205533 A1 WO 2018205533A1
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resistance
devices
circuit structure
resistive
voltage
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PCT/CN2017/110871
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English (en)
French (fr)
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李辛毅
吴华强
宋森
张清天
高滨
钱鹤
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清华大学
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Priority to US16/071,985 priority Critical patent/US11468300B2/en
Publication of WO2018205533A1 publication Critical patent/WO2018205533A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means

Definitions

  • Embodiments of the present disclosure relate to a circuit structure, a driving method thereof, and a neural network.
  • the function of the neuron-like elements needs to be realized through circuit design. Due to the limitation of hardware resources, the electronic devices of the neuron-like elements have high energy consumption and cannot handle complex tasks, and thus limit the brain-like computing system. development of.
  • At least one embodiment of the present disclosure provides a circuit structure, a driving method thereof, and a neural network.
  • the circuit structure uses a resistance grading device and a resistance mutation device to be connected in series to form a neuron-like structure, so as to simulate the calculation, integral emission, attenuation and filtering of human brain neurons.
  • the resistance of a resistive graded device changes slowly under applied voltage and can be used to simulate the behavior of a biological dendritic S-type growth curve.
  • the circuit structure has the advantages of simple structure, low power consumption, small area, complex functions, and compatibility with standard CMOS processes.
  • At least one embodiment of the present disclosure provides a circuit structure including: at least one circuit unit, each circuit unit includes a first set of resistive devices and a second set of resistive devices, and the first set of resistive devices includes a resistance grading device
  • the second group of resistive devices includes a resistance mutation device, the first group of resistive devices and the second group of resistive devices are connected in series, and the resistance of the first group of resistive devices is greater than that of the second group without voltage application. Resistance change The resistance of the device.
  • the resistance gradation device has a first resistance value
  • the resistance value abrupt device has a second resistance value
  • the first resistance value ranges from 1-100 megohms
  • the second resistance range is 1-1000 kohms.
  • the resistance grading device includes a stacked first oxide layer and a second oxide layer, and the first oxide layer has an oxygen content higher than that of the second oxide layer Oxygen content.
  • the material of the first oxide layer is tantalum pentoxide or aluminum oxide
  • the material of the second oxide layer is germanium dioxide
  • the resistance gradation device further includes a first electrode layer and a second electrode layer, and the first oxide layer and the second oxide layer are disposed on the first electrode layer and Between the two electrode layers, the first electrode layer is electrically connected to the first oxide layer, and the second electrode layer is electrically connected to the second oxide layer.
  • the material of the first electrode layer is an active metal.
  • the active metal is aluminum, nickel, or titanium.
  • the resistance abrupt change device includes a stacked third electrode layer, a third oxide layer, and a fourth electrode layer, and the third oxide layer is disposed on the third electrode layer and Between the fourth electrode layers.
  • the material of the third oxide layer is tantalum pentoxide, vanadium dioxide or germanium dioxide.
  • the material of the third electrode layer is an inert metal.
  • the inert metal is platinum, rhodium, ruthenium or palladium.
  • the first set of resistive devices includes a plurality of resistance grading devices
  • the second set of resistive devices includes a plurality of resistance abrupt devices
  • the plurality of resistance grading devices One-to-one connection with a plurality of resistance-mutation devices is connected in series.
  • the first group of resistive devices includes a plurality of resistance grading devices
  • the second group of resistive devices includes a resistance abrupt device, and a plurality of resistance grading devices.
  • the resistance values of at least two resistance grading devices are different when no voltage is applied.
  • At least two resistance grading devices are connected in parallel.
  • the first group of resistive devices includes a resistance grading device
  • the second group of resistive devices includes a plurality of resistance abrupt devices
  • one resistance grading device corresponds to multiple
  • the resistance mutation device is connected in series with the plurality of resistance mutation devices.
  • threshold voltages of at least two resistance abrupt devices are different.
  • At least two resistance abrupt devices are connected in parallel.
  • At least one embodiment of the present disclosure also provides a neural network comprising: a neuron unit.
  • the neuron unit includes the circuit structure described in any of the above embodiments.
  • the neuron unit further includes at least one signal line.
  • the signal line is electrically coupled to one of the first set of resistive devices and the second set of resistive devices.
  • one signal line is electrically connected to a resistance gradation device of the first group of resistive devices, or corresponds to a resistance mutation device of the second group of resistive devices. Electrical connection.
  • a neural network provided by at least one embodiment of the present disclosure further includes a driver.
  • the driver is configured to apply a voltage signal to the circuit unit through the signal line.
  • the voltage signal is a forward voltage signal.
  • a neural network provided by at least one embodiment of the present disclosure further includes a synapse unit.
  • the synapse unit is comprised of a third set of resistive devices, and the third set of resistive devices includes a memristor.
  • At least one embodiment of the present disclosure also provides a driving method for the circuit structure described in any of the above embodiments.
  • the driving method includes: applying a voltage signal to the circuit unit through the signal line to change the resistance of the first group of the resistive device, thereby performing signal integration; and when the resistance of the second group of resistive devices is abrupt, transmitting the signal.
  • the driving method provided by at least one embodiment of the present disclosure further includes: when the resistance of the second group of resistive devices is abrupt, the voltage signal is turned off, so that the resistance of the first group of resistive devices and the second group of resistive devices are blocked. The value is restored to its initial state to attenuate the signal.
  • the voltage signal is a forward voltage signal, the voltage value of the voltage signal remains unchanged, or the voltage value of the voltage signal gradually increases.
  • the driving method provided in at least one embodiment of the present disclosure further includes:
  • a voltage signal is applied to the circuit unit through the signal line, and when the voltage signal is greater than the threshold voltage of the first group of resistive devices, the signal is transmitted.
  • Figure 1a is a schematic diagram of a biological neuron unit
  • Figure 1b is a schematic diagram of an information processing model of a neuron
  • Figure 1c is a schematic view of a dendritic structure
  • FIG. 2a is a schematic diagram of a circuit structure according to an embodiment of the present disclosure
  • 2b is a schematic diagram showing a change in resistance of an attenuation process of a resistance gradation device according to an embodiment of the present disclosure
  • FIG. 3a is a schematic structural diagram of a resistance gradation device according to an embodiment of the present disclosure.
  • 3b is a schematic diagram of a voltage-current curve of a resistance gradation device according to an embodiment of the present disclosure
  • 3c is a schematic diagram of a response current curve of a resistance gradation device under forward voltage according to an embodiment of the present disclosure
  • 3d is a schematic diagram of a response current curve of a resistance gradation device under a negative voltage according to an embodiment of the present disclosure
  • FIG. 3 e is a schematic diagram of a response current curve when a forward voltage and a negative voltage are alternately applied to a resistance gradation device according to an embodiment of the present disclosure
  • FIG. 3f is a schematic diagram of a response current curve when a forward voltage is continuously applied to a resistance gradation device according to an embodiment of the present disclosure
  • 3g is a schematic diagram of a filtering function of a resistance gradation device according to an embodiment of the present disclosure
  • 4a is a schematic structural diagram of a resistance value abrupt device according to an embodiment of the present disclosure.
  • 4b is a schematic diagram of a voltage-current curve of a resistance variable device according to an embodiment of the present disclosure
  • 5a and 5b are schematic diagrams showing a circuit structure provided by a first example of an embodiment of the present disclosure
  • 5c is a schematic diagram of a circuit structure according to a second example of an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a circuit structure according to a third example of an embodiment of the present disclosure.
  • FIG. 6a is a structural block diagram of a neural network according to an embodiment of the present disclosure.
  • FIG. 6b is a schematic structural diagram of a neural network according to an embodiment of the present disclosure.
  • 6c is a schematic structural diagram of a neuron unit of a neural network according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of another neuron unit of a neural network according to an embodiment of the present disclosure.
  • 6e is a schematic structural diagram of still another neuron unit of a neural network according to an embodiment of the present disclosure.
  • FIG. 7 is a timing diagram of operations of a driving method according to an embodiment of the present disclosure.
  • Neurons are the basic unit of the brain's nervous system processing information, which can be used to receive, integrate, filter, store and transmit information, so that people's various functional activities can be carried out regularly to adapt to changes in the internal and external environment.
  • Fig. 1a shows a biological neuron unit
  • Fig. 1b shows an information processing model of a neuron
  • Fig. 1c shows a dendritic structure.
  • Neurons are the basic building blocks of neural networks that can pass, filter, and integrate information.
  • a signal emanating from a neuron passes through an axon, first reaching the axon tip, causing a change in the vesicle in the axon tip to release the neurotransmitter, which passes through the neurotransmitter.
  • the synaptic gap enters into the dendrites of another neuron.
  • the receptors on the dendrites can accept neurotransmitters and change the membrane-to-ion permeability of the cell body, causing changes in the concentration of ions inside and outside the cell membrane. The potential of the cells in vitro and in vivo changes. Thus, information is transmitted from one neuron to another.
  • some axons can form multiple branches at the axon tip, and the potential action from the main branch of the axon can be transmitted simultaneously on each branch, eventually reaching different target neurons, so that the axons can be realized. Communication between multiple neurons.
  • branches of axon terminals of different neurons can reach the dendrites of the same neuron and form a large number of synapses, and the neurotransmitters released by different synapses can be the same.
  • the change in membrane potential of a cell body of a neuron produces an effect whereby neurons can integrate input information from different sources.
  • the release of the neurotransmitter in the synapse and the change in the membrane potential of the cell body are continuous.
  • the input information is transmitted by the axon; when the membrane potential When it is less than the threshold, the input information cannot be transmitted, and thus the neuron implements the function of filtering information.
  • a neuron is a multi-input, single-output information processing unit that processes information non-linearly. It can be abstracted into a simple mathematical model based on the function and characteristics of the neuron. As shown in Fig. 1b, in a neuron, x 0 , x 1 , x 2 , ..., x n are signals from axonal transmissions of the previous plurality of neurons, w 0 , w 1 , w 2 ,... , w n is the transmission efficiency of synapse 01, x 0 , x 1 , x 2 , . . . , x n input signals P 0 , P 1 , P 2 , . . .
  • the input signal 02 enters the dendrites; then, the dendritic cell body 02 and 03 pairs of input signals are processed, and to obtain an output signal Y, output signal Y eventually transferred to the axons of the neurons 04, 04 can axon
  • the output signal Y is continuously transmitted to other neurons.
  • the dendrites 02 When a neuron receives information from other neurons, the dendrites 02 have the function of a threshold function Yes, its function can be expressed as formula (1):
  • the value of the channel is 1, so that the voltage-gated ion channel in the dendrite 02 is turned on, and the input signal can be transmitted to the cell body 03; when the value of the input signal is less than the threshold At ⁇ , the channel has a value of 0, so that the voltage-gated ion channel in the dendrite 02 is turned off, and the input signal is attenuated during the transmission of the dendrites 02, so that it cannot be transmitted to the cell body 03.
  • the cell body 03 receives the input signal from the dendrites 02, its membrane potential gradually changes gradually with time.
  • the cell body 03 When the membrane potential changes beyond a certain threshold, the cell body 03 generates a pulse signal with a sudden increase, and the pulse signal is The output signal of the neuron, which is then transmitted along the axon 04 to other neurons, thereby completing the information transfer of the neuron.
  • i, j and k represent the number of excitatory synaptic inputs.
  • D ex represents the excitatory synaptic potential produced.
  • the neuron transmits, filters, and integrates the input signal to form an output signal Y, and then passes the output signal Y to other neurons through the axon.
  • the output signal Y can be expressed as equation (3):
  • D ex-upstream indicates the excitatory synaptic potential generated by the upstream dendrites
  • D inhibi indicates the inhibitory synaptic input received by the cell body
  • D ex-downstream indicates the excitatory synaptic potential generated by the downstream dendrites.
  • Artificial neural network is a computer system that simulates the connection of brain neurons through synapses. It can be widely used in image recognition, automatic control, predictive estimation and data analysis. Artificial neural networks mainly use spatially distributed neuron-like electronics and synapse-like electronic devices to nonlinearly transform input signals into output signals. Artificial neural networks can process information in parallel in dense interconnected structures. Adaptability and fast processing speed.
  • neuron-like electronic devices are mainly realized by circuit design. Due to the limitation of hardware resources, at least one capacitor, six transistors and some electricity are needed in the circuit design of neuron-like electronic devices for the most basic integral-and-fire function of neurons. Resisting components to achieve. Therefore, the neuron-like electronic device has a relatively complicated circuit structure, and its power consumption is high, and the ability to handle complex tasks is low, and thus, in the artificial neural network, the function of the neuron is simplified. For the human brain, every function of a neuron plays a key role in the process of processing complex tasks; if only the simplest neuron-like model is used, the artificial neural network cannot truly realize the information processing of the simulated human brain. . Therefore, the development of high-density, low-power-like neuron-like electronic devices has become a bottleneck limiting the development of artificial neural networks.
  • At least one embodiment of the present disclosure provides a circuit structure, a driving method thereof, and a neural network.
  • the circuit structure comprises: at least one circuit unit, each circuit unit comprises a first set of resistive devices and a second set of resistive devices, the first set of resistive devices comprises a resistance grading device, and the second set of resistive devices comprises a resistance value
  • the abrupt device, the first group of resistive devices and the second group of resistive devices are connected in series, and the resistance of the first group of resistive devices is greater than the resistance of the second group of resistive devices without voltage application.
  • the circuit structure utilizes a resistance grading device and a resistance mutant device to be connected in series to form a neuron-like structure, so as to simulate the calculation, integral emission, attenuation and filtering of human brain neurons, wherein the resistance value of the resistance device is
  • the slowly changing voltage applied can be used to simulate the behavior of the S-shaped growth curve of biological dendrites.
  • the circuit structure has the advantages of simple structure, low power consumption, small area, complicated functions, and easy preparation process can be easily compatible with standard CMOS processes. Therefore, the circuit structure, the neural network, and the driving components thereof according to the embodiments of the present disclosure can be fabricated in the same chip by a CMOS process, so that miniaturization of the device can be achieved, and operating power consumption can also be reduced.
  • FIG. 2a is a schematic diagram showing a circuit structure provided by an embodiment of the present disclosure.
  • the circuit structure 100 includes: at least one circuit unit 101, each circuit unit 101 includes a first set of resistive switching devices 1 and a second set of resistive switching devices 2, the first set of resistive switching devices 1 including The resistance gradation device 10, the second group of resistive devices 2 includes a resistance abrupt device 20, the first group of resistive devices 1 and the second group of resistive devices 2 are connected in series, in the case of no voltage, the first group of resistors The resistance of the variable device 1 is greater than the resistance of the second group of resistive devices 2.
  • the circuit structure uses a resistance grading device and a resistance mutation device to be connected in series to form a neuron-like structure to realize the function of simulating human brain neurons.
  • the resistance of the resistance grading device changes slowly under the applied voltage, so that it can be used to simulate the behavior of the S-shaped growth curve of the biological dendrites.
  • the circuit structure has the advantages of simple structure, low power consumption, small area, complex functions, and compatibility with standard CMOS processes.
  • the resistance grading device 10 when the applied voltage signal is less than the threshold voltage of the resistance grading device 10, the resistance grading device The resistance value of the device 10 is small; and when the applied voltage signal is greater than the threshold voltage of the resistance gradation device 10, the resistance variation of the resistance gradation device 10 becomes large. That is to say, as the applied voltage signal increases, the resistance value of the resistance gradation device 10 also gradually increases. For example, when the first voltage is greater than the threshold voltage of the resistance grading device 10, and the second voltage is less than the threshold voltage of the resistance grading device 10, the resistance value of the resistance gradation device 10 at the first voltage is greater than The magnitude of the change in resistance at two voltages.
  • the threshold voltage of the resistance gradation device 10 is related to the material of the resistance gradation device 10 and the like.
  • a current detector 3 can be provided in the circuit structure 100, and the current detector 3 can be used to detect a response current in the circuit unit 101.
  • the current detector 3 can be, for example, an ammeter or the like.
  • the resistance grading device 10 has a first resistance value
  • the resistance abrupt device 20 has a second resistance value.
  • the first resistance value ranges from 1 to 100 megaohms (M ⁇ )
  • the second The resistance range is 1-1000 kohms (K ⁇ ).
  • the resistance values of the resistance grading device 10 and the resistance abrupt change device 20 are largely different, and the resistance value of the resistance gradation device 10 is greater than the resistance value of the resistance abrupt change device 20, so that when an applied voltage signal is applied to the circuit unit 101, In the initial stage, almost all of the applied voltage signal is applied to the resistance grading device 10, so that the resistance value of the resistance gradation device 10 is slowly decreased, and the response current in the entire circuit unit 101 is slowly increased; when the resistance gradation device 10 The resistance value is reduced to a certain extent.
  • the resistance gradation device 10 is The divided voltage will be transferred to the resistance abrupt change device 20, so that the resistance value of the resistance abrupt change device 20 suddenly becomes sharply small, and the current in the entire circuit unit 101 suddenly becomes large to form an ascending pulse current, which is a pulse current. Can be passed out.
  • the applied voltage signal is mostly applied to the resistance gradation device 10, and the process of slowly changing the current in the circuit unit 101 corresponds to the integration phase; and the applied voltage signal is transferred to the resistance abrupt device 20, in the circuit unit 101.
  • the process in which the current suddenly becomes large corresponds to the emission phase, so that the circuit structure 100 can realize the integral emission function of the neurons.
  • the resistance value of the resistance gradation device 10 gradually decreases at the beginning, and when the resistance value decreases to a certain extent, the gradual decrease cannot be continued. small.
  • the resistance of the resistance grading device 10 is reduced to a different extent.
  • the first voltage is applied to the resistance grading device 10, and the resistance is changed by ⁇ R1; and when the second voltage is applied to the resistance grading device 10, the resistance is changed by ⁇ R2, and ⁇ R2 is greater than ⁇ R1, wherein ⁇ R1 and ⁇ R2 represent the absolute values of the amount of change in resistance.
  • the resistance gradation device 10 and the resistance mutation device 20 are The resistance gradually returns to its initial resistance state, so that the circuit structure 100 can also achieve the attenuation function of the neuron.
  • the resistance grading device 10 quickly returns to the initial resistance state, and the recovery time is on the order of milliseconds, and the recovery time is related to the applied voltage signal, the resistance of the device itself, etc., for example, provided by the embodiment of the present disclosure.
  • the recovery time of the resistance grading device 10 is 50-60 milliseconds.
  • the resistance of the resistance gradation device 10 is 10 M ⁇ without voltage application.
  • Fig. 2b the resistance of the resistance gradation device 10 is 10 M ⁇ without voltage application.
  • curve 45 represents the attenuation process after the application of the first voltage to the resistance grading device 10
  • curve 46 represents the attenuation process after the application of the second voltage to the resistance grading device 10.
  • the resistance grading device 10 exhibits a characteristic that the resistance value increases slowly; after the voltage signal applied to the resistance abrupt change device 20 reaches its threshold voltage, the resistance mutation device 20 exhibits The characteristic that the resistance suddenly becomes sharply decreased; after the applied voltage signal is removed, the resistance of the resistance gradation device 10 and the resistance abrupt change device 20 slowly returns to the initial state. Therefore, the circuit structure 100 provided by the embodiment of the present disclosure can simulate the behavior of a neuron, wherein the resistance gradation device 10 can be used to simulate the behavior of a dendrite in a neuron, thereby being a key component in a brain-like neural network chip. section.
  • FIGS. 3b-3g are various electrical characteristic curves of the resistance gradation device according to an embodiment of the present disclosure.
  • the resistance gradation device 10 provided by the embodiment of the present disclosure includes a stacked first oxide layer 12 and a second oxide layer 13, and the first oxide layer 12 has a higher oxygen content than the second oxide.
  • the materials of the first oxide layer 12 and the second oxide layer 13 are both metal oxides.
  • the material of the first oxide layer 12 may be tantalum pentoxide (Ta 5 O 2 ) or aluminum oxide (Al 2 O 3 ), etc.
  • the material of the second oxide layer 13 may be tantalum dioxide (TaO 2 ). Wait.
  • the resistance gradation device 10 further includes a first electrode layer 11 and a second electrode layer 14, and the first oxide layer 12 and the second oxide layer 13 are disposed between the first electrode layer 11 and the second electrode layer 14, The first electrode layer 11 is electrically connected to the first oxide layer 12, and the second electrode layer 14 is electrically connected to the second oxide layer 13.
  • the material of the first electrode layer 11 is an active metal material, so that the resistance value of the resistance gradation device 10 is slowly changed under the applied voltage signal.
  • the active metal may be, for example, aluminum (Al), nickel (Ni), or titanium (Ti).
  • the material of the second electrode layer 14 may be a conductive material such as metal, and may be, for example, copper (Cu), aluminum (Al), or tungsten (W).
  • the resistance grading device 10 can be used to simulate the behavior of a sigmoidal growth curve of a dendrite in a neuron, and its resistance value changes slowly under an applied voltage signal. As shown in FIG. 3b, when the forward voltage and the reverse voltage are applied to the resistance gradation device 10, the resistance changes differently. Under the forward voltage, if the resistance gradation device 10 is forward-scanned, that is, the voltage is gradually increased from 0 V to 4 V, the voltage-current curve of the resistance gradation device 10 is represented by the curve 15, at this time.
  • the resistance value of the resistance grading device 10 decreases as the forward voltage increases; if the resistance gradation device 10 is reversely scanned, that is, the voltage gradually decreases from 4V to 0V, and the resistance gradually changes.
  • the voltage-current curve of device 10 is represented by curve 16, at which point the resistance of the resistance grading device 10 slowly decreases as the forward voltage decreases. Under the negative voltage, if the resistance gradation device 10 is forward-scanned, that is, the voltage is gradually decreased from 0 V to -4 V, the voltage-current curve of the resistance gradation device 10 is represented by the curve 17 at this time.
  • the resistance value of the resistance gradation device 10 increases as the negative voltage increases; if the resistance gradation device 10 is reversely scanned, that is, the voltage gradually increases from -4V to 0V, and the resistance is blocked.
  • the voltage-current curve of the value grading device 10 is represented by a curve 18, at which time the resistance of the resistance grading device 10 slowly increases as the negative voltage decreases.
  • the resistance value of the resistance grading device 10 decreases as the forward voltage increases, that is, the response current of the resistance grading device 10 increases nonlinearly with an increase in the forward voltage; and the resistance value of the resistance grading device 10 follows The increase in the negative voltage increases, that is, the response current of the resistance gradation device 10 decreases or does not change as the negative voltage increases.
  • a forward voltage 31 is applied to the resistance grading device 10, and the forward response current 33 of the gradual change device 10 gradually increases with time, that is, at a forward voltage of 31,
  • the resistance of the value grading device 10 is gradually decreased;
  • the negative voltage 32 is applied to the resistance grading device 10, and the negative response current 34 of the gradual change device 10 is slowly decreased with time, that is, under the negative voltage 32.
  • the resistance value of the resistance gradation device 10 is gradually increased. As shown in FIGS.
  • the amount of change in the forward response current 33 is larger than the amount of change in the negative response current 34, that is,
  • the change amount of the resistance value of the resistance gradation device 10 under the forward voltage 31 is larger than the change amount of the resistance value of the resistance gradation device 10 under the negative voltage 32. It should be noted that the voltage values of the forward voltage 31 and the negative voltage 32 remain constant during the response time.
  • the resistance gradation device 10 provided by the embodiment of the present disclosure can also simulate the function of the synapse.
  • the resistance value of the resistance gradation device 10 is gradually decreased, and the response current is gradually increased, so that the resistance gradation device 10 can simulate the excitatory synapse;
  • the resistance value of the resistance gradation device 10 is gradually increased, and the response current is gradually decreased, so that the resistance gradation device 10 can simulate the suppression synapse.
  • the forward response current 33 and the negative response current 34 of the resistance gradation device 10 also alternately appear. With the increase of time, the response currents of the resistance grading device 10 cancel each other out, and no accumulation occurs. As shown in FIG. 3f, when the forward voltage 31 is continuously applied to the resistance gradation device 10, the forward response current 33 of the resistance gradation device 10 gradually increases with time.
  • the resistance gradation device 10 can also implement a dendritic filtering function.
  • the threshold voltage of the resistance grading device 10 can be, for example, 3V.
  • the voltage signal 36 is applied to the resistance grading device 10.
  • the response current 37 of the resistance gradation device 10 is compared. Small (almost 0 ⁇ A), at this time, the circuit unit does not transmit a signal (this signal is the response current).
  • the response current 37 of the resistance grading device 10 sharply increases, and at this time, the circuit unit starts transmitting signals. That is to say, when the value of the voltage signal 36 is less than 3V, the circuit unit cannot perform signal transmission, so that the resistance gradation device 10 can filter a voltage signal having a voltage value of less than 3V.
  • applying a forward voltage to the resistance gradation device 10 indicates that the voltage applied to the first electrode layer 11 is greater than the voltage applied to the second electrode layer 14; applying a negative voltage to the resistance gradation device 10 indicates that the voltage is applied to the first The voltage of one electrode layer 11 is smaller than the voltage applied to the second electrode layer 14.
  • FIG. 4a is a schematic structural diagram of a resistance-change device according to an embodiment of the present disclosure
  • FIG. 4b is a schematic diagram of a voltage-current curve of a resistance-change device according to an embodiment of the present disclosure.
  • the resistance value abrupt device 20 provided by the embodiment of the present disclosure includes a stacked third electrode layer 21, a third oxide layer 22, and a fourth electrode layer 23, and the third oxide layer 22 is disposed at the 23 between the three electrode layer 21 and the fourth electrode layer.
  • the material of the third oxide layer 22 is a metal oxide.
  • the metal oxide may be tantalum pentoxide (Ta 5 O 2 ), vanadium dioxide (VO 2 ) or cerium oxide (NbO 2 ).
  • the material of the third electrode layer 21 may be an inert metal material such that the resistance mutation device 20 has a sudden change process under an applied voltage signal.
  • the inert metal is, for example, platinum (Pt), ruthenium (Ru), iridium (Ir) or palladium (Pd).
  • the material of the fourth electrode layer 23 may be a conductive material such as metal. For example, it may be copper (Cu), aluminum (Al), or tungsten (W).
  • a voltage signal is applied to the resistance abrupt device 20, and the resistance of the resistance abrupt device 20 is substantially unchanged until the voltage signal reaches its threshold voltage.
  • the resistance of the resistance abrupt device 20 is abrupt.
  • the resistance value test device 20 is subjected to a resistance test.
  • the voltage-current curve diagram is as shown in FIG. 4b.
  • the resistance value abrupt device 20 is forwardly scanned.
  • the resistance value is The resistance value of the abrupt device 20 suddenly becomes small; under the negative voltage, the resistance mutation device 20 is forward-scanned, and when the negative voltage is about -1 V, the resistance value of the resistance abrupt device 20 suddenly becomes small.
  • the curve 25, the curve 26, and the curve 27 respectively show a graph of the resistance change of the resistance value abrupt device 20 for 1, 5, and 10 times.
  • the resistance value of the resistance device 20 is subjected to multiple resistance tests.
  • the resistance mutation device 20 exhibits the same characteristics that the resistance mutation device 20 can be used repeatedly to maintain the same characteristics.
  • applying a forward voltage to the resistance abrupt change device 20 indicates that the voltage of the third electrode layer 21 is greater than the voltage of the fourth electrode layer 23; applying a reverse voltage to the resistance abrupt change device 20 indicates the voltage of the third electrode layer 21. It is smaller than the voltage of the fourth electrode layer 23.
  • the resistance values of the resistance grading device 10 and the resistance abrupt device 20 are quickly restored to the initial resistance state, and the recovery time is on the order of milliseconds, and the recovery time depends on the application of the resistance gradation device 10 and The voltage value of the resistance abrupt device 20 and the time when the voltage is applied, and the like, the larger the voltage value, the shorter the recovery time.
  • the recovery time of the resistance mutant device 20 provided by the embodiment of the present disclosure is less than 1 s.
  • 5a and 5b are schematic diagrams showing a circuit structure provided by a first example of an embodiment of the present disclosure.
  • the first group of resistive devices 1 may include a plurality of resistance grading devices 10, and the second group of resist devices 2 may include a plurality of resistance abrupt devices 20, and multiple resistors
  • the value grading device 10 is connected in series with the plurality of resistance abrupt devices 20 in a one-to-one correspondence. It should be noted that, in each circuit unit 101, at least two resistance grading devices 10 may be connected in parallel, so that each circuit unit 101 can realize multi-channel synchronous transmission signals.
  • the first group of resistive devices 1 includes a resistance grading device 10
  • the second group of resist devices 2 includes a resistance abrupt device 20.
  • a plurality of circuit units 101 may be connected in parallel to realize multi-channel synchronous transmission of signals. As shown in FIG. 5a, the plurality of circuit units 101 can receive the same input signal; as shown in FIG. 5b, the plurality of circuit units 101 can also receive different input signals. It should be noted that the plurality of circuit units 101 may also be connected in series.
  • the output signals output by the plurality of circuit units 101 can be respectively transmitted to different paths 5 and simultaneously transmitted in different paths 5, eventually reaching different target units.
  • Each circuit unit 101 can correspond to one path 5, and further corresponds to one target unit; each circuit unit 101 can also correspond to a plurality of paths 5, thereby corresponding to a plurality of target units.
  • the output signals output by the plurality of circuit units 101 can also be integrated, and the integrated output signals can be transmitted to the same path 5, and finally transmitted to a target unit, so that each target unit corresponds to multiple The circuit unit 101; the integrated output signal can also be simultaneously transmitted to different target units through different paths 5.
  • each adjacent five circuit units 101 can perform output signal integration and then transmit to a target unit through a path 5.
  • the plurality of circuit units 101 can be arranged in different combinations to meet different practical needs, thereby realizing most functions of human brain neurons.
  • FIG. 5c is a schematic diagram showing a circuit structure provided by a second example of the embodiment of the present disclosure.
  • the first group of resistive devices 1 includes a plurality of resistance grading devices 10
  • the second group of resist devices 2 includes a resistance abrupt device 20, and a plurality of resistance grading devices 10 Corresponding to a resistance mutation device 20, and respectively connected in series with the one resistance abrupt change device 20.
  • the arrangement of the circuit unit 101 may be the same as the first example, or may be different, and details are not described herein again.
  • the plurality of resistance grading devices 10 at least two resistance grading devices 10 are connected in parallel, that is, one resistance abrupt device 20 may correspond to the plurality of resistance grading devices 10, and are transmitted from different resistance grading devices 10 signal of.
  • the different resistance grading devices 10 correspond to the same resistance abrupt device 20 and form different information transmission paths, thereby saving the number of resistance abrupt devices 20 in the circuit structure 100 and saving production costs.
  • the resistance values of the at least two resistance grading devices 10 are different.
  • different resistance grading devices 10 can be selected, thereby different input signals (ie, The applied voltage signal can be transmitted through different information transmission paths to realize different functions.
  • the resistance grading devices 10 of different resistance values have different response currents, so that the same input signal can select different resistance grading devices 10;
  • the resistance grading devices 10 of different resistance values may have the same response current, and different input signals may generate the same output signal, so that a certain range can be Input signal inside select.
  • the first group of resistive devices 1 includes two resistance grading devices 10 in parallel, and the second group of resistive devices 2 includes a resistance abrupt device 20.
  • Two resistance grading devices 10 connected in parallel can receive different input signals.
  • FIG. 5d is a schematic diagram showing a circuit structure provided by a third example of the embodiment of the present disclosure.
  • the first group of resistive devices 1 includes a resistance grading device 10
  • the second group of resist devices 2 includes a plurality of resistance abrupt devices 20, and a resistance grading device 10 corresponds to A plurality of resistance abrupt devices 20 are connected in series with the plurality of resistance abrupt devices 20, respectively.
  • the arrangement of the circuit unit 101 may be the same as the first example, or may be different, and details are not described herein again.
  • the plurality of resistance abrupt devices 20 at least two resistance abrupt devices 20 are connected in parallel, that is, one resistance gradation device 10 may correspond to the plurality of resistance abrupt devices 20 and be transmitted to different resistance abrupt devices 20 signal.
  • the different resistance abrupt devices 20 correspond to the same resistance grading device 10 and form different information transmission paths, thereby saving the number of the resistance grading devices 10 in the circuit structure 100 and saving production costs.
  • the threshold voltages of the at least two resistance abrupt devices 20 are different, and by controlling the applied voltage signals, different resistance abrupt devices 20 can be selected, thereby different input signals (ie, The applied voltage signal can be transmitted through different information transmission paths.
  • the second group of resistive devices 2 includes two resistance abrupt devices 20, and the two resistance abrupt devices 20 are connected in parallel, so that the resistance of the second group of resistive devices 2 is smaller than the two resistors. The resistance of any one of the value abrupt devices 20 is.
  • the second set of resistive devices 2 can be divided into smaller applied voltage signals, and the second set of resistive devices 2 have less influence on the response current of the entire circuit unit 101.
  • the two resistance abrupt devices 20 can be applied with the same applied voltage signal; it should be understood that the two resistance abrupt devices 20 can also be applied with different applied voltage signals.
  • the arrangement of the resistance grading device 10 and the resistance abrupt change device 20 is not limited to the above embodiments, and may be arranged and combined in various ways according to actual needs to realize different functions.
  • FIG. 6a is a structural block diagram of a neural network according to an embodiment of the present disclosure
  • FIG. 6b is a schematic structural diagram of a neural network according to an embodiment of the present disclosure
  • FIG. 6c - FIG. A schematic diagram of the structure of the different neuronal units provided.
  • the neural network includes a neuron unit 200.
  • Neuron unit 200 includes the circuit structure 100 of any of the above embodiments.
  • the neuron unit 200 also includes at least one signal line.
  • One end of the circuit unit 101 is connected to the signal line, and the other end of the circuit unit 101 can be connected to the ground. It should be noted that both ends of the circuit unit 101 can be connected to the signal line, as long as the voltage difference between the two ends of the circuit unit 101 is ensured.
  • the neuron unit 200 can include a first signal line 50 that is electrically coupled to the first set of resistive device 1 or the second set of resistive devices 2, correspondingly Ground, the ground line 4 is electrically connected to the second group of resistive devices 2 or the first group of resistive devices 1.
  • the neuron unit 200 may further include a second signal line 51 and a third signal line 52. The first signal line 50, the second signal line 51, and the third signal line 52 are respectively connected to different circuit units 101 to provide different voltage signals for different circuit units 101.
  • one signal line is electrically connected to a resistance grading device of the first group of resistive devices or to a resistance abrupt device of the second group of resistive devices.
  • the neuron unit 200 may include, for example, a plurality of signal lines, and the plurality of signal lines may be electrically connected to the plurality of resistance grading devices 10 of the first group of resistive devices 1 in one-to-one correspondence; or the second group of resistive devices 2
  • the plurality of resistance abrupt devices 20 are electrically connected one by one.
  • the neuron unit 200 may include a first signal line 50 and a second signal line 51, and the first signal line 50 and the second signal line 51 may respectively have two resistance values of the first group of resistive devices 1.
  • the grading device 10 is electrically connected, that is, the first signal line 50 can be electrically connected to one of the resistance change grading devices 10 of the first group of resistive devices 1, and the second signal line 51 can be coupled to the first group of resistive devices 1
  • the other resistance grading device 10 is electrically connected, so that the first signal line 50 and the second signal line 51 can provide different applied voltage signals for the two resistance grading devices 10 of the first group of resistive devices 1.
  • the neural network also includes a driver 400.
  • the driver 400 is configured to control a signal line (eg, the first signal line 50, the second signal line 51, the third signal line 52, etc.) to apply a voltage signal to the circuit unit 101.
  • a signal line eg, the first signal line 50, the second signal line 51, the third signal line 52, etc.
  • the driver 400 can be implemented by hardware, software, firmware, and any combination thereof, for example, by a computing device such as a CPU, an FPGA, a DSP, a CMU, or the like, or by a CPU and a software instruction stored in a memory.
  • a computing device such as a CPU, an FPGA, a DSP, a CMU, or the like, or by a CPU and a software instruction stored in a memory.
  • the voltage signal is a forward voltage signal, so that the resistance of the resistance grading device 10 changes slowly.
  • the forward voltage signal means that the voltage applied to the first electrode layer of the resistance grading device 10 is greater than the voltage applied to its second electrode layer.
  • the neural network also includes a synapse unit 300.
  • the synapse unit 300 It is composed of a third group of resistive devices 301, so that the neural network can be a fully resistive device neural network, that is, the neuron unit in the neural network is formed by a resistive device, and the synapse unit is also formed by the resistive device. That is, in the neural network, the first set of resistive devices 1 are used to simulate dendrites, the second set of resistive devices 2 are used to simulate cell bodies, and the third resistive change device 301 is used to simulate synapses.
  • the third set of resistive devices 301 can include a memristor.
  • the synapse unit 300 may include an n ⁇ n synapse array composed of a memristor, and the signals x 0 , x 1 , . . . , x n form an input signal of the neuron after passing through the synapse array.
  • the input signal can then be passed to the circuit structure 100 of the neuron unit 200; the input signal is processed via the circuit structure 100 and then passed through the pathway 5 to other neuronal units.
  • the third resistive device 301 can simulate the plasticity function of the synapse, and the synaptic plasticity is mainly expressed as excitability and inhibition.
  • the resistance When a forward voltage signal is applied to the memristor, the resistance is gradually reduced, so that the excitatory synapse can be simulated; when a negative voltage signal is applied to the memristor, the resistance gradually becomes larger, so that the simulation can be suppressed.
  • Sexual synapse When a forward voltage signal is applied to the memristor, the resistance is gradually reduced, so that the excitatory synapse can be simulated; when a negative voltage signal is applied to the memristor, the resistance gradually becomes larger, so that the simulation can be suppressed.
  • Sexual synapse When a forward voltage signal is applied to the memristor, the resistance is gradually reduced, so that the excitatory synapse can be simulated; when a negative voltage signal is applied to the memristor, the resistance gradually becomes larger, so
  • the memristor in the embodiment of the present disclosure may be a metal oxide memristor such as a memristor prepared using titanium dioxide or a memristor prepared using a combination of alumina and titania.
  • FIG. 7 is a working sequence diagram of the driving method according to the embodiment of the present disclosure.
  • the driving method includes the following operations: for example, using a driver, applying a voltage signal to the circuit unit through a signal line to change the resistance of the first group of resistive devices, thereby performing signal integration; when the resistance of the second group of resistive devices is When a mutation occurs, a signal is emitted.
  • the driving method reduces the resistance of the first group of resistive devices by applying a voltage signal to the circuit unit, so that the current in the circuit unit is slowly increased, thereby realizing the integral function; when the resistance of the second group of resistive devices suddenly becomes smaller Then, the current in the circuit unit suddenly increases, forming a rising pulse current and being transmitted, thereby realizing the transmitting function.
  • the integration phase corresponds to the A period in the figure.
  • the applied voltage signal is mostly applied to the first group of resistive devices, and the resistance of the first-stage resistive device is changed. Gradually decreasing, that is, the conductance of the resistance gradual device is gradually increased, so that the response current in the circuit unit is slowly increased; the emission phase corresponds to the B period in the figure, and at this time, the applied voltage signal is transferred to the second group of resistance changes.
  • the resistance value of the resistance change device in the second group of resistive devices is abruptly changed, and the resistance value suddenly decreases, that is, the conductance of the resistance change device suddenly becomes large, so that the response current in the circuit unit suddenly Increase to form a rising pulse current.
  • the circuit structure can realize neuron Integral launch function.
  • the driving method further includes: when the resistance of the second group of resistive devices is abrupt, the applied voltage signal is turned off, and the resistance values of the first group of resistive devices and the second group of resistive devices are restored to an initial state to attenuate signal.
  • the attenuation phase corresponds to the C period in the figure.
  • the applied voltage signal is removed, and the resistance value of the resistance gradation device and the resistance mutation device gradually returns to the initial state, and the response current in the circuit unit. Gradually reduced, so that the circuit structure can achieve the attenuation function of neurons.
  • the applied voltage signal can be a forward voltage signal.
  • the voltage value of the applied voltage signal can remain unchanged; or the voltage value of the applied voltage signal can be gradually increased.
  • the forward voltage signal means that the voltage applied to the first electrode layer of the resistance grading device 10 is greater than the voltage applied to its second electrode layer.
  • the driving method may further include: applying a voltage signal to the circuit unit through the signal line, for example, by using a driver, when the voltage signal is smaller than a threshold voltage of the first group of resistive devices, in the first group of resistive devices
  • the resistance of all resistance grading devices does not change.
  • the response current generated by the circuit unit is small (almost 0 ⁇ A), the circuit unit does not transmit signals (the signal is the response current); when the voltage signal is greater than the first group
  • the threshold voltage of the resistive device is changed, the resistance value of the resistance grading device in the first group of resistive devices gradually becomes smaller.
  • the response current generated by the circuit unit is large, and the circuit unit starts to transmit signals.
  • the circuit unit can implement the function of filtering the voltage signals.
  • the threshold voltages of all of the resistance grading devices in the first set of resistive devices may be the same, such that the threshold voltage of the gradual change device may be the threshold voltage of the first set of resistive devices.
  • the threshold voltages of all the resistance grading devices in the first group of resistive devices may also be different. At this time, the threshold voltage of the resistance grading device having the largest initial resistance may be the threshold voltage of the first group of resistive devices. .
  • the initial resistance value indicates the resistance of the resistance grading device without applying a voltage.
  • the circuit structure can filter the applied voltage signal smaller than the threshold voltage of the resistance grading device, and the circuit structure can realize the filtering function of the neuron.
  • the first group of resistive devices may include a plurality of resistance grading devices, and the plurality of resistance grading devices include, for example, a first resistance grading device and a second resistance grading device, and the first resistance grading device The device is connected in parallel with the second resistance grading device. If the voltage signal is less than the threshold voltage of the first resistance grading device and greater than the threshold voltage of the second resistance grading device, the voltage signal can be transmitted through the second resistance grading device. That is, according to different voltage signals, the circuit structure can select different resistance grading devices.

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Abstract

一种电路结构及其驱动方法、神经网络。该电路结构（100）包括：至少一个电路单元（101），每个电路单元（101）包括第一组阻变器件（1）和第二组阻变器件（2），第一组阻变器件（1）包括阻值渐变器件（10），第二组阻变器件（2）包括阻值突变器件（20），第一组阻变器件（1）和第二组阻变器件（2）串联连接，在未加电压的情况下，第一组阻变器件（1）的阻值大于第二组阻变器件（2）的阻值。该电路结构利用阻值渐变器件和阻值突变器件串联连接形成类神经元结构，以实现模拟人脑神经元的功能。

Description

电路结构及其驱动方法、神经网络
本申请要求于2017年05月09日递交的中国专利申请第201710322907.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种电路结构及其驱动方法、神经网络。
背景技术
随着信息技术的高速发展，运行速度的提升和能耗的降低成为了传统冯诺依曼计算架构发展的瓶颈，而类脑计算体系以其可大规模并行操作、低能耗、自主学习和自适应等特性被认为是目前寻求高性能计算机的突破方向。在人脑中，神经元和突触是最主要、数量最多的神经单元。由此，构建类脑计算体系需要大量的类神经元和类突触的电子器件，这些电子器件除了需要实现模拟神经元和突触的功能外，还需要具有面积小、功耗低以及速度高等性能。
目前，在类脑计算体系中，类神经元的功能需要通过电路设计实现，由于硬件资源的限制，类神经元的电子器件存在能耗高、无法处理复杂任务等缺陷，进而限制类脑计算体系的发展。
发明内容
本公开至少一实施例提供一种电路结构及其驱动方法、神经网络。该电路结构利用阻值渐变器件和阻值突变器件串联连接形成类神经元结构，以实现模拟人脑神经元的计算、积分发射、衰减和过滤等功能。例如，阻值渐变器件的阻值在外加电压下缓慢变化，可以用于模拟生物树突的S型生长曲线的行为。该电路结构具有结构简单、功耗低、面积小、可以实现复杂功能以及与标准CMOS工艺容易兼容等优点。
本公开至少一实施例提供一种电路结构，其包括：至少一个电路单元，每个电路单元包括第一组阻变器件和第二组阻变器件，第一组阻变器件包括阻值渐变器件，第二组阻变器件包括阻值突变器件，第一组阻变器件和第二组阻变器件串联连接，在未加电压的情况下，第一组阻变器件的阻值大于第二组阻变 器件的阻值。
例如，在本公开至少一实施例提供的电路结构中，阻值渐变器件具有第一阻值，阻值突变器件具有第二阻值，在未加电压的情况下，第一阻值的范围为1-100兆欧，第二阻值的范围为1-1000千欧。
例如，在本公开至少一实施例提供的电路结构中，阻值渐变器件包括层叠的第一氧化物层和第二氧化物层，第一氧化物层的氧含量高于第二氧化物层的氧含量。
例如，在本公开至少一实施例提供的电路结构中，第一氧化物层的材料为五氧化二钽或氧化铝，第二氧化物层的材料为二氧化钽。
例如，在本公开至少一实施例提供的电路结构中，阻值渐变器件还包括第一电极层和第二电极层，第一氧化物层和第二氧化物层设置在第一电极层和第二电极层之间，且第一电极层与第一氧化物层电连接，第二电极层与第二氧化物层电连接。
例如，在本公开至少一实施例提供的电路结构中，第一电极层的材料为活性金属。
例如，在本公开至少一实施例提供的电路结构中，该活性金属为铝、镍、或钛。
例如，在本公开至少一实施例提供的电路结构中，阻值突变器件包括层叠的第三电极层、第三氧化物层和第四电极层，第三氧化物层设置在第三电极层和第四电极层之间。
例如，在本公开至少一实施例提供的电路结构中，第三氧化物层的材料为五氧化二钽、二氧化钒或二氧化铌。
例如，在本公开至少一实施例提供的电路结构中，第三电极层的材料为惰性金属。
例如，在本公开至少一实施例提供的电路结构中，该惰性金属为铂、钌、铱或钯。
例如，在本公开至少一实施例提供的电路结构中，第一组阻变器件包括多个阻值渐变器件，第二组阻变器件包括多个阻值突变器件，且多个阻值渐变器件分别与多个阻值突变器件一一对应串联连接。
例如，在本公开至少一实施例提供的电路结构中，第一组阻变器件包括多个阻值渐变器件，第二组阻变器件包括一个阻值突变器件，多个阻值渐变器件 对应一个阻值突变器件，且分别与该一个阻值突变器件串联连接。
例如，在本公开至少一实施例提供的电路结构中，在未加电压的情况下，至少两个阻值渐变器件的阻值不相同。
例如，在本公开至少一实施例提供的电路结构中，至少两个阻值渐变器件并联连接。
例如，在本公开至少一实施例提供的电路结构中，第一组阻变器件包括一个阻值渐变器件，第二组阻变器件包括多个阻值突变器件，一个阻值渐变器件对应多个阻值突变器件，且与该多个阻值突变器件分别串联连接。
例如，在本公开至少一实施例提供的电路结构中，至少两个阻值突变器件的阈值电压不相同。
例如，在本公开至少一实施例提供的电路结构中，至少两个阻值突变器件并联连接。
本公开至少一实施例还提供一种神经网络，其包括：神经元单元。该神经元单元包括上述任一实施例所述的电路结构。
例如，在本公开至少一实施例提供的神经网络中，神经元单元还包括至少一条信号线。该信号线与第一组阻变器件和第二组阻变器件其中之一电连接。
例如，在本公开至少一实施例提供的神经网络中，一条信号线与第一组阻变器件的一个阻值渐变器件对应电连接，或与第二组阻变器件的一个阻值突变器件对应电连接。
例如，本公开至少一实施例提供的神经网络，还包括驱动器。该驱动器被配置为通过信号线向电路单元施加电压信号。
例如，在本公开至少一实施例提供的神经网络中，电压信号为正向电压信号。
例如，本公开至少一实施例提供的神经网络，还包括突触单元。该突触单元由第三组阻变器件构成，第三组阻变器件包括忆阻器。
本公开至少一实施例还提供一种用于上述任一实施例所述的电路结构的驱动方法。该驱动方法包括：通过信号线向电路单元施加电压信号以改变第一组阻变器件的阻值，由此进行信号积分；当第二组阻变器件的阻值发生突变时，发射信号。
例如，本公开至少一实施例提供的驱动方法，还包括：当第二组阻变器件的阻值发生突变后，关闭电压信号，使第一组阻变器件和第二组阻变器件的阻 值恢复初始状态，以衰减信号。
例如，在本公开至少一实施例提供的驱动方法中，电压信号为正向电压信号，电压信号的电压值保持不变或电压信号的电压值逐渐增大。
例如，本公开至少一实施例提供的驱动方法，还包括：
通过信号线向电路单元施加电压信号，当电压信号大于第一组阻变器件的阈值电压时，传输信号。
需要理解的是本公开的上述概括说明和下面的详细说明都是示例性和解释性的，用于进一步说明所要求的发明。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1a为一种生物神经元单元的示意图；
图1b为一个神经元的信息处理模型的示意图；
图1c为一种树突结构的示意图；
图2a为本公开一实施例提供的一种电路结构的示意图；
图2b为本公开一实施例提供的阻值渐变器件的衰减过程的电阻变化的曲线示意图；
图3a为本公开一实施例提供的一种阻值渐变器件的结构示意图；
图3b为本公开一实施例提供的一种阻值渐变器件的电压-电流曲线示意图；
图3c为本公开一实施例提供的阻值渐变器件在正向电压下的响应电流曲线示意图；
图3d为本公开一实施例提供的阻值渐变器件在负向电压下的响应电流曲线示意图；
图3e为对本公开一实施例提供的阻值渐变器件交替施加正向电压和负向电压时的响应电流曲线示意图；
图3f为对本公开一实施例提供的阻值渐变器件连续施加正向电压时的响应电流曲线示意图；
图3g为本公开一实施例提供的阻值渐变器件的过滤功能的示意图；
图4a为本公开一实施例提供的一种阻值突变器件的结构示意图；
图4b为本公开一实施例提供的一种阻值突变器件的电压-电流曲线示意图；
图5a和5b为本公开一实施例的第一示例提供的一种电路结构的示意图；
图5c为本公开一实施例的第二示例提供的一种电路结构的示意图；
图5d为本公开一实施例的第三示例提供的一种电路结构的示意图；
图6a为本公开一实施例提供的一种神经网络的组成框图；
图6b为本公开一实施例提供的一种神经网络的结构示意图；
图6c为本公开一实施例提供的神经网络的一种神经元单元的结构示意图；
图6d为本公开一实施例提供的神经网络的另一种神经元单元的结构示意图；
图6e为本公开一实施例提供的神经网络的又一种神经元单元的结构示意图；以及
图7为本公开一实施例提供的一种驱动方法的工作时序图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和 已知部件的详细说明。
人的大脑主要依靠神经元和在神经元之间进行信息传递的突触来实现信息的传递和处理。神经元是大脑神经系统处理信息的基本单元，其可以用于接收、整合、过滤、存储和传递信息等，从而使人的各种机能活动有规律的进行，以适应内、外环境的变化。
图1a示出了一种生物神经元单元，图1b示出了一个神经元的信息处理模型，图1c示出了一种树突结构。
神经元是神经网络的基本组成单元，其可以对信息进行传递、过滤和整合等。如图1a所示，在神经元内，由一个神经元传出的信号通过轴突，首先到达轴突末梢，使轴突末梢中的囊泡产生变化从而释放神经递质，该神经递质通过突触的间隙进入到另一个神经元的树突中，树突上的受体能够接受神经递质从而改变细胞体的膜向离子的通透性，使细胞膜内外离子的浓度产生变化，进而使细胞体内外的电位产生变化。由此，信息就由一个神经元传输到另一个神经元中。在信息传递过程中，一些轴突在轴突末梢可以形成多个分支，来自轴突主支上的电位动作可以在各个分支上同时继续传递，最终到达不同的目标神经元，从而轴突可以实现多个神经元之间的通信。另一方面，在神经网络结构上，不同神经元的轴突末梢的分支可以到达同一个神经元的树突并形成大量的突触，来源不同的突触所释放的神经递质都可以对同一个神经元的细胞体的膜电位的变化产生作用，由此，神经元可以对来源不同的输入信息进行整合。再一方面，在神经元中，突触中神经递质的释放和细胞体的膜电位的变化是连续的，当膜电位高于一定阈值时，输入信息则由轴突传递出去；当膜电位小于该阈值时，则输入信息无法被传递出去，由此，神经元实现过滤信息的功能。
神经元是一个多输入单输出的信息处理单元，它对信息的处理是非线性的，根据神经元的功能和特性，其可以被抽象为一个简单的数学模型。如图1b所示，在一个神经元中，x0，x1，x2，….，xn是来自前多个神经元的轴突传输的信号，w0，w1，w2，….，wn是突触01的传递效率，x0，x1，x2，….，xn经过突触01后形成神经元的输入信号P0，P1，P2，….，Pn，该输入信号进入树突02；然后，树突02和细胞体03对输入信号进行处理，并得到输出信号Y，输出信号Y最终被传输到该神经元的轴突04，轴突04可以将输出信号Y继续传输给其他的神经元。
当一个神经元接收来自其他神经元的信息时，树突02具有阈值函数的功 能，其功能可以被表示为公式(1)：
Figure PCTCN2017110871-appb-000001
当输入信号的值大于阈值θ时，channel(通道)的值为1，从而树突02中的电压门控离子通道打开，输入信号可以被传输到细胞体03中；当输入信号的值小于阈值θ时，channel的值为0，从而树突02中的电压门控离子通道关闭，输入信号在树突02的传输过程中衰减，从而无法传输到细胞体03中。当细胞体03接收到来自树突02传递的输入信号后，其膜电位按时间连续逐渐变化，当膜电位的变化超出一定阈值时，细胞体03产生突变上升的脉冲信号，该脉冲信号即为神经元的输出信号，接着，这个脉冲信号沿轴突04传递到其他的神经元中，从而完成神经元的信息传递。
如图1c所示，根据神经元理论，15％的树突位于细胞体的近端，且携带有抑制性突触和兴奋性突触；其余85％的树突位于细胞体的远端，且只携带有兴奋性突触。抑制性突触对位于细胞体远端的树突上的兴奋性突触具有抵消作用，且抑制性突触对于输入信号不发挥作用。因此，树突中产生的兴奋性突触电位可以通过叠加所有大于阈值θ的兴奋性突触表示，如公式(2)所示：
Figure PCTCN2017110871-appb-000002
其中，i，j和k表示兴奋性突触输入的数量。Dex表示产生的兴奋性突触电位。
神经元对输入信号进行传递、过滤和整合后形成输出信号Y，然后通过轴突将输出信号Y传递给其他的神经元，其输出信号Y可以表示为公式(3)：
Y＝Dex-upstream-Dinhibi+Dex-downstream    (3)
其中，Dex-upstream表示上游树突产生的兴奋性突触电位，Dinhibi表示细胞体接收的抑制性突触输入，Dex-downstream表示下游树突产生的兴奋性突触电位。
人工神经网络是一种模拟大脑神经元通过突触相互联接的计算机系统，其可以广泛应用于图像识别、自动控制、预测估计以及数据分析等领域。人工神经网络主要使用空间分布的类神经元电子器件和类突触电子器件将输入信号非线性地变换为输出信号，人工神经网络可以在密集互连结构中并行处理信息，其具有非线性、自适应性及处理速度快等特点。
目前，在人工神经网络中，类神经元电子器件主要通过电路设计实现。由于硬件资源的限制，对于神经元最基本的积分-发射(Integrate-and-fire)功能，在类神经元电子器件的电路设计中至少需要一个电容、六个晶体管以及一些电 阻等元件来实现。因此，类神经元电子器件具有相对复杂的电路结构，且其功耗高、处理复杂任务的能力低，从而，在人工神经网络中，神经元的功能被简化。对于人脑而言，神经元的每一项功能在其处理复杂任务的过程中都起关键作用；如果只使用最简单的类神经元模型，则人工神经网络无法真正实现模拟人脑进行信息处理。因此，高密度、低功耗的类神经元电子器件的开发成为限制人工神经网络发展的瓶颈。
本公开至少一实施例提供一种电路结构及其驱动方法、神经网络。该电路结构包括：至少一个电路单元，每个电路单元包括第一组阻变器件和第二组阻变器件，第一组阻变器件包括阻值渐变器件，第二组阻变器件包括阻值突变器件，第一组阻变器件和第二组阻变器件串联连接，在未加电压的情况下，第一组阻变器件的阻值大于第二组阻变器件的阻值。该电路结构利用阻值渐变器件和阻值突变器件串联连接形成类神经元结构，以实现模拟人脑神经元的计算、积分发射、衰减和过滤等功能，其中，阻值渐变器件的阻值在外加电压下缓慢变化，可以用于模拟生物树突的S型生长曲线的行为。该电路结构具有结构简单、功耗低、面积小、可以实现复杂功能以及其制备工艺可与标准CMOS工艺容易兼容等优点。因此，根据本公开实施例的电路结构、神经网络及其驱动部件可以通过CMOS工艺制备在同一芯片之中，从而可以实现器件的小型化，而且运行功耗也可以得到降低。
在本公开的下面的描述中，以第一电压大于第二电压为例进行描述。
图2a示出了本公开实施例提供的一种电路结构的示意图。
例如，如图2a所示，该电路结构100包括：至少一个电路单元101，每个电路单元101包括第一组阻变器件1和第二组阻变器件2，第一组阻变器件1包括阻值渐变器件10，第二组阻变器件2包括阻值突变器件20，第一组阻变器件1和第二组阻变器件2串联连接，在未加电压的情况下，第一组阻变器件1的阻值大于第二组阻变器件2的阻值。
该电路结构利用阻值渐变器件和阻值突变器件串联连接形成类神经元结构，以实现模拟人脑神经元的功能。在电路结构中，阻值渐变器件的阻值在外加电压下缓慢变化，从而其可以用于模拟生物树突的S型生长曲线的行为。同时，该电路结构具有结构简单、功耗低、面积小、可以实现复杂功能以及可与标准CMOS工艺容易兼容等优点。
例如，当外加电压信号小于阻值渐变器件10的阈值电压时，阻值渐变器 件10的阻值变化幅度较小；而当外加电压信号大于阻值渐变器件10的阈值电压时，阻值渐变器件10的阻值变化幅度变大。也就是说，随着外加电压信号的增大，阻值渐变器件10的阻值变化幅度也逐渐增大。例如，当第一电压大于阻值渐变器件10的阈值电压，而第二电压小于阻值渐变器件10的阈值电压时，阻值渐变器件10在第一电压下的阻值变化幅度大于其在第二电压下的阻值变化幅度。阻值渐变器件10的阈值电压与阻值渐变器件10的材料等相关。
例如，如图2a所示，在该电路结构100中可以设置电流检测器3，电流检测器3可用于检测电路单元101中的响应电流。电流检测器3例如可以为安培表或类似器件。
例如，阻值渐变器件10具有第一阻值，阻值突变器件20具有第二阻值，在未加电压的情况下，第一阻值的范围为1-100兆欧(MΩ)，第二阻值的范围为1-1000千欧(KΩ)。阻值渐变器件10和阻值突变器件20的阻值相差较大，且阻值渐变器件10的阻值大于阻值突变器件20的阻值，从而当外加电压信号施加到该电路单元101时，最开始阶段，外加电压信号几乎全部被施加到阻值渐变器件10上，从而使阻值渐变器件10的阻值缓慢减小，整个电路单元101中的响应电流缓慢增加；当阻值渐变器件10的阻值减小到一定程度，例如当阻值渐变器件10的阻值与阻值突变器件20的阻值相差不大或小于阻值突变器件20的阻值时，在阻值渐变器件10上的分压将会转移到阻值突变器件20上，从而阻值突变器件20的阻值会突然急剧变小，整个电路单元101中的电流突然变大，形成一个上升的脉冲电流，该脉冲电流可以被传递出去。在此过程中，外加电压信号大部分施加到阻值渐变器件10上，电路单元101中的电流缓慢变化的过程对应积分阶段；而外加电压信号转移到阻值突变器件20上，电路单元101中的电流突然变大的过程对应发射阶段，从而电路结构100可以实现神经元的积分发射功能。
需要说明的是，当对阻值渐变器件10施加不变的外加电压信号时，开始时，阻值渐变器件10的阻值逐渐减小，当阻值减小到一定程度后，则无法继续减小。在不同的外加电压信号下，阻值渐变器件10的电阻减小的程度不相同。例如，对阻值渐变器件10施加第一电压，其阻值的变化量为ΔR1；而对阻值渐变器件10施加第二电压，其阻值的变化量为ΔR2，则ΔR2大于ΔR1，其中，ΔR1和ΔR2表示阻值的变化量的绝对值。
例如，当外加电压信号去掉之后，阻值渐变器件10和阻值突变器件20的 阻值逐渐恢复到其初始电阻状态，从而该电路结构100还可以实现神经元的衰减功能。例如，当外加电压信号去掉之后，阻值渐变器件10快速恢复到初始电阻状态，且恢复时间为毫秒量级，恢复时间与外加电压信号、器件本身的阻值等有关，例如本公开实施例提供的阻值渐变器件10的恢复时间为50-60毫秒。在图2b所示的阻值渐变器件的衰减过程中，在未加电压下，阻值渐变器件10的阻值为10MΩ。在图2b中，曲线45表示对该阻值渐变器件10施加第一电压后的衰减过程，曲线46表示对该阻值渐变器件10施加第二电压后的衰减过程。由图2b可知，在较大的外加电压信号下，阻值渐变器件10的阻值的变化较大，阻值的恢复时间也较长。例如，如图2b所示，在第一电压下，阻值渐变器件10阻值可以减小到3MΩ左右，阻值的恢复时间大约为70ms；而在第二电压下，阻值渐变器件10阻值可以减小到2MΩ以下，恢复时间大于100ms。
综上所述，在外加电压信号下，阻值渐变器件10表现出阻值缓慢增加的特性；在施加到阻值突变器件20上的电压信号达到其阈值电压后，阻值突变器件20表现出电阻突然急剧变小的特性；在撤去外加电压信号之后，阻值渐变器件10和阻值突变器件20阻值缓慢恢复到初始状态。因此，本公开实施例提供的电路结构100可以模拟神经元的行为，其中，阻值渐变器件10可以用于模拟神经元中的树突的行为，从而可以作为类脑神经网络芯片中的关键组成部分。
图3a为本公开实施例提供的一种阻值渐变器件的结构示意图，图3b-3g为本公开实施例提供的阻值渐变器件的各种电学特性曲线图。
例如，如图3a所示，本公开实施例提供的阻值渐变器件10包括层叠的第一氧化物层12和第二氧化物层13，第一氧化物层12的氧含量高于第二氧化物层12的氧含量。需要说明的是，氧含量为氧化物中氧的摩尔百分比含量。
例如，第一氧化物层12和第二氧化物层13的材料均为金属氧化物。例如，第一氧化物层12的材料可以为五氧化二钽(Ta5O2)或氧化铝(Al2O3)等，第二氧化物层13的材料可以为二氧化钽(TaO2)等。
例如，阻值渐变器件10还包括第一电极层11和第二电极层14，第一氧化物层12和第二氧化物层13设置在第一电极层11和第二电极层14之间，且第一电极层11与第一氧化物层12电连接，第二电极层14与第二氧化物层13电连接。
例如，第一电极层11的材料为活性金属材料，从而在外加电压信号下，使阻值渐变器件10的阻值缓慢变化。活性金属例如可以为铝(Al)、镍(Ni)、或钛(Ti)等。第二电极层14的材料可以为金属等导电材料，例如，可以为铜(Cu)、铝(Al)或钨(W)等。
例如，该阻值渐变器件10可以用于模拟神经元中的树突的S型生长曲线的行为，在外加电压信号下，其阻值缓慢变化。如图3b所示，对阻值渐变器件10施加正向电压和反向电压时，其阻值的变化不同。在正向电压下，若对阻值渐变器件10进行正向扫描，也就是说，电压从0V逐渐增加到4V，此时阻值渐变器件10的电压-电流变化曲线由曲线15表示，此时，阻值渐变器件10的阻值随着正向电压的增加而减小；若对阻值渐变器件10进行反向扫描，也就是说，电压从4V逐渐减小到0V，此时阻值渐变器件10的电压-电流变化曲线由曲线16表示，此时，阻值渐变器件10的阻值随着正向电压的减小而缓慢减小。在负向电压下，若对阻值渐变器件10进行正向扫描，也就是说，电压从0V逐渐减小到-4V，此时阻值渐变器件10的电压-电流变化曲线由曲线17表示，此时，阻值渐变器件10的阻值随着负向电压的增加而增大；若对阻值渐变器件10进行反向扫描，也就是说，电压从-4V逐渐增加到0V，此时阻值渐变器件10的电压-电流变化曲线由曲线18表示，此时，阻值渐变器件10的阻值随着负向电压的减小而缓慢增大。
例如，阻值渐变器件10的阻值随正向电压的增加而减小，即阻值渐变器件10的响应电流随正向电压的增加而非线性增加；而阻值渐变器件10的阻值随负向电压的增加而增大，即阻值渐变器件10的响应电流随负向电压的增加而减小或不变。例如，如图3c和3d所示，对阻值渐变器件10施加正向电压31，阻值渐变器件10的正向响应电流33随时间逐渐增加，也就是说，在正向电压31下，阻值渐变器件10的阻值逐渐减小；对阻值渐变器件10施加负向电压32，阻值渐变器件10的负向响应电流34随时间缓慢减小，也就是说，在负向电压32下，阻值渐变器件10的阻值逐渐增大。如图3c和3d所示，在相同的响应时间内，当正向电压31和负向电压32的绝对值相同，正向响应电流33的变化量比负向响应电流34的变化量大，即正向电压31下阻值渐变器件10的阻值的变化量大于负向电压32下阻值渐变器件10的阻值的变化量。需要说明的是，在响应时间内，该正向电压31和负向电压32的电压值保持恒定。
综上所述，本公开实施例提供的阻值渐变器件10还可以模拟突触的功能。 对阻值渐变器件10施加正向电压，且进行正向扫描时，阻值渐变器件10的阻值逐渐减小，其响应电流逐渐增大，从而阻值渐变器件10可以模拟兴奋性突触；对阻值渐变器件10施加负向电压，且进行正向扫描时，阻值渐变器件10的阻值逐渐增大，其响应电流逐渐减小，从而阻值渐变器件10可以模拟抑制性突触。
例如，如图3e所示，当对阻值渐变器件10交替施加正向电压31和负向电压32时，阻值渐变器件10的正向响应电流33和负向响应电流34也交替出现，随着时间的增加，阻值渐变器件10的响应电流相互抵消，不会产生积累。如图3f所示，当对阻值渐变器件10连续施加正向电压31，则阻值渐变器件10的正向响应电流33随时间逐渐增加。
例如，本公开实施例提供的阻值渐变器件10还可以实现树突的过滤功能。阻值渐变器件10的阈值电压例如可以为3V，如图3g所示，对阻值渐变器件10施加电压信号36，当电压信号36的值小于3V时，阻值渐变器件10的响应电流37较小(几乎为0μA)，此时，电路单元不传输信号(该信号即响应电流)。而当电压信号36的值大于3V时，阻值渐变器件10的响应电流37急剧增加，此时，电路单元开始传输信号。也就是说，当电压信号36的值小于3V时，电路单元无法进行信号传输，从而该阻值渐变器件10可以过滤电压值小于3V的电压信号。
需要说明的是，对阻值渐变器件10施加正向电压表示施加给第一电极层11的电压大于施加给第二电极层14的电压；对阻值渐变器件10施加负向电压表示施加给第一电极层11的电压小于施加给第二电极层14的电压。
图4a为本公开实施例提供的一种阻值突变器件的结构示意图，图4b为本公开实施例提供的阻值突变器件的电压-电流曲线示意图。
例如，如图4a所示，本公开实施例提供的阻值突变器件20包括层叠的第三电极层21、第三氧化物层22和第四电极层23，第三氧化物层22设置在第三电极层21和第四电极层之间23。
例如，第三氧化物层22的材料为金属氧化物，例如，金属氧化物可以为五氧化二钽(Ta5O2)、二氧化钒(VO2)或二氧化铌(NbO2)等。
例如，第三电极层21的材料可以为惰性金属材料，从而在外加电压信号下，该阻值突变器件20具有一个突然变化的过程。该惰性金属例如为铂(Pt)、钌(Ru)、铱(Ir)或钯(Pd)等。第四电极层23的材料可以为金属等导电材料，例 如，可以为铜(Cu)、铝(Al)或钨(W)等。
例如，对阻值突变器件20施加电压信号，在电压信号达到其阈值电压前，阻值突变器件20的阻值基本不变。而在电压信号达到阈值电压时，阻值突变器件20的阻值产生突变。对阻值突变器件20进行电阻测试，其电压-电流曲线图如图4b所示，在正向电压下，对阻值突变器件20进行正向扫描，当正向电压为1V左右时，阻值突变器件20的阻值突然变小；在负向电压下，对阻值突变器件20进行正向扫描，当负向电压为-1V左右时，阻值突变器件20的阻值突然变小。曲线25、曲线26、和曲线27分别表示对阻值突变器件20进行1次、5次和10次电阻测试的曲线图，由图4b可知，对阻值突变器件20进行多次电阻测试，该阻值突变器件20表现出相同的特性，即该阻值突变器件20可以反复使用而保持相同的特性。
需要说明的是，对阻值突变器件20施加正向电压表示第三电极层21的电压大于第四电极层23的电压；对阻值突变器件20施加反向电压表示第三电极层21的电压小于第四电极层23的电压。
例如，当撤去外加电压信号后，阻值渐变器件10和阻值突变器件20的阻值快速恢复到初始电阻状态，其恢复时间为毫秒量级，恢复时间取决于施加到阻值渐变器件10和阻值突变器件20的电压值和施加电压的时间等因素，电压值越大则恢复时间越短。例如，本公开实施例提供的阻值突变器件20的恢复时间小于1s。
图5a和5b示出了本公开实施例第一示例提供的一种电路结构的示意图。
例如，在第一示例提供的电路结构中，第一组阻变器件1可以包括多个阻值渐变器件10，第二组阻变器件2可以包括多个阻值突变器件20，且多个阻值渐变器件10分别与多个阻值突变器件20一一对应串联连接。需要说明的是，在每个电路单元101中，至少两个阻值渐变器件10可以并联连接，从而每个电路单元101可以实现多通道同步传输信号。
例如，如图5a所示，在每个电路单元101中，第一组阻变器件1包括一个阻值渐变器件10，第二组阻变器件2包括一个阻值突变器件20。
例如，多个电路单元101可以并联连接，从而实现多通道同步传输信号。如图5a所示，该多个电路单元101可以接收相同的输入信号；如图5b所示，该多个电路单元101还可以接收不同的输入信号。需要说明的是，多个电路单元101还可以串联连接。
例如，如图5a所示，多个电路单元101输出的输出信号可以分别传输到不同的通路5中，且在不同的通路5中同时传输，最终到达不同的目标单元。每个电路单元101可以对应一个通路5，进而对应一个目标单元；每个电路单元101也可以对应多个通路5，进而对应多个目标单元。如图5b所示，该多个电路单元101输出的输出信号也可以进行整合，整合后的输出信号可以传输到同一个通路5中，最终传输到一个目标单元，从而每个目标单元对应多个电路单元101；整合后的输出信号还可以通过不同的通路5同时传输到不同的目标单元。
需要说明的是，该多个电路单元101还可以进行部分整合。例如，在电路结构100中，每相邻的五个电路单元101可以进行输出信号整合，然后通过一个通路5传输到一个目标单元。多个电路单元101可以进行不同的排列组合，以满足不同的实际需求，从而实现人脑神经元的大部分功能。
图5c示出了本公开实施例第二示例提供的一种电路结构的示意图。
例如，在第二示例提供的电路结构中，第一组阻变器件1包括多个阻值渐变器件10，第二组阻变器件2包括一个阻值突变器件20，多个阻值渐变器件10对应一个阻值突变器件20，且分别与该一个阻值突变器件20串联连接。
例如，在第二示例中，电路单元101的排列方式可以与第一示例相同，也可以不同，在此不再赘述。
例如，在多个阻值渐变器件10中，至少两个阻值渐变器件10并联连接，即一个阻值突变器件20可以对应多个阻值渐变器件10，且传递来自不同的阻值渐变器件10的信号。不同的阻值渐变器件10对应同一个阻值突变器件20，且形成不同的信息传输通路，从而可以节省电路结构100中阻值突变器件20的数量，节约生产成本。
例如，在多个阻值渐变器件10中，至少两个阻值渐变器件10的阻值不相同，通过控制外加电压信号，则可以选择不同的阻值渐变器件10，从而不同的输入信号(即外加电压信号)可以通过不同的信息传输通路进行传递，进而实现不同的功能。例如，当对该多个阻值渐变器件10施加相同的外加电压信号时，不同阻值的阻值渐变器件10具有不同的响应电流，从而相同的输入信号可以选择不同的阻值渐变器件10；当对该多个阻值渐变器件10施加不同的外加电压信号时，不同阻值的阻值渐变器件10可以具有相同的响应电流，不同的输入信号可以产生相同的输出信号，从而可以对一定范围内的输入信号进行 选择。
例如，如图5c所示，在每个电路单元101中，第一组阻变器件1包括并联的两个阻值渐变器件10，第二组阻变器件2包括一个阻值突变器件20。并联的两个阻值渐变器件10可以接收不同的输入信号。
图5d示出了本公开实施例第三示例提供的一种电路结构的示意图。
例如，在第三示例提供的电路结构中，第一组阻变器件1包括一个阻值渐变器件10，第二组阻变器件2包括多个阻值突变器件20，一个阻值渐变器件10对应多个阻值突变器件20，且与该多个阻值突变器件20分别串联连接。
例如，在第三示例中，电路单元101的排列方式也可以与第一示例相同，也可以不同，在此不再赘述。
例如，在多个阻值突变器件20中，至少两个阻值突变器件20并联连接，即一个阻值渐变器件10可以对应多个阻值突变器件20，且向不同的阻值突变器件20传递信号。不同的阻值突变器件20对应同一个阻值渐变器件10，且形成不同的信息传输通路，从而可以节省电路结构100中阻值渐变器件10的数量，节约生产成本。
例如，在多个阻值突变器件20中，至少两个阻值突变器件20的阈值电压不相同，通过控制外加电压信号，则可以选择不同的阻值突变器件20，从而不同的输入信号(即外加电压信号)可以通过不同的信息传输通路进行传递。如图5d所示，第二组阻变器件2包括两个阻值突变器件20，且该两个阻值突变器件20并联连接，从而第二组阻变器件2的阻值小于该两个阻值突变器件20中任意一个的阻值。在积分阶段，第二组阻变器件2可以分得更小的外加电压信号，第二组阻变器件2对整个电路单元101的响应电流的影响更小。如图5d所示，该两个阻值突变器件20可以被施加相同的外加电压信号；需要理解的是，该两个阻值突变器件20也可以被施加不同的外加电压信号。
需要说明的是，阻值渐变器件10和阻值突变器件20排列方式不限于上述实施例所述，根据实际需求，其可以按照各种方式排列组合，以实现不同的功能。
本公开实施例提供一种神经网络，图6a为本公开实施例提供的神经网络的组成框图；图6b为本公开实施例提供的神经网络的结构示意图；图6c-图6e为本公开实施例提供的不同的神经元单元的结构示意图。
例如，如图6a所示，该神经网络包括：神经元单元200。该神经元单元 200包括上述任一实施例所述的电路结构100。
例如，该神经元单元200还包括至少一条信号线。电路单元101的其中一端连接该信号线，电路单元101的另一端可以连接地线。需要说明的是，电路单元101的两端都可以接信号线，只要保证电路单元101的两端具有电压差即可。
例如，如图6c所示，在一个示例中，神经元单元200可以包括第一信号线50，第一信号线50与第一组阻变器件1或第二组阻变器件2电连接，相应地，地线4与第二组阻变器件2或第一组阻变器件1电连接。又例如，如图6d所示，在另一个示例中，神经元单元200还可以包括第二信号线51和第三信号线52。第一信号线50、第二信号线51和第三信号线52分别与不同的电路单元101连接，从而为不同的电路单元101提供不同的电压信号。
例如，一条信号线与第一组阻变器件的一个阻值渐变器件对应电连接，或与第二组阻变器件的一个阻值突变器件对应电连接。神经元单元200例如可以包括多条信号线，且多条信号线可以分别与第一组阻变器件1的多个阻值渐变器件10一一对应电连接；或与第二组阻变器件2的多个阻值突变器件20一一对应电连接。如图6e所示，神经元单元200可以包括第一信号线50和第二信号线51，第一信号线50和第二信号线51可以分别与第一组阻变器件1的两个阻值渐变器件10电连接，也就是说，第一信号线50可以与第一组阻变器件1中的一个阻值渐变器件10电连接，而第二信号线51可以与第一组阻变器件1中的另一个阻值渐变器件10电连接，从而第一信号线50和第二信号线51可以为第一组阻变器件1中的两个阻值渐变器件10提供不同的外加电压信号。
例如，如图6a所示，神经网络还包括驱动器400。该驱动器400被配置为控制信号线(例如，第一信号线50、第二信号线51、第三信号线52等)向电路单元101施加电压信号。
例如，该驱动器400可以通过硬件、软件、固件及其任意组合来实现，例如可以通过CPU、FPGA、DSP、CMU等计算器件实现，也可以通过CPU与存储在存储器中的软件指令来实现等。
例如，电压信号为正向电压信号，从而使阻值渐变器件10的阻值缓慢变化。正向电压信号指的是施加到阻值渐变器件10的第一电极层的电压大于施加到其第二电极层的电压。
例如，如图6a和6b所示，神经网络还包括突触单元300。该突触单元300 由第三组阻变器件301构成，从而该神经网络可以为全阻变器件神经网络，即该神经网络中的神经元单元由阻变器件形成，突触单元也由阻变器件形成。也就是说，在该神经网络中，第一组阻变器件1用于模拟树突，第二组阻变器件2用于模拟细胞体，第三阻变器件301用于模拟突触。
例如，第三组阻变器件301可以包括忆阻器。如图6b所示，该突触单元300可以包括由忆阻器构成的n×n的突触阵列，信号x0，x1，….，xn通过突触阵列后形成神经元的输入信号；然后，该输入信号可以被传递至神经元单元200的电路结构100中；该输入信号经由电路结构100处理之后通过通路5传递至其他的神经元单元中。
例如，第三阻变器件301可以模拟突触的可塑性功能，突触的可塑性主要表现为兴奋性和抑制性。当对忆阻器外施加正向电压信号时，其电阻逐渐减小，从而可以模拟兴奋性突触；当对忆阻器外施加负向电压信号时，其电阻逐渐变大，从而可以模拟抑制性突触。
例如，本公开实施例中的忆阻器可以为金属氧化物忆阻器，例如使用二氧化钛制备的忆阻器或者使用氧化铝和二氧化钛结合制备的忆阻器等。
本公开实施例提供一种用于上述任一所述的电路结构的驱动方法，图7为本公开实施例提供的驱动方法的工作时序图。
例如，该驱动方法包括如下操作：例如利用驱动器，通过信号线向电路单元施加电压信号以改变第一组阻变器件的阻值，由此进行信号积分；当第二组阻变器件的阻值发生突变时，发射信号。
该驱动方法通过对电路单元施加电压信号，减小第一组阻变器件的阻值，使电路单元中的电流缓慢增加，从而实现积分功能；当第二组阻变器件的阻值突然变小，则电路单元中的电流突然增大，形成一个上升的脉冲电流而被传递出去，从而实现发射功能。
例如，如图7所示，积分阶段对应于图中A时段，此时，外加电压信号大部分施加到第一组阻变器件上，第一组阻变器件中的阻值渐变器件的阻值逐渐减小，也就是说，阻值渐变器件的电导逐渐增大，从而电路单元中的响应电流缓慢增加；发射阶段对应于图中B时段，此时，外加电压信号转移到第二组阻变器件上，第二组阻变器件中的阻值突变器件的阻值发生突变，其阻值突然减小，也就是说，阻值突变器件的电导突然变大，从而电路单元中的响应电流突然增大，形成一个上升的脉冲电流。综上所述，该电路结构可以实现神经元的 积分发射功能。
例如，该驱动方法还包括：当第二组阻变器件的阻值发生突变后，关闭外加电压信号，使第一组阻变器件和第二组阻变器件的阻值恢复初始状态，以衰减信号。
例如，如图7所示，衰减阶段对应于图中C时段，此时，外加电压信号被撤去，阻值渐变器件和阻值突变器件的阻值逐渐恢复到初始状态，电路单元中的响应电流逐渐减小，从而该电路结构可以实现神经元的衰减功能。
例如，外加电压信号可以为正向电压信号。在响应时间内，外加电压信号的电压值可以保持不变；或者，外加电压信号的电压值也可以逐渐增大。正向电压信号指的是施加到阻值渐变器件10的第一电极层的电压大于施加到其第二电极层的电压。
例如，在一个示例中，驱动方法还可以包括：例如利用驱动器，通过信号线向电路单元施加电压信号，当电压信号小于第一组阻变器件的阈值电压时，第一组阻变器件中的所有阻值渐变器件的阻值不发生变化，此时，电路单元产生的响应电流较小(几乎为0μA)，电路单元不传输信号(该信号即为响应电流)；当电压信号大于第一组阻变器件的阈值电压时，第一组阻变器件中的阻值渐变器件的阻值逐渐变小，此时，电路单元产生的响应电流较大，电路单元开始传输信号。也就是说，小于第一组阻变器件的阈值电压的电压信号被阻挡，从而电路单元可以实现过滤电压信号的功能。例如，第一组阻变器件中所有阻值渐变器件的阈值电压可以相同，从而阻值渐变器件的阈值电压可以为第一组阻变器件的阈值电压。又例如，第一组阻变器件中所有阻值渐变器件的阈值电压也可以不相同，此时，具有最大初始阻值的阻值渐变器件的阈值电压可以为第一组阻变器件的阈值电压。初始阻值表示在未加电压的情况下阻值渐变器件的阻值。
例如，如图3g所示，在外加电压信号小于其阈值电压时，阻值渐变器件的阻值基本不产生变化，电路单元产生的响应电流较小；当外加电压信号大于其阈值电压时，阻值渐变器件的阻值逐渐减小，电路单元产生的响应电流较大，且该响应电流逐渐增加。综上可知，该电路结构可以过滤小于阻值渐变器件的阈值电压的外加电压信号，进而该电路结构可以实现神经元的过滤功能。
需要说明的是，第一组阻变器件可以包括多个阻值渐变器件，多个阻值渐变器件例如包括第一阻值渐变器件和第二阻值渐变器件，且该第一阻值渐变器 件和第二阻值渐变器件并联连接。若电压信号小于第一阻值渐变器件的阈值电压而大于第二阻值渐变器件的阈值电压时，该电压信号可以通过第二阻值渐变器件进行传递。即根据不同的电压信号，该电路结构可以对不同的阻值渐变器件进行选择。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种电路结构，包括：至少一个电路单元，
    每个所述电路单元包括第一组阻变器件和第二组阻变器件，所述第一组阻变器件包括阻值渐变器件，所述第二组阻变器件包括阻值突变器件，所述第一组阻变器件和所述第二组阻变器件串联连接，在未加电压的情况下，所述第一组阻变器件的阻值大于所述第二组阻变器件的阻值。
  2. 根据权利要求1所述的电路结构，其中，所述阻值渐变器件具有第一阻值，所述阻值突变器件具有第二阻值，在未加电压的情况下，所述第一阻值的范围为1-100兆欧，所述第二阻值的范围为1-1000千欧。
  3. 根据权利要求1或2所述的电路结构，其中，所述阻值渐变器件包括层叠的第一氧化物层和第二氧化物层，所述第一氧化物层的氧含量高于第二氧化物层的氧含量。
  4. 根据权利要求3所述的电路结构，其中，所述第一氧化物层的材料为五氧化二钽或氧化铝，所述第二氧化物层的材料为二氧化钽。
  5. 根据权利要求3或4所述的电路结构，其中，所述阻值渐变器件还包括第一电极层和第二电极层，
    所述第一氧化物层和第二氧化物层设置在所述第一电极层和第二电极层之间，且
    所述第一电极层与所述第一氧化物层电连接，所述第二电极层与所述第二氧化物层电连接。
  6. 根据权利要求5所述的电路结构，其中，所述第一电极层的材料为活性金属。
  7. 根据权利要求6所述的电路结构，其中，所述活性金属为铝、镍、或钛。
  8. 根据权利要求1-7任一项所述的电路结构，其中，所述阻值突变器件包括层叠的第三电极层、第三氧化物层和第四电极层，所述第三氧化物层设置在所述第三电极层和第四电极层之间。
  9. 根据权利要求8所述的电路结构，其中，所述第三氧化物层的材料为五氧化二钽、二氧化钒或二氧化铌。
  10. 根据权利要求8或9所述的电路结构，其中，所述第三电极层的材料 为惰性金属。
  11. 根据权利要求10所述的电路结构，其中，所述惰性金属为铂、钌、铱或钯。
  12. 根据权利要求1-11任一项所述的电路结构，其中，所述第一组阻变器件包括多个所述阻值渐变器件，所述第二组阻变器件包括多个所述阻值突变器件，且所述多个阻值渐变器件分别与所述多个阻值突变器件一一对应串联连接。
  13. 根据权利要求1-11任一项所述的电路结构，其中，所述第一组阻变器件包括多个所述阻值渐变器件，所述第二组阻变器件包括一个所述阻值突变器件，多个所述阻值渐变器件对应一个所述阻值突变器件，且分别与该一个所述阻值突变器件串联连接。
  14. 根据权利要求13所述的电路结构，其中，在未加电压的情况下，至少两个所述阻值渐变器件的阻值不相同。
  15. 根据权利要求13或14所述的电路结构，其中，至少两个所述阻值渐变器件并联连接。
  16. 根据权利要求1-11任一项所述的电路结构，其中，所述第一组阻变器件包括一个所述阻值渐变器件，所述第二组阻变器件包括多个所述阻值突变器件，一个所述阻值渐变器件对应多个所述阻值突变器件，且与该多个所述阻值突变器件分别串联连接。
  17. 根据权利要求16所述的电路结构，其中，至少两个所述阻值突变器件的阈值电压不相同。
  18. 根据权利要求16或17所述的电路结构，其中，至少两个所述阻值突变器件并联连接。
  19. 一种神经网络，包括：神经元单元，所述神经元单元包括权利要求1-18任一项所述的电路结构。
  20. 根据权利要求19所述的神经网络，其中，所述神经元单元还包括至少一条信号线，
    其中，所述信号线与所述第一组阻变器件和所述第二组阻变器件其中之一电连接。
  21. 根据权利要求20所述的神经网络，其中，一条所述信号线与所述第一组阻变器件的一个所述阻值渐变器件对应电连接，或与所述第二组阻变器件 的一个所述阻值突变器件对应电连接。
  22. 根据权利要求19-21任一项所述的神经网络，还包括驱动器，
    其中，所述驱动器被配置为通过所述信号线向所述电路单元施加电压信号。
  23. 根据权利要求22所述的神经网络，其中，所述电压信号为正向电压信号。
  24. 根据权利要求19-23任一项所述的神经网络，还包括突触单元，
    其中，所述突触单元由第三组阻变器件构成，所述第三组阻变器件包括忆阻器。
  25. 一种用于权利要求1-18任一项所述的电路结构的驱动方法，包括：
    通过信号线向所述电路单元施加电压信号以改变所述第一组阻变器件的阻值，由此进行信号积分；
    当所述第二组阻变器件的阻值发生突变时，发射信号。
  26. 根据权利要求25所述的驱动方法，还包括：
    当所述第二组阻变器件的阻值发生突变后，关闭所述电压信号，使所述第一组阻变器件和所述第二组阻变器件的阻值恢复初始状态，以衰减信号。
  27. 根据权利要求25或26所述的驱动方法，其中，所述电压信号为正向电压信号，所述电压信号的电压值保持不变或所述电压信号的电压值逐渐增大。
  28. 根据权利要求25-27任一项所述的驱动方法，还包括：
    通过所述信号线向所述电路单元施加所述电压信号，当所述电压信号大于所述第一组阻变器件的阈值电压时，传输信号。
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