WO2018201546A1 - 液晶像素电路及其驱动方法与液晶显示面板 - Google Patents

液晶像素电路及其驱动方法与液晶显示面板 Download PDF

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WO2018201546A1
WO2018201546A1 PCT/CN2017/086642 CN2017086642W WO2018201546A1 WO 2018201546 A1 WO2018201546 A1 WO 2018201546A1 CN 2017086642 W CN2017086642 W CN 2017086642W WO 2018201546 A1 WO2018201546 A1 WO 2018201546A1
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Prior art keywords
switch
liquid crystal
path end
component
pixel
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PCT/CN2017/086642
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English (en)
French (fr)
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陈猷仁
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/556,059 priority Critical patent/US20200043434A1/en
Publication of WO2018201546A1 publication Critical patent/WO2018201546A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes

Definitions

  • the present invention relates to a liquid crystal pixel circuit and a driving method thereof, and more particularly to a liquid crystal pixel circuit using a shared gate line for a main and sub-pixel, a driving method thereof and a liquid crystal display panel.
  • This design method divides the pixel unit into two areas of a main pixel (Main) and a sub-pixel (Sub).
  • the main pixel includes a first switch component electrically coupled to the corresponding data line and a gate charge charging line.
  • the sub-pixel includes a second switch component and a charge sharing switch, the second switch component is electrically coupled to the corresponding data line and the gate scan charging line, and the charge sharing switch is further connected to the gate share sharing line (Gate Share Line).
  • the switching components are generally Thin Film Transistor (TFT) components.
  • the first and second switching components respectively charge the main pixel and the sub-pixel.
  • the gate scan charging line is turned off and the gate scan sharing line is turned on.
  • the charge sharing switch is opened to redistribute the charge of the capacitance of the sub-pixel and the charge in the shared capacitance of the charge sharing switch, and finally the potential of the main pixel and the sub-pixel is redistributed to achieve a low color shift effect.
  • the general design is to independently control the signal scanning lines of the gate scanning charging line and the gate scanning sharing line. If the charge sharing function is to be turned off, the gate scanning sharing line can be turned off (such as switching to a low voltage such as VGL). The charge sharing switch is turned off.
  • an object of the present application is to provide a liquid crystal pixel circuit using a shared gate line and maintaining charge sharing, a driving method thereof, and a liquid crystal display panel.
  • a liquid crystal pixel circuit includes: a plurality of pixel units arranged in a matrix, each pixel unit coupled to a corresponding data line and a gate line, and each pixel includes: a main pixel, including: a switch assembly having a first path end, a second path end, and a control end, wherein the first path end of the first switch component is electrically coupled to the data line, and the control end of the first switch component is electrically The first storage component is electrically coupled to the second path end of the first switch component; and the sub-pixel includes: a second switch component having a first path end a second path end and a control end, the control end of the second switch component is electrically coupled to the gate line, The first path end of the second switch component is electrically coupled to the data line; the second storage component is electrically coupled to the second path end of the second switch component; and the charge sharing switch has the first a second end of the charge sharing switch is
  • control signals provided by the nth gate line and the n+1th gate line are enabled at different times.
  • the nth gate line is the gate scan charging line to provide a gate scan pulse signal
  • the n+1th gate line is a gate scan sharing line to provide Charge sharing gate scan pulse signal
  • the gate scan pulse signal is equal to a pulse width of the charge sharing gate scan pulse signal.
  • the gate scan pulse signal is one pulse width ahead of the charge share gate scan pulse signal.
  • the nth gate line provides a gate scan pulse signal, and the first switch component and the second switch component of the pixel unit of the nth row are turned on, and the charge sharing switch Turning off; the nth gate line is dissipated, and when the n+1th gate line provides a charge sharing gate scan pulse signal, the charge sharing switch of the pixel unit of the nth row is turned on; When the n+1th gate line is dissipated and the sharing gate scan pulse signal is provided, the first switch component and the second switch component of the pixel unit of the (n+1)th row are turned on, the n+1th row The charge sharing switch of the pixel unit is turned off.
  • the first storage component includes a first liquid crystal capacitor and a first storage capacitor, and the first storage component is connected between the second path end of the first switch component and a shared voltage .
  • the second storage component includes a second liquid crystal capacitor and a second storage capacitor, and the second storage component is connected between the second path end of the second switch component and the shared voltage .
  • the third storage component includes a third storage capacitor, and the third storage component is coupled between the first path end of the charge sharing switch and the shared voltage.
  • each pixel unit is arranged in a matrix and coupled to a corresponding data line and a gate line
  • the driving method includes: providing a gate scan when the nth gate line is provided a pulse signal, the first switch component and the second switch component of the pixel unit of the nth row are turned on, and the charge sharing switch of the pixel cell of the nth row is turned off; when the nth gate line is disabled, the n+th
  • one gate line provides a charge sharing gate scan pulse signal, the charge sharing of the pixel unit in the nth row is opened Turning off; and, when the n+1th gate line is dissipated to provide a shared gate scan pulse signal, the first switch component and the second switch component of the pixel unit of the (n+1)th row are turned on, The charge sharing switch of the pixel unit of the n+1 row is turned off.
  • a further object of the present application is a liquid crystal display panel comprising: a first substrate; a second substrate; a liquid crystal layer formed between the first substrate and the second substrate; and the liquid crystal pixel circuit, Formed on the first substrate or the second substrate.
  • This application can simplify the pixel trace design in charge-sharing pixel design while maintaining charge sharing. Only one gate scan line can be used for gate charge and gate charge sharing simultaneously, reducing gate integrated circuits and The amount of flip chip used, while increasing the pixel aperture ratio. Secondly, the technique of the present application can be applied to a plurality of types of liquid crystal display panels with high applicability.
  • FIG. 1a is a partial schematic structural view of an exemplary liquid crystal pixel circuit.
  • FIG. 1b is a schematic diagram of an equivalent circuit of a pixel unit of an exemplary liquid crystal pixel circuit.
  • FIG. 2a is a partial structural diagram showing a liquid crystal pixel circuit according to an embodiment of the present application.
  • 2b is a schematic diagram showing an equivalent circuit of a pixel unit of a liquid crystal pixel circuit according to an embodiment of the present application.
  • the word “comprising” is to be understood to include the component, but does not exclude any other component.
  • “on” means located above or below the target component, and does not mean that it must be on the top based on the direction of gravity.
  • the liquid crystal display panel to which the liquid crystal pixel circuit of the present application is applied may be a wide-angle liquid crystal display panel.
  • FIG. 1a is a partial structural diagram of an exemplary liquid crystal pixel circuit
  • FIG. 1b is a schematic diagram of an equivalent circuit of a pixel unit of an exemplary liquid crystal pixel circuit.
  • the pixel electrode in order to increase the viewing angle, for example, is designed to have a "m" shape structure.
  • the pixel electrode comprises a strip-shaped vertical stem and a strip-shaped horizontal stem, and the vertical stem and the horizontal stem center intersect perpendicularly, the so-called central vertical intersection is The vertical trunk and the horizontal trunk are perpendicular to each other, and both divide the entire pixel electrode area into four domains equally.
  • Each pixel electrode region is composed of strips of slits (Slit) at an angle of ⁇ 45° and ⁇ 135° to the vertical stem or horizontal stem, and each strip branch is on the same plane as the vertical stem and the horizontal stem.
  • a pixel electrode structure of a "m" shape in which the upper and lower sides and the left and right are mirror-symmetrical as shown in FIG. 1a is formed.
  • the pixel structure of the "meter” type has a certain visual chromatic aberration or visual color shift due to the same angle between the strip branches in each pixel electrode region and the vertical trunk and the horizontal trunk, and the liquid crystal panel is worn. The penetration rate will also drop.
  • the prior art divides one pixel unit into a main pixel 110 area and a sub-pixel 120 area, and sets a separate main pixel 110 electrode in the main pixel 110 area, and sets a sub-pixel 120 area.
  • the independent sub-pixel 120 electrodes, the main pixel 110 electrode and the sub-pixel electrode are both designed in a "meter" shape structure.
  • the liquid crystal pixel circuit shown in FIG. 1b adopts a charge sharing pixel design method in order to achieve a low color shift (LCS) specification.
  • This design divides the pixel unit into two regions, a main pixel 110 (main) and a sub-pixel 120 (sub).
  • the main pixel 110 includes a first switch component T1 electrically coupled to a corresponding data line D(n) and a gate scan charging line GC(n).
  • the sub-pixel 120 includes a second switch component T2 and a charge sharing switch T3.
  • the second switch component T2 is electrically coupled to the corresponding data line D(n) and the gate scan charging line GC(n), and the charge sharing switch T3 is further Connect the gate scan sharing line GS(n) (Gate Share Line).
  • each of the switch components is a Thin Film Transistor TFT component.
  • the gate scan charging line GC(n) When the gate scan charging line GC(n) is turned on, the first switching component T1 and the second switching component T2 charge the main pixel 110 and the sub-pixel 120, respectively.
  • the main pixel 110 is controlled by the gate scanning charging line GC(n), and the data is taken from the data line D(n) (Data Line) by the first switching component T1 and stored in the storage capacitor Cst1; the sub-pixel 120 is also subjected to
  • the control of the gate scan charging line GC(n) takes data from the data line D(n) using the second switching component T2 and stores it in the storage capacitor Cst2.
  • the gate scan charging line GC(n) is turned off, the gate scan sharing line GS(n) (Gate Share Line) is turned on, and the charge sharing switch T3 is turned on to store the stored charge Cst2 and the liquid crystal capacitor Clc2 of the capacitance of the sub-pixel 120.
  • the charge in the shared capacitor Cst3 of the charge sharing switch T3 is redistributed, that is, the sub-pixel 120 is controlled by the gate scan sharing line GS(n) to perform the storage capacitor Cst2 and the storage capacitor Cst3 by using the charge sharing switch T3. Charge sharing.
  • the liquid crystal pixel circuit can appropriately control the ratio of the voltage stored in the storage capacitor Cst1 and the storage capacitor Cst2, thereby driving the liquid crystal capacitor Clc1 and the liquid crystal capacitor Clc2 to be driven by a default voltage, thereby eliminating the color at the time of display. Partial problem. As described above, only one of the structures of the liquid crystal display panel to which the liquid crystal pixel circuit is applied is described as an example. However, the scope of application of the present application is not limited thereto, and it is more applicable to various types of liquid crystal display panels.
  • a liquid crystal pixel circuit includes a plurality of pixel units arranged in a matrix, and each pixel unit 100 is coupled to a corresponding data line D(n) and a gate.
  • the epipolar line G(n) and each pixel unit 100 includes a main pixel 110 and a sub-pixel 120.
  • the main pixel 110 includes: a first switch component The first path end 311 of the first switch component 310 is electrically coupled to the data line D(n), the first The control terminal 313 of the switch component 310 is electrically coupled to the gate line G(n); and the first storage component is electrically coupled to the second via end 312 of the first switch component 310.
  • the sub-pixel 120 includes a second switch component 320 having a first path end 321 , a second path end 322 , and a control end 323 . The control end 323 of the second switch component 320 is electrically coupled to the gate line G.
  • the first path end 321 of the second switch component 320 is electrically coupled to the data line D(n); the second storage component is electrically coupled to the second switch component 320.
  • the second path end 322 has a first path end 331 , a second path end 332 and a control end 333 , and the second path end 332 of the charge sharing switch 330 is electrically coupled to the second switch.
  • the second path end 322 of the component 320 and the third storage component are electrically coupled to the first path end 331 of the charge sharing switch 330.
  • the control terminal 313 of the first switch component 310 of the pixel unit of the n+1th row, the control terminal 323 of the second switch component 320, and the charge sharing switch of the pixel unit of the nth row The control terminal 333 of the 330 is electrically coupled to the n+1th gate line G(n+1). That is, the n+1th gate line G(n+1) is the gate scan sharing line GS of the pixel unit of the nth row, and the gate scan charging of the pixel unit of the n+1th row Can line GS.
  • the first storage component includes a first liquid crystal capacitor 314 and a first storage capacitor 315, and the first storage component is connected to the second path end 312 of the first switch component 310. Between the shared voltage CL (Common Line).
  • the second storage component includes a second liquid crystal capacitor 324 and a second storage capacitor 325, and the second storage component is connected to the second path end 322 of the second switch component 320. Sharing voltage between CL.
  • the third storage component includes a third storage capacitor 335, and the third storage component is connected between the first path end 331 of the charge sharing switch 330 and the shared voltage CL.
  • control signals provided by the nth gate line G(n) and the n+1th gate line G(n+1) are enabled at different times.
  • the nth gate line G(n) is the gate scan charging line GC(n) to provide a gate scan pulse signal
  • the n+1th gate line G(n+1) is the gate scan share line GS(n) to provide a charge sharing gate scan pulse signal
  • the gate scan pulse signal is equal to a pulse width of the charge sharing gate scan pulse signal.
  • the gate scan pulse signal is one pulse width ahead of the charge share gate scan pulse signal.
  • a pixel driving method in which each pixel unit 100 is arranged in a matrix and coupled to a corresponding data line D(n) and a gate line G(n), and the pixel driving method includes :
  • the first switch component 310 and the second switch component 320 of the pixel unit of the nth row are turned on, and the charge sharing switch of the pixel unit of the nth row is turned on. 330 closed;
  • the n+1th gate line G(n+1) provides a charge sharing gate scan pulse signal, and the charge sharing of the pixel unit in the nth row Switch 330 is open;
  • the first switch component 310 and the second switch component 320 of the pixel unit of the n+1th row Turning on, the charge sharing switch 330 of the pixel unit of the (n+1)th row is turned off.
  • a liquid crystal display panel includes: a first substrate; a second substrate; a liquid crystal layer formed between the first substrate and the second substrate; And the liquid crystal pixel circuit is formed on the first substrate or the second substrate.
  • the liquid crystal pixel circuit can be applied, for example, to a curved display panel.
  • This application can simplify the pixel routing design in charge-sharing pixel design without significantly changing the existing production process and maintaining the charge sharing. Only one gate scan line can be used for gate charging and gate charge sharing. , reducing the amount of use of the gate integrated circuit and the flip chip, while increasing the pixel aperture ratio. Secondly, the technique of the present application can be applied to a plurality of types of liquid crystal display panels with high applicability.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶像素电路及其驱动方法与液晶显示面板，液晶像素电路包括多个以矩阵方式排列的像素单元（100），每一像素单元（100）耦接相应的数据线（D(n)）与栅极线（G(n), G(n+1)）；每一像素单元（100）包括分布在主、子像素区域（110, 120），并与数据线（D(n)）与栅极线（G(n), G(n+1)）电性耦接的第一开关组件（310）、第二开关组件（320）与电荷分享开关（330）；其中，第n+1行像素单元（100）的第一开关组件（310）的控制端（313）、第二开关组件（320）的控制端（323）与第n行像素单元（100）的电荷分享开关（330）的控制端（333）电性耦接至第n+1条栅极线（G(n+1)）；驱动方法用以驱动液晶像素电路。

Description

液晶像素电路及其驱动方法与液晶显示面板 技术领域
本申请涉及一种液晶像素电路及其驱动方法，尤其涉及一种主、子像素采用共享栅极线路的液晶像素电路及其驱动方法与液晶显示面板。
背景技术
在液晶显示器中，有时为达到低色偏(Low Color Shift，LCS)的规格，会采用一种采取电荷分享式的(Charge Sharing)画素设计方式。此方式是使像素单元中的多个电容在彼此之间进行电荷分享，是一种为了解决色偏问题而衍生出来的技术。
此种设计方式将像素单元分为主像素(Main)与子像素(Sub)两区域。主像素包括第一开关组件，电性耦接相对应的数据线与栅极扫描充能线(Gate Charge Line)。子像素包括第二开关组件及电荷共享开关，第二开关组件电性耦接相对应的数据线与栅极扫描充能线，电荷共享开关还连接栅极扫描分享线(Gate Share Line)，此等开关组件一般为薄膜晶体管(Thin Film Transistor，TFT)组件。
当栅极扫描充能线开启时，第一、二开关组件分别对主像素与子像素充电。之后，栅极扫描充能线关闭，栅极扫描分享线开启。此时电荷共享开关打开将子像素的电容的电荷与电荷共享开关的共享电容中的电荷做重新分布，最后使主像素与子像素的电位重新分配而达到低色偏的效果。
一般设计是将栅极扫描充能线与栅极扫描分享线的信号走线独立控制，如需关闭电荷分享功能时可将栅极扫描分享线关闭(像是切换至低电压，如VGL)使电荷共享开关关闭。
但此方式会增加约一倍栅极集成电路(Gate IC)与覆晶薄膜(Chip On Flex，Chip On Film，COF)使用量。而且栅极扫描分享线所占面积相对较高，进而会降低像素开口率。
发明内容
为了解决上述技术问题，本申请的目的在于，提供一种采用共享栅极线路且维持电荷共享的液晶像素电路及其驱动方法与液晶显示面板。
本申请的目的及解决其技术问题是采用以下技术方案来实现的。依据本申请提出的一种液晶像素电路，包括：多个以矩阵方式排列的像素单元，每一像素单元耦接相应的数据线与栅极线，且每一像素包括：主像素，包括：第一开关组件，具有第一通路端、第二通路端及控制端，所述第一开关组件的第一通路端电性耦接至所述数据线，所述第一开关组件的控制端电性耦接至所述栅极线；及，第一储存组件，电性耦接至所述第一开关组件的第二通路端；以及，子像素，包括：第二开关组件，具有第一通路端、第二通路端及控制端，所述第二开关组件的控制端电性耦接至所述栅极线， 所述第二开关组件的第一通路端电性耦接至所述数据线；第二储存组件，电性耦接至所述第二开关组件的第二通路端；电荷分享开关，具有第一通路端、第二通路端及控制端，且所述电荷分享开关的第二通路端电性耦接至所述第二开关组件的第二通路端；及，第三储存组件，电性耦接至所述电荷分享开关的第一通路端；其中，第n+1行所述像素单元的所述第一开关组件的控制端、所述第二开关组件的控制端、与第n行所述像素单元的所述电荷分享开关的控制端是电性耦接至第n+1条栅极线。
本申请解决其技术问题还可采用以下技术措施进一步实现。
在本申请的一实施例中，第n条栅极线及所述第n+1条栅极线提供的控制信号是在不同时间使能。
在本申请的一实施例中，第n条栅极线为所述栅极扫描充能线以提供栅极扫描脉冲信号，所述第n+1条栅极线为栅极扫描分享线以提供电荷分享栅极扫描脉冲信号。
在本申请的一实施例中，所述栅极扫描脉冲信号与所述电荷分享栅极扫描脉冲信号的脉冲宽度相等。
在本申请的一实施例中，所述栅极扫描脉冲信号比所述电荷分享栅极扫描脉冲信号提前一个脉冲宽度。
在本申请的一实施例中，所述第n条栅极线提供栅极扫描脉冲信号，第n行所述像素单元的所述第一开关组件与所述第二开关组件打开，电荷分享开关关闭；所述第n条栅极线消能，所述第n+1条栅极线提供电荷分享栅极扫描脉冲信号时，第n行所述像素单元的所述电荷分享开关打开；所述第n+1条栅极线消能后提供分享栅极扫描脉冲信号时，第n+1行所述像素单元的所述第一开关组件与所述第二开关组件打开，第n+1行所述像素单元的所述电荷分享开关关闭。
在本申请的一实施例中，所述第一储存组件包括第一液晶电容与第一储存电容，所述第一储存组件接于所述第一开关组件的第二通路端与共享电压之间。
在本申请的一实施例中，所述第二储存组件包括第二液晶电容与第二储存电容，所述第二储存组件接于所述第二开关组件的第二通路端与共享电压之间。
在本申请的一实施例中，所述第三储存组件包括第三储存电容，所述第三储存组件接于所述电荷分享开关的第一通路端与共享电压之间。
本申请的另一目的为一种像素驱动方法，每一像素单元以矩阵方式排列并耦接相应的数据线与栅极线，所述驱动方法包括：当第n条栅极线提供栅极扫描脉冲信号，第n行所述像素单元的第一开关组件与第二开关组件打开，第n行所述像素单元的电荷分享开关关闭；当所述第n条栅极线消能，第n+1条栅极线提供电荷分享栅极扫描脉冲信号时，第n行所述像素单元的电荷分享开 关打开；以及，当所述第n+1条栅极线消能后提供分享栅极扫描脉冲信号时，第n+1行所述像素单元的第一开关组件与第二开关组件打开，第n+1行所述像素单元的电荷分享开关关闭。
本申请的又一目的为一种液晶显示面板，包括：第一基板；第二基板；液晶层，形成于所述第一基板及所述第二基板之间；以及所述的液晶像素电路，形成于所述第一基板或所述第二基板上。
有益效果
本申请可以在维持电荷共享的前提，于电荷分享式的画素设计时简化像素走线设计，仅利用一条栅极扫描线同时做到栅极充能与栅极电荷分享，减少栅极集成电路与覆晶薄膜使用量，同时增加像素开口率。其次此本申请技术可使用于多种类型的液晶显示面板的制程中，适用性较高。
附图说明
图1a为范例性的液晶像素电路的局部结构示意图。
图1b为范例性的液晶像素电路的像素单元等效电路示意图。
图2a为显示本申请一实施例的液晶像素电路的局部结构示意图。
图2b为显示本申请一实施例的液晶像素电路的像素单元等效电路示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本申请为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本申请提出的一种液晶像素电路及其驱动方法与液晶显示面板，其具体实施方式、结构、特征及其功效，详细说明如后。
在一些实施例中，本申请的液晶像素电路所适用的液晶显示面板可为广角型液晶显示面板。
图1a为范例性的液晶像素电路的局部结构示意图，图1b为范例性的液晶像素电路的像素单元等效电路示意图。如图1a，为了增大视角，例如将像素电极设计为“米”字型结构。像素电极包含条状的竖直主干和条状的水平主干，且竖直主干和水平主干中心垂直相交，所谓中心垂直相交是 指竖直主干和水平主干相互垂直，且二者将整个像素电极面积平均分成4个区域(domain)。每个像素电极区域都由与竖直主干或水平主干呈±45°、±135°角度的条状分支(Slit)平铺组成，各条状分支与竖直主干和水平主干位于同一平面上，形成图1a所示的上下和左右均镜像对称的“米”字型的像素电极结构。这种“米”字型的像素电极结构，因每一像素电极区域内的条状分支与竖直主干和水平主干的夹角相同，会存在一定的视觉色差或视觉色偏，液晶面板的穿透率也会下降。为了改善视觉色差或视觉色偏，现有技术会将一个像素单元分成主像素110区域和子像素120区域，在主像素110区域内设置一个独立的主像素110电极、在子像素120区域内设置一个独立的子像素120电极，主像素110电极与次像素电极均采用“米”字型结构设计。
如图1b所示的液晶像素电路，为了达到低色偏(Low color shift，LCS)的规格，例如采取电荷分享式的(charge sharing)画素设计方式。此种设计方式将像素单元分为主像素110(main)与子像素120(sub)两区域。主像素110包括第一开关组件T1，电性耦接相对应的数据线D(n)与栅极扫描充能线GC(n)(Gate Charge Line)。子像素120包括第二开关组件T2及电荷共享开关T3，第二开关组件T2电性耦接相对应的数据线D(n)与栅极扫描充能线GC(n)，电荷共享开关T3还连接栅极扫描分享线GS(n)(Gate Share Line)。在一些实施例中，各开关组件为薄膜晶体管(Thin Film Transistor TFT)组件。
当栅极扫描充能线GC(n)开启时，第一开关组件T1、第二开关组件T2分别对主像素110与子像素120充电。主像素110受到栅极扫描充能线GC(n)的控制，利用第一开关组件T1从数据线D(n)(Data Line)取得数据并储存到储存电容Cst1之中；子像素120同样受到栅极扫描充能线GC(n)的控制，利用第二开关组件T2从数据线D(n)取得数据并储存到储存电容Cst2。之后，栅极扫描充能线GC(n)关闭，栅极扫描分享线GS(n)(Gate Share Line)开启，电荷共享开关T3打开以将子像素120的电容的储存电荷Cst2及液晶电容Clc2与电荷共享开关T3的共享电容Cst3中的电荷做重新分布，即是指子像素120受到栅极扫描分享线GS(n)的控制，以利用电荷共享开关T3使储存电容Cst2与储存电容Cst3进行电荷分享。藉由此种架构，液晶像素电路可以适当控制储存电容Cst1与储存电容Cst2所储存的电压的比例，以藉此使液晶电容Clc1与液晶电容Clc2受到默认的电压驱动，进而得以消除显示时的色偏问题。以上所述，仅是液晶像素电路所适用的液晶显示面板其中一结构为例来作一说明，但本申请的应用范围并不仅限于此，其更可应用于各类型的液晶显示面板。
图2a为显示本申请一实施例的液晶像素电路的局部结构示意图，图2b为显示本申请一实施例的液晶像素电路的像素单元等效电路示意图。请参照图2a及图2b，在本申请一实施例中，一种液晶像素电路，包括多个以矩阵方式排列的像素单元，每一像素单元100耦接相应的数据线D(n)与栅极线G(n)，且每一像素单元100包括主像素110与子像素120。主像素110包括：第一开关组件 310，具有第一通路端311、第二通路端312及控制端313，所述第一开关组件310的第一通路端311电性耦接至所述数据线D(n)，所述第一开关组件310的控制端313电性耦接至所述栅极线G(n)；及第一储存组件，电性耦接至所述第一开关组件310的第二通路端312。子像素120包括：第二开关组件320，具有第一通路端321、第二通路端322及控制端323，所述第二开关组件320的控制端323电性耦接至所述栅极线G(n)，所述第二开关组件320的第一通路端321电性耦接至所述数据线D(n)；第二储存组件，电性耦接至所述第二开关组件320的第二通路端322；电荷分享开关330，具有第一通路端331、第二通路端332及控制端333，且所述电荷分享开关330的第二通路端332电性耦接至所述第二开关组件320的第二通路端322；及第三储存组件，电性耦接至所述电荷分享开关330的第一通路端331。其中，第n+1行所述像素单元的所述第一开关组件310的控制端313、所述第二开关组件320的控制端323、与第n行所述像素单元的所述电荷分享开关330的控制端333是电性耦接至第n+1条栅极线G(n+1)。即是指，第n+1条栅极线G(n+1)是为第n行所述像素单元的栅极扫描分享线GS，与第n+1行所述像素单元的栅极扫描充能线GS。
在本申请的一实施例中，所述第一储存组件包括第一液晶电容314与第一储存电容315，所述第一储存组件接于所述第一开关组件310的第二通路端312与共享电压CL(Common Line)之间。
在本申请的一实施例中，所述第二储存组件包括第二液晶电容324与第二储存电容325，所述第二储存组件接于所述第二开关组件320的第二通路端322与共享电压CL之间。
在本申请的一实施例中，所述第三储存组件包括第三储存电容335，所述第三储存组件接于所述电荷分享开关330的第一通路端331与共享电压CL之间。
在本申请的一实施例中，第n条栅极线G(n)及所述第n+1条栅极线G(n+1)提供的控制信号是在不同时间使能。
在本申请的一实施例中，第n条栅极线G(n)为所述栅极扫描充能线GC(n)以提供栅极扫描脉冲信号，所述第n+1条栅极线G(n+1)为栅极扫描分享线GS(n)以提供电荷分享栅极扫描脉冲信号。
在本申请的一实施例中，所述栅极扫描脉冲信号与所述电荷分享栅极扫描脉冲信号的脉冲宽度相等。
在本申请的一实施例中，所述栅极扫描脉冲信号比所述电荷分享栅极扫描脉冲信号提前一个脉冲宽度。
在本申请的一实施例中，一种像素驱动方法，每一像素单元100以矩阵方式排列并耦接相应的数据线D(n)与栅极线G(n)，所述像素驱动方法包括：
当第n条栅极线G(n)提供栅极扫描脉冲信号，第n行所述像素单元的第一开关组件310与第二开关组件320打开，第n行所述像素单元的电荷分享开关330关闭；
当所述第n条栅极线G(n)消能，第n+1条栅极线G(n+1)提供电荷分享栅极扫描脉冲信号时，第n行所述像素单元的电荷分享开关330打开；以及
当所述第n+1条栅极线G(n+1)消能后提供分享栅极扫描脉冲信号时，第n+1行所述像素单元的第一开关组件310与第二开关组件320打开，第n+1行所述像素单元的电荷分享开关330关闭。
请再参考图2a和图2b，在一实施例中，一种液晶显示面板，包括：第一基板；第二基板；液晶层，形成于所述第一基板及所述第二基板之间；以及所述的液晶像素电路，形成于所述第一基板或所述第二基板上。
在一些实施例中，液晶像素电路可例如应用于曲面显示面板上。
本申请可以不大幅改变现有生产流程且维持电荷共享的前提，于电荷分享式的画素设计时简化像素走线设计，仅利用一条栅极扫描线同时做到栅极充能与栅极电荷分享，减少栅极集成电路与覆晶薄膜使用量，同时增加像素开口率。其次此本申请技术可使用于多种类型的液晶显示面板的制程中，适用性较高。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。此用语通常不是指相同的实施例；但它也可以是指相同的实施例。“包含”、“具有”及“包括”等用词是同义词，除非其前后文意显示出其它意思。
以上所述，仅是本申请的较佳实施例而已，并非对本申请作任何形式上的限制，虽然本申请已以较佳实施例揭露如上，然而并非用以限定本申请，任何熟悉本专业的技术人员，在不脱离本申请技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本申请技术方案的范围内。

Claims (16)

  1. 一种液晶像素电路，包括：
    多个以矩阵方式排列的像素单元，每一像素耦接相应的数据线与栅极线，且每一像素单元包括：
    主像素，包括：
    第一开关组件，具有第一通路端、第二通路端及控制端，所述第一开关组件的第一通路端电性耦接至所述数据线，所述第一开关组件的控制端电性耦接至所述栅极线；及
    第一储存组件，电性耦接至所述第一开关组件的第二通路端；以及
    子像素，包括：
    第二开关组件，具有第一通路端、第二通路端及控制端，所述第二开关组件的控制端电性耦接至所述栅极线，所述第二开关组件的第一通路端电性耦接至所述数据线；
    第二储存组件，电性耦接至所述第二开关组件的第二通路端；
    电荷分享开关，具有第一通路端、第二通路端及控制端，且所述电荷分享开关的第二通路端电性耦接至所述第二开关组件的第二通路端；及
    第三储存组件，电性耦接至所述电荷分享开关的第一通路端；
    其中，第n+1行所述像素单元的所述第一开关组件的控制端、所述第二开关组件的控制端、与第n行所述像素单元的所述电荷分享开关的控制端是电性耦接至第n+1条栅极线。
  2. 如权利要求1所述的液晶像素电路，其中，第n条栅极线及所述第n+1条栅极线提供的控制信号是在不同时间使能。
  3. 如权利要求1所述的液晶像素电路，其中，第n条栅极线为栅极扫描充能线以提供栅极扫描脉冲信号，所述第n+1条栅极线为栅极扫描分享线以提供电荷分享栅极扫描脉冲信号。
  4. 如权利要求3所述的液晶像素电路，其中所述栅极扫描脉冲信号与所述电荷分享栅极扫描脉冲信号的脉冲宽度相等。
  5. 如权利要求3所述的液晶像素电路，其中所述栅极扫描脉冲信号比所述电荷分享栅极扫描脉冲信号提前一个脉冲宽度。
  6. 如权利要求3所述的液晶像素电路，其中所述第n条栅极线提供栅极扫描脉冲信号，第n行所述像素单元的所述第一开关组件与所述第二开关组件打开，电荷分享开关关闭。
  7. 如权利要求3所述的液晶像素电路，其中所述第n条栅极线消能，所述第n+1条栅极线提供电荷分享栅极扫描脉冲信号时，第n行所述像素单元的所述电荷分享开关打开。
  8. 如权利要求3所述的液晶像素电路，其中所述第n+1条栅极线消能后提供分享栅极扫描脉冲信号时，第n+1行所述像素单元的所述第一开关组件与所述第二开关组件打开，第n+1行所述像素 单元的所述电荷分享开关关闭。
  9. 如权利要求1所述的液晶像素电路，其中所述第一储存组件包括第一液晶电容与第一储存电容，所述第一储存组件接于所述第一开关组件的第二通路端与共享电压之间。
  10. 如权利要求1所述的液晶像素电路，其中所述第二储存组件包括第二液晶电容与第二储存电容，所述第二储存组件接于所述第二开关组件的第二通路端与共享电压之间。
  11. 如权利要求1所述的液晶像素电路，其中所述第三储存组件包括第三储存电容，所述第三储存组件接于所述电荷分享开关的第一通路端与共享电压之间。
  12. 一种像素驱动方法，每一像素单元以矩阵方式排列并耦接相应的数据线与栅极线，所述像素驱动方法包括：
    当第n条栅极线提供栅极扫描脉冲信号，第n行所述像素单元的第一开关组件与第二开关组件打开，第n行所述像素单元的电荷分享开关关闭；
    当所述第n条栅极线消能，第n+1条栅极线提供电荷分享栅极扫描脉冲信号时，第n行所述像素单元的电荷分享开关打开；以及
    当所述第n+1条栅极线消能后提供分享栅极扫描脉冲信号时，第n+1行所述像素单元的第一开关组件与第二开关组件打开，第n+1行所述像素单元的电荷分享开关关闭。
  13. 一种液晶显示面板，包括：
    第一基板；
    第二基板；
    液晶层，形成于所述第一基板及所述第二基板之间；以及
    液晶像素电路，包括：
    多个以矩阵方式排列的像素单元，每一像素耦接相应的数据线与栅极线，且每一像素单元包括：
    主像素，包括：
    第一开关组件，具有第一通路端、第二通路端及控制端，所述第一开关组件的第一通路端电性耦接至所述数据线，所述第一开关组件的控制端电性耦接至所述栅极线；及
    第一储存组件，电性耦接至所述第一开关组件的第二通路端；以及
    子像素，包括：
    第二开关组件，具有第一通路端、第二通路端及控制端，所述第二开关组件的控制端电性耦接至所述栅极线，所述第二开关组件的第一通路端电性耦接至所述数据线；
    第二储存组件，电性耦接至所述第二开关组件的第二通路端；
    电荷分享开关，具有第一通路端、第二通路端及控制端，且所述电荷分享开关的第二通路端电性耦接至所述第二开关组件的第二通路端；及
    第三储存组件，电性耦接至所述电荷分享开关的第一通路端；
    其中，第n+1行所述像素单元的所述第一开关组件的控制端、所述第二开关组件的控制端、与第n行所述像素单元的所述电荷分享开关的控制端是电性耦接至第n+1条栅极线；
    其中，所述液晶像素电路形成于所述第一基板或所述第二基板上。
  14. 如权利要求13所述的液晶显示面板，其中所述第一储存组件包括第一液晶电容与第一储存电容，所述第一储存组件接于所述第一开关组件的第二通路端与共享电压之间。
  15. 如权利要求13所述的液晶显示面板，其中所述第二储存组件包括第二液晶电容与第二储存电容，所述第二储存组件接于所述第二开关组件的第二通路端与共享电压之间。
  16. 如权利要求13所述的液晶显示面板，其中所述第三储存组件包括第三储存电容，所述第三储存组件接于所述电荷分享开关的第一通路端与共享电压之间。
PCT/CN2017/086642 2017-05-05 2017-05-31 液晶像素电路及其驱动方法与液晶显示面板 WO2018201546A1 (zh)

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