WO2018196498A1 - 一种biss协议数据解码方法及接口系统 - Google Patents

一种biss协议数据解码方法及接口系统 Download PDF

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Publication number
WO2018196498A1
WO2018196498A1 PCT/CN2018/078940 CN2018078940W WO2018196498A1 WO 2018196498 A1 WO2018196498 A1 WO 2018196498A1 CN 2018078940 W CN2018078940 W CN 2018078940W WO 2018196498 A1 WO2018196498 A1 WO 2018196498A1
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WIPO (PCT)
Prior art keywords
signal
module
data
crc check
receiving
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PCT/CN2018/078940
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English (en)
French (fr)
Inventor
王晗
张芳健
陈新
陈新度
蔡念
贺云波
赵翼翔
林灿然
辛正一
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广东工业大学
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Priority to US16/333,245 priority Critical patent/US10833805B2/en
Publication of WO2018196498A1 publication Critical patent/WO2018196498A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
    • G01D5/32—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light
    • G01D5/34—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells

Definitions

  • the invention relates to the field of data decoding of the BISS protocol, in particular to a BISS protocol data decoding method and an interface system.
  • the grating ruler is the core component of the position measuring device.
  • the grating ruler is a high-precision line displacement sensor. It uses a high-precision long grating as a measurement reference, and uses an optical sensor to convert an optical signal into an electrical signal, and processes the electrical signal to finally obtain position information.
  • the grating scale Compared with other line displacement sensors (such as magnetic grids, ball grids, laser interferometers, etc.), the grating scale has a high comprehensive advantage in terms of measurement accuracy, resolution, reliability, requirements for the application environment, and price. Therefore, the grating scale has a very wide range of applications in digital display, numerical control machine tools and measuring instruments. According to the different measuring methods, the grating scale can be divided into an incremental grating scale and an absolute grating scale.
  • the absolute scale is obtained by reading the position code to obtain absolute position information. Each time the power is turned on, the absolute scale can read the current position code without the “zeroing” operation, and immediately obtain the absolute position information of each axis of the current machine tool, so that it can immediately enter the machining state or continue the last operation, improving the machine tool. Processing efficiency.
  • the application of absolute grating scales on CNC machine tools has been rapidly promoted and has become a trend of mainstream applications. Therefore, it is necessary to develop a data interface that can adapt to the data reception requirements of absolute grating scales such as high speed, large data volume, and high stability.
  • the BISS (Bidirectional Synchronous Serial) protocol is a new type of freely usable synchronous serial communication protocol proposed by the German IC-Haus company.
  • the BISS protocol baud rate can be selected in a range of up to 10MHz, higher than other commonly used communication protocols (such as SSI, EnDat, Hiperface, etc.), with alarm bits, adjustable protocol length, and its industrial application. Better, and there is no agreement on property rights.
  • the main port measures and automatically compensates for the transmission delay of the line, allowing the communication interface to use high-speed data transmission; allowing the sensor to have data acquisition and data processing time (delayed transmission); only two signal lines MA and SL are included.
  • the BISS protocol includes two modes: Sensor Mode (Senor Mode) and Register Mode.
  • the sensor mode begins to cause the interface to quickly read information such as the position value of the corresponding encoder.
  • the register allows the interface to perform bidirectional read and write operations with the encoder to obtain the information needed by the interface.
  • the mode selection is mainly based on the length of the first low level of the MA line in the communication cycle. The time greater than "timeoutSENS" indicates that the register model communication will be performed next. The time is less than "timeoutSENS” indicating that the sensor will be executed next. Mode communication.
  • the data reception of the interface here mainly uses the sensor mode.
  • the commonly used decoding method of the BISS protocol is carried out by the IC-Haus official chip BISS Mater, MCU or FPGA.
  • the application of the official chip BISS Mater method has higher cost and less data processing flexibility, and it is not easy to personalize the expansion of the module function; the data decoding of the single-chip microcomputer is often subject to the performance of the single-chip microcomputer; and some of today's use of FPGA decoding achieves There are still gaps in the function.
  • the embodiment of the invention provides a BISS protocol data decoding method and an interface system, which solves the technical problem that the data processing flexibility commonly used in the BISS protocol for the absolute scale is insufficient and the function is achieved.
  • FPGA chip FPGA chip includes MA drive module, SL receiving module, CRC check module;
  • the method step includes: the MA driving module receives the enable signal en, sends the MA clock signal to the SL receiving module, and the SL receiving module starts detecting the arrival of the trigger signal of the SL;
  • the SL receiving module When the SL receiving module detects that the start bit of the SL arrives, it starts to read the SL data, and after the SL data is read, sends a done signal to the MA driving module to stop the MA driving module and issue a did signal to the CRC check module;
  • the CRC check module After receiving the did signal, the CRC check module performs CRC check on the SL data and outputs the correct position value after the check is completed.
  • the MA driving module receives the enable signal en, sends the MA clock signal to the SL receiving module, and the arrival of the trigger signal of the SL receiving module to start detecting the SL includes:
  • the MA driving module receives the enable signal en, and sends the MA clock signal to the SL receiving module.
  • the SL receiving module generates a maclk signal according to the time difference between the MA clock signal and the SL signal, and starts detecting the arrival of the SL trigger signal by using the rising edge of the maclk signal. .
  • the SL receiving module generates a maclk signal according to a time difference between the MA clock signal and the SL signal, and starts detecting the trigger signal of the SL by using a rising edge of the maclk signal, including:
  • the SL receiving module generates a maclk signal according to a time difference between the second rising edge of the MA clock signal and the first falling edge of the SL signal, and starts detecting the arrival of the SL trigger signal by using the rising edge of the maclk signal.
  • the SL receiving module starts to read the SL data when detecting the start bit of the SL, and sends a done signal to the MA driving module after the SL data is read, stops the MA driving module, and issues a did signal to the CRC check.
  • Modules include:
  • the SL receiving module When the SL receiving module detects that the start bit of the SL arrives, it starts to read the level value of the SL and stores the level value in the register, and sends a done signal to the MA after reading all the bits of the level value of the SL.
  • the drive module stops the MA drive module and issues a did signal to the CRC check module.
  • the CRC check module performs a CRC check on the SL data, and outputs the correct position value after the check is completed, including:
  • the CRC check module After receiving the did signal, the CRC check module performs CRC check on the correctness of the SL data, and outputs SL data that can pass the check after the check is completed, and outputs the correct one for the SL data that cannot pass the check. Data value.
  • An FPGA chip the FPGA chip is connected to the encoder;
  • the FPGA chip includes a MA driving module, an SL receiving module, and a CRC check module;
  • the MA driving module is connected to the SL receiving module, and the SL module is also connected to the CRC check module;
  • the MA driving module is configured to receive the enable signal en, and send the MA clock signal to the SL receiving module;
  • the SL receiving module is configured to start the detection of the trigger signal of the SL after acquiring the MA clock signal, and start to read the SL data when the start bit of the SL is detected, and issue a done signal to the MA driver after reading the SL data.
  • the module stops the MA driving module and issues a did signal to the CRC check module;
  • the CRC check module is configured to perform CRC check on the SL data after receiving the did signal, and output the correct position value after the check is completed.
  • the SL receiving module includes:
  • the signal generating unit is configured to generate a maclk signal according to a time difference between the MA clock signal and the SL signal, and start detecting the arrival of the trigger signal of the SL by using a rising edge of the maclk signal.
  • the signal generating unit comprises:
  • the signal generating sub-unit is configured to generate a maclk signal according to a time difference between a second rising edge of the MA clock signal and a first falling edge of the SL signal, and start detecting the arrival of the SL trigger signal by using a rising edge of the maclk signal.
  • the SL receiving module further includes:
  • the reading unit is configured to start reading the level value of the SL and store the level value in the register when the start bit of the SL is detected, and issue a done after reading all the digits of the level value of the SL.
  • the signal to MA drive module stops the MA drive module and issues a did signal to the CRC check module.
  • the CRC check module includes:
  • the verification unit is configured to perform CRC check on the correctness of the SL data after receiving the did signal, and output the SL data that can pass the verification after the verification is completed, and output the correct one for the SL data that cannot pass the verification. Data value.
  • the BISS protocol data decoding method and interface system includes: an FPGA chip, the FPGA chip includes an MA driving module, an SL receiving module, and a CRC check module; and the method steps include: the MA driving module receives the enabling signal En, sends the MA clock signal to the SL receiving module, and the SL receiving module starts detecting the arrival of the trigger signal of the SL; the SL receiving module starts to read the SL data when detecting the start bit of the SL, and after reading the SL data Send the done signal to the MA driver module to stop the MA driver module and issue the did signal to the CRC check module; after receiving the did signal, the CRC check module performs CRC check on the SL data and outputs the correct position after the verification is completed.
  • the protocol of the absolute scale based on the BISS protocol is decoded by using the FPGA chip, and the MA driving module, the SL receiving module, and the CRC check module are set in the FPGA chip, and the data length is added.
  • Time adjustment, CRC check and other functions, while enabling the interface system provided in the embodiment of the present invention to perform high speed, large data volume, high stability data connection Can effectively adapt to the absolute information transmission grating, the prior art to solve the lack of a single and reached for the adaptation absolute encoders BISS protocol commonly used way of decoding data processing flexibility features technical problems.
  • FIG. 1 is a schematic flowchart diagram of an embodiment of a BISS protocol data decoding method according to an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart diagram of another embodiment of a BISS protocol data decoding method according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing the external overall structure connection of a BISS protocol data decoding interface system according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of an FPGA module according to an embodiment of the present invention.
  • FIG. 5 is a state transition diagram of a MA driving module according to an embodiment of the present invention.
  • FIG. 6 is a state transition diagram of a SL receiving module according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a BISS protocol data decoding interface system according to an embodiment of the present invention.
  • the embodiment of the present invention provides a BISS protocol data decoding method and an interface system, which are used to solve the technical problem that the data processing flexibility commonly used in the BISS protocol for the absolute scale is insufficient and the function is achieved. .
  • a BISS protocol data decoding method provided by an embodiment of the present invention includes:
  • FPGA chip FPGA chip includes MA drive module, SL receiving module, CRC check module;
  • the method steps include: 101.
  • the MA driving module receives the enable signal en, sends an MA clock signal to the SL receiving module, and the SL receiving module starts detecting the arrival of the trigger signal of the SL;
  • the MA driver module receives the enable signal en, sends the MA clock signal to the SL receiver module, and the SL receiver module begins to detect the arrival of the SL trigger signal.
  • the SL receiving module detects that the start bit of the SL arrives, it starts to read the SL data, and after the SL data is read, sends a done signal to the MA driving module to stop the MA driving module and issue a did signal to the CRC check module;
  • the SL receiving module When the SL receiving module detects that the start bit of the SL arrives, it starts to read the SL data, and after the SL data is read, sends a done signal to the MA driving module to stop the MA driving module and issue a did signal to the CRC check module.
  • the CRC check module After receiving the did signal, the CRC check module performs a CRC check on the SL data, and outputs a correct position value after the verification ends.
  • the CRC check module After the CRC check module receives the did signal, the CRC check is performed on the SL data, and the correct position value is output after the check is completed.
  • FIG. 2 another embodiment of a BISS protocol data decoding method according to an embodiment of the present invention includes:
  • the MA driving module receives the enable signal en, and sends the MA clock signal to the SL receiving module.
  • the SL receiving module generates a maclk signal according to the time difference between the MA clock signal and the SL signal, and starts detecting the trigger signal of the SL by using the rising edge of the maclk signal. 's arrival
  • the MA driving module When the MA driving module receives the enable signal en, the MA clock signal is sent to the SL receiving module, and the SL receiving module generates a maclk signal according to the time difference between the MA clock signal and the SL signal, and starts detecting the trigger signal of the SL by using the rising edge of the maclk signal. 's arrival
  • the SL receiving module generates a maclk signal according to a time difference between a second rising edge of the MA clock signal and a first falling edge of the SL signal, and starts detecting the arrival of the trigger signal of the SL by using a rising edge of the maclk signal.
  • the SL receiving module can generate a maclk signal according to the time difference between the second rising edge of the MA clock signal and the first falling edge of the SL signal, and start detecting using the rising edge of the maclk signal. The arrival of the SL trigger signal.
  • the SL receiving module detects that the start bit of the SL arrives, it starts to read the level value of the SL and stores the level value in the register, and sends a done signal after reading all the digits of the level value of the SL.
  • the MA drive module stops the MA drive module and issues a did signal to the CRC check module.
  • the SL receiving module When the SL receiving module detects the arrival of the start bit of the SL, it starts to read the level value of the SL and stores the level value in the register, and after the reading of all the digits of the level value of the SL, the done signal is sent to The MA driver module stops the MA driver module and issues a did signal to the CRC check module.
  • the CRC check module After receiving the did signal, the CRC check module performs CRC check on the correctness of the SL data, and outputs SL data that can pass the check after the check is finished, and outputs the previous SL data that cannot pass the check. The correct data value.
  • the CRC check module After receiving the did signal sent by the SL receiving module, the CRC check module performs CRC check on the correctness of the SL data, and outputs SL data that can pass the check after the verification is completed, and the SL data that cannot pass the check is performed. Output the correct data value.
  • FIG. 3 is a schematic diagram of the external overall structure connection of a BISS protocol data decoding interface system according to an embodiment of the present invention.
  • the encoder absolute scale readhead
  • the differential circuit which is passed through the differential circuit to the FPGA chip.
  • the BISS sensor mode is used for communication here.
  • the signal of the absolute scale readhead usually uses differential information transmission, and the differential receiving circuit can make the information transmission more stable.
  • the SL signal is differentially processed, it is read from the absolute scale, and the differential chip-based inverse differential circuit receives and restores the signal to the SL signal required by the FPGA.
  • the MA signal is sent from the FPGA pin and processed by the differential circuit to be sent to the scale reading head.
  • One of the input pins of the FPGA controls whether the interface control module starts to work. When the interface control module works and derives the position value, it sends the information to the subsequent module.
  • the FPGA can be designed as a MA driver module, a SL receiver module, and a CRC check module.
  • the data interface part is used as a control part to cause the module to send a pulse as a clock for the encoder to transmit data.
  • the BISS protocol can flexibly adjust the total length of a data transmission period according to actual needs. The total time of each data transmission may be different. The specific required time is determined by the encoder.
  • the MA driving module and the SL receiving module are matched by the MA line and the done line, wherein the MA signal is controlled by the MA driving module; the done signal is controlled by the SL receiving module, and sent by the SL receiving module to the MA driving module.
  • the SL receiving module reads the data sent by the grating head reading head, and controls the total length of the MA clock through the done line, and controls the subsequent CRC check module by the obtained position value and the did line.
  • the MA drive signal sends the MA clock signal.
  • the SL receive module receives the response signal from the encoder, it starts counting the delay time and waits for the start bit to arrive; after the start bit, it starts receiving the SL data; After the reception is completed, the did signal is sent, and the done signal is issued at a certain time to stop the MA drive module.
  • the CRC check module receives the did signal, it starts the CRC check; after the end, it outputs a correct position value.
  • the MA signal In the idle wait state, that is, when data transmission is not performed, the MA signal remains high and the done signal remains low.
  • the MA driver module receives the enable signal en from the incremental scale interface module, it starts to work and enters the next state.
  • This state only needs to pull the MA signal low and keep it for half MA clock cycle, that is, enter the next state.
  • the MA pulse signal is continuously generated, and the MA is inverted every half of the MA clock cycle. It is necessary to detect the signal of the done line all the time while generating the pulse. If a high level appears on the done line, the next state is entered. This state needs to maintain a high level of timeoutSENS time length, and then enters the idle waiting state after the end.
  • FIG. 6 is a state transition diagram of the SL receiving module.
  • a sufficient number of registers in the FPGA chip are used to store the data sent by the SL.
  • the data including the position value, the error bit and the parity bit are designed and stored in a register.
  • a delayed clock signal (maclk is taken as an example) is generated, and the SL edge reading is triggered by its rising edge.
  • the maclk signal needs to be generated after the first falling edge of the SL signal and before the end of the data transmission.
  • a delay is generated to generate a rising edge of a maclk signal.
  • This delay is the time difference between the second rising edge of the MA signal and the first falling edge of the SL signal, in order to compensate for the delay of the SL signal.
  • the rising edge of the maclk is the trigger signal for reading the SL. When the rising edge of the maclk does not come, it is not detected and is in the idle waiting state. When the start bit of SL is detected (that is, the first signal of 1 on the SL line) comes, a high level of the clock is generated on the kaishi signal line, and the reading state is entered, and the level of SL is read at the rising edge. Value, whose value is stored in a pre-set register. At the same time, counting is required. When all the digits are read, the reading is no longer performed, and a did signal is sent to start the CRC check module, and a done signal is generated to respond to the MA boot module.
  • the CRC check module uses the CRC check algorithm implemented by the FPGA to verify the collected data. If it can pass the check, the data value is output, otherwise the correct data value is output.
  • the SL receiving module is the main control module of the entire BISS interface.
  • the MA driving module receives the start signal from the outside and starts to work first.
  • the CRC check module verifies the received data and outputs the correct position value.
  • a BISS protocol data decoding interface system provided by an embodiment of the present invention includes:
  • An FPGA chip the FPGA chip is connected to the encoder;
  • the FPGA chip includes a MA driving module 301, an SL receiving module 302, and a CRC check module 303;
  • the MA driver module 301 is connected to the SL receiving module 302, and the SL module 302 is also connected to the CRC check module.
  • the MA driving module 301 is configured to receive the enable signal en, and send an MA clock signal to the SL receiving module.
  • the SL receiving module 302 is configured to start the detection of the trigger signal of the SL after acquiring the MA clock signal, and start to read the SL data when the start bit of the SL is detected, and send a done signal to the MA after reading the SL data.
  • the driving module 301 stops the MA driving module 301 and issues a did signal to the CRC check module 303.
  • the SL receiving module 302 includes:
  • the signal generating unit 3021 is configured to generate a maclk signal according to a time difference between the MA clock signal and the SL signal, and start detecting the arrival of the trigger signal of the SL by using a rising edge of the maclk signal; the signal generating unit 3021 includes:
  • the signal generating subunit 30211 is configured to generate a maclk signal according to a time difference between a second rising edge of the MA clock signal and a first falling edge of the SL signal, and start detecting the arrival of the trigger signal of the SL by using a rising edge of the maclk signal .
  • the reading unit 3022 is configured to start reading the level value of the SL and store the level value in the register when the start bit of the SL is detected, and send out all the digits of the level value of the read SL.
  • the done signal to the MA driving module 301 stops the MA driving module 301 and issues a did signal to the CRC check module 303.
  • the CRC check module 303 is configured to perform CRC check on the SL data after receiving the did signal, and output a correct position value after the check ends; the CRC check module 303 includes:
  • the checking unit 3031 is configured to perform CRC check on the correctness of the SL data after receiving the did signal, and output the SL data that can pass the verification after the verification is completed, and output the previous SL data that cannot pass the verification. The correct data value.
  • the disclosed system, apparatus, and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention which is essential or contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

本发明实施例公开了一种BISS协议数据解码方法及接口系统，用于解决现有技术中针对适应绝对式光栅尺的BISS协议常用的解码方式数据处理灵活性不足且达到的功能单一的技术问题。本发明实施例包括：FPGA芯片，FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；方法步骤包括：MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块开始检测SL的触发信号的到来；SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块；CRC校验模块接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值。

Description

一种BISS协议数据解码方法及接口系统
本申请要求于2017年04月27日提交中国专利局、申请号为201710287684.1、发明名称为“一种BISS协议数据解码方法及接口系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及BISS协议数据解码领域，尤其涉及一种BISS协议数据解码方法及接口系统。
背景技术
在数控系统中，光栅尺是位置测量装置的核心元件。光栅尺是一种高精度线位移传感器，它以高精度长光栅作为测量基准，使用光电传感器将光学信号转化为电学信号，通过对电学信号进行处理，最终得到位置信息。与其它线位移传感器(例如磁栅、球栅、激光干涉仪等)相比，光栅尺在测量精度、分辨率、可靠性、对应用环境的要求、价格等几方面具有较高的综合优势，因此光栅尺在数显、数控机床以及测量仪器中有非常广泛的应用。光栅尺按照其测量方法的不同，可以分为增量式光栅尺和绝对式光栅尺。
其中绝对式光栅尺通过读取位置编码获取绝对位置信息。每次开机，绝对式光栅尺通过读取当前的位置编码，无需“归零”操作就能立即获取当前机床各轴的绝对位置信息，因而可以立即进入加工状态或继续上次操作，提高了机床的加工效率。绝对式光栅尺在数控机床上的应用得到迅速推广，并有逐渐成为主流应用的趋势。因此研制可适应绝对式光栅尺高速、大数据量、高稳定性等数据接收要求的数据接口是有必要的。
BISS(Bidirectional Synchronous Serial)协议是由德国IC-Haus公司提出的一种新型的可自由使用的同步串行通信协议。BISS协议的波特率可有较范围的选择，最高可达10MHz，高于其他的常用通信协议(如SSI、EnDat、Hiperface等)，有报警位、可调整协议时间长度，其在工业应用上较好，且无协议产权问题。另外，主端口会对线的传输延迟作出测量及自动补偿，让通讯接口可使用高速的数据传输；允许传感器有数据采集和数据处理时间(延迟传 输)；只包括两条信号线MA与SL。
BISS协议包括了“传感器模式(Senor Mode)”和“寄存器模式(Register Mode)”两种模式。传感器模式开始使接口快速地读取相应编码器的位置值等信息。寄存器可以让接口与编码器进行双向读写操作，得到接口需要的信息。模式的选择主要是依据MA线在该通信周期内的第一个低电平的时间长度，时间大于“timeoutSENS”表示接下来会进行寄存器模型的通信，时间小于“timeoutSENS”表示接下来会进行传感器模式的通信。此处接口的数据接收主要用到传感器模式。
BISS协议常用的解码方式是通过IC-Haus公司官方芯片BISS Mater、单片机或者FPGA进行。应用官方芯片BISS Mater方法的芯片成本较高而且数据处理灵活性不足，不易进行模块功能的个性化扩展；单片机进行数据解码往往会受受制于单片机的性能；而现今一些利用FPGA解码，所达到的功能比较单一还存在着缺漏。
发明内容
本发明实施例提供了一种BISS协议数据解码方法及接口系统，解决了现有技术中针对适应绝对式光栅尺的BISS协议常用的解码方式数据处理灵活性不足且达到的功能单一的技术问题。
本发明实施例提供的一种BISS协议数据解码方法，包括：
FPGA芯片，FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；
方法步骤包括：MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块开始检测SL的触发信号的到来；
SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块；
CRC校验模块接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值。
可选地，MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收 模块，SL接收模块开始检测SL的触发信号的到来包括：
MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块根据MA时钟信号与SL信号的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
可选地，SL接收模块根据MA时钟信号与SL信号的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来包括：
SL接收模块根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
可选地，SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块包括：
SL接收模块在检测到SL的start位到来时，开始读取SL的电平值并将电平值储存于寄存器中，在读取完毕SL的电平值的所有位数后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块。
可选地，CRC校验模块接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值包括：
CRC校验模块接收到did信号后，对SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
本发明实施例提供的一种BISS协议数据解码接口系统，包括：
FPGA芯片，FPGA芯片与编码器连接；
FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；
MA驱动模块与SL接收模块连接，SL模块还与CRC校验模块连接；
MA驱动模块用于接收到使能信号en，发出MA时钟信号至SL接收模块；
SL接收模块用于获取到MA时钟信号后开始检测SL的触发信号的到来，在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后 发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块；
CRC校验模块用于接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值。
可选地，SL接收模块包括：
信号产生单元，用于根据MA时钟信号与SL信号的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
可选地，信号产生单元包括：
信号产生子单元，用于根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
可选地，SL接收模块还包括：
读取单元，用于在检测到SL的start位到来时，开始读取SL的电平值并将电平值储存于寄存器中，在读取完毕SL的电平值的所有位数后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块。
可选地，CRC校验模块包括：
检验单元，用于接收到did信号后，对SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
从以上技术方案可以看出，本发明实施例具有以下优点：
本发明实施例提供的一种BISS协议数据解码方法及接口系统，包括：FPGA芯片，FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；方法步骤包括：MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块开始检测SL的触发信号的到来；SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块；CRC校验模块接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值，本发明实施例中通过利用FPGA芯片对基于BISS协议的绝 对式光栅尺的协议进行解码，并在FPGA芯片中设置了MA驱动模块、SL接收模块、CRC校验模块，加入了数据长度及时间调整、CRC校验等功能，同时使得本发明实施例中提供的接口系统可进行高速、大数据量、高稳定性的数据接收，可有效适应绝对式光栅尺的信息传输，解决了现有技术中针对适应绝对式光栅尺的BISS协议常用的解码方式数据处理灵活性不足且达到的功能单一的技术问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本发明实施例提供的一种BISS协议数据解码方法的一个实施例的流程示意图；
图2为本发明实施例提供的一种BISS协议数据解码方法的另一个实施例的流程示意图；
图3为本发明实施例提供的BISS协议数据解码接口系统的外部整体结构连接示意图；
图4为本发明实施例提供的FPGA模块设计图；
图5为本发明实施例提供的MA驱动模块的状态跃迁图；
图6为本发明实施例提供的SL接收模块的状态跃迁图；
图7为本发明实施例提供的一种BISS协议数据解码接口系统的结构示意图。
具体实施方式
本发明实施例提供了一种BISS协议数据解码方法及接口系统，用于解决现有技术中针对适应绝对式光栅尺的BISS协议常用的解码方式数据处理灵活性不足且达到的功能单一的技术问题。
为使得本发明的发明目的、特征、优点能够更加的明显和易懂，下面 将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，下面所描述的实施例仅仅是本发明一部分实施例，而非全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
请参阅图1，本发明实施例提供的一种BISS协议数据解码方法，包括：
FPGA芯片，FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；
方法步骤包括：101、MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块开始检测SL的触发信号的到来；
首先，由MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块开始检测SL的触发信号的到来。
102、SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块；
SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块。
103、CRC校验模块接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值。
在CRC校验模块接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值。
以上为对本发明实施例提供的一种BISS协议数据解码方法的一个实施例的详细描述，以下将对本发明实施例提供的一种BISS协议数据解码方法的另一个实施例进行详细的描述。
请参阅图2，本发明实施例提供的一种BISS协议数据解码方法的另一个实施例，包括：
201、MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，SL接收模块根据MA时钟信号与SL信号的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
在MA驱动模块接收到使能信号en时，发出MA时钟信号至SL接收模块，SL接收模块根据MA时钟信号与SL信号的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
202、SL接收模块根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
为了对SL信号的延时进行补偿，SL接收模块可以根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
203、SL接收模块在检测到SL的start位到来时，开始读取SL的电平值并将电平值储存于寄存器中，在读取完毕SL的电平值的所有位数后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块。
在SL接收模块在检测到SL的start位到来时，开始读取SL的电平值并将电平值储存于寄存器中，在读取完毕SL的电平值的所有位数后发出done信号至MA驱动模块停止MA驱动模块及发出did信号至CRC校验模块。
204、CRC校验模块接收到did信号后，对SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
CRC校验模块接收到SL接收模块发送的did信号后，对SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
以上为对本发明实施例提供的一种BISS协议数据解码方法的另一个实施例得详细描述，为便于理解，以下将对本发明实施例提供的BISS协议数据解码方法的具体工作原理步骤进行详细的描述。
请参阅图3，为本发明实施例提供的BISS协议数据解码接口系统的外部整体结构连接示意图。编码器(绝对式光栅尺读数头)把数据结果通过物理接口传到差分电路，经过差分电路后传递到FPGA芯片。此处采用BISS 传感器模式进行通信。绝对式光栅尺读数头的信号通常采用差分信息发送方式，结合差分接收电路可以使得信息传送更稳定。SL信号经差分处理之后从绝对式光栅尺读数头发出，以差分芯片为核心的反差分电路将信号接收并还原出FPGA所需的SL信号。同样的，MA信号通过从FPGA引脚发出，通过差分电路处理在发送给光栅尺读数头。FPGA的输入引脚之一控制着接口控制模块是否开始工作，当接口控制模块工作并得出位置值，会把信息送到后续模块。
请参阅图4，根据FPGA的至上而下的模块设计思想及对系统功能需求的分析，可以把FPGA设计成MA驱动模块、SL接收模块、CRC校验模块。在实际应用中，数据接口部分是作为控制部分，令本模块发送作为时钟的脉冲，以供编码器发送数据。BISS协议可以根据实际需要，对一个数据传输周期的时间总长进行灵活的调整，每一个数据传输的总时间是可能不相同的，具体需要的时间由编码器来决定。
MA驱动模块与SL接收模块之间通过MA线和done线进行配合，其中MA信号由MA驱动模块进行控制；done信号由SL接收模块进行控制，由SL接收模块发送给MA驱动模块。SL接收模块读取光栅尺读数头发送过来的数据，同时通过done线控制MA时钟的总长度，通过所得到的位置值和did线控制着后续CRC校验模块。
启动使能信号en到来时，MA驱动信号发出MA时钟信号，SL接收模块接收到来自编码器的响应信号时，开始计数延时时间并等待start位的到来；start位之后开始接收SL数据；数据接收完毕之后时发出did信号，同时在一定的时间发出done信号停止MA驱动模块。CRC校验模块接收到did信号时，开始进行CRC校验；结束后输出一个正确的位置值。
请参阅图5，为MA驱动模块的状态跃迁图。在空闲等待状态，即不进行数据传输的时候，MA信号保持高电平，done信号保持低电平。当MA驱动模块接收到来自增量尺接口模块的使能信号en的时候开始工作，进入下一个状态。此状态只需把MA信号拉低，并保持半个MA时钟周期，即进入下一状态。在该状态不断产生MA脉冲信号，每半个MA时钟周期即取反MA一次。产生脉冲的同时需要一直检测done线的信号，若done线 出现一个高电平，即进入下一状态。此状态需保持一个timeoutSENS时间长度的高电平，结束后即重新进入空闲等待状态。
请参阅图6，为SL接收模块的状态跃迁图。在FPGA芯片内部设计一个位数足够的寄存器用来存放SL发送过来的数据，此处设计包括位置值、错误位和校验位等的数据同时存放在一个寄存器里。首先制作出对经过延时补偿的接收时钟信号(maclk为例)，并利用其上升沿检测SL读数触发。maclk信号需要在SL信号第一个下降沿之后以及数据传输结束之前，每当MA信号的下降产生之后，经过若干延时就产生一个沿产生一个maclk信号上升沿。而此延时是MA信号的第二个上升沿和SL信号的第一个下降沿之间的时间差，目的是对SL信号的延时进行补偿。maclk的上升沿为读取SL的触发信号，maclk上升沿没到来时不进行检测，处于空闲等待状态。当检测到SL的start位(即SL线上的第一个为1的信号)到来时在kaishi信号线产生一个时钟的高电平，并进入读数状态，在上升沿时读入SL的电平值，其值存放在预先设置好的寄存器里。同时需要进行计数，当读完所有位数，即不再进行读数，并发出一个did信号以启动CRC校验模块，并产生一个done信号来回应MA启动模块。
CRC校验模块利用FPGA实现的CRC校验算法，对上述收集到的数据进行校验，若能通过校验，即输出数据值，否则输出上一个正确的数据值。
其中，SL接收模块为整个BISS接口的主要控制模块，MA驱动模块接收来自外部的启动信号并开始首先开始工作，CRC校验模块对接收到的数据进行校验并输出正确的位置值。
以上为对本发明实施例提供的BISS协议数据解码方法的具体工作原理步骤所进行的详细描述，以下将对本发明实施例提供的一种BISS协议数据解码接口系统进行详细的描述。
请参阅图7，本发明实施例提供的一种BISS协议数据解码接口系统包括：
FPGA芯片，FPGA芯片与编码器连接；
FPGA芯片包括MA驱动模块301、SL接收模块302、CRC校验模块 303；
MA驱动模块301与SL接收模块302连接，SL模块302还与CRC校验模块连接；
MA驱动模块301用于接收到使能信号en，发出MA时钟信号至SL接收模块；
SL接收模块302用于获取到MA时钟信号后开始检测SL的触发信号的到来，在检测到SL的start位到来时，开始读取SL数据，并在读取完毕SL数据后发出done信号至MA驱动模块301停止MA驱动模块301及发出did信号至CRC校验模块303；SL接收模块302包括：
信号产生单元3021，用于根据MA时钟信号与SL信号的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来；信号产生单元3021包括：
信号产生子单元30211，用于根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用maclk信号的上升沿开始检测SL的触发信号的到来。
读取单元3022，用于在检测到SL的start位到来时，开始读取SL的电平值并将电平值储存于寄存器中，在读取完毕SL的电平值的所有位数后发出done信号至MA驱动模块301停止MA驱动模块301及发出did信号至CRC校验模块303。
CRC校验模块303用于接收到did信号后，进行对SL数据的CRC校验，并在校验结束后输出正确的位置值；CRC校验模块303包括：
检验单元3031，用于接收到did信号后，对SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅 是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

  1. 一种BISS协议数据解码方法，其特征在于，包括：
    FPGA芯片，所述FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；
    方法步骤包括：所述MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，所述SL接收模块开始检测SL的触发信号的到来；
    所述SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕所述SL数据后发出done信号至所述MA驱动模块停止所述MA驱动模块及发出did信号至所述CRC校验模块；
    所述CRC校验模块接收到did信号后，进行对所述SL数据的CRC校验，并在校验结束后输出正确的位置值。
  2. 根据权利要求1所述的BISS协议数据解码方法，其特征在于，所述MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，所述SL接收模块开始检测SL的触发信号的到来包括：
    所述MA驱动模块接收到使能信号en，发出MA时钟信号至SL接收模块，所述SL接收模块根据MA时钟信号与SL信号的时间差产生maclk信号，并利用所述maclk信号的上升沿开始检测SL的触发信号的到来。
  3. 根据权利要求2所述的BISS协议数据解码方法，其特征在于，所述SL接收模块根据MA时钟信号与SL信号的时间差产生maclk信号，并利用所述maclk信号的上升沿开始检测SL的触发信号的到来包括：
    所述SL接收模块根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用所述maclk信号的上升沿开始检测SL的触发信号的到来。
  4. 根据权利要求3所述的BISS协议数据解码方法，其特征在于，所述SL接收模块在检测到SL的start位到来时，开始读取SL数据，并在读取完毕所述SL数据后发出done信号至所述MA驱动模块停止所述MA驱动模块及发出did信号至所述CRC校验模块包括：
    所述SL接收模块在检测到SL的start位到来时，开始读取SL的电平值 并将所述电平值储存于寄存器中，在读取完毕所述SL的电平值的所有位数后发出done信号至所述MA驱动模块停止所述MA驱动模块及发出did信号至所述CRC校验模块。
  5. 根据权利要求4所述的BISS协议数据解码方法，其特征在于，所述CRC校验模块接收到did信号后，进行对所述SL数据的CRC校验，并在校验结束后输出正确的位置值包括：
    所述CRC校验模块接收到did信号后，对所述SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
  6. 一种BISS协议数据解码接口系统，其特征在于，包括：
    FPGA芯片，所述FPGA芯片与编码器连接；
    所述FPGA芯片包括MA驱动模块、SL接收模块、CRC校验模块；
    所述MA驱动模块与所述SL接收模块连接，所述SL模块还与所述CRC校验模块连接；
    所述MA驱动模块用于接收到使能信号en，发出MA时钟信号至SL接收模块；
    所述SL接收模块用于获取到MA时钟信号后开始检测SL的触发信号的到来，在检测到SL的start位到来时，开始读取SL数据，并在读取完毕所述SL数据后发出done信号至所述MA驱动模块停止所述MA驱动模块及发出did信号至所述CRC校验模块；
    所述CRC校验模块用于接收到did信号后，进行对所述SL数据的CRC校验，并在校验结束后输出正确的位置值。
  7. 根据权利要求6的BISS协议数据解码接口系统，其特征在于，所述SL接收模块包括：
    信号产生单元，用于根据MA时钟信号与SL信号的时间差产生maclk信号，并利用所述maclk信号的上升沿开始检测SL的触发信号的到来。
  8. 根据权利要求7所述的BISS协议数据解码接口系统，其特征在于，所述信号产生单元包括：
    信号产生子单元，用于根据MA时钟信号的第二个上升沿与SL信号的第一个下降沿之间的时间差产生maclk信号，并利用所述maclk信号的上升沿开始检测SL的触发信号的到来。
  9. 根据权利要求8所述的BISS协议数据解码接口系统，其特征在于，所述SL接收模块还包括：
    读取单元，用于在检测到SL的start位到来时，开始读取SL的电平值并将所述电平值储存于寄存器中，在读取完毕所述SL的电平值的所有位数后发出done信号至所述MA驱动模块停止所述MA驱动模块及发出did信号至所述CRC校验模块。
  10. 根据权利要求9所述的BISS协议数据解码接口系统，其特征在于，所述CRC校验模块包括：
    检验单元，用于接收到did信号后，对所述SL数据的正确性进行CRC校验，并在校验结束后输出能通过校验的SL数据，对于不能通过校验的SL数据则输出上一个正确的数据值。
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