WO2018196378A1 - 显示面板、像素驱动电路及其驱动方法 - Google Patents

显示面板、像素驱动电路及其驱动方法 Download PDF

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Publication number
WO2018196378A1
WO2018196378A1 PCT/CN2017/113911 CN2017113911W WO2018196378A1 WO 2018196378 A1 WO2018196378 A1 WO 2018196378A1 CN 2017113911 W CN2017113911 W CN 2017113911W WO 2018196378 A1 WO2018196378 A1 WO 2018196378A1
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Prior art keywords
switch
terminal
voltage
control
control signal
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PCT/CN2017/113911
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English (en)
French (fr)
Inventor
陈小龙
温亦谦
周明忠
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to KR1020197035185A priority Critical patent/KR20190141754A/ko
Priority to JP2019558480A priority patent/JP2020518023A/ja
Priority to EP17907541.1A priority patent/EP3618046A4/en
Priority to US15/744,080 priority patent/US10453391B2/en
Publication of WO2018196378A1 publication Critical patent/WO2018196378A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method of the pixel driving circuit, and a display panel including the pixel driving circuit.
  • the threshold voltage of the driving transistor of each pixel unit in the OLED display panel may be different, which will cause each pixel unit.
  • the currents of the middle light emitting diodes are inconsistent, causing uneven brightness of the OLED display panel.
  • the drive transistor material ages and mutates, causing problems such as drift of the threshold voltage of the drive transistor.
  • the degree of aging of the driving transistor materials is different, which causes the threshold voltage of each driving transistor in the OLED display panel to drift differently, which may also cause uneven display of the OLED display panel, and the display unevenness may follow the driving time.
  • the aging and aging of the drive transistor material becomes more severe.
  • an object of the present application is to provide a pixel driving circuit, a driving method thereof, and a display panel including the pixel driving circuit to improve brightness uniformity of the display panel.
  • the present application provides a pixel driving circuit including a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second capacitor, and a charging voltage terminal.
  • the driving transistor is provided with a gate terminal, a source terminal and a drain terminal;
  • the first capacitor is connected between the source terminal and the gate terminal, and the second capacitor is connected to The source terminal and the charging voltage terminal, the charging voltage terminal is respectively connected to the reset voltage signal terminal and the data voltage signal terminal through the first switch and the second switch; the drain terminal passes The third switch is connected to the driving voltage signal end, and the gate end is connected to the initial voltage signal end through the fourth switch.
  • the pixel driving circuit further includes a first control signal end, and the first control signal end is connected to the control end of the first switch and the control end of the second switch to control the first switch and The second switch is turned on and off.
  • the pixel driving circuit further includes a second control signal end, and the second control signal end is connected to the control end of the third switch to control the on and off of the third switch.
  • the pixel driving circuit further includes a third control signal end, and the third control signal end is connected to the control end of the fourth switch to control the on and off of the fourth switch.
  • the pixel driving circuit further includes a fifth switch, a fourth control signal end, a light emitting diode and a negative voltage signal end, wherein the fourth control signal end is connected to the control end of the fifth switch to control the first
  • the fifth switch is turned on and off; the light emitting diode has a positive terminal and a negative terminal, and the fifth switch is connected between the source terminal and the positive terminal to control on and off of the driving transistor and the LED
  • the negative terminal is connected to the negative voltage signal terminal.
  • the embodiment of the present application provides a display panel including the pixel driving circuit of any of the above embodiments.
  • Embodiments of the present application provide a pixel driving method, including
  • a pixel driving circuit comprising: a driving transistor, a light emitting diode, a first capacitor, a second capacitor, a charging voltage terminal, a data voltage signal terminal, and a reset voltage signal terminal; wherein the driving transistor is provided with a gate terminal, a source terminal and a drain terminal; The first capacitor is connected between the source terminal and the gate terminal, the second capacitor is connected to the source terminal and the charging voltage terminal, and the charging voltage terminal is connected to the reset voltage signal terminal and The data voltage signal end; the source terminal is connected to the light emitting diode;
  • a reset voltage is applied to the charging voltage terminal to change the potential of the gate terminal and The source extreme potential to stabilize the driving current of the driving transistor;
  • the reset voltage is applied to the charging voltage terminal, and the driving voltage is applied to the drain terminal to turn on the driving transistor and the light emitting diode.
  • the pixel driving circuit further includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an initial voltage signal end, a driving voltage signal end, a first control signal end, and a second control a signal terminal, a third control signal, and a fourth control signal terminal;
  • the charging voltage terminal is respectively connected to the reset voltage signal terminal and the data voltage signal terminal through the first switch and the second switch; a drain terminal connected to the driving voltage signal terminal through the third switch, the gate terminal being connected to the initial voltage signal terminal through the fourth switch;
  • the fifth switch being connected to the source terminal and the
  • the first control signal end is connected to the control end of the first switch and the control end of the second switch, and the second control signal end is connected to the control end of the third switch.
  • the third control signal end is connected to the control end of the fourth switch, and the fourth control signal end is connected to the control end of the fifth switch;
  • the first control signal end and the fourth control signal end are loaded with a low level signal, and the second control signal end and the third control signal end are loaded with a high level signal,
  • the second switch, the third switch, and the fourth switch are turned on, and the first switch and the fifth switch are turned off, and the charging voltage terminal is loaded by the second switch.
  • a data voltage the data voltage is Vdata
  • the gate terminal loads the initial voltage through the fourth switch
  • the initial voltage is Vini
  • the driving voltage passes through the third switch and the driving transistor pair
  • the source is extremely charged until the potential of the source terminal is Vini-Vth.
  • the first control signal end is loaded with a high level signal
  • the second control signal end, the third control signal end and the fourth control signal end are loaded with a low level Signaling to turn on the first switch
  • the second switch, the third switch, the fourth switch, and the fifth switch are turned off
  • the charging voltage terminal passes the first switch Loading the reset voltage
  • the reset voltage is Vref
  • the potential of the gate terminal is Vini+(Vref ⁇ Vdata)
  • the potential of the source terminal is Vini ⁇ Vth+ ⁇ V
  • the gate terminal potential is The difference between the potentials of the source terminals is Vref - Vdata + Vth - ⁇ V
  • the ⁇ V (Vref - Vdata) * C2 / (C1 + C2)
  • the C1 is the capacitance value of the first capacitor
  • the C2 is a capacitance value of the second capacitor such that the drive current is independent of the threshold voltage.
  • the pixel driving circuit further includes a negative voltage signal terminal, the light emitting diode has a positive terminal and a negative terminal, and the fifth switch is connected between the source terminal and the positive terminal, and the negative terminal Connected to the negative voltage signal terminal;
  • the first control signal end, the second control signal end and the fourth control signal end are loaded with a high level signal, and the third control signal end is loaded with a low level signal,
  • the first switch, the third switch, and the fifth switch are turned on, and the second switch and the fourth switch are turned off, and the charging voltage terminal loads the first switch Resetting the voltage to make the potential of the source terminal unchanged, the third switch, the driving transistor and the fifth switch being turned on to make the driving voltage terminal and the negative voltage signal terminal conductive, so as to facilitate
  • the drive current drives the light emitting diode to emit light.
  • the pixel driving circuit provided by the present application includes a driving transistor, wherein the driving transistor is provided with a gate terminal, a source terminal and a drain terminal; and the first capacitor is disposed between the source terminal and the gate terminal, wherein the a second capacitor connected to the source terminal and the charging voltage terminal, wherein the charging voltage terminal is respectively connected to the reset voltage signal terminal and the data voltage signal terminal through the first switch and the second switch; The terminal is connected to the driving voltage signal terminal through the third switch, and the gate terminal is connected to the initial voltage signal terminal through the fourth switch.
  • the light-emitting brightness of the light-emitting diode is ensured to be uniform.
  • the display panel provided by the present application includes the above pixel driving circuit, so that the driving current generated by the driving transistor can be independent of the threshold voltage of the driving transistor, so that the driving transistor is The generated driving current is stable, eliminating the problem of threshold voltage drift in the pixel unit due to aging of the driving transistor or manufacturing process limitation, thereby stabilizing the current flowing through the LED, ensuring uniform brightness of the LED, and improving the picture. display effect.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to a first embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit according to a second embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 4 is a timing diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 5 is a flowchart of a pixel driving method provided by an embodiment of the present application.
  • FIG. 6 is a state diagram of a reset phase of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 7 is a state diagram of a storage phase of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 8 is a state diagram of a light emitting phase of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 1 is a pixel driving circuit according to a first embodiment of the present disclosure, including a driving transistor T0, a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, and a first capacitor C11.
  • the second capacitor C12 the charging voltage terminal n, the initial voltage signal terminal VINI, the data voltage signal terminal VDATA, the reset voltage Vref signal terminal VREF, and the driving voltage signal terminal OVDD.
  • the driving transistor T0 is provided with a gate terminal g, a source terminal s and a drain terminal d.
  • the first capacitor C11 is connected between the source terminal s and the gate terminal g to store a potential difference between the gate terminal g and the source terminal s.
  • the second capacitor C12 is connected to the source terminal s and the charging voltage terminal n, and the charging voltage terminal n is divided by the first switch T1 and the second switch T2.
  • the reset voltage signal terminal VREF and the data voltage signal terminal VDATA are not connected to load the reset voltage Vref or the data voltage Vdata at the charging voltage terminal n.
  • the drain terminal d is connected to the driving voltage signal terminal OVDD through the third switch T3 to load the driving voltage Vdd at the drain terminal d.
  • the gate terminal g is connected to the initial voltage signal terminal VINI through the fourth switch T4 to load an initial voltage Vini at the gate terminal g.
  • the switch described in this embodiment includes, but is not limited to, a switch circuit, a thin film transistor, and the like having a control circuit on/off function.
  • the pixel driving circuit provided in this embodiment controls the second switch T2, the third switch T3, and the fourth switch T4 to be turned on in the reset storage phase by the driving method, and the first switch T1 is turned off, so that the first switch T1 is turned off.
  • the gate terminal g loads the initial voltage Vini
  • the drain terminal d loads the driving voltage Vdd
  • the driving voltage Vdd charges the source terminal s through the third switch T3 and the driving transistor T0.
  • the potential difference between the gate terminal g and the source terminal s is the threshold voltage Vth of the driving transistor T0; the first switch T1 is turned on during the charge sharing phase, and the second switch T2 is The third switch T3 and the fourth switch T4 are turned off, so that the charging voltage terminal n is loaded with the reset voltage Vref, so that the potential of the gate terminal g and the potential of the source terminal s are changed, and the driving is further performed.
  • the drive current I generated by the transistor T0 is independent of the threshold voltage Vth of the drive transistor T0, thereby stabilizing the drive current I generated by the drive transistor T0.
  • the pixel driving circuit further includes a first control signal end Scan1, and the first control signal end Scan1 is connected to the control end of the first switch T1 and the control end of the second switch T2. To control the on and off of the first switch T1 and the second switch T2.
  • the pixel driving circuit further includes a second control signal end Scan2, and the second control signal end Scan2 is connected to the control end of the third switch T3 to control the third switch T3. On and off.
  • the pixel driving circuit further includes a third control signal end Scan3, and the third control signal end Scan3 is connected to the control end of the fourth switch T4 to control the fourth switch T4. On and off.
  • FIG. 2 is a pixel driving circuit according to a second embodiment of the present invention.
  • the pixel driving circuit provided by the first embodiment is configured to stabilize the driving current I generated by the driving transistor T0.
  • the embodiment further includes a light emitting diode L, a fifth switch T5, and a negative voltage signal terminal OVSS.
  • the light emitting diode L may be an organic light emitting diode or the like.
  • the light emitting diode L has a positive terminal and a negative terminal, and the fifth switch T5 is connected between the source terminal s and the positive terminal to control the driving transistor T0.
  • the anode and the cathode are connected to the negative voltage signal terminal OVSS.
  • the driving voltage signal terminal OVDD is turned on with the negative voltage signal terminal OVSS, and the driving of the driving transistor T0 is driven.
  • the current I drives the light-emitting diode L to emit light.
  • the driving current I in the present embodiment is independent of the threshold voltage Vth of the driving transistor T0, and eliminates the problem that the threshold voltage Vth drifts in the pixel unit due to the aging of the driving transistor T0 or the manufacturing process limitation, thereby flowing through the light emitting diode.
  • the current of L is stable, ensuring uniform brightness of the light-emitting diode L, and improving the display effect of the picture.
  • the pixel driving circuit further includes a fourth control signal end Scan4, and the fourth control signal end Scan4 is connected to the control end of the fifth switch T5 to control the fifth switch T5. On and off.
  • the first switch T1, the driving transistor T0, the third switch T3, the fourth switch T4, and the fifth switch T5 are all N-type thin film transistors, when the above switch When the control terminal applies a high level voltage, the switch is in an on state, and when a low level voltage is applied to the control terminal of the switch, the switch is in an off state.
  • the second switch T2 is a P-type thin film transistor. When a low-level voltage is applied to the control terminal of the switch, the second switch T2 is in an on state. When a control terminal of the switch applies a high-level voltage, the first The second switch T2 is in an off state.
  • the first switch T1, the driving transistor T0, the second switch T2, the third switch T3, the fourth switch T4, and the fifth switch T5 may also be other P-type or / and N-type thin film transistor combinations, this application is not limited.
  • control signal end when the pixel driving circuit is applied to a display panel or a display device, the control signal end may be connected to a scanning signal line in the display panel or the display device.
  • the embodiment of the present application further provides a display panel 100, including the pixel driving circuit provided by any of the above embodiments, and further includes an initial voltage signal line V1, a data voltage signal line V2, and a driving voltage signal line V3.
  • the initial voltage signal terminal VINI is connected to the initial voltage signal line V1 to load the initial voltage Vini.
  • the data voltage signal terminal VDATA is connected to the data voltage signal line V2 to load the data voltage Vdata.
  • the driving voltage signal terminal OVDD is connected to the driving voltage signal line V3 to load the driving voltage Vdd.
  • the negative voltage signal terminal OVSS is connected to the negative voltage signal line V4 to load the negative voltage Vss.
  • the reset voltage signal terminal VREF is connected to the reset voltage signal line V5 to load the reset voltage Vref.
  • the display panel may include a plurality of pixel arrays, and each pixel corresponds to the above Any of the pixel driving circuits in the present exemplary embodiment. Since the pixel driving circuit eliminates the influence of the threshold voltage on the driving current I, the display of the LED L is stabilized, and the uniformity of the display brightness of the display panel is improved, so that the display quality can be greatly improved.
  • FIG. 4 is a timing diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG. 5 is a pixel driving method S100 according to an embodiment of the present disclosure, for driving the pixel driving circuit described in the above embodiment, including
  • S101 please refer to FIG. 2 and FIG. 3, and provide a pixel driving circuit, including a driving transistor T0, a light emitting diode L, a first capacitor C11, a second capacitor C12, a charging voltage terminal n, a data voltage signal terminal VDATA, and a reset voltage signal terminal VREF.
  • the driving transistor T0 is provided with a gate terminal g, a source terminal s and a drain terminal d.
  • the first capacitor C11 is connected between the source terminal s and the gate terminal g
  • the second capacitor C12 is connected to the source terminal s and the charging voltage terminal n
  • the charging voltage terminal n is connected.
  • the source terminal s is connected to the light emitting diode L.
  • the pixel driving circuit further includes a first switch T1, a second switch T2, a third switch T3, a fourth switch T4, a fifth switch T5, an initial voltage signal terminal VINI, a driving voltage signal terminal OVDD, and a first control.
  • the charging voltage terminal n is connected to the reset voltage signal terminal VREF and the data voltage signal terminal VDATA through the first switch T1 and the second switch T2, respectively.
  • the drain terminal d is connected to the driving voltage signal terminal OVDD through the third switch T3, and the gate terminal g is connected to the initial voltage signal terminal VINI through the fourth switch T4.
  • the fifth switch T5 is connected between the source terminal s and the light emitting diode L.
  • the first control signal end Scan1 is connected to the control end of the first switch T1 and the control end of the second switch T2, and the second control signal end Scan2 is connected to the control end of the third switch T3.
  • the third control signal end Scan3 is connected to the control end of the fourth switch T4, and the fourth control signal end Scan4 is connected to the control end of the fifth switch T5.
  • the pixel driving circuit further includes a negative voltage signal terminal OVSS, the light emitting diode L has a positive terminal and a negative terminal, and the fifth switch T5 is connected between the source terminal s and the positive terminal.
  • the negative terminal is connected to the negative voltage signal terminal OVSS.
  • the initial voltage signal terminal VINI is connected to the initial voltage signal line V1 for loading the initial voltage Vini.
  • the data voltage signal terminal VDATA is connected to the data voltage signal line V2 for loading data Voltage Vdata.
  • the driving voltage signal terminal OVDD is connected to the driving voltage signal line V3 for loading the driving voltage Vdd.
  • the negative voltage signal terminal OVSS is connected to the negative voltage signal line V4 for loading the negative voltage Vss.
  • the reset voltage signal terminal VREF is connected to the reset voltage signal line V5 for loading the reset voltage Vref.
  • S102 enter a reset phase t1, load a data voltage Vdata at the charging voltage terminal n, and load an initial voltage Vini at the gate terminal g, and load the driver at the drain terminal d.
  • the voltage Vdd charges the source terminal s until the difference between the gate terminal g potential and the source terminal s potential is Vth, the Vth is a threshold voltage of the driving transistor T0, and the Vth is stored in the In the first capacitor C11.
  • the first control signal end Scan1 and the fourth control signal end Scan4 are loaded with a low level signal, and the second control signal end Scan2 and the third control signal end Scan3 are loaded high.
  • Level signal such that the second switch T2, the third switch T3, and the fourth switch T4 are turned on, and the first switch T1 and the fifth switch T5 are turned off, the charging voltage
  • the terminal n loads the data voltage Vdata through the second switch T2, and the gate terminal g loads the initial voltage Vini through the fourth switch T4, the driving voltage Vdd passing through the third switch T3 and the The driving transistor T0 charges the source terminal s until the potential of the source terminal s is Vini-Vth.
  • S103 enter a charge sharing phase t2, and load a reset voltage Vref at the charging voltage terminal n to change the potentials of the gate terminal g and the source terminal s, so that The driving current of the driving transistor T0 is stabilized.
  • the first control signal end Scan1 and the third control signal end Scan3 are loaded with a high level signal, and the second control signal end Scan2 and the fourth control signal end Scan4 are loaded low.
  • a level signal to turn on the first switch T1, and the second switch T2, the third switch T3, the fourth switch T4, and the fifth switch T5 are turned off, the charging voltage
  • the terminal n loads the reset voltage Vref through the first switch T1 to change the potential of the gate terminal g and the source terminal s.
  • the potential of the gate terminal g is Vini+(Vref ⁇ Vdata); the potential of the source terminal s is Vini ⁇ Vth+ ⁇ V, and the potential of the gate terminal g and the potential of the source terminal s
  • Vgs is Vref - Vdata + Vth - ⁇ V
  • the ⁇ V (Vref - Vdata) * C2 / (C1 + C2)
  • the C1 is the capacitance value of the first capacitor C11
  • the C2 is the The capacitance value of the second capacitor C12.
  • S104 enter an illumination phase t3, load the reset voltage Vref at the charging voltage terminal n, and load the driving voltage Vdd at the drain terminal d to be turned on.
  • the first control signal end Scan1, the second control signal end Scan2, and the fourth control signal end Scan4 are loaded with a high level signal, and the third control signal end Scan3 is loaded low. a level signal such that the first switch T1, the third switch T3, and the fifth switch T5 are turned on, and the second switch T2 and the fourth switch T4 are turned off, the charging voltage
  • the terminal n loads the reset voltage Vref through the first switch T1 such that the potential of the source terminal s does not change, and the driving current I does not change.
  • the third switch T3, the driving transistor T0 and the fifth switch T5 are turned on such that the driving voltage Vdd terminal is turned on with the negative voltage signal terminal OVSS, so that the driving current I drives the light emitting diode L. Glowing. Therefore, the pixel driving method provided by the embodiment of the present application eliminates the influence of the threshold voltage Vth on the light emitting diode L, can improve the uniformity of the panel display, and improve the luminous efficiency.

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Abstract

一种像素驱动电路以及一种像素驱动方法和显示面板，像素驱动电路，包括驱动晶体管(T0)、第一开关(T1)、第二开关(T2)、第三开关(T3)、第四开关(T4)、第一电容(C1)、第二电容(C2)、初始电压信号端(VINI)、数据电压信号端(VDATA)、复位电压信号端(VREF)和驱动电压信号端(OVDD)。驱动晶体管设有栅极端(g)、源极端(s)和漏极端(d)。第一电容(C1)连接于源极端(s)和栅极端(g)之间，第二电容(C2)连接于源极端(s)和充电电压端(n)，充电电压端(n)通过第一开关(T1)和第二开关(T2)分别连接于复位电压信号端(VREF)和数据电压信号端(VDATA)。漏极端(d)通过第三开关(T3)连接于驱动电压信号端(OVDD)，栅极端(g)通过第四开关(T4)连接于初始电压信号端(VINI)。以及一种像素驱动方法和显示面板。

Description

显示面板、像素驱动电路及其驱动方法
本申请要求于2017年04月28日提交中国专利局、申请号为201710297657.2、申请名称为“显示面板、像素驱动电路及其驱动方法”的中国专利申请的优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本申请涉及显示技术领域，具体涉及一种像素驱动电路及该像素驱动电路的驱动方法和包括该像素驱动电路的显示面板。
背景技术
由于发光二极管(Organic Light Emitting Diode，OLED)显示面板制备过程不稳定性和技术受限等原因，OLED显示面板内每个像素单元的驱动晶体管的阈值电压会有差别，这样会造成每个像素单元中发光二极管的电流不一致，从而引起OLED显示面板的亮度不均匀。
另外，随着驱动晶体管驱动时间的推移，会造成驱动晶体管材料老化、变异，从而导致驱动晶体管的阈值电压发生漂移等问题。而且，驱动晶体管材料的老化程度不同，导致OLED显示面板内各个驱动晶体管的阈值电压的漂移量不同，也会造成OLED显示面板显示的不均匀现象，并且这种显示不均匀现象会随着驱动时间的推移和驱动晶体管材料的老化变得更严重。
发明内容
针对以上的问题，本申请的目的是提供一种像素驱动电路及其驱动方法和包括该像素驱动电路的显示面板，以提高显示面板的亮度均匀性。
为了解决背景技术中存在的问题，本申请提供了一种像素驱动电路，包括驱动晶体管、第一开关、第二开关、第三开关、第四开关、第一电容、第二电容、充电电压端、初始电压信号端、数据电压信号端、复位电压信号端和驱动电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；
所述第一电容连接于所述源极端和所述栅极端之间，所述第二电容连接于 所述源极端和所述充电电压端，所述充电电压端通过所述第一开关和所述第二开关分别连接于所述复位电压信号端和所述数据电压信号端；所述漏极端通过所述第三开关连接于所述驱动电压信号端，所述栅极端通过所述第四开关连接于所述初始电压信号端。
其中，所述像素驱动电路还包括第一控制信号端，所述第一控制信号端连接于所述第一开关的控制端和所述第二开关的控制端，以控制所述第一开关和所述第二开关的通断。
其中，所述像素驱动电路还包括第二控制信号端，所述第二控制信号端连接于所述第三开关的控制端，以控制所述第三开关的通断。
其中，所述像素驱动电路还包括第三控制信号端，所述第三控制信号端连接于所述第四开关的控制端，以控制所述第四开关的通断。
其中，所述像素驱动电路还包括第五开关、第四控制信号端、发光二极管和负极电压信号端，所述第四控制信号端连接于所述第五开关的控制端，以控制所述第五开关的通断；所述发光二极管具有正极端和负极端，所述第五开关连接于所述源极端和所述正极端之间，以控制所述驱动晶体管与所述发光二极管的通断，所述负极端连接于所述负极电压信号端。
本申请实施例提供了一种显示面板，包括上述任一实施方式所述的像素驱动电路。
本申请实施例提供了一种像素驱动方法，包括
提供像素驱动电路，包括驱动晶体管、发光二极管、第一电容、第二电容、充电电压端、数据电压信号端及复位电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；所述第一电容连接于所述源极端和所述栅极端之间，所述第二电容连接于所述源极端和所述充电电压端，所述充电电压端连接于所述复位电压信号端和所述数据电压信号端；所述源极端连接于所述发光二极管；
复位存储阶段，在所述充电电压端加载数据电压，及在所述栅极端加载初始电压，及在所述漏极端加载驱动电压以对所述源极端充电，直到所述源极端电位和所述栅极端电位之差为Vth，所述Vth为所述驱动晶体管的阈值电压，并所述Vth存储于所述第一电容中；
电荷分享阶段，在所述充电电压端加载复位电压以改变所述栅极端电位和 所述源极端电位，以使所述驱动晶体管的驱动电流稳定；
发光阶段，在所述充电电压端加载所述复位电压，且在所述漏极端加载所述驱动电压以导通所述驱动晶体管和所述发光二极管。
其中，提供的所述像素驱动电路还包括第一开关、第二开关、第三开关、第四开关、第五开关、初始电压信号端、驱动电压信号端、第一控制信号端、第二控制信号端、第三控制信号和第四控制信号端；所述充电电压端通过所述第一开关和所述第二开关分别连接于所述复位电压信号端和所述数据电压信号端；所述漏极端通过所述第三开关连接于所述驱动电压信号端，所述栅极端通过所述第四开关连接于所述初始电压信号端；所述第五开关连接于所述源极端和所述发光二极管之间；所述第一控制信号端连接于所述第一开关的控制端和所述第二开关的控制端，所述第二控制信号端连接于所述第三开关的控制端，所述第三控制信号端连接于所述第四开关的控制端，所述第四控制信号端连接于所述第五开关的控制端；
所述复位存储阶段，设置所述第一控制信号端和所述第四控制信号端加载低电平信号，且所述第二控制信号端和所述第三控制信号端加载高电平信号，以使所述第二开关、所述第三开关和所述第四开关导通，及所述第一开关和所述第五开关关断，所述充电电压端通过所述第二开关加载所述数据电压，所述数据电压为Vdata，所述栅极端通过所述第四开关加载所述初始电压，所述初始电压为Vini，所述驱动电压通过所述第三开关和所述驱动晶体管对所述源极端充电，直至所述源极端的电位为Vini-Vth。
其中，所述电荷分享阶段，设置所述第一控制信号端加载高电平信号，且所述第二控制信号端、所述第三控制信号端和所述第四控制信号端加载低电平信号，以使所述第一开关导通，及所述第二开关、所述第三开关、所述第四开关和所述第五开关关断，所述充电电压端通过所述第一开关加载所述复位电压，所述复位电压为Vref，并使得所述栅极端的电位为Vini+(Vref–Vdata)；所述源极端的电位为Vini–Vth+δV，所述栅极端电位与所述源极端的电位之差为Vref–Vdata+Vth–δV，所述δV＝(Vref–Vdata)*C2/(C1+C2)，所述C1为所述第一电容的电容值，所述C2为所述第二电容的电容值，以使所述驱动电流与所述阈值电压无关。
其中，提供的所述像素驱动电路还包括负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述源极端和所述正极端之间，所述负极端连接于所述负极电压信号端；
所述发光阶段，设置所述第一控制信号端、所述第二控制信号端和所述第四控制信号端加载高电平信号，且所述第三控制信号端加载低电平信号，以使所述第一开关、所述第三开关和所述第五开关导通，及所述第二开关和所述第四开关关断，所述充电电压端通过所述第一开关加载所述复位电压，以使所述源极端的电位不变，所述第三开关、所述驱动晶体管及所述第五开关导通使得所述驱动电压端与所述负极电压信号端导通，以便于所述驱动电流驱动所述发光二极管发光。
本申请提供的像素驱动电路，包括驱动晶体管，所述驱动晶体管设有栅极端、源极端和漏极端；设置所述第一电容连接于所述源极端和所述栅极端之间，所述第二电容连接于所述源极端和充电电压端，所述充电电压端通过所述第一开关和所述第二开关分别连接于所述复位电压信号端和所述数据电压信号端；所述漏极端通过所述第三开关连接于所述驱动电压信号端，所述栅极端通过所述第四开关连接于所述初始电压信号端。所述驱动电压信号端给源极端充电至栅极端与源极端的电位差为驱动晶体管的阈值电压Vth，再通过复位电压信号端给充电电压端充电，以使栅极端与源极端的电位差为Vref–Vdata+Vth–δV，使得驱动电流I＝k(Vref–Vdata–δV)2，其中δV与Vth无关，以使驱动电流与所述阈值电压Vth无关，从而使流过发光二极管的电流稳定，保证所述发光二极管的发光亮度均匀。
本申请提供的像素驱动方法，通过所述驱动电压信号端给源极端充电至栅极端与源极端的电位差为驱动晶体管的阈值电压Vth，再通过复位电压信号端给充电电压端充电，以使栅极端与源极端的电位差为Vref–Vdata+Vth–δV，使得驱动电流I＝k(Vref–Vdata–δV)2，其中δV与Vth无关，以使驱动电流与所述阈值电压Vth无关，从而使流过发光二极管的电流稳定，保证所述发光二极管的发光亮度均匀。
本申请提供的显示面板，包括上述像素驱动电路，可以使所述驱动晶体管产生的驱动电流与所述驱动晶体管的阈值电压无关，从而使所述驱动晶体管产 生的驱动电流稳定，消除了像素单元中由于驱动晶体管老化或制作工艺限制造成的阈值电压漂移的问题，从而使流过发光二极管的电流稳定，保证所述发光二极管的发光亮度均匀，改善画面的显示效果。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施例提供的像素驱动电路结构示意图。
图2是本申请第二实施例提供的像素驱动电路结构示意图。
图3是本申请实施例提供的一种显示面板的结构示意图。
图4是本申请实施例提供的像素驱动电路的时序图。
图5是本申请实施例提供的一种像素驱动方法流程图。
图6是本申请实施例提供的像素驱动电路的复位阶段的状态图。
图7是本申请实施例提供的像素驱动电路的存储阶段的状态图。
图8是本申请实施例提供的像素驱动电路的发光阶段的状态图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例的技术方案进行清楚、完整地描述。
请参阅图1，图1是本申请第一实施例提供的像素驱动电路，包括驱动晶体管T0、第一开关T1、第二开关T2、第三开关T3、第四开关T4、第一电容C11、第二电容C12、充电电压端n、初始电压信号端VINI、数据电压信号端VDATA、复位电压Vref信号端VREF和驱动电压信号端OVDD。所述驱动晶体管T0设有栅极端g、源极端s和漏极端d。
所述第一电容C11连接于所述源极端s和所述栅极端g之间，以存储所述栅极端g和所述源极端s之间的电位差。所述第二电容C12连接于所述源极端s和所述充电电压端n，所述充电电压端n通过所述第一开关T1和所述第二开关T2分 别连接于所述复位电压信号端VREF和所述数据电压信号端VDATA，以在所述充电电压端n加载复位电压Vref或数据电压Vdata。所述漏极端d通过所述第三开关T3连接于所述驱动电压信号端OVDD，以在所述漏极端d加载驱动电压Vdd。所述栅极端g通过所述第四开关T4连接于所述初始电压信号端VINI，以在所述栅极端g加载初始电压Vini。本实施例所述的开关包括但不限于开关电路、薄膜晶体管等具有控制电路通断功能的模块。
本实施例提供的像素驱动电路通过驱动方法控制在复位存储阶段所述第二开关T2、所述第三开关T3和所述第四开关T4导通，及所述第一开关T1关断，使所述栅极端g加载所述初始电压Vini，所述漏极端d加载所述驱动电压Vdd，所述驱动电压Vdd通过所述第三开关T3和所述驱动晶体管T0对所述源极端s充电，直至所述栅极端g与所述源极端s之间的电位差为所述驱动晶体管T0的阈值电压Vth；在电荷分享阶段所述第一开关T1导通，及所述第二开关T2、所述第三开关T3和所述第四开关T4关断，使所述充电电压端n加载复位电压Vref，以使所述栅极端g的电位和所述源极端s的电位变化，进而所述驱动晶体管T0产生的驱动电流I与所述驱动晶体管T0的阈值电压Vth无关，从而使所述驱动晶体管T0产生的驱动电流I稳定。
一种实施方式中，所述的像素驱动电路还包括第一控制信号端Scan1，所述第一控制信号端Scan1连接于所述第一开关T1的控制端和所述第二开关T2的控制端，以控制所述第一开关T1和所述第二开关T2的通断。
一种实施方式中，所述的像素驱动电路还包括第二控制信号端Scan2，所述第二控制信号端Scan2连接于所述第三开关T3的控制端，以控制所述第三开关T3的通断。
一种实施方式中，所述的像素驱动电路还包括第三控制信号端Scan3，所述第三控制信号端Scan3连接于所述第四开关T4的控制端，以控制所述第四开关T4的通断。
请参阅图2，图2是本申请第二实施例提供的像素驱动电路，包括第一实施例提供的像素驱动电路，使所述驱动晶体管T0产生的驱动电流I稳定。本实施例还包括发光二极管L、第五开关T5及负极电压信号端OVSS。所述发光二极管L可以是有机发光二极管等。所述发光二极管L具有正极端和负极端，所述第五开关T5连接于所述源极端s和所述正极端之间，以控制所述驱动晶体管T0 与所述发光二极管L的通断，所述负极端连接于所述负极电压信号端OVSS。当所述第三开关T3、所述驱动晶体管T0、所述第五开关T5导通时，所述驱动电压信号端OVDD与所述负极电压信号端OVSS导通，所述驱动晶体管T0产生的驱动电流I驱动所述发光二极管L发光。本实施例中所述驱动电流I与所述驱动晶体管T0的阈值电压Vth无关，消除了像素单元中由于驱动晶体管T0老化或制作工艺限制造成的阈值电压Vth漂移的问题，从而使流过发光二极管L的电流稳定，保证所述发光二极管L的发光亮度均匀，改善画面的显示效果。
一种实施方式中，所述的像素驱动电路还包括第四控制信号端Scan4，所述第四控制信号端Scan4连接于所述第五开关T5的控制端，以控制所述第五开关T5的通断。
一种实施方式中，所述第一开关T1、所述驱动晶体管T0、所述第三开关T3、所述第四开关T4、所述第五开关T5均为N型薄膜晶体管，当上述开关的控制端施加高电平电压时，开关处于导通状态，当上述开关的控制端施加低电平电压时，开关处于关断状态。所述第二开关T2为P型薄膜晶体管，当开关的控制端施加低电平电压时，所述第二开关T2处于导通状态，当开关的控制端施加高电平电压时，所述第二开关T2处于关断状态。在其他实施方式中，所述第一开关T1、所述驱动晶体管T0、所述第二开关T2、所述第三开关T3、所述第四开关T4、所述第五开关T5还可以为其他P型或/和N型薄膜晶体管组合，本申请不做限定。
本申请实施例中，像素驱动电路应用于显示面板或显示装置时，所述的控制信号端可以连接于显示面板或显示装置中的扫描信号线。
请参阅图3，本申请实施例还提供了一种显示面板100，包括上述任一种实施例提供的像素驱动电路，还包括初始电压信号线V1、数据电压信号线V2、驱动电压信号线V3、负极电压信号线V4及复位电压信号线V5。所述初始电压信号端VINI连接于所述初始电压信号线V1，以加载初始电压Vini。所述数据电压信号端VDATA连接于所述数据电压信号线V2，以加载数据电压Vdata。所述驱动电压信号端OVDD连接于所述驱动电压信号线V3，以加载驱动电压Vdd。所述负极电压信号端OVSS连接于所述负极电压信号线V4，以加载负极电压Vss。所述复位电压信号端VREF连接于所述复位电压信号线V5，以加载复位电压Vref。具体地，所述显示面板可以包括多个像素阵列，每个像素对应上述 本示例实施方式中的任一像素驱动电路。由于所述像素驱动电路消除了阈值电压对驱动电流I的影响，使得发光二极管L显示稳定，改善了显示面板显示亮度的均匀性，因此可以极大的提升显示品质。
请参阅一并参阅图4～图8，图4是本申请实施例提供的像素驱动电路的时序图。图5是本申请实施例提供的一种像素驱动方法S100，用于驱动上述实施例所述的像素驱动电路，包括
S101、请参阅图2及图3，提供像素驱动电路，包括驱动晶体管T0、发光二极管L、第一电容C11、第二电容C12、充电电压端n、数据电压信号端VDATA及复位电压信号端VREF。所述驱动晶体管T0设有栅极端g、源极端s和漏极端d。所述第一电容C11连接于所述源极端s和所述栅极端g之间，所述第二电容C12连接于所述源极端s和所述充电电压端n，所述充电电压端n连接于所述复位电压信号端VREF和所述数据电压信号端VDATA。所述源极端s连接于所述发光二极管L。
进一步地，所述像素驱动电路还包括第一开关T1、第二开关T2、第三开关T3、第四开关T4、第五开关T5、初始电压信号端VINI、驱动电压信号端OVDD、第一控制信号端Scan1、第二控制信号端Scan2、第三控制信号端Scan3和第四控制信号端Scan4。所述充电电压端n通过所述第一开关T1和所述第二开关T2分别连接于所述复位电压信号端VREF和所述数据电压信号端VDATA。所述漏极端d通过所述第三开关T3连接于所述驱动电压信号端OVDD，所述栅极端g通过所述第四开关T4连接于所述初始电压信号端VINI。所述第五开关T5连接于所述源极端s和所述发光二极管L之间。所述第一控制信号端Scan1连接于所述第一开关T1的控制端和所述第二开关T2的控制端，所述第二控制信号端Scan2连接于所述第三开关T3的控制端，所述第三控制信号端Scan3连接于所述第四开关T4的控制端，所述第四控制信号端Scan4连接于所述第五开关T5的控制端。
进一步地，所述像素驱动电路还包括负极电压信号端OVSS，所述发光二极管L具有正极端和负极端，所述第五开关T5连接于所述源极端s和所述正极端之间，所述负极端连接于所述负极电压信号端OVSS。
所述初始电压信号端VINI连接于初始电压信号线V1，用于加载初始电压Vini。所述数据电压信号端VDATA连接于数据电压信号线V2，用于加载数据 电压Vdata。所述驱动电压信号端OVDD连接于驱动电压信号线V3，用于加载驱动电压Vdd。所述负极电压信号端OVSS连接于负极电压信号线V4，用于加载负极电压Vss。所述复位电压信号端VREF连接于复位电压信号线V5，用于加载复位电压Vref。
S102、请一并参阅图4至图6，进入复位阶段t1，在所述充电电压端n加载数据电压Vdata，及在所述栅极端g加载初始电压Vini，及在所述漏极端d加载驱动电压Vdd以对所述源极端s充电，直到所述栅极端g电位和所述源极端s电位之差为Vth，所述Vth为所述驱动晶体管T0的阈值电压，并所述Vth存储于所述第一电容C11中。
一种实施方式中，设置所述第一控制信号端Scan1和所述第四控制信号端Scan4加载低电平信号，且所述第二控制信号端Scan2和所述第三控制信号端Scan3加载高电平信号，以使所述第二开关T2、所述第三开关T3和所述第四开关T4导通，及所述第一开关T1和所述第五开关T5关断，所述充电电压端n通过所述第二开关T2加载所述数据电压Vdata，所述栅极端g通过所述第四开关T4加载所述初始电压Vini，所述驱动电压Vdd通过所述第三开关T3和所述驱动晶体管T0对所述源极端s充电，直至所述源极端s的电位为Vini-Vth。
S103、请一并参阅图4、图5及图7，进入电荷分享阶段t2，在所述充电电压端n加载复位电压Vref以改变所述栅极端g和所述源极端s的电位，以使所述驱动晶体管T0的驱动电流稳定。
一种实施方式中，设置所述第一控制信号端Scan1和所述第三控制信号端Scan3加载高电平信号，且所述第二控制信号端Scan2和所述第四控制信号端Scan4加载低电平信号，以使所述第一开关T1导通，及所述第二开关T2、所述第三开关T3、所述第四开关T4和所述第五开关T5关断，所述充电电压端n通过所述第一开关T1加载所述复位电压Vref，以改变所述栅极端g和所述源极端s的电位。由电荷分享原理可知，所述栅极端g的电位为Vini+(Vref–Vdata)；所述源极端s的电位为Vini–Vth+δV，所述栅极端g电位与所述源极端s的电位之差Vgs为Vref–Vdata+Vth–δV，所述δV＝(Vref–Vdata)*C2/(C1+C2)，所述C1为所述第一电容C11的电容值，所述C2为所述第二电容C12的电容值。根据晶体管I-V曲线方程I＝k(Vgs-Vth)2，可计算得到I＝k[(Vref–Vdata)*C1/(C1+C2)]2,k为驱动晶体管T0的本征导电因子，由驱动晶体管T0本 身特性决定。可知，驱动电流I与驱动晶体管T0的阈值电压Vth无关，从而使所述驱动晶体管T0的驱动电流I稳定。
S104、请一并参阅图4、图5及图8，进入发光阶段t3，在所述充电电压端n加载所述复位电压Vref，且在所述漏极端d加载所述驱动电压Vdd以导通所述驱动晶体管T0和所述发光二极管L。
一种实施方式中，设置所述第一控制信号端Scan1、所述第二控制信号端Scan2和所述第四控制信号端Scan4加载高电平信号，且所述第三控制信号端Scan3加载低电平信号，以使所述第一开关T1、所述第三开关T3和所述第五开关T5导通，及所述第二开关T2和所述第四开关T4关断，所述充电电压端n通过所述第一开关T1加载所述复位电压Vref，以使所述源极端s的电位不变，则驱动电流I不变。所述第三开关T3、所述驱动晶体管T0及所述第五开关T5导通使得所述驱动电压Vdd端与所述负极电压信号端OVSS导通，以使驱动电流I驱动所述发光二极管L发光。因此，本申请实施例提供的像素驱动方法消除了阈值电压Vth对发光二极管L的影响，可提高面板显示的均匀性，提高发光效率。
综上所述，虽然本申请已以较佳实施例揭露如上，但该较佳实施例并非用以限制本申请，该领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种像素驱动电路，其中，包括驱动晶体管、第一开关、第二开关、第三开关、第四开关、第一电容、第二电容、充电电压端、初始电压信号端、数据电压信号端、复位电压信号端和驱动电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；
    所述第一电容连接于所述源极端和所述栅极端之间，所述第二电容连接于所述源极端和所述充电电压端，所述充电电压端通过所述第一开关和所述第二开关分别连接于所述复位电压信号端和所述数据电压信号端；所述漏极端通过所述第三开关连接于所述驱动电压信号端，所述栅极端通过所述第四开关连接于所述初始电压信号端。
  2. 如权利要求1所述的像素驱动电路，其中，还包括第一控制信号端，所述第一控制信号端连接于所述第一开关的控制端和所述第二开关的控制端，以控制所述第一开关和所述第二开关的通断。
  3. 如权利要求2所述的像素驱动电路，其中，还包括第二控制信号端，所述第二控制信号端连接于所述第三开关的控制端，以控制所述第三开关的通断。
  4. 如权利要求3所述的像素驱动电路，其中，还包括第三控制信号端，所述第三控制信号端连接于所述第四开关的控制端，以控制所述第四开关的通断。
  5. 如权利要求4所述的像素驱动电路，其中，还包括第五开关、第四控制信号端、发光二极管和负极电压信号端，所述第四控制信号端连接于所述第五开关的控制端，以控制所述第五开关的通断；所述发光二极管具有正极端和负极端，所述第五开关连接于所述源极端和所述正极端之间，以控制所述驱动晶体管与所述发光二极管的通断，所述负极端连接于所述负极电压信号端。
  6. 一种显示面板，其中，包括像素驱动电路，所述像素驱动电路包括驱动晶体管、第一开关、第二开关、第三开关、第四开关、第一电容、第二电容、充电电压端、初始电压信号端、数据电压信号端、复位电压信号端和驱动电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；
    所述第一电容连接于所述源极端和所述栅极端之间，所述第二电容连接于所述源极端和所述充电电压端，所述充电电压端通过所述第一开关和所述第二开关分别连接于所述复位电压信号端和所述数据电压信号端；所述漏极端通过所述第三开关连接于所述驱动电压信号端，所述栅极端通过所述第四开关连接于所述初始电压信号端。
  7. 如权利要求6所述的显示面板，其中，还包括第一控制信号端，所述第一控制信号端连接于所述第一开关的控制端和所述第二开关的控制端，以控制所述第一开关和所述第二开关的通断。
  8. 如权利要求7所述的显示面板，其中，还包括第二控制信号端，所述第二控制信号端连接于所述第三开关的控制端，以控制所述第三开关的通断。
  9. 如权利要求8所述的显示面板，其中，还包括第三控制信号端，所述第三控制信号端连接于所述第四开关的控制端，以控制所述第四开关的通断。
  10. 如权利要求9所述的显示面板，其中，还包括第五开关、第四控制信号端、发光二极管和负极电压信号端，所述第四控制信号端连接于所述第五开关的控制端，以控制所述第五开关的通断；所述发光二极管具有正极端和负极端，所述第五开关连接于所述源极端和所述正极端之间，以控制所述驱动晶体管与所述发光二极管的通断，所述负极端连接于所述负极电压信号端。
  11. 一种像素驱动方法，其中，包括
    提供像素驱动电路，包括驱动晶体管、发光二极管、第一电容、第二电容、充电电压端、数据电压信号端及复位电压信号端；所述驱动晶体管设有栅极端、源极端和漏极端；所述第一电容连接于所述源极端和所述栅极端之间，所述第二电容连接于所述源极端和所述充电电压端，所述充电电压端连接于所述复位电压信号端和所述数据电压信号端；所述源极端连接于所述发光二极管；
    复位存储阶段，在所述充电电压端加载数据电压，及在所述栅极端加载初始电压，及在所述漏极端加载驱动电压以对所述源极端充电，直到所述源极端电位和所述栅极端电位之差为Vth，所述Vth为所述驱动晶体管的阈值电压，并所述Vth存储于所述第一电容中；
    电荷分享阶段，在所述充电电压端加载复位电压以改变所述栅极端电位和所述源极端电位，以使所述驱动晶体管的驱动电流稳定；
    发光阶段，在所述充电电压端加载所述复位电压，且在所述漏极端加载所述驱动电压以导通所述驱动晶体管和所述发光二极管。
  12. 如权利要求11所述的像素驱动方法，其中，
    提供的所述像素驱动电路还包括第一开关、第二开关、第三开关、第四开关、第五开关、初始电压信号端、驱动电压信号端、第一控制信号端、第二控制信号端、第三控制信号和第四控制信号端；所述充电电压端通过所述第一开关和所述第二开关分别连接于所述复位电压信号端和所述数据电压信号端；所述漏极端通过所述第三开关连接于所述驱动电压信号端，所述栅极端通过所述第四开关连接于所述初始电压信号端；所述第五开关连接于所述源极端和所述发光二极管之间；所述第一控制信号端连接于所述第一开关的控制端和所述第二开关的控制端，所述第二控制信号端连接于所述第三开关的控制端，所述第三控制信号端连接于所述第四开关的控制端，所述第四控制信号端连接于所述第五开关的控制端；
    所述复位存储阶段，设置所述第一控制信号端和所述第四控制信号端加载低电平信号，且所述第二控制信号端和所述第三控制信号端加载高电平信号，以使所述第二开关、所述第三开关和所述第四开关导通，及所述第一开关和所述第五开关关断，所述充电电压端通过所述第二开关加载所述数据电压，所述数据电压为Vdata，所述栅极端通过所述第四开关加载所述初始电压，所述初始电压为Vini，所述驱动电压通过所述第三开关和所述驱动晶体管对所述源极端充电，直至所述源极端的电位为Vini-Vth。
  13. 如权利要求12所述的像素驱动方法，其中，
    所述电荷分享阶段，设置所述第一控制信号端加载高电平信号，且所述第二控制信号端、所述第三控制信号端和所述第四控制信号端加载低电平信号，以使所述第一开关导通，及所述第二开关、所述第三开关、所述第四开关和所述第五开关关断，所述充电电压端通过所述第一开关加载所述复位电压，所述复位电压为Vref，并使得所述栅极端的电位为Vini+(Vref–Vdata)；所述源极端的电位为Vini–Vth+δV，所述栅极端电位与所述源极端的电位之差为Vref–Vdata+Vth–δV，所述δV＝(Vref–Vdata)*C2/(C1+C2)，所述C1为所述第一电容的电容值，所述C2为所述第二电容的电容值，以使所述驱动电流 与所述阈值电压无关。
  14. 如权利要求13所述的像素驱动方法，其中，
    提供的所述像素驱动电路还包括负极电压信号端，所述发光二极管具有正极端和负极端，所述第五开关连接于所述源极端和所述正极端之间，所述负极端连接于所述负极电压信号端；
    所述发光阶段，设置所述第一控制信号端、所述第二控制信号端和所述第四控制信号端加载高电平信号，且所述第三控制信号端加载低电平信号，以使所述第一开关、所述第三开关和所述第五开关导通，及所述第二开关和所述第四开关关断，所述充电电压端通过所述第一开关加载所述复位电压，以使所述源极端的电位不变，所述第三开关、所述驱动晶体管及所述第五开关导通使得所述驱动电压端与所述负极电压信号端导通，以便于所述驱动电流驱动所述发光二极管发光。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107025883B (zh) * 2017-04-28 2019-05-03 深圳市华星光电半导体显示技术有限公司 显示面板、像素驱动电路及其驱动方法
CN107301845A (zh) * 2017-08-23 2017-10-27 深圳市华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法
KR20210114389A (ko) * 2019-01-16 2021-09-23 소니 세미컨덕터 솔루션즈 가부시키가이샤 전기 광학 장치 및 전자 기기
CN110428774A (zh) * 2019-07-19 2019-11-08 深圳市华星光电半导体显示技术有限公司 像素驱动电路和显示面板
KR102657133B1 (ko) 2019-07-22 2024-04-16 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
KR102591507B1 (ko) * 2019-07-22 2023-10-23 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
CN110534060A (zh) * 2019-09-05 2019-12-03 京东方科技集团股份有限公司 一种像素电路、其驱动方法、显示面板及显示装置
TWI720655B (zh) * 2019-10-17 2021-03-01 友達光電股份有限公司 畫素電路及其驅動方法
KR20210106052A (ko) 2020-02-19 2021-08-30 삼성디스플레이 주식회사 표시 장치
TWI738426B (zh) 2020-07-20 2021-09-01 友達光電股份有限公司 畫素電路及畫素電路驅動方法
KR20220014366A (ko) 2020-07-23 2022-02-07 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치
KR20220042007A (ko) * 2020-09-25 2022-04-04 삼성디스플레이 주식회사 발광 표시 장치
CN115440167B (zh) * 2022-08-30 2023-11-07 惠科股份有限公司 像素电路、显示面板和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102682706A (zh) * 2012-06-06 2012-09-19 四川虹视显示技术有限公司 一种amoled像素驱动电路
CN203300187U (zh) * 2013-05-21 2013-11-20 京东方科技集团股份有限公司 一种像素电路
CN103985351A (zh) * 2014-05-09 2014-08-13 深圳市华星光电技术有限公司 一种像素驱动电路及其驱动方法、显示面板
CN104167167A (zh) * 2013-05-17 2014-11-26 友达光电股份有限公司 像素电路及其驱动方法、显示装置
CN104183211A (zh) * 2013-05-20 2014-12-03 友达光电股份有限公司 像素电路及其驱动方法、发光显示器
US20160148571A1 (en) * 2014-11-24 2016-05-26 Samsung Display Co., Ltd. Organic light-emitting display device and method of driving the same
CN107025883A (zh) * 2017-04-28 2017-08-08 深圳市华星光电技术有限公司 显示面板、像素驱动电路及其驱动方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100606416B1 (ko) * 2004-11-17 2006-07-31 엘지.필립스 엘시디 주식회사 유기전계발광 다이오드의 구동 장치 및 구동방법
EP1857998A1 (en) * 2006-05-19 2007-11-21 TPO Displays Corp. System for displaying image and driving display element method
KR101194861B1 (ko) * 2006-06-01 2012-10-26 엘지디스플레이 주식회사 유기발광다이오드 표시소자
KR101030002B1 (ko) * 2009-10-08 2011-04-20 삼성모바일디스플레이주식회사 화소 회로 및 이를 이용한 유기전계발광 표시 장치
KR101127582B1 (ko) * 2010-01-04 2012-03-27 삼성모바일디스플레이주식회사 화소 회로, 유기 전계 발광 표시 장치 및 그 구동 방법
KR101859474B1 (ko) * 2011-09-05 2018-05-23 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치의 화소 회로
KR101893167B1 (ko) * 2012-03-23 2018-10-05 삼성디스플레이 주식회사 화소 회로, 이의 구동 방법 및 유기 발광 표시 장치
CN104240634B (zh) * 2013-06-17 2017-05-31 群创光电股份有限公司 像素结构及显示装置
CN104200779B (zh) * 2014-09-25 2016-09-07 上海天马有机发光显示技术有限公司 像素电路及其驱动方法、显示面板、显示装置
KR102324865B1 (ko) * 2014-12-29 2021-11-12 엘지디스플레이 주식회사 유기발광 표시장치와 그의 휘도 제어 방법
CN104751799B (zh) * 2015-04-10 2016-12-14 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN105161051A (zh) * 2015-08-21 2015-12-16 京东方科技集团股份有限公司 像素电路及其驱动方法、阵列基板、显示面板及显示装置
TWI569249B (zh) * 2016-07-01 2017-02-01 友達光電股份有限公司 畫素電路
CN205992407U (zh) * 2016-07-29 2017-03-01 上海中航光电子有限公司 一种双向扫描单元及栅极驱动电路
US10127859B2 (en) * 2016-12-29 2018-11-13 Lg Display Co., Ltd. Electroluminescent display

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102682706A (zh) * 2012-06-06 2012-09-19 四川虹视显示技术有限公司 一种amoled像素驱动电路
CN104167167A (zh) * 2013-05-17 2014-11-26 友达光电股份有限公司 像素电路及其驱动方法、显示装置
CN104183211A (zh) * 2013-05-20 2014-12-03 友达光电股份有限公司 像素电路及其驱动方法、发光显示器
CN203300187U (zh) * 2013-05-21 2013-11-20 京东方科技集团股份有限公司 一种像素电路
CN103985351A (zh) * 2014-05-09 2014-08-13 深圳市华星光电技术有限公司 一种像素驱动电路及其驱动方法、显示面板
US20160148571A1 (en) * 2014-11-24 2016-05-26 Samsung Display Co., Ltd. Organic light-emitting display device and method of driving the same
CN107025883A (zh) * 2017-04-28 2017-08-08 深圳市华星光电技术有限公司 显示面板、像素驱动电路及其驱动方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3618046A4 *

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