WO2016201847A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2016201847A1
WO2016201847A1 PCT/CN2015/092680 CN2015092680W WO2016201847A1 WO 2016201847 A1 WO2016201847 A1 WO 2016201847A1 CN 2015092680 W CN2015092680 W CN 2015092680W WO 2016201847 A1 WO2016201847 A1 WO 2016201847A1
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WIPO (PCT)
Prior art keywords
transistor
pole
voltage
phase
storage capacitor
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PCT/CN2015/092680
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English (en)
French (fr)
Inventor
徐攀
吴仲远
张玉婷
李永谦
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/102,993 priority Critical patent/US10068526B2/en
Publication of WO2016201847A1 publication Critical patent/WO2016201847A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to a pixel circuit, a method of driving a pixel circuit, and a display device.
  • the Organic Light-Emitting Diode (OLED) display device has the advantages of self-luminous, high contrast, wide color gamut, and the like, and has a broad application prospect due to its low power consumption and easy implementation of flexible display.
  • a set of thin film transistors and storage capacitors are integrated in each pixel circuit of the organic light emitting diode display device, and current control through the light emitting elements is realized by driving control of the thin film transistors and the storage capacitors.
  • the magnitude of the drive current is affected by the voltage across the light-emitting element when it is illuminated.
  • different light-emitting elements in the display device are affected by the process conditions, and the voltages at both ends of the light-emitting elements when they emit light are not completely the same, so that uneven brightness occurs.
  • a pixel circuit, a driving method of a pixel circuit, and a display device are provided to prevent an overvoltage of a light emitting element from affecting a driving current.
  • a pixel circuit provided by an embodiment of the present disclosure includes: a driving transistor, a storage capacitor, a data writing module, a light emitting element, and a predetermined voltage writing module;
  • a first end of the storage capacitor is connected to a gate of the driving transistor, a second end of the storage capacitor is connected to a second electrode of the driving transistor, and a first pole and a high level input of the driving transistor Connected to the end, the second pole of the driving transistor is connected to the anode of the light emitting element, and the cathode of the light emitting element is connected to the low level input end;
  • the predetermined voltage writing module is configured to cause a second pole of the driving transistor to reach a predetermined potential in a pre-charging phase and a compensation phase;
  • the data write module is configured to store a data voltage on the data line into the storage capacitor during a compensation phase.
  • a first input end of the data writing module is connected to the high level input end
  • a second input end of the data writing module is connected to a data line
  • an output end of the data writing module is Connected to the first end of the storage capacitor
  • the data write module is configured to store a voltage of a high level input terminal in the storage capacitor during a precharge phase, such that the storage capacitor is in the compensation phase
  • the first terminal potential is higher than a potential of the second end of the storage capacitor, and discharges the storage capacitor, and stores a data voltage and a voltage equivalent to a threshold voltage of the driving transistor to the storage capacitor after the discharging process ends .
  • the data writing module includes: a first transistor, a second transistor, a third transistor, a first scanning end, and a second scanning end;
  • a gate of the first transistor is connected to the first scan end, a first pole of the first transistor is connected to the high level input terminal, a second pole of the first transistor is opposite to the driving transistor Connected to the gate;
  • a gate of the second transistor is connected to the second scan end, a first pole of the second transistor is connected to a data line, a second pole of the second transistor is opposite to a second pole of the third transistor Connected, a first pole and a gate of the third transistor are both connected to a gate of the driving transistor, and a threshold voltage of the third transistor is the same as a threshold voltage of the driving transistor;
  • the first scan end is for providing an on signal during a precharge phase; the second scan end is for providing an on signal during a compensation phase.
  • the first scan end is connected to the first gate line
  • the second scan end is connected to the second gate line.
  • the predetermined voltage writing module includes a fourth transistor, a fourth scanning end, and a predetermined voltage input terminal,
  • a gate of the fourth transistor is connected to the fourth scan end, a first pole of the fourth transistor is connected to a second pole of the driving transistor, and a second pole of the fourth transistor is opposite to the predetermined
  • the voltage input terminals are connected to provide an turn-on signal during the pre-charge phase and the compensation phase and a turn-off signal during the light-emitting phase.
  • the predetermined voltage writing module further includes a fifth transistor and a fifth scanning end, a gate of the fifth transistor is connected to the fifth scanning end, and a first pole of the fifth transistor is The high level input terminal is connected, the second pole of the fifth transistor is connected to the first pole of the driving transistor, and the fifth scan terminal is used to provide off in the precharge phase and the compensation phase. The signal is broken and an on signal is provided during the illumination phase.
  • the fourth scan end is connected to the fourth gate line
  • the fifth scan end is connected to the fifth gate line.
  • the input voltage of the predetermined voltage input is zero.
  • the low level input serves as the predetermined voltage input.
  • the embodiment of the present disclosure further provides a driving method of a pixel circuit, which is the above-mentioned pixel circuit provided in the embodiment of the present disclosure, and the driving method includes:
  • a precharge phase wherein a voltage is written to the second electrode of the driving transistor by a predetermined voltage writing module such that a potential of the second electrode of the driving transistor is the predetermined potential;
  • the data voltage on the data line is stored into the storage capacitor through the data writing module;
  • a high level input terminal is electrically connected to an anode of the light emitting element to cause the light emitting element to emit light.
  • the driving method comprises:
  • the data line is electrically connected to the first end of the storage capacitor through the data writing module to discharge the storage capacitor, and the data voltage on the data line and the driving transistor are discharged after the end of discharging The voltage of the threshold voltage equivalent is stored to the storage capacitor.
  • the data writing module includes a first transistor, a second transistor, a third transistor, a first scanning end, and a second scanning end, and a gate of the first transistor is connected to the first scanning end, a first pole of the first transistor is connected to the high level input terminal, and a second pole of the first transistor is connected to a gate of the driving transistor;
  • a gate of the second transistor is connected to the second scan end, a first pole of the second transistor is connected to a data line, a second pole of the second transistor is opposite to a second pole of the third transistor Connected, a first pole and a gate of the third transistor are both connected to a gate of the driving transistor, and a threshold voltage of the third transistor is the same as a threshold voltage of the driving transistor;
  • the driving method includes:
  • an opening signal is respectively provided to the first scanning end, and an off signal is provided to the second scanning end, so that the first transistor is turned on, the second crystal The tube is turned off, and the voltage of the high level input terminal is stored to the storage capacitor through the first transistor;
  • an open signal is respectively provided to the second scan end, and an off signal is provided to the first scan end, so that the second transistor and the third transistor are turned on, and the first transistor is turned off. Disconnecting, and causing the data voltage and the threshold voltage of the third transistor to be stored to the storage capacitor after the storage capacitor is discharged;
  • a turn-off signal is provided to the first scan end and the second scan end, respectively, such that the first transistor and the second transistor are turned off.
  • the predetermined voltage writing module includes a fourth transistor, a fourth scanning end and a predetermined voltage input end, a gate of the fourth transistor is connected to the fourth scanning end, and a fourth transistor One pole is connected to the second pole of the driving transistor, and the second pole of the fourth transistor is connected to the predetermined voltage input terminal;
  • the driving method includes:
  • a turn-off signal is provided to the fourth scan terminal to turn off the fourth transistor and cause the high level input to be conductive to the anode of the light emitting element.
  • the predetermined voltage writing module further includes a fifth transistor and a fifth scanning end, a gate of the fifth transistor is connected to the fifth scanning end, and a first pole of the fifth transistor is The high-level input terminal is connected, and the second electrode of the fifth transistor is connected to the first pole of the driving transistor, and the driving method further includes:
  • the pre-charging phase and the compensation phase are turned off and turned on in the light-emitting phase such that the high-level input is disconnected from the light-emitting element during the pre-charging phase and the compensation phase, and the light is emitted
  • the stage is turned on.
  • the voltage input to the predetermined voltage input is zero.
  • the low level input serves as the predetermined voltage input.
  • an embodiment of the present disclosure further provides a display device including the above-described pixel circuits provided in the embodiments of the present disclosure.
  • the second pole of the driving transistor reaches a predetermined potential in the pre-charging phase and the compensation phase.
  • the voltage stored by the storage capacitor is independent of the voltage across the light-emitting element, and the gate-source voltage of the driving transistor is also It is independent of the cross-voltage of the light-emitting element. Due to the bootstrap action of the storage capacitor, the gate-source voltage of the driving transistor is kept the same as the compensation phase in the light-emitting phase, so that the driving current flowing through the light-emitting element is independent of the voltage across the light-emitting element, thereby eliminating factors such as degradation of the light-emitting element.
  • the display is uneven and so on.
  • 1 is a schematic structural view of a known pixel circuit
  • FIG. 2 is a block diagram showing the structure of a pixel circuit in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a specific structure of a pixel circuit in an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of signals provided by respective scanning ends of a pixel circuit in an embodiment of the present disclosure.
  • the pixel circuit includes four thin film transistors T1, T2, T3, and Tr and a storage capacitor Cs.
  • ELVDD is the high level input
  • VSS is the low level input
  • Data is the data line
  • Vn-1 and Vn are the scan lines.
  • the driving current through the light-emitting element is:
  • I oled k(V data -V oled ) 2
  • V data is a data voltage
  • Voled is a voltage at both ends when the light emitting element emits light.
  • FIG. 2 schematically shows a structural block diagram of a pixel circuit in an embodiment of the present disclosure.
  • a pixel circuit including a drive transistor Tr, a storage capacitor Cs, a data write module 10, a light-emitting element 20, and a predetermined voltage write module 30 is provided.
  • the first end of the storage capacitor Cs is connected to the gate of the driving transistor Tr, and the storage capacitor Cs The second end is connected to the second pole of the drive transistor Tr.
  • the first electrode of the driving transistor Tr is connected to the high level input terminal ELVDD
  • the second electrode of the driving transistor Tr is connected to the anode of the light emitting element 20
  • the cathode of the light emitting element is connected to the low level input terminal VSS.
  • the predetermined voltage writing module 30 is for causing the second pole (ie, node P) of the driving transistor Tr to reach a predetermined potential in the precharge phase and the compensation phase.
  • the data write module 10 is used to store the data voltage on the data line into the storage capacitor Cs during the compensation phase.
  • the storage capacitor Cs is connected between the gate and the second pole of the drive transistor Tr, and the second pole of the drive transistor Tr reaches a predetermined potential V 0 in the precharge phase and the compensation phase.
  • Data write phase compensation module 10 may be a data voltage V data stored in the storage capacitor Cs. Therefore, in the compensation phase, the voltage across the storage capacitor Cs is V data -V 0 . That is, the gate-source voltage V gs of the drive transistor Tr is V data -V 0 before the light-emitting phase.
  • V thr is a threshold voltage of the driving transistor Tr.
  • the second end of the storage capacitor is connected to the low-level input terminal VSS, and the cathode of the light-emitting element 20 is also connected to the low-level input terminal, and the voltage across the light-emitting element 20 in each pixel unit is
  • the (cross voltage) may be different, so that the gate-source voltage V gs of the driving transistor Tr in different pixel units may also be different, so that the driving current flowing through the light-emitting elements in different pixel units may be different, resulting in uneven illumination.
  • one end of the storage capacitor Cs is connected to the anode of the light-emitting element 20, and the other end is connected to the gate of the drive transistor Tr.
  • the driving current flowing through the light-emitting element 20 is not affected by the voltage across the light-emitting element, thereby eliminating the influence of the inconsistency of the cross-voltage of the different light-emitting elements 20 on the uniformity of the light.
  • the first input end of the data writing module 10 is connected to the high level input terminal ELVDD
  • the second input end of the data writing module 10 is connected to the data line Data
  • the data writing module 10 is The output terminal is connected to the first end of the storage capacitor Cs.
  • Data write module 10 for storing the voltage of the high-level input terminal into the storage capacitor Cs in the pre-charging phase, so that the potential of the first end of the storage capacitor Cs is higher than the potential of the second end of the storage capacitor Cs during the compensation phase, so that the storage capacitor Cs The discharge is performed, and after the end of the discharge, the data voltage and the voltage equivalent to the threshold voltage of the drive transistor Tr are stored to the storage capacitor Cs.
  • the second pole of the drive transistor Tr reaches a predetermined potential V 0 in the precharge phase and the compensation phase, and the threshold voltage of the drive transistor Tr is V thr .
  • the voltage between the first terminal of the storage capacitor Cs and ground is equal to the voltage of the high level input terminal ELVDD, and the voltage between the second terminal of the storage capacitor and ground is V 0 . Therefore, in the compensation phase, after the discharge of the storage capacitor is completed, the voltage across the storage capacitor Cs is V data +V thr -V 0 .
  • the gate-source voltage Vgs of the drive transistor Tr is also kept constant, and the drive current through the light-emitting element is:
  • the driving current Ioled is independent of the threshold voltage of the driving transistor Tr, thereby eliminating the phenomenon that the luminance of the light-emitting element is uneven due to the threshold voltage drift of the driving transistor.
  • the drive current is also independent of the voltage at the high level input ELVDD, thereby eliminating the problem of IR drop.
  • the light emitting element 20 in the embodiment of the present disclosure is an organic electroluminescent diode. It can be understood that since the pre-charging phase and the compensation phase before the illuminating phase take a short time in one frame period, the voltage of the second pole of the driving transistor has less influence on the driving current of the illuminating element. In order to prevent the light-emitting element 20 from emitting light before the light-emitting phase, the predetermined potential V 0 may not be greater than the cathode potential of the light-emitting element 20.
  • the voltage equivalent to the threshold voltage of the driving transistor Tr indicates that the manner of acquiring the threshold voltage is not limited, and the threshold voltage of the driving transistor Tr can be directly obtained, or the threshold voltage of the transistor whose threshold voltage is equal to the driving transistor can be obtained, thereby obtaining indirectly.
  • the threshold voltage to the drive transistor Tr indicates that the manner of acquiring the threshold voltage is not limited, and the threshold voltage of the driving transistor Tr can be directly obtained, or the threshold voltage of the transistor whose threshold voltage is equal to the driving transistor can be obtained, thereby obtaining indirectly.
  • the threshold voltage to the drive transistor Tr indicates that the manner of acquiring the threshold voltage is not limited, and the threshold voltage of the driving transistor Tr can be directly obtained, or the threshold voltage of the transistor whose threshold voltage is equal to the driving transistor can be obtained, thereby obtaining indirectly.
  • FIG. 3 exemplarily shows a schematic structural diagram of a pixel circuit in an embodiment of the present disclosure.
  • the data writing module 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a first scanning end S1, and a second scanning end S2.
  • the gate of the first transistor T1 is connected to the first scan terminal S1
  • the first electrode of the first transistor T1 is connected to the high level input terminal ELVDD (ie, the first pole of the first transistor T1 and the first data writing module 10)
  • ELVDD high level input terminal
  • the second electrode of the first transistor T1 is connected to the gate of the driving transistor Tr.
  • the gate of the second transistor T2 is connected to the second scan terminal S2, and the first pole of the second transistor T2 is connected to the data line Data (ie, the first pole of the second transistor T2 and the second input terminal of the data writing module 10) For the same end).
  • the second pole of the second transistor T2 is connected to the second pole of the third transistor T3.
  • the first electrode and the gate of the third transistor T3 are both connected to the gate of the drive transistor Tr.
  • the threshold voltage of the third transistor T3 is the same as the threshold voltage of the drive transistor Tr.
  • the first scanning end S1 is for providing an on signal during the precharge phase; the second scanning end S2 is for providing an on signal during the compensation phase.
  • the first scan terminal S1 controls the first transistor T1 to be turned on, and the high level signal terminal ELVDD charges the storage capacitor Cs through the first transistor T1 until the potential of the first terminal of the storage capacitor Cs reaches V dd .
  • the second scanning terminal S2 controls the second transistor T2 to be turned on, the third transistor T3 forms a diode connection, and the storage capacitor Cs discharges until the potential of the first terminal of the storage capacitor Cs reaches V data + V th3 .
  • the third transistor T3 is a mirror transistor of the drive transistor Tr and has the same electrical characteristics as the drive transistor Tr.
  • the threshold voltage of the driving transistor Tr can be indirectly obtained by acquiring the threshold voltage of the third transistor T3, and the third transistor T3 and the driving transistor Tr form a mirror current source, thereby providing a stable driving current for the light emitting element and improving the stability of the circuit. Sex.
  • the predetermined voltage writing module 30 includes a fourth transistor T4, a fourth scanning terminal S4, and a predetermined voltage input terminal.
  • the gate of the fourth transistor T4 is connected to the fourth scanning terminal S4, the first electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor Tr, and the second electrode of the fourth transistor T4 is connected to the predetermined voltage input terminal.
  • the fourth scanning terminal S4 is for providing an on signal during the precharge phase and the compensation phase, and providing an off signal during the illumination phase, so that the fourth transistor T4 is turned on in the precharge phase and the compensation phase, and the node P reaches a predetermined potential.
  • the predetermined voltage writing module 30 may alternatively be A fifth transistor T5 and a fifth scan terminal S5 are included.
  • the gate of the fifth transistor T5 is connected to the fifth scan terminal S5, the first electrode of the fifth transistor T5 is connected to the high level input terminal ELVDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor Tr.
  • the fifth scanning terminal T5 is for providing a turn-off signal during the pre-charge phase and the compensation phase, and providing an turn-on signal during the light-emitting phase. Therefore, in the pre-charging phase and the compensation phase, the fifth The transistor T5 is turned off, and the potential at the point P reaches a predetermined potential without being affected by the voltage of the high-level input terminal ELVDD.
  • the input voltage of the predetermined voltage input may be zero, ie the predetermined voltage input is connected to ground.
  • the low level input terminal VSS can serve as the predetermined voltage input terminal to reduce the setting of the signal terminal, thereby simplifying the circuit structure.
  • the voltage across the storage capacitor Cs is V data +V th3 .
  • the voltage across the storage capacitor Cs remains the same as the compensation phase, still V data + V th3 .
  • the driving current flowing through the light emitting element 20 is:
  • I oled (W/2L) ⁇ n C ox (V gs -V thr ) 2
  • I oled is a driving current flowing through the light emitting element 20;
  • V th3 is a threshold voltage of the third transistor T3
  • V thr is a threshold voltage of the driving transistor Tr
  • n n is the carrier mobility
  • C ox is the unit capacitance of the gate oxide of the driving transistor
  • W/L is the aspect ratio of the conductive channel of the driving transistor.
  • I oled (W / 2L) ⁇ n C ox (V data ) 2 .
  • a first gate line, a second gate line, a fourth gate line, a fifth gate line, and a gate driving circuit may be disposed, and the first scanning end may be coupled to the first gate Connected to the line, the second scan end may be connected to the second gate line, the fourth scan end may be connected to the fourth gate line, and the fifth scan end may be connected to the fifth gate line to make the gate drive
  • the circuit provides drive signals for the first scan end, the second scan end, the fourth scan end, and the fifth scan end.
  • Each of the transistors in the embodiments of the present disclosure is an N-type transistor, a drain of the first very N-type transistor, and a source of the second extremely N-type transistor.
  • the turn-on signal is a high level signal and the turn-off signal is a low level signal.
  • each transistor can also be set as a P-type transistor, in which case the source of the first extreme P-type transistor and the second extreme P-type transistor.
  • the drain, correspondingly, the turn-on signal supplied to the P-type transistor is a low level signal, and the turn-off signal is a high level signal.
  • FIG. 4 shows a schematic diagram of signals provided by respective scanning ends of a pixel circuit in an embodiment of the present disclosure.
  • a driving method of the above pixel circuit comprising the following steps:
  • a voltage is written to the second electrode of the drive transistor Tr through the predetermined voltage write module 20 such that the potential of the second electrode of the drive transistor is at the predetermined potential and is passed through the data write module 10
  • the voltage of the high level input terminal is stored to the storage capacitor Cs;
  • the data voltage on the data line is stored into the storage capacitor Cs through the data writing module 30;
  • the high level input terminal is turned on with the anode of the light emitting element 20 to cause the light emitting element 20 to emit light.
  • the voltage across the storage capacitor Cs is V data +V thr -V 0 . That is, the gate-source voltage V gs of the drive transistor Tr is V data -V 0 before the light-emitting phase. Therefore, in the light-emitting phase, even if the voltage V oled across the light-emitting element 20 causes the second-pole potential of the drive transistor Tr to rise, the gate-source voltage V gs of the drive transistor Tr is maintained due to the bootstrap action of the storage capacitor Cs.
  • the constant driving current through the light-emitting element is:
  • V thr is a threshold voltage of the driving transistor Tr.
  • the driving current flowing through the light-emitting element is independent of the voltage across the light-emitting element 20, thereby eliminating the phenomenon of display unevenness caused by factors such as degradation of the light-emitting element.
  • the driving method includes:
  • the voltage of the high-level input terminal is stored into the storage capacitor through the data writing module 10; in the compensation phase, the data line is stored by the data writing module 10
  • the first end of the storage capacitor Cs is turned on to discharge the storage capacitor Cs, and the data voltage on the data and the voltage equivalent to the threshold voltage of the driving transistor are stored to the storage capacitor Cs after the end of the discharge.
  • the voltage between the first terminal of the storage capacitor Cs and ground is equal to the voltage of the high level input terminal ELVDD, and the voltage between the second terminal of the storage capacitor and ground is V 0 . Therefore, in the compensation phase, after the discharge of the storage capacitor is completed, the voltage across the storage capacitor Cs is V data +V thr -V 0 .
  • the gate-source voltage of the drive transistor Tr is also caused by the bootstrap action of the storage capacitor Cs. V gs remains unchanged, and the driving current through the light-emitting elements is:
  • the driving current Ioled is independent of the threshold voltage of the driving transistor Tr, thereby eliminating the phenomenon that the luminance of the light-emitting element is uneven due to the threshold voltage drift of the driving transistor.
  • the drive current is also independent of the voltage at the high level input ELVDD, thereby eliminating the problem of IR drop.
  • the data writing module 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a first scan terminal S1, and a second scan terminal S2, the gate of the first transistor T1 and The first scan terminal S1 is connected, the first pole of the first transistor T1 is connected to the high level input terminal, and the second pole of the first transistor T1 is connected to the gate of the driving transistor Tr;
  • the gate of the second transistor T2 is connected to the second scanning terminal S2, the first electrode of the second transistor T2 is connected to the data line, the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3, and the third transistor
  • the first pole and the gate of T3 are both connected to the gate of the drive transistor Tr, and the threshold voltage of the third transistor T3 is the same as the threshold voltage of the drive transistor Tr.
  • the driving method includes:
  • an open signal is supplied to the first scan terminal S1, and a turn-off signal is supplied to the second scan terminal S2, so that the first transistor T1 is turned on and the second transistor T2 is turned off. Break, the voltage of the high level input terminal is stored to the storage capacitor Cs through the first transistor;
  • an open signal is respectively supplied to the second scan terminal S2, and an off signal is provided to the first scan terminal S1, so that the second transistor T2 and the third transistor T3 are turned on.
  • the first transistor T1 is turned off, and the storage voltage is discharged, and the data voltage V data and the threshold voltage of the third transistor T3 are stored to the storage capacitor Cs.
  • the potential of the first terminal of the storage capacitor Cs reaches Vdd after the end of the precharge phase, and the third transistor T3 is turned on. Therefore, the storage capacitor Cs is discharged through the third transistor, and the potential of the first terminal of the storage capacitor Cs is lowered to V.
  • the third transistor T3 is turned off, and the storage capacitor Cs stops discharging;
  • a turn-off signal is supplied to the first scan terminal S1 and the second scan terminal S2, respectively, so that the first transistor T1 and the second transistor T2 are turned off.
  • the predetermined voltage writing module 30 includes a fourth transistor T4, a fourth scanning terminal S4 and a predetermined voltage input terminal, a gate of the fourth transistor T4 is connected to the fourth scanning terminal S4, and a first electrode of the fourth transistor T4 and a driving transistor Tr The second pole of the fourth transistor T4 is connected to the predetermined voltage input terminal.
  • the driving method includes:
  • an on signal is provided to the fourth scanning terminal S4 to turn on the fourth transistor T4, so that the second electrode of the driving transistor Tr is turned on with the predetermined voltage input terminal, thereby causing the driving transistor Tr to be The potential of the two poles reaches a predetermined potential;
  • a turn-off signal is supplied to the fourth scan terminal S4 to turn off the fourth transistor and cause the high-level input terminal ELVDD to be turned on with the anode of the light-emitting element 20.
  • the predetermined voltage writing module further includes a fifth transistor T5 and a fifth scanning terminal S5.
  • the gate of the fifth transistor T5 is connected to the fifth scanning terminal S5, and the first electrode of the fifth transistor T5 is connected to the high level input terminal ELVDD.
  • the second electrode of the fifth transistor T5 is connected to the first electrode of the drive transistor Tr.
  • the driving method further includes:
  • a turn-off signal is supplied to the fifth scan terminal S5, and an turn-on signal is supplied to the fifth scan terminal S5 in the light-emitting phase, so that the fifth transistor T5 is turned off during the pre-charge phase and turned on during the light-emitting phase.
  • the high level input terminal ELVDD is disconnected from the light emitting element 20 during the precharge phase and the compensation phase, and is turned on during the light emitting phase, thereby preventing the light emitting element 20 from emitting light during the precharge phase and the compensation phase.
  • the input voltage of the predetermined voltage input is zero, ie, the potential at point P is zero during the pre-charge phase and the compensation phase.
  • the low level input terminal VSS serves as the predetermined voltage input terminal, thereby reducing the setting of the signal terminal and simplifying the circuit structure.
  • a display device including a plurality of the above pixel circuits.
  • the display device further includes a plurality of data lines, each column of pixel circuits corresponding to one data line, and the second input end of the data writing module is connected to the corresponding data line, in the compensation stage Segment, the data voltage on the data line is stored in the storage capacitor.
  • the display device may further include a plurality of gate line groups, each of the gate line groups including a first gate line, a second gate line, and a gate driving circuit, the first gate line being connected to the first scanning end S1 and Between the gate driving circuits, the second gate line is connected between the second scanning terminal S2 and the gate driving circuit, and the gate driving circuit can provide an opening signal to the first scanning terminal S1 in a precharge phase An on signal is provided to the second scanning terminal S2 during the compensation phase.
  • the predetermined voltage writing module 30 includes a fourth transistor T4, a fourth scanning terminal S4 and a predetermined voltage input terminal, a gate of the fourth transistor T4 is connected to the fourth scanning terminal S4, and a first electrode of the fourth transistor T4 and a driving transistor Tr The second pole of the fourth transistor T4 is connected to the predetermined voltage input terminal.
  • Each of the gate line groups further includes a fourth gate line connected between the fourth scan terminal S4 and the gate driving circuit, and the gate driving circuit may be in the precharge phase and the compensation
  • the stage provides an on signal to the fourth scan terminal S4 and provides an off signal to the fourth scan terminal S4 during the illumination phase, thereby causing the fourth transistor T4 to be turned on during the precharge phase and the compensation phase, so that the potential of the node P reaches a predetermined level.
  • the fourth transistor T4 is turned off during the light emitting phase so that the high level input terminal is turned on with the anode of the light emitting element.
  • the predetermined voltage writing module further includes a fifth transistor T5 and a fifth scanning terminal S5.
  • the gate of the fifth transistor T5 is connected to the fifth scanning terminal S5, and the first electrode of the fifth transistor T5 is connected to the high level input terminal ELVDD.
  • the second electrode of the fifth transistor T5 is connected to the first electrode of the drive transistor Tr.
  • Each of the gate line groups further includes a fifth gate line connected between the fifth scan terminal S5 and the gate driving circuit, and the gate driving circuit may be in the pre-charging phase and the compensation phase
  • the fifth scan terminal S5 provides a turn-off signal, and provides an turn-on signal to the fifth scan terminal S5 during the light-emitting phase, so that the fifth transistor T5 is turned off during the pre-charge phase and the compensation phase, and is turned on during the light-emitting phase to prevent the light-emitting component from being pre-charged.
  • the charging phase and the compensation phase illuminate.
  • the display device may further include a ground line, the predetermined voltage input end being connected to the ground line, and the low level input end may also be connected to the ground line.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the driving current is not subject to the threshold.
  • the value voltage and the voltage across the light-emitting element affect the uniformity of the brightness of the light-emitting element, thereby improving the display effect of the display device.

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Abstract

公开了一种像素电路及其驱动方法和一种显示装置。该像素电路包括：驱动晶体管（Tr）、存储电容（Cs）、数据写入模块（10）、发光元件（20）和预定电压写入模块（30）。存储电容（Cs）的第一端与驱动晶体管（Tr）的栅极相连，存储电容（Cs）的第二端与驱动晶体管（Tr）的第二极相连，预定电压写入模块（30）用于使得驱动晶体管（Tr）的第二极在预充电阶段和补偿阶段达到预定电位；数据写入模块（10）用于在补偿阶段将数据线上的数据电压存储至存储电容（Cs）中。在该像素电路及其驱动方法和显示装置中，驱动电流不受阈值电压的影响，且消除了发光元件的跨压对驱动电流的影响，因此，提高了发光元件亮度的均匀性，改善了显示装置的显示效果。

Description

像素电路及其驱动方法、显示装置 技术领域
本公开涉及一种像素电路、一种像素电路的驱动方法和一种显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置具有能自发光、对比度高、色域度广等优点，同时由于其功耗低、易于实现柔性显示，因而具有广阔的应用前景。
有机发光二极管显示装置的每个像素电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对通过发光元件的电流控制。
然而，驱动电流的大小会受到发光元件发光时两端的电压的影响。而显示装置中不同的发光元件受工艺条件的影响，其发光元件发光时两端的电压也不完全相同，从而出现亮度不均匀的现象。
发明内容
在本公开的一些实施例中提供一种像素电路、一种像素电路的驱动方法和一种显示装置，以防止发光元件的跨压对驱动电流产生影响。
本公开实施例提供的像素电路，包括：驱动晶体管、存储电容、数据写入模块、发光元件和预定电压写入模块；
所述存储电容的第一端与所述驱动晶体管的栅极相连，所述存储电容的第二端与所述驱动晶体管的第二极相连，所述驱动晶体管的第一极与高电平输入端相连，所述驱动晶体管的第二极与所述发光元件的阳极相连，所述发光元件的阴极与低电平输入端相连；
所述预定电压写入模块用于使得所述驱动晶体管的第二极在预充电阶段和补偿阶段达到预定电位；
所述数据写入模块用于在补偿阶段将数据线上的数据电压存储至所述存储电容中。
可选择地，所述数据写入模块的第一输入端与所述高电平输入端相连，所述数据写入模块的第二输入端与数据线相连，所述数据写入模块的输出端与所述存储电容的第一端相连，所述数据写入模块用于在预充电阶段将高电平输入端的电压存储在所述存储电容中，以使得在所述补偿阶段所述存储电容的第一端电位高于所述存储电容的第二端的电位，并使得所述存储电容放电，并在放电过程结束后将数据电压以及与驱动晶体管的阈值电压等值的电压存储至所述存储电容。
可选择地，所述数据写入模块包括：第一晶体管、第二晶体管、第三晶体管、第一扫描端和第二扫描端；
所述第一晶体管的栅极与所述第一扫描端相连，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述驱动晶体管的栅极相连；
所述第二晶体管的栅极与所述第二扫描端相连，所述第二晶体管的第一极与数据线相连，所述第二晶体管的第二极与所述第三晶体管的第二极相连，所述第三晶体管的第一极和栅极均与所述驱动晶体管的栅极相连，所述第三晶体管的阈值电压与所述驱动晶体管的阈值电压相同；
所述第一扫描端用于在预充电阶段提供开启信号；所述第二扫描端用于在补偿阶段提供开启信号。
可选择地，所述第一扫描端与第一栅线相连，所述第二扫描端与第二栅线相连。
可选择地，所述预定电压写入模块包括第四晶体管、第四扫描端和预定电压输入端，
所述第四晶体管的栅极与所述第四扫描端相连，所述第四晶体管的第一极与所述驱动晶体管的第二极相连，所述第四晶体管的第二极与所述预定电压输入端相连，所述第四扫描端用于在预充电阶段和补偿阶段提供开启信号、在发光阶段提供关断信号。
可选择地，所述预定电压写入模块还包括第五晶体管和第五扫描端，所述第五晶体管的栅极与所述第五扫描端相连，所述第五晶体管的第一极与所述高电平输入端相连，所述第五晶体管的第二极与所述驱动晶体管的第一极相连，所述第五扫描端用于在预充电阶段和补偿阶段提供关 断信号、在发光阶段提供开启信号。
可选择地，所述第四扫描端与第四栅线相连，所述第五扫描端与第五栅线相连。
可选择地，所述预定电压输入端的输入电压为零。
可选择地，所述低电平输入端作为所述预定电压输入端。
相应地，本公开的实施例中还提供一种像素电路的驱动方法，所述像素电路为本公开实施例中提供的上述像素电路，所述驱动方法包括：
预充电阶段，通过预定电压写入模块向所述驱动晶体管的第二极写入电压，以使得所述驱动晶体管的第二极的电位为所述预定电位；
补偿阶段，通过数据写入模块将数据线上的数据电压存储至所述存储电容中；
发光阶段，将高电平输入端与所述发光元件的阳极导通，以使得所述发光元件发光。
可选择地，所述驱动方法包括：
在所述预充电阶段，通过所述数据写入模块将高电平输入端的电压存储至所述存储电容中；
在所述补偿阶段，通过所述数据写入模块将数据线与所述存储电容的第一端导通，以使得存储电容放电，并在放电结束后将数据线上的数据电压以及与驱动晶体管的阈值电压等值的电压存储至所述存储电容。
可选择地，所述数据写入模块包括第一晶体管、第二晶体管、第三晶体管、第一扫描端和第二扫描端，所述第一晶体管的栅极与所述第一扫描端相连，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述驱动晶体管的栅极相连；
所述第二晶体管的栅极与所述第二扫描端相连，所述第二晶体管的第一极与数据线相连，所述第二晶体管的第二极与所述第三晶体管的第二极相连，所述第三晶体管的第一极和栅极均与所述驱动晶体管的栅极相连，所述第三晶体管的阈值电压与所述驱动晶体管的阈值电压相同；
所述驱动方法包括：
在所述预充电阶段，分别向所述第一扫描端提供开启信号，向所述第二扫描端提供关断信号，以使得所述第一晶体管开启、所述第二晶体 管关断，所述高电平输入端的电压通过所述第一晶体管存储至所述存储电容；
在所述补偿阶段，分别向所述第二扫描端提供开启信号，向所述第一扫描端提供关断信号，以使得所述第二晶体管和所述第三晶体管开启，同时第一晶体管关断，并使得所述存储电容放电结束后将数据电压以及所述第三晶体管的阈值电压存储至所述存储电容；
在所述发光阶段，分别向所述第一扫描端和所述第二扫描端提供关断信号，以使得所述第一晶体管和所述第二晶体管关断。
可选择地，所述预定电压写入模块包括第四晶体管、第四扫描端和预定电压输入端，所述第四晶体管的栅极与所述第四扫描端相连，所述第四晶体管的第一极与所述驱动晶体管的第二极相连，所述第四晶体管的第二极与所述预定电压输入端相连；所述驱动方法包括：
在所述预充电阶段和所述补偿阶段，向所述第四扫描端提供开启信号，以使得所述第四晶体管开启，所述驱动晶体管的第二极与所述预定电压输入端导通；
在所述发光阶段，向第四扫描端提供关断信号，以使得所述第四晶体管关断，并使得所述高电平输入端与所述发光元件的阳极导通。
可选择地，所述预定电压写入模块还包括第五晶体管和第五扫描端，所述第五晶体管的栅极与所述第五扫描端相连，所述第五晶体管的第一极与所述高电平输入端相连，所述第五晶体管的第二极与所述驱动晶体管的第一极相连，所述驱动方法还包括：
在所述预充电阶段和所述补偿阶段，向所述第五扫描端提供关断信号，在所述发光阶段，向所述第五扫描端提供开启信号，以使得所述第五晶体管在所述预充电阶段和所述补偿阶段关断，并在所述发光阶段开启，使得所述高电平输入端与发光元件在所述预充电阶段和所述补偿阶段断开，并在所述发光阶段导通。
可选择地，所述预定电压输入端输入的电压为零。
可选择地，所述低电平输入端作为所述预定电压输入端。
相应地，本公开的实施例中还提供一种显示装置，包括多个本公开实施例中提供的上述像素电路。
在本公开的实施例中，驱动晶体管的第二极在预充电阶段和补偿阶段达到预定电位，在补偿阶段，存储电容所存储的电压与发光元件的跨压无关，驱动晶体管的栅源电压也与发光元件的跨压无关。由于存储电容的自举作用使得在发光阶段驱动晶体管的栅源电压保持与补偿阶段相同，以使得流过发光元件的驱动电流与发光元件的跨压无关，从而消除了发光元件的退化等因素造成的显示不均匀等现象。
附图说明
图1是已知的像素电路的结构示意图；
图2是本公开的实施例中像素电路的结构框图；
图3是本公开的实施例中像素电路的具体结构示意图；
图4是本公开的实施例中像素电路的各扫描端提供的信号示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
图1是一种已知的像素电路的结构示意图。如图1所示，该像素电路包括四个薄膜晶体管T1、T2、T3和Tr以及一个存储电容Cs。ELVDD为高电平输入端，VSS为低电平输入端，Data为数据线，Vn-1和Vn为扫描线。
图1中，通过发光元件的驱动电流为：
Ioled＝k(Vdata-Voled)2
其中，k为与驱动晶体管Tr结构相关的常数，Vdata为数据电压，Voled为发光元件发光时两端的电压。
图2示意性地示出了本公开的实施例中像素电路的结构框图。
如图2所示，作为本公开的一方面，提供一种像素电路，该像素电路包括：驱动晶体管Tr、存储电容Cs、数据写入模块10、发光元件20和预定电压写入模块30。
存储电容Cs的第一端与驱动晶体管Tr的栅极相连，存储电容Cs的 第二端与驱动晶体管Tr的第二极相连。驱动晶体管Tr的第一极与高电平输入端ELVDD相连，驱动晶体管Tr的第二极与发光元件20的阳极相连，所述发光元件的阴极与低电平输入端VSS相连。
预定电压写入模块30用于使得驱动晶体管Tr的第二极(即节点P)在预充电阶段和补偿阶段达到预定电位。
数据写入模块10用于在补偿阶段将数据线上的数据电压存储至存储电容Cs中。
在本公开的实施例中，存储电容Cs连接在驱动晶体管Tr的栅极和第二极之间，驱动晶体管Tr的第二极在预充电阶段和补偿阶段达到预定电位V0。数据写入模块10在补偿阶段可以将数据电压Vdata存储至存储电容Cs中。因此，在补偿阶段，存储电容Cs两端的电压为Vdata-V0。也就是说，在发光阶段前，驱动晶体管Tr的栅源电压Vgs为Vdata-V0。因此，在发光阶段，即使发光元件20两端的电压Voled使得驱动晶体管Tr的第二极电位升高，而由于存储电容Cs的自举作用，也会使得驱动晶体管Tr的栅源电压Vgs保持不变，通过发光元件的驱动电流为：
Ioled＝k(Vgs-Vthr)2＝k(Vdata-V0-Vthr)2；
其中，k为与驱动晶体管的结构有关的常数，Vthr为驱动晶体管Tr的阈值电压。
在图1中所示的像素电路中，存储电容的第二端连接低电平输入端VSS，发光元件20的阴极也连接低电平输入端，而由于各个像素单元中发光元件20两端的电压(跨压)可能不同，使得不同像素单元内驱动晶体管Tr的栅源电压Vgs也可能不同，从而会使得不同像素单元中流过发光元件的驱动电流不同，而导致发光不均匀。
在图2所示的本公开实施例中，存储电容Cs的一端与发光元件20的阳极相连，另一端与驱动晶体管Tr的栅极相连。由上述驱动电流的公式可以看出，流过发光元件20的驱动电流不会受到发光元件的跨压的影响，从而消除了不同发光元件20的跨压不一致对发光均匀性的影响。
进一步地，如图2所示，数据写入模块10的第一输入端与高电平输入端ELVDD相连，数据写入模块10的第二输入端与数据线Data相连，数据写入模块10的输出端与存储电容Cs的第一端相连。数据写入模块 10用于在预充电阶段将高电平输入端的电压存储至存储电容Cs中，以使得在补偿阶段存储电容Cs的第一端的电位高于存储电容Cs的第二端的电位，使得存储电容Cs放电，并在放电结束后将数据电压以及与驱动晶体管Tr的阈值电压等值的电压存储至存储电容Cs。
驱动晶体管Tr的第二极在预充电阶段和补偿阶段达到预定电位V0，驱动晶体管Tr的阈值电压为Vthr。在预充电阶段，存储电容Cs的第一端与地之间的电压与高电平输入端ELVDD的电压相等，存储电容的第二端与地之间的电压为V0。因此，在补偿阶段，存储电容放电结束后，存储电容Cs两端的电压为Vdata+Vthr-V0。在发光阶段，由于存储电容Cs的自举作用，也会使得驱动晶体管Tr的栅源电压Vgs保持不变，通过发光元件的驱动电流为：
Ioled＝k(Vgs-Vthr)2＝k(Vdata-V0)2。
可以看出，驱动电流Ioled与驱动晶体管Tr的阈值电压无关，从而消除了由驱动晶体管的阈值电压漂移造成的发光元件亮度不均匀的现象。另外，驱动电流与高电平输入端ELVDD的电压也无关，从而消除了电阻压降(IR drop)的问题。
本公开实施例中的发光元件20为有机电致发光二极管。可以理解的是，由于发光阶段前的预充电阶段和补偿阶段在一帧周期内所占的时间较短，因此，驱动晶体管第二极的电压对发光元件的驱动电流影响较小。为了防止发光元件20在发光阶段前发光，所述预定电位V0可以不大于发光元件20阴极电位。
与驱动晶体管Tr的阈值电压等值的电压表示，获取阈值电压的方式不做限定，可以直接获取驱动晶体管Tr的阈值电压，也可以获取阈值电压与驱动晶体管相等的晶体管的阈值电压，从而间接获取到驱动晶体管Tr的阈值电压。
图3示例性地示出了本公开实施例中的一种像素电路的结构示意图。如图3所示，数据写入模块10包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一扫描端S1和第二扫描端S2。第一晶体管T1的栅极与第一扫描端S1相连，第一晶体管T1的第一极与高电平输入端ELVDD相连(即第一晶体管T1的第一极与上述数据写入模块10的第一输入端为 同一端)，第一晶体管T1的第二极与驱动晶体管Tr的栅极相连。
第二晶体管T2的栅极与第二扫描端S2相连，第二晶体管T2的第一极与数据线Data相连(即第二晶体管T2的第一极与上述数据写入模块10的第二输入端为同一端)。第二晶体管T2的第二极与第三晶体管T3的第二极相连。第三晶体管T3的第一极和栅极均与驱动晶体管Tr的栅极相连。第三晶体管T3的阈值电压与驱动晶体管Tr的阈值电压相同。
第一扫描端S1用于在预充电阶段提供开启信号；第二扫描端S2用于在补偿阶段提供开启信号。
在预充电阶段，第一扫描端S1控制第一晶体管T1开启，高电平信号端ELVDD通过第一晶体管T1向存储电容Cs的充电，直至存储电容Cs的第一端的电位达到Vdd。在补偿阶段，第二扫描端S2控制第二晶体管T2开启，第三晶体管T3形成二极管连接，存储电容Cs放电，直至存储电容Cs第一端的电位达到Vdata+Vth3。
第三晶体管T3为驱动晶体管Tr的镜像晶体管，与驱动晶体管Tr具有相同的电学特性。通过获取第三晶体管T3的阈值电压即可间接获取驱动晶体管Tr的阈值电压，且第三晶体管T3和驱动晶体管Tr形成镜像电流源，从而可以为发光元件提供稳定的驱动电流，提高了电路的稳定性。
进一步地，如图3所示，预定电压写入模块30包括第四晶体管T4、第四扫描端S4和预定电压输入端。第四晶体管T4的栅极与第四扫描端S4相连，第四晶体管T4的第一极与驱动晶体管Tr的第二极相连，第四晶体管T4的第二极与预定电压输入端相连。第四扫描端S4用于在预充电阶段和补偿阶段提供开启信号、在发光阶段提供关断信号，从而使得第四晶体管T4在预充电阶段和补偿阶段开启，节点P达到预定电位。
当预定电压写入模块30包括第四晶体管T4时，为了防止出现第四晶体管T4和驱动晶体管Tr串联分压而导致节点P电位升高的情况，可选择地，预定电压写入模块30还可以包括第五晶体管T5和第五扫描端S5。第五晶体管T5的栅极与第五扫描端S5相连，第五晶体管T5的第一极与高电平输入端ELVDD相连，第五晶体管T5的第二极与驱动晶体管Tr的第一极相连。第五扫描端T5用于在预充电阶段和补偿阶段提供关断信号、在发光阶段提供开启信号。因此，在预充电阶段和补偿阶段，第五 晶体管T5关断，P点电位达到预定电位，而不受高电平输入端ELVDD的电压的影响。
可替换地，所述预定电压输入端的输入电压可以为零，即预定电压输入端与地相连。所述低电平输入端VSS可以作为所述预定电压输入端，减少信号端的设置，从而简化了电路结构。
在补偿阶段，存储电容Cs放电完成后，存储电容Cs两端的电压为Vdata+Vth3。在发光阶段，由于存储电容的自举作用，使得存储电容Cs两端的电压保持与补偿阶段相同，仍为Vdata+Vth3。流过发光元件20的驱动电流为：
Ioled＝(W/2L)μnCox(Vgs-Vthr)2
＝(W/2L)μnCox(Vdata+Vth3-Vthr)2
其中，Ioled为流过发光元件20的驱动电流；
Vth3为第三晶体管T3的阈值电压；
Vthr为驱动晶体管Tr的阈值电压；
μn为载流子迁移率；
Cox为驱动晶体管栅氧化层的单位电容；
W/L为驱动晶体管导电沟道的宽长比。
如上文中所述，第三晶体管T3的阈值电压与驱动晶体管Tr的阈值电压相同，即Vth3＝Vthr，所以，流过发光元件20的驱动电流为：
Ioled＝(W/2L)μnCox(Vdata)2。
在包括所述像素电路的显示装置中，可以设置有第一栅线、第二栅线、第四栅线、第五栅线以及栅极驱动电路，所述第一扫描端可以和第一栅线相连，所述第二扫描端可以和第二栅线相连，所述第四扫描端可以和第四栅线相连，所述第五扫描端可以和第五栅线相连，以使得栅极驱动电路为第一扫描端、第二扫描端、第四扫描端和第五扫描端提供驱动信号。
本公开实施例中的各个晶体管均为N型晶体管，第一极为N型晶体管的漏极，第二极为N型晶体管的源极。相应地，所述开启信号为高电平信号，关断信号为低电平信号。当然，也可以将各个晶体管均设置为P型晶体管，这时，第一极为P型晶体管的源极，第二极为P型晶体管的 漏极，相应地，提供给P型晶体管的开启信号为低电平信号，关断信号为高电平信号。
图4示出了本公开的实施例中像素电路的各扫描端提供的信号示意图。
作为本公开的另一方面，提供一种上述像素电路的驱动方法，包括下列步骤：
在预充电阶段，通过预定电压写入模块20向驱动晶体管Tr的第二极写入电压，以使得所述驱动晶体管的第二极的电位为所述预定电位，并通过数据写入模块10将所述高电平输入端的电压存储至存储电容Cs；
在补偿阶段，通过数据写入模块30将数据线上的数据电压存储至存储电容Cs中；
在发光阶段，将高电平输入端与发光元件20的阳极导通，以使得发光元件20发光。
示例性地，在预充电阶段，存储电容的第二端与地之间的电压为V0。在补偿阶段，存储电容Cs两端的电压为Vdata+Vthr-V0。也就是说，在发光阶段前，驱动晶体管Tr的栅源电压Vgs为Vdata-V0。因此，在发光阶段，即使发光元件20两端的电压Voled使得驱动晶体管Tr的第二极电位升高，而由于存储电容Cs的自举作用，也会使得驱动晶体管Tr的栅源电压Vgs保持不变，通过发光元件的驱动电流为：
Ioled＝k(Vgs-Vthr)2＝k(Vdata-V0-Vthr)2；
其中，k为与驱动晶体管的结构有关的常数，Vthr为驱动晶体管Tr的阈值电压。
可以看出，流过发光元件的驱动电流与发光元件20的跨压无关，从而消除了发光元件的退化等因素造成的显示不均匀等现象。
如上文所述，数据写入模块10的第一输入端与高电平输入端ELVDD相连，数据写入模块10的第二输入端与数据线Data相连，数据写入模块10的输出端与存储电容Cs的第一端相连。在这种情况下，所述驱动方法包括：
在所述预充电阶段，通过数据写入模块10将高电平输入端的电压存储至存储电容中；在所述补偿阶段，通过数据写入模块10将数据线与存 储电容Cs的第一端导通，以使得存储电容Cs放电，并在放电结束后将数据上的数据电压以及与驱动晶体管的阈值电压等值的电压存储至存储电容Cs。
在预充电阶段，存储电容Cs的第一端与地之间的电压与高电平输入端ELVDD的电压相等，存储电容的第二端与地之间的电压为V0。因此，补偿阶段，存储电容放电结束后，存储电容Cs两端的电压为Vdata+Vthr-V0，在发光阶段，由于存储电容Cs的自举作用，也会使得驱动晶体管Tr的栅源电压Vgs保持不变，通过发光元件的驱动电流为：
Ioled＝k(Vgs-Vthr)2＝k(Vdata-V0)2。
可以看出，驱动电流Ioled与驱动晶体管Tr的阈值电压无关，从而消除了由驱动晶体管的阈值电压漂移造成的发光元件亮度不均匀的现象。另外，驱动电流与高电平输入端ELVDD的电压也无关，从而消除了电阻压降(IR drop)的问题。
示例性地，如上文中所述，数据写入模块10包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一扫描端S1和第二扫描端S2，第一晶体管T1的栅极与第一扫描端S1相连，第一晶体管T1的第一极与所述高电平输入端相连，第一晶体管T1的第二极与驱动晶体管Tr的栅极相连；
第二晶体管T2的栅极与第二扫描端S2相连，第二晶体管T2的第一极与数据线相连，第二晶体管T2的第二极与第三晶体管T3的第二极相连，第三晶体管T3的第一极和栅极均与驱动晶体管Tr的栅极相连，第三晶体管T3的阈值电压与驱动晶体管Tr的阈值电压相同。在这种情况下，所述驱动方法包括：
在预充电阶段(如图4中所示的t1阶段)，向第一扫描端S1提供开启信号，向第二扫描端S2提供关断信号，以使得第一晶体管T1开启、第二晶体管T2关断，高电平输入端的电压通过第一晶体管存储至存储电容Cs；
在补偿阶段(如图4中所示的t2阶段)，分别向第二扫描端S2提供开启信号，向第一扫描端S1提供关断信号，以使得第二晶体管T2和第三晶体管T3开启，同时第一晶体管T1关断，并使得存储电容放电后将数据电压Vdata以及第三晶体管T3的阈值电压存储至存储电容Cs。存储电 容Cs的第一端的电位在预充电阶段结束后达到Vdd，会将第三晶体管T3开启，因此，存储电容Cs通过第三晶体管放电，当存储电容Cs的第一端的电位降低至Vdata+Vth3时，第三晶体管T3关闭，存储电容Cs停止放电；
在发光阶段(如图4中所示的t3阶段)，分别向第一扫描端S1和第二扫描端S2提供关断信号，以使得第一晶体管T1和第二晶体管T2关断。
预定电压写入模块30包括第四晶体管T4、第四扫描端S4和预定电压输入端，第四晶体管T4的栅极与第四扫描端S4相连，第四晶体管T4的第一极与驱动晶体管Tr的第二极相连，第四晶体管T4的第二极与所述预定电压输入端相连。在这种情况下，所述驱动方法包括：
在预充电阶段和补偿阶段，向第四扫描端S4提供开启信号，以使得第四晶体管T4开启，从而使得驱动晶体管Tr的第二极与预定电压输入端导通，进而使得驱动晶体管Tr的第二极的电位达到预定电位；
在发光阶段，向第四扫描端S4提供关断信号，以使得第四晶体管关断，并使得高电平输入端ELVDD与发光元件20的阳极导通。
预定电压写入模块还包括第五晶体管T5和第五扫描端S5，第五晶体管T5的栅极与第五扫描端S5相连，第五晶体管T5的第一极与高电平输入端ELVDD相连，第五晶体管T5的第二极与驱动晶体管Tr的第一极相连。在这种情况下，驱动方法还包括：
在预充电阶段和补偿阶段，向第五扫描端S5提供关断信号，在发光阶段向第五扫描端S5提供开启信号，以使得第五晶体管T5在预充电阶段关断，在发光阶段开启，使得高电平输入端ELVDD与发光元件20在预充电阶段和补偿阶段断开连接，并在发光阶段导通，从而防止发光元件20在预充电阶段和补偿阶段发光。
示例性地，所述预定电压输入端的输入电压为零，即，P点电位在预充电阶段和补偿阶段为零。
可选择地，所述低电平输入端VSS作为所述预定电压输入端，从而减少信号端的设置，简化电路结构。
作为本公开的再一个方面，提供一种显示装置，包括多个上述像素电路。所述显示装置还包括多条数据线，每一列的像素电路对应一条数据线，所述数据写入模块的第二输入端与相应的数据线相连，在补偿阶 段，数据线上的数据电压存储至存储电容内。
此外，所述显示装置还可以包括多个栅线组，每个栅线组包括第一栅线、第二栅线和栅极驱动电路，所述第一栅线连接在第一扫描端S1和栅极驱动电路之间，所述第二栅线连接在第二扫描端S2和栅极驱动电路之间，所述栅极驱动电路可以在预充电阶段向所述第一扫描端S1提供开启信号，在补偿阶段向第二扫描端S2提供开启信号。
预定电压写入模块30包括第四晶体管T4、第四扫描端S4和预定电压输入端，第四晶体管T4的栅极与第四扫描端S4相连，第四晶体管T4的第一极与驱动晶体管Tr的第二极相连，第四晶体管T4的第二极与所述预定电压输入端相连。
每个栅线组还包括第四栅线，所述第四栅线连接在第四扫描端S4和栅极驱动电路之间，所述栅极驱动电路可以在所述预充电阶段和所述补偿阶段向第四扫描端S4提供开启信号、并在发光阶段向第四扫描端S4提供关断信号，从而使得第四晶体管T4在所述预充电阶段和补偿阶段开启，使得节点P的电位达到预定电位，第四晶体管T4在发光阶段关断，以使得高电平输入端与发光元件的阳极导通。
预定电压写入模块还包括第五晶体管T5和第五扫描端S5，第五晶体管T5的栅极与第五扫描端S5相连，第五晶体管T5的第一极与高电平输入端ELVDD相连，第五晶体管T5的第二极与驱动晶体管Tr的第一极相连。
每个栅线组还包括第五栅线，所述第五栅线连接在第五扫描端S5和栅极驱动电路之间，栅极驱动电路可以在所述预充电阶段和所述补偿阶段向第五扫描端S5提供关断信号、在发光阶段向第五扫描端S5提供开启信号，从而使得第五晶体管T5在预充电阶段和补偿阶段关断，在发光阶段导通，防止发光元件在预充电阶段和补偿阶段发光。
所述显示装置还可以包括接地线，所述预定电压输入端与所述接地线相连，同时，所述低电平输入端也可以与所述接地线相连。
所述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于本公开实施例提供的像素电路的稳定性较好，驱动电流不受阈 值电压和发光元件的跨压影响，因而可以提高发光元件亮度的均匀性，从而改善所述显示装置的显示效果。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。
本申请要求于2015年6月19日递交的中国专利申请第201510346349.5号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (18)

  1. 一种像素电路，包括：驱动晶体管、存储电容、数据写入模块、发光元件和预定电压写入模块；
    所述存储电容的第一端与所述驱动晶体管的栅极相连，所述存储电容的第二端与所述驱动晶体管的第二极相连，所述驱动晶体管的第一极与高电平输入端相连，所述驱动晶体管的第二极与所述发光元件的阳极相连，所述发光元件的阴极与低电平输入端相连；
    所述预定电压写入模块用于使得所述驱动晶体管的第二极在预充电阶段和补偿阶段达到预定电位；
    所述数据写入模块用于在补偿阶段将数据线上的数据电压存储至所述存储电容中。
  2. 根据权利要求1所述的像素电路，其中，所述数据写入模块的第一输入端与所述高电平输入端相连，所述数据写入模块的第二输入端与数据线相连，所述数据写入模块的输出端与所述存储电容的第一端相连，所述数据写入模块用于在预充电阶段将高电平输入端的电压存储在所述存储电容中，以使得在所述补偿阶段所述存储电容的第一端电位高于所述存储电容的第二端的电位，并使得所述存储电容放电，并在放电过程结束后将数据电压以及与驱动晶体管的阈值电压等值的电压存储至所述存储电容。
  3. 根据权利要求2所述的像素电路，其中，所述数据写入模块包括：第一晶体管、第二晶体管、第三晶体管、第一扫描端和第二扫描端；
    所述第一晶体管的栅极与所述第一扫描端相连，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述驱动晶体管的栅极相连；
    所述第二晶体管的栅极与所述第二扫描端相连，所述第二晶体管的第一极与数据线相连，所述第二晶体管的第二极与所述第三晶体管的第二极相连，所述第三晶体管的第一极和栅极均与所述驱动晶体管的栅极相连，所述第三晶体管的阈值电压与所述驱动晶体管的阈值电压相同；
    所述第一扫描端用于在预充电阶段提供开启信号；所述第二扫描端 用于在补偿阶段提供开启信号。
  4. 根据权利要求3所述的像素电路，其中，所述第三晶体管为所述驱动晶体管的镜像晶体管，所述第三晶体管和所述驱动晶体管形成镜像电流源。
  5. 根据权利要求3或4所述的像素电路，其中，所述第一扫描端与第一栅线相连，所述第二扫描端与第二栅线相连。
  6. 根据权利要求1至5中任意一项所述的像素电路，其中，所述预定电压写入模块包括第四晶体管、第四扫描端和预定电压输入端，
    所述第四晶体管的栅极与所述第四扫描端相连，所述第四晶体管的第一极与所述驱动晶体管的第二极相连，所述第四晶体管的第二极与所述预定电压输入端相连，所述第四扫描端用于在预充电阶段和补偿阶段提供开启信号、在发光阶段提供关断信号。
  7. 根据权利要求6所述的像素电路，其中，所述预定电压写入模块还包括第五晶体管和第五扫描端，所述第五晶体管的栅极与所述第五扫描端相连，所述第五晶体管的第一极与所述高电平输入端相连，所述第五晶体管的第二极与所述驱动晶体管的第一极相连，所述第五扫描端用于在预充电阶段和补偿阶段提供关断信号、在发光阶段提供开启信号。
  8. 根据权利要求7所述的像素电路，其中，所述第四扫描端与第四栅线相连，所述第五扫描端与第五栅线相连。
  9. 根据权利要求6所述的像素电路，其中，所述预定电压输入端的输入电压为零。
  10. 根据权利要求6所述的像素电路，其中，所述低电平输入端作为所述预定电压输入端。
  11. 一种像素电路的驱动方法，所述像素电路为权利要求1所述的像素电路，所述驱动方法包括：
    预充电阶段，通过预定电压写入模块向所述驱动晶体管的第二极写入电压，以使得所述驱动晶体管的第二极的电位为所述预定电位；
    补偿阶段，通过数据写入模块将数据线上的数据电压存储至所述存储电容中；
    发光阶段，将高电平输入端与所述发光元件的阳极导通，以使得所 述发光元件发光。
  12. 根据权利要求11所述的驱动方法，其中，所述驱动方法包括：
    在所述预充电阶段，通过所述数据写入模块将高电平输入端的电压存储至所述存储电容中；
    在所述补偿阶段，通过所述数据写入模块将数据线与所述存储电容的第一端导通，以使得存储电容放电，并在放电结束后将数据线上的数据电压以及与驱动晶体管的阈值电压等值的电压存储至所述存储电容。
  13. 根据权利要求12所述的驱动方法，其中，所述数据写入模块包括第一晶体管、第二晶体管、第三晶体管、第一扫描端和第二扫描端，所述第一晶体管的栅极与所述第一扫描端相连，所述第一晶体管的第一极与所述高电平输入端相连，所述第一晶体管的第二极与所述驱动晶体管的栅极相连；
    所述第二晶体管的栅极与所述第二扫描端相连，所述第二晶体管的第一极与数据线相连，所述第二晶体管的第二极与所述第三晶体管的第二极相连，所述第三晶体管的第一极和栅极均与所述驱动晶体管的栅极相连，所述第三晶体管的阈值电压与所述驱动晶体管的阈值电压相同；
    所述驱动方法包括：
    在所述预充电阶段，分别向所述第一扫描端提供开启信号，向所述第二扫描端提供关断信号，以使得所述第一晶体管开启、所述第二晶体管关断，所述高电平输入端的电压通过所述第一晶体管存储至所述存储电容；
    在所述补偿阶段，分别向所述第二扫描端提供开启信号，向所述第一扫描端提供关断信号，以使得所述第二晶体管和所述第三晶体管开启，同时第一晶体管关断，并使得所述存储电容放电结束后将数据电压以及所述第三晶体管的阈值电压存储至所述存储电容；
    在所述发光阶段，分别向所述第一扫描端和所述第二扫描端提供关断信号，以使得所述第一晶体管和所述第二晶体管关断。
  14. 根据权利要求11至13中任意一项所述的驱动方法，其中，所述预定电压写入模块包括第四晶体管、第四扫描端和预定电压输入端，所述第四晶体管的栅极与所述第四扫描端相连，所述第四晶体管的第一 极与所述驱动晶体管的第二极相连，所述第四晶体管的第二极与所述预定电压输入端相连；所述驱动方法包括：
    在所述预充电阶段和所述补偿阶段，向所述第四扫描端提供开启信号，以使得所述第四晶体管开启，所述驱动晶体管的第二极与所述预定电压输入端导通；
    在所述发光阶段，向第四扫描端提供关断信号，以使得所述第四晶体管关断，并使得所述高电平输入端与所述发光元件的阳极导通。
  15. 根据权利要求14所述的驱动方法，其中，所述预定电压写入模块还包括第五晶体管和第五扫描端，所述第五晶体管的栅极与所述第五扫描端相连，所述第五晶体管的第一极与所述高电平输入端相连，所述第五晶体管的第二极与所述驱动晶体管的第一极相连，所述驱动方法还包括：
    在所述预充电阶段和所述补偿阶段，向所述第五扫描端提供关断信号，在所述发光阶段，向所述第五扫描端提供开启信号，以使得所述第五晶体管在所述预充电阶段和所述补偿阶段关断，并在所述发光阶段开启，使得所述高电平输入端与发光元件在所述预充电阶段和所述补偿阶段断开，并在所述发光阶段导通。
  16. 根据权利要求14所述的驱动方法，其中，所述预定电压输入端输入的电压为零。
  17. 根据权利要求14所述的驱动方法，其中，所述低电平输入端作为所述预定电压输入端。
  18. 一种显示装置，包括多个权利要求1至10中任意一项所述的像素电路。
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