WO2018186196A1 - Dispositif d'imagerie à semi-conducteurs et appareil électronique - Google Patents

Dispositif d'imagerie à semi-conducteurs et appareil électronique Download PDF

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Publication number
WO2018186196A1
WO2018186196A1 PCT/JP2018/011569 JP2018011569W WO2018186196A1 WO 2018186196 A1 WO2018186196 A1 WO 2018186196A1 JP 2018011569 W JP2018011569 W JP 2018011569W WO 2018186196 A1 WO2018186196 A1 WO 2018186196A1
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substrate
solid
state imaging
multilayer wiring
wiring layer
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PCT/JP2018/011569
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English (en)
Japanese (ja)
Inventor
日出登 橋口
庄子　礼二郎
堀越　浩
生枝 三橋
匡 飯島
隆季 亀嶋
石田　実
雅希 羽根田
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ソニーセミコンダクタソリューションズ株式会社
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Priority to US16/497,497 priority Critical patent/US11411037B2/en
Publication of WO2018186196A1 publication Critical patent/WO2018186196A1/fr
Priority to US17/869,659 priority patent/US11948961B2/en

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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
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    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Definitions

  • the present disclosure relates to a solid-state imaging device and an electronic device.
  • Patent Document 1 discloses a three-layer stacked solid in which a pixel chip, a logic chip, and a memory chip on which a memory circuit that holds a pixel signal acquired in a pixel portion of the pixel chip is mounted.
  • An imaging device is disclosed.
  • a semiconductor substrate on which a pixel chip, a logic chip, or a memory chip is formed and a multilayer wiring layer formed on the semiconductor substrate are combined.
  • This configuration is also referred to as “substrate”.
  • the “substrate” is referred to as “first substrate”, “second substrate”, “third substrate” in order from the upper side (side on which the observation light is incident) to the lower side in the laminated structure. ⁇ These are called and distinguished from each other.
  • the stacked solid-state imaging device is manufactured by dicing each substrate into a plurality of stacked solid-state imaging devices (that is, stacked solid-state imaging device chips) after the substrates are stacked in a wafer state.
  • stacked solid-state imaging devices that is, stacked solid-state imaging device chips
  • the “substrate” may mean the state of the wafer before dicing, and may also mean the state of the chip after dicing.
  • the present disclosure proposes a new and improved solid-state imaging device and electronic apparatus that can further improve performance.
  • a first substrate having a first semiconductor substrate on which a pixel portion in which pixels are arranged is formed, and a first multilayer wiring layer stacked on the first semiconductor substrate, and a predetermined function
  • the first connection structure for electrically connecting the circuit of the first substrate and the circuit of the second substrate is bonded so that one multilayer wiring layer and the second semiconductor substrate are opposed to each other. Affixing the first substrate and the second substrate formed from one substrate It does not include a connecting structure through the Align surface, or, the first connection structure does not exist, the solid-state imaging device is provided.
  • a solid-state imaging device that electronically captures an observation target
  • the solid-state imaging device including a first semiconductor substrate on which a pixel unit in which pixels are arranged is formed, and the first semiconductor A first substrate having a first multilayer wiring layer stacked on the substrate; a second semiconductor substrate having a circuit having a predetermined function; and a second multilayer wiring stacked on the second semiconductor substrate.
  • a third substrate having a layer, a third semiconductor substrate on which a circuit having a predetermined function is formed, and a third multilayer wiring layer stacked on the third semiconductor substrate, Are stacked in this order, and the first substrate and the second substrate are bonded so that the first multilayer wiring layer and the second semiconductor substrate face each other, and the circuit of the first substrate and the second substrate
  • a first connection structure for electrically connecting the circuit of the second substrate. Does not include a connection structure via a bonding surface between the first substrate and the second substrate formed from the first substrate, or the first connection structure does not exist Is provided.
  • the performance of the solid-state imaging device can be further improved.
  • the above effects are not necessarily limited, and any of the effects shown in the present specification, or other effects that can be grasped from the present specification, together with or in place of the above effects. May be played.
  • FIG. 3A It is a figure for demonstrating the further another example of arrangement
  • FIG. 3A It is a figure for demonstrating the parasitic capacitance between PWELL and power supply wiring in the solid-state imaging device shown to FIG. 3A.
  • FIG. 4 is a diagram for describing a parasitic capacitance between PWELL and a power supply wiring in the solid-state imaging device shown in FIG. 3B. It is a figure which shows roughly arrangement
  • FIG. 3B is a diagram schematically showing the arrangement of power supply wiring and GND wiring in the solid-state imaging device shown in FIG. 3B. It is a figure which shows one structural example for reducing the impedance in the solid-state imaging device shown to FIG. 5A. It is a longitudinal cross-sectional view which shows an example of the solid-state imaging device which concerns on a 1st structural example.
  • FIG. 15 is a diagram illustrating an appearance of a smartphone, which is an example of an electronic device to which the solid-state imaging devices 1 to 15E according to the present embodiment can be applied.
  • FIG. 16 is a diagram illustrating an appearance of a digital camera, which is another example of an electronic apparatus to which the solid-state imaging devices 1 to 15E according to the present embodiment can be applied.
  • FIG. 16 is a diagram illustrating an appearance of a digital camera, which is another example of an electronic apparatus to which the solid-state imaging devices 1 to 15E according to the present embodiment can be applied. It is sectional drawing which shows the structural example of the solid-state imaging device which can apply the technique which concerns on this indication. It is explanatory drawing which shows schematic structure of the solid-state imaging device with which the technique which concerns on this indication can be applied.
  • FIG. 16 is an explanatory diagram illustrating a configuration example of a video camera to which the technology according to the present disclosure can be applied. It is a figure which shows an example of a schematic structure of an endoscopic surgery system. It is a block diagram which shows an example of a function structure of a camera head and CCU. It is a block diagram which shows an example of a schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of a vehicle exterior information detection part and an imaging part.
  • connection structure 4-1 First configuration example 4-2. Second configuration example 4-3. Third configuration example 4-4. Fourth configuration example 4-5. Fifth configuration example 4-6. Sixth configuration example 4-7. Seventh configuration example 4-8. Eighth configuration example 4-9. Ninth Configuration Example 4-10. 10. Tenth configuration example Application example 6. Supplement
  • FIG. 1 is a longitudinal sectional view illustrating a schematic configuration of a solid-state imaging device according to an embodiment of the present disclosure.
  • the solid-state imaging device 1 according to the present embodiment includes a three-layer stacked solid that is configured by stacking a first substrate 110A, a second substrate 110B, and a third substrate 110C.
  • a broken line AA indicates a bonding surface between the first substrate 110A and the second substrate 110B
  • a broken line BB indicates a bonding surface between the second substrate 110B and the third substrate 110C.
  • the first substrate 110A is a pixel substrate provided with a pixel portion.
  • the second substrate 110B and the third substrate 110C are provided with circuits for performing various signal processes related to the operation of the solid-state imaging device 1.
  • the second substrate 110B and the third substrate 110C are, for example, a logic substrate on which a logic circuit is provided or a memory substrate on which a memory circuit is provided.
  • the solid-state imaging device 1 is a backside illumination type CMOS (Complementary Metal-Oxide-Semiconductor) image sensor that photoelectrically converts light incident from the backside, which will be described later, of the first substrate 110A in a pixel portion.
  • CMOS Complementary Metal-Oxide-Semiconductor
  • each circuit can be more appropriately configured so as to correspond to the function of each substrate. Therefore, it is possible to easily achieve higher functionality of the solid-state imaging device 1. it can.
  • the pixel portion in the first substrate 110A and the logic circuit or the memory circuit in the second substrate 110B and the third substrate 110C may be appropriately configured so as to correspond to the function of each substrate. Therefore, a highly functional solid-state imaging device 1 can be realized.
  • the stacking direction of the first substrate 110A, the second substrate 110B, and the third substrate 110C is also referred to as a z-axis direction.
  • the direction in which the first substrate 110A is located in the z-axis direction is defined as the positive direction of the z-axis.
  • Two directions orthogonal to each other on a plane (horizontal plane) perpendicular to the z-axis direction are also referred to as an x-axis direction and a y-axis direction, respectively.
  • a surface on which a functional component such as a transistor is provided, or a functional component of the two surfaces provided on the semiconductor substrate 101, 121, 131, which will be described later, facing the main surface of the substrate.
  • One side surface on which multilayer wiring layers 105, 125, and 135 to be described later are operated is also referred to as a front surface (also referred to as a front side surface), and the other surface facing the surface is referred to as a back surface (back side surface). Call it.
  • the first substrate 110A mainly includes a semiconductor substrate 101 made of, for example, silicon (Si) and a multilayer wiring layer 105 formed on the semiconductor substrate 101.
  • a pixel portion in which pixels are arranged in a predetermined arrangement and a pixel signal processing circuit that processes pixel signals are mainly formed on the semiconductor substrate 101.
  • Each pixel includes a photodiode (PD) that receives and photoelectrically converts light (observation light) from an observation target, a transistor for reading an electrical signal (pixel signal) corresponding to the observation light acquired by the PD, and the like. And a drive circuit having the same.
  • various signal processing such as analog-digital conversion (AD conversion) is performed on the pixel signal.
  • AD conversion analog-digital conversion
  • the first substrate 110A may be a substrate formed using a material other than a semiconductor instead of the semiconductor substrate 101.
  • the first substrate 110A has a form in which pixels are formed by forming a film (for example, a general organic photoelectric conversion film) that performs photoelectric conversion on a sapphire substrate that is a substrate made of a material other than a semiconductor. May be.
  • An insulating film 103 is laminated on the surface side of the semiconductor substrate 101 on which the pixel portion and the pixel signal processing circuit are formed.
  • a multilayer wiring layer 105 for transmitting various signals such as a pixel signal and a driving signal for driving a transistor of a driving circuit is formed.
  • the multilayer wiring layer 105 further includes power supply wiring, ground wiring (GND wiring), and the like.
  • the lowermost wiring of the multilayer wiring layer 105 can be electrically connected to the pixel portion or the pixel signal processing circuit by a contact 107 in which a conductive material such as tungsten (W) is embedded.
  • a plurality of wiring layers can be formed by repeating the formation of an interlayer insulating film having a predetermined thickness and the formation and patterning of a metal film.
  • the plurality of interlayer insulating films are collectively referred to as an insulating film 103, and the plurality of wiring layers are collectively referred to as a multilayer wiring layer 105.
  • a pad 151 functioning as an external input / output unit (I / O unit) for exchanging various signals with the outside can be formed.
  • the pad 151 can be provided along the outer periphery of the chip.
  • the second substrate 110B is, for example, a logic substrate.
  • the second substrate 110 ⁇ / b> B mainly includes a semiconductor substrate 121 made of, for example, Si and a multilayer wiring layer 125 formed on the semiconductor substrate 121.
  • a logic circuit is formed on the semiconductor substrate 121.
  • various signal processing related to the operation of the solid-state imaging device 1 is executed. For example, in the logic circuit, control of a drive signal for driving the pixel portion of the first substrate 110A (that is, drive control of the pixel portion) and exchange of signals with the outside can be controlled.
  • the second substrate 110 ⁇ / b> B may be a substrate formed using a material other than a semiconductor instead of the semiconductor substrate 121.
  • the second substrate 110B has a form in which a circuit is formed by forming a semiconductor film (for example, a silicon film) on which a circuit element can be formed on a sapphire substrate that is a substrate made of a material other than a semiconductor. Also good.
  • a semiconductor film for example, a silicon film
  • An insulating film 123 is laminated on the surface side of the semiconductor substrate 121 on which the logic circuit is formed.
  • a multilayer wiring layer 125 for transmitting various signals related to the operation of the logic circuit is formed inside the insulating film 123.
  • the multilayer wiring layer 125 further includes power supply wiring, GND wiring, and the like.
  • the lowermost wiring of the multilayer wiring layer 125 can be electrically connected to the logic circuit by a contact 127 in which a conductive material such as W is embedded.
  • the insulating film 123 is a general term for a plurality of interlayer insulating films in the second substrate 110B
  • the multilayer wiring layer 125 is a wiring of a plurality of layers. It can be a generic term for layers.
  • an insulating film 129 having a predetermined thickness is formed on the back side of the semiconductor substrate 121.
  • the multilayer wiring layer 125 may be formed with pads 151 that function as external input / output units (I / O units) for exchanging various signals with the outside.
  • the pad 151 can be provided along the outer periphery of the chip.
  • the third substrate 110C is, for example, a memory substrate.
  • the third substrate 110 ⁇ / b> C mainly includes a semiconductor substrate 131 made of, for example, Si and a multilayer wiring layer 135 formed on the semiconductor substrate 131.
  • a memory circuit is formed on the semiconductor substrate 131.
  • the pixel signal acquired by the pixel portion of the first substrate 110A and subjected to AD conversion by the pixel signal processing circuit is temporarily held.
  • a global shutter system is realized, and the pixel signal can be read from the solid-state imaging device 1 to the outside at a higher speed. Therefore, even during high-speed shooting, it is possible to take a higher quality image with suppressed distortion.
  • the third substrate 110C may be a substrate formed using a material other than a semiconductor instead of the semiconductor substrate 131.
  • the third substrate 110C has a form in which a circuit is formed by forming a film (for example, a phase change material film) on which a memory element can be formed on a sapphire substrate that is a substrate made of a material other than a semiconductor. May be.
  • An insulating film 133 is stacked on the surface side of the semiconductor substrate 131 on which the memory circuit is formed.
  • a multilayer wiring layer 135 for transmitting various signals related to the operation of the memory circuit is formed inside the insulating film 133.
  • the multilayer wiring layer 135 further includes power supply wiring, GND wiring, and the like.
  • the lowermost wiring of the multilayer wiring layer 135 can be electrically connected to the memory circuit by a contact 137 in which a conductive material such as W is embedded.
  • the insulating film 133 is also a generic term for a plurality of interlayer insulating films in the third substrate 110C, and the multilayer wiring layer 135 is a wiring of a plurality of layers. It can be a generic term for layers.
  • a pad 151 that functions as an I / O unit for exchanging various signals with the outside can be formed.
  • the pad 151 can be provided along the outer periphery of the chip.
  • the first substrate 110A, the second substrate 110B, and the third substrate 110C are each fabricated in a wafer state. Then, these are bonded together, and each process for electrically connecting the signal lines and the power lines provided on the first substrate 110A, the second substrate 110B, and the third substrate 110C, respectively, is performed.
  • the surface of the second substrate 110B in the wafer state (the surface on the side where the multilayer wiring layer 125 is provided) and the surface of the third substrate 110C in the wafer state (the surface on the side where the multilayer wiring layer 135 is provided).
  • the second substrate 110B and the third substrate 110C are bonded together so that they face each other.
  • an insulating film having a predetermined thickness is formed on the back surface of the bonded second substrate 110B. 129 is formed.
  • Face to Face Face
  • the back surface of the second substrate 110B (the surface facing the surface on which the multilayer wiring layer 125 is provided) and the surface of the first substrate 110A (the surface on the side on which the multilayer wiring layer 105 is provided) face each other.
  • the stacked body of the second substrate 110B and the third substrate 110C and the first substrate 110A in a wafer state are further bonded together.
  • such a state in which the two substrates are bonded with the front surface and the back surface facing each other is also referred to as Face to Back (FtoB).
  • a color structure is provided on the back surface side of the semiconductor substrate 101 of the first substrate 110A via the insulating film 109.
  • a filter layer 111 (CF layer 111) and a microlens array 113 (ML array 113) are formed.
  • the CF layer 111 is configured by arranging a plurality of CFs so as to correspond to pixels.
  • the ML array 113 is configured by arranging a plurality of MLs so as to correspond to pixels.
  • the CF layer 111 and the ML array 113 are formed immediately above the pixel portion, and one CF and one ML are disposed for one pixel PD.
  • Each CF of the CF layer 111 has, for example, one of red, green, and blue.
  • the observation light that has passed through the CF is incident on the PD of the pixel and the pixel signal is acquired, whereby the pixel signal of the color component of the color filter is acquired for the observation target (that is, in color) Imaging is possible).
  • one pixel corresponding to one CF functions as a subpixel, and one pixel can be formed by a plurality of subpixels.
  • a pixel provided with a red CF ie, a red pixel
  • a pixel provided with a green CF ie, a green pixel
  • a blue CF ie, a blue pixel
  • One pixel can be formed by sub-pixels of four colors, that is, a pixel) and a pixel not provided with CF (that is, a white pixel).
  • a subpixel and a pixel are not distinguished from each other, and a configuration corresponding to one subpixel is also simply referred to as a pixel.
  • the CF arrangement method is not particularly limited, and may be various arrangements such as a delta arrangement, a stripe arrangement, a diagonal arrangement, or a rectangle arrangement, for example.
  • the ML array 113 is formed so that each ML is located immediately above each CF.
  • the observation light collected by the ML is incident on the PD of the pixel via the CF, so that the collection efficiency of the observation light is improved and the sensitivity as the solid-state imaging device 1 is improved. The effect which improves can be acquired.
  • Pad openings 153a, 153b, 153c are formed.
  • the pad opening 153a is formed from the back side of the first substrate 110A so as to penetrate the semiconductor substrate 101 and reach the connection surface of the pad 151 provided in the multilayer wiring layer 105 of the first substrate 110A.
  • the pad opening 153b is formed so as to penetrate from the back surface side of the first substrate 110A to the connection surface of the pad 151 provided in the multilayer wiring layer 125 of the second substrate 110B.
  • the pad opening 153c is formed so as to penetrate from the back surface side of the first substrate 110A to the connection surface of the pad 151 provided in the multilayer wiring layer 135 of the third substrate 110C through the first substrate 110A and the second substrate 110B. Is done.
  • the pad 151 and an external circuit are electrically connected through the pad openings 153a, 153b, and 153c, for example, by wire bonding. That is, various wirings in the first substrate 110A, various wirings in the second substrate 110B, and various wirings in the third substrate 110C can be electrically connected via the external circuit.
  • Various wirings can be electrically connected.
  • the first substrate 110 ⁇ / b> A, the second substrate 110 ⁇ / b> B, and the second substrate 110 ⁇ / b> B are connected by connecting the pads 151 via electrical connection means such as wirings and substrates provided outside the solid-state imaging device 1.
  • Signal wirings for transmitting signals provided on each of the third substrates 110C can be electrically connected to each other across the plurality of substrates.
  • a plurality of power supply wirings (and GND wirings that are grounded to the ground (GND)) provided for each of the first substrate 110A, the second substrate 110B, and the third substrate 110C are provided. Can be electrically connected to each other across the substrate.
  • various wiring such as signal wiring, power supply wiring, and GND wiring may be simply referred to as “wiring”.
  • a structure that electrically connects various wirings provided on the substrates such as the pad 151 and the pad openings 153a, 153b, and 153c shown in FIG. 1 is also collectively referred to as a connection structure.
  • the semiconductor substrates 101, 121, and 131 are formed from one surface of any one of the TSVs (first substrate 110 ⁇ / b> A, second substrate 110 ⁇ / b> B, and third substrate 110 ⁇ / b> C) to be described later.
  • connection structure Vias provided through at least one of the semiconductor substrates) and an electrode bonding structure (bonding surface of the first substrate 110A and the second substrate 110B, or bonding of the second substrate 110B and the third substrate 110C).
  • the connection structure also includes a structure in which the electrodes formed on the surfaces are joined together in direct contact with each other.
  • the semiconductor substrates 101, 121, and 131 can be made of a material other than a semiconductor such as silicon, the TSV referred to in this specification penetrates the substrate. It is assumed that the material of the substrate is not particularly limited.
  • the TSV is provided from one side of any of the first substrate 110A, the second substrate 110B, and the third substrate 110C through at least one of the semiconductor substrates 101, 121, and 131.
  • each wiring is electrically connected by contacting each wiring (for example, a signal line and a power supply line) provided on the substrate.
  • the TSV has, for example, a twin contact structure formed by exposing wirings in different multilayer wiring layers through two through holes and embedding a conductive material in the two through holes, and a plurality of multilayer wiring layers It is divided into a shared contact structure formed by exposing the side surface and the upper surface of the wiring through one through hole and embedding a conductive material in the one through hole.
  • the electrode bonding structure is, for example, a heat treatment in a state where an electrode formed on the uppermost layer of the multilayer wiring layer of one substrate and an electrode formed on the uppermost layer of the multilayer wiring layer of the other substrate are in direct contact with each other.
  • the electrodes are joined to each other.
  • the electrode bonding structure electrically connects each of the signal line and the power supply line provided on the substrates having the electrode bonding structure formed on the bonding surface.
  • the connection structure for electrically connecting the signal lines and power lines of the first substrate 110A and the signal lines and power lines of the second substrate 110B is the first substrate. It does not include a connection structure (for example, a TSV and an electrode bonding structure described later) via a bonding surface between 110A and the second substrate 110B. That is, in the solid-state imaging device 1, the signal line and the power line of the first substrate 110A and the signal line and the power line of the second substrate 110B are connected by the pad 151, the pad openings 153a, 153b, 153c, wire bonding, and the like. It can be electrically connected through other external circuits.
  • a connection structure for example, a TSV and an electrode bonding structure described later
  • connection structure for electrically connecting the signal line and the power line of the first substrate 110A and the signal line and the power line of the second substrate 110B.
  • the connection structure that electrically connects the signal line and the power supply line of the second substrate 110B and the signal line and the power supply line of the third substrate 110C, and the signal line of the first substrate 110A
  • a connection structure for electrically connecting the power supply line to the signal line and the power supply line of the third substrate 110C, the signal lines and the power supply of the first substrate 110A, the second substrate 110B, and the third substrate 110C are provided.
  • the wires can be electrically connected.
  • the multilayer wiring layer 105 of the first substrate 110A, the multilayer wiring layer 125 of the second substrate 110B, and the multilayer wiring layer 135 of the third substrate 110C are formed of a plurality of first metals having a relatively low resistance.
  • a first metal wiring layer 141 is included.
  • the first metal is, for example, copper (Cu). By using Cu wiring, signals can be exchanged at a higher speed.
  • the pad 151 can be formed of a second metal different from the first metal in consideration of the adhesiveness to the wire of wire bonding and the like.
  • the multilayer wiring layer 105 of the first substrate 110A, the multilayer wiring layer 125 of the second substrate 110B, and the multilayer wiring layer 135 of the third substrate 110C are formed of the second metal in the same layer as the pad 151.
  • a second metal wiring layer 143 may be included.
  • the second metal is, for example, aluminum (Al).
  • the Al wiring can be used as, for example, a power supply wiring or a GND wiring that is generally formed as a wide wiring.
  • the contacts 107, 127, and 137 can be formed of a third metal different from the first metal and the second metal in consideration of filling properties at the time of film formation.
  • the third metal is, for example, tungsten (W).
  • the W via can be formed as a via having a smaller opening since it has a high filling property during film formation. By using the W via, for example, it is possible to easily form a fine pitch via provided at a finer size and interval.
  • first metal, the second metal, and the third metal are not limited to Cu, Al, and W exemplified above.
  • Various metals may be used as the first metal, the second metal, and the third metal.
  • each wiring layer included in the multilayer wiring layers 105, 125, and 135 may be formed of a conductive material other than metal. These wiring layers may be formed of a conductive material, and the material is not limited. Instead of using two kinds of conductive materials, all the wiring layers including the pads 151 of the multilayer wiring layers 115, 125, and 135 may be formed of the same conductive material.
  • the TSV which will be described later, and the electrodes and vias constituting the electrode bonding structure can be formed of a first metal (for example, Cu).
  • a first metal for example, Cu
  • these structures can be formed by a single damascene method or a dual damascene method.
  • this embodiment is not limited to such an example, and some or all of these structures may be other metals different from both the first metal and the second metal, or other non-metallic conductive materials. May be formed.
  • conductive materials such as the first metal and the second metal are the semiconductor substrates 101, 121, 131.
  • the insulating material may be various known materials such as SiO 2 or SiN.
  • the insulating material may exist so as to be interposed between the conductive material and the semiconductor substrates 101, 121, 131, or exist inside the semiconductor substrates 101, 121, 131 away from the contact portions between the two. Also good.
  • an insulating material may exist between the inner wall of the through hole provided in the semiconductor substrate 101, 121, 131 and the conductive material embedded in the through hole (that is, the through hole).
  • An insulating material can be deposited on the inner wall of the substrate.
  • it is a part inside semiconductor substrates 101, 121, and 131, and a part away from a penetration hole provided in the semiconductor substrates 101, 121, and 131 by a predetermined distance in a horizontal plane direction, An insulating material may be present.
  • the processed laminated structure is diced for each solid-state imaging device 1 to complete the solid-state imaging device 1.
  • each component formed on the semiconductor substrates 101, 121, and 131 of each substrate (a pixel portion and a pixel signal processing circuit provided on the first substrate 110A, a logic circuit provided on the second substrate 110B, and a third substrate 110C)
  • the specific configuration and formation method of the provided memory circuit), the multilayer wiring layers 105, 125, and 135 and the insulating films 103, 109, 123, 129, and 133 may be the same as various known ones. Detailed description is omitted here.
  • the insulating films 103, 109, 123, 129, and 133 may be formed using an insulating material, and the material is not limited.
  • the insulating films 103, 109, 123, 129, and 133 can be formed of, for example, silicon oxide (SiO 2 ), silicon nitride (SiN), or the like.
  • each of the insulating films 103, 109, 123, 129, and 133 may not be formed of one type of insulating material, and may be formed by stacking a plurality of types of insulating materials.
  • a low-k material having insulating properties and a low relative dielectric constant may be used.
  • the parasitic capacitance between the wirings can be reduced, which can further contribute to speeding up signal transmission.
  • the pixel signal processing circuit that performs signal processing such as AD conversion on the pixel signal is mounted on the first substrate 110A.
  • the present embodiment is not limited to this example. Some or all of the functions of the pixel signal processing circuit may be provided on the second substrate 110B.
  • the pixel signal acquired by the PD provided in each pixel is the pixel A so-called pixel-by-pixel analog-digital conversion (pixel ADC) type solid-state imaging device in which each pixel is transmitted to the pixel signal processing circuit of the second substrate 110B and subjected to AD conversion for each pixel can be realized.
  • pixel ADC pixel-by-pixel analog-digital conversion
  • the signal line and the power line of the first substrate 110A and the signal line and the power line of the second substrate 110B are electrically connected for each pixel.
  • An electrode bonding structure is provided.
  • the second substrate 110B is a logic substrate and the third substrate 110C is a memory substrate has been described, but the present embodiment is not limited to this example.
  • the second substrate 110B and the third substrate 110C may be substrates having functions other than the pixel substrate, and the functions may be arbitrarily determined.
  • the solid-state imaging device 1 may not have a memory circuit.
  • both the second substrate 110B and the third substrate 110C can function as a logic substrate.
  • the logic circuit and the memory circuit may be formed in a distributed manner on the second substrate 110B and the third substrate 110C, and these substrates may cooperate to serve as a logic substrate and a memory substrate.
  • the second substrate 110B may be a memory substrate
  • the third substrate 110C may be a logic substrate.
  • Si substrates are used as the semiconductor substrates 101, 121, and 131 in each substrate, but the present embodiment is not limited to this example.
  • the semiconductor substrates 101, 121, and 131 for example, other types of semiconductor substrates such as a gallium arsenide (GaAs) substrate and a silicon carbide (SiC) substrate may be used.
  • a substrate made of a non-semiconductor material such as a sapphire substrate may be used instead of the semiconductor substrates 101, 121, 131.
  • connection structure As described with reference to FIG. 1, in the solid-state imaging device 1, the pad 151 provided on any of the first substrate 110 ⁇ / b> A, the second substrate 110 ⁇ / b> B, and the third substrate 110 ⁇ / b> C is provided outside the solid-state imaging device 1.
  • the connection structure connects each other by electrical connection means such as a wiring and a substrate. Therefore, the signal lines and the power supply lines provided on the first substrate 110A, the second substrate 110B, and the third substrate 110C can be electrically connected to each other across the plurality of substrates through these connection structures.
  • connection structures in the horizontal plane can be appropriately determined so that the performance of the solid-state imaging device 1 as a whole can be improved in consideration of the configuration and performance of each substrate (each chip).
  • each substrate each chip
  • 2A and 2B are diagrams for explaining an example of the arrangement of the connection structure in the solid-state imaging device 1 in the horizontal plane.
  • 2A and 2B show the arrangement of connection structures when, for example, the solid-state imaging device 1 includes a pixel signal processing circuit that performs processing such as AD conversion on pixel signals on the first substrate 110A. Yes.
  • FIG. 2A schematically shows the first substrate 110A, the second substrate 110B, and the third substrate 110C constituting the solid-state imaging device 1. Then, the electrical connection through the connection structure between the lower surface of the first substrate 110A (the surface facing the second substrate 110B) and the upper surface of the second substrate 110B (the surface facing the first substrate 110A) is simulated by a broken line. The electrical connection through the connection structure between the lower surface of the second substrate 110B (the surface facing the third substrate 110C) and the upper surface of the third substrate 110C (the surface facing the second substrate 110B) is simulated by a solid line. Is shown.
  • connection structure 201 functions as an external input / output unit (I / O unit) for exchanging various signals such as a power supply signal and a GND signal with the outside.
  • the connection structure 201 may be a pad 151 provided on the upper surface of the first substrate 110A.
  • the connection structure 201 may be a pad opening 153 provided to expose a connection surface of the pad 151 with an external input.
  • the pixel portion 206 is provided in the center of the chip, and the connection structure 201 constituting the I / O portion is arranged around the pixel portion 206 (that is, the outer periphery of the chip). Along).
  • a pixel signal processing circuit can also be disposed around the pixel portion 206.
  • connection structure 202 on the lower surface of the first substrate 110A, the position of the connection structure 203 on the upper surface of the second substrate 110B, the position of the connection structure 204 on the lower surface of the second substrate 110B, and the upper surface of the third substrate 110C.
  • These connection structures 202 to 205 may be TSVs or electrode bonding structures provided between the substrates.
  • the pad 151 is embedded in the multilayer wiring layer 125 of the second substrate 110B or the multilayer wiring layer 135 of the third substrate 110C, the pad 151 is located immediately below the connection structure 201 among the connection structures 202 to 205.
  • connection structures 202 to 205 are shown in conformity with the linear form representing the electrical connection shown in FIG. 2A. That is, the connection structure 202 on the lower surface of the first substrate 110A and the connection structure 203 on the upper surface of the second substrate 110B are indicated by broken lines, and the connection structure 204 on the lower surface of the second substrate 110B and the connection on the upper surface of the third substrate 110C.
  • the structure 205 is indicated by a solid line.
  • the pixel signal processing circuit is mounted around the pixel portion 206 of the first substrate 110A. Accordingly, in the first substrate 110A, the pixel signal acquired by the pixel unit 206 is transmitted to the second substrate 110B after being subjected to processing such as AD conversion in the pixel signal processing circuit. Further, as described above, in the first substrate 110A, the connection structure 201 constituting the I / O portion is also arranged around the pixel portion 206 of the first substrate 110A. Therefore, as shown in FIG. 2B, the connection structure 202 on the lower surface of the first substrate 110A is used to electrically connect the pixel signal processing circuit and the I / O unit to the wiring provided in the second substrate 110B.
  • connection structure 203 on the upper surface of the second substrate 110B is also arranged along the outer periphery of the chip.
  • connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are arranged over the entire surface of the chip.
  • 2C and 2D are diagrams for explaining another example of the arrangement of the connection structure in the solid-state imaging device 1 in the horizontal plane.
  • 2C and 2D show the arrangement of the connection structure when the solid-state imaging device 1 is configured to be able to execute the pixel ADC, for example.
  • the pixel signal processing circuit is mounted not on the first substrate 110A but on the second substrate 110B.
  • FIG. 2C schematically shows the first substrate 110A, the second substrate 110B, and the third substrate 110C that constitute the solid-state imaging device 1, as in FIG. 2A.
  • the electrical connection through the connection structure between the lower surface of the first substrate 110A (the surface facing the second substrate 110B) and the upper surface of the second substrate 110B (the surface facing the first substrate 110A) is indicated by a broken line or a dotted line.
  • the electrical connection through the connection structure between the lower surface of the second substrate 110B (the surface facing the third substrate 110C) and the upper surface of the third substrate 110C (the surface facing the second substrate 110B) is schematically shown. This is simulated.
  • the broken line indicates the electrical connection related to, for example, the I / O portion that also exists in FIG. These show the electrical connections for the pixel ADC that did not exist in FIG. 2A.
  • connection structures 202 to 205 are shown in conformity with the linear form representing the electrical connection shown in FIG. 2C. That is, of the connection structure 202 on the lower surface of the first substrate 110A and the connection structure 203 on the upper surface of the second substrate 110B, the one corresponding to the electrical connection related to, for example, the I / O portion that also exists in FIG. Those that can correspond to the electrical connection of the pixel ADC are indicated by dotted lines.
  • the connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are indicated by solid lines.
  • the pixel signal processing circuit is mounted on the second substrate 110B, and the pixel ADC is configured. That is, the pixel signal acquired in each pixel of the pixel unit 206 is transmitted to the pixel signal processing circuit mounted on the second substrate 110B immediately below for each pixel, and processing such as AD conversion is performed in the pixel signal processing circuit. Done. Accordingly, as shown in FIGS. 2C and 2D, in the configuration example, the connection structure 202 on the lower surface of the first substrate 110A is used to transmit the signal from the I / O unit to the second substrate 110B.
  • connection structure 202 shown by a broken line in the figure.
  • the pixel portion 206 is disposed over the entire region where the pixel portion 206 exists (connection structure 202 indicated by a dotted line in the figure).
  • connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C are arranged over the entire surface of the chip.
  • 2E and 2F are diagrams for explaining still another example of the arrangement of the connection structure in the solid-state imaging device 1 in the horizontal plane.
  • 2E and 2F show the arrangement of the connection structure when, for example, a memory circuit is mounted on the second substrate 110B.
  • FIG. 2E schematically shows the first substrate 110A, the second substrate 110B, and the third substrate 110C that constitute the solid-state imaging device 1, as in FIG. 2A.
  • the electrical connection through the connection structure between the lower surface of the first substrate 110A (the surface facing the second substrate 110B) and the upper surface of the second substrate 110B (the surface facing the first substrate 110A) is indicated by a broken line or a dotted line.
  • the electrical connection through the connection structure between the lower surface of the second substrate 110B (the surface facing the third substrate 110C) and the upper surface of the third substrate 110C (the surface facing the second substrate 110B) is schematically shown. Or it is simulating with a dotted line.
  • the broken line indicates the electrical connection related to, for example, the I / O portion that also exists in FIG. These show the electrical connections for the memory circuit that did not exist in FIG. 2A.
  • the solid line is a signal that is also present in FIG. 2A and is not directly related to the operation of the memory circuit, for example.
  • the dotted line indicates the electrical connection related to the memory circuit that did not exist in FIG. 2A.
  • connection structures 202 to 205 are shown in conformity with the linear form representing the electrical connection shown in FIG. 2E. That is, of the connection structure 202 on the lower surface of the first substrate 110A and the connection structure 203 on the upper surface of the second substrate 110B, the one corresponding to the electrical connection related to, for example, the I / O portion that also exists in FIG.
  • connection structure 204 on the lower surface of the second substrate 110B and the connection structure 205 on the upper surface of the third substrate 110C for example, an electric signal related to a signal that does not directly relate to the operation of the memory circuit, which also exists in FIG.
  • Those corresponding to the electrical connection are indicated by solid lines, and those that can correspond to the electrical connection relating to the memory circuit are indicated by dotted lines.
  • the memory circuit is mounted on the second substrate 110B.
  • the pixel signal processing circuit is mounted on the first substrate 110A, and the pixel signal acquired by the pixel unit 206 and AD-converted by the pixel signal processing circuit on the first substrate 110A is the memory circuit of the second substrate 110B. Can be transmitted and held. Then, in order to read out the pixel signal held in the memory circuit of the second substrate 110B, for example, to the outside, signal transmission is performed between the memory circuit of the second substrate 110B and the logic circuit of the third substrate 110C.
  • connection structure 202 on the lower surface of the first substrate 110A has the I / O unit and the pixel signal processing circuit in order to transmit signals from the I / O unit and the wiring provided in the second substrate 110B.
  • connection structure 202 indicated by a broken line in the figure the AD-converted pixel signal of the second substrate 110B A transmission (connection structure 202 indicated by a dotted line in the figure) for transmission to the memory circuit is arranged.
  • connection structures 202 to 205 can be centrally provided near the center in the horizontal plane. However, if the wiring length can be made substantially uniform, the connection structures 202 to 205 are not necessarily provided near the center in the horizontal plane as in the illustrated example.
  • connection structure in the solid-state imaging device 1 in the horizontal plane has been described. Note that the present embodiment is not limited to the example described above.
  • the configuration mounted on each substrate in the solid-state imaging device 1 may be appropriately determined, and the arrangement of the connection structure in the solid-state imaging device 1 in the horizontal plane may be appropriately determined according to the configuration.
  • Various well-known things may be applied as a structure mounted in each board
  • the connection structure 201 constituting the I / O unit is arranged along the three sides of the outer periphery of the chip.
  • the present embodiment is not limited to this example.
  • Various well-known things may be applied also about arrangement
  • the connection structure 201 constituting the I / O unit may be arranged along one side, two sides, or four sides of the outer periphery of the chip.
  • the solid-state imaging device 1 In the configuration example shown in FIG. 1, in the solid-state imaging device 1, the first substrate 110A and the second substrate 110B are bonded together by FtoB (that is, the back surface side of the second substrate 110B is the surface side of the first substrate 110A). It was suitable).
  • the solid-state imaging device 1 may be configured by bonding the first substrate 110A and the second substrate 110B with FtoF (that is, the surface side of the second substrate 110B faces the surface side of the first substrate 110A). May be)
  • the direction of the second substrate 110B may be determined as appropriate so that the performance of the solid-state imaging device 1 as a whole can be improved in consideration of, for example, the configuration and performance of each substrate (each chip). .
  • two concepts for determining the direction of the second substrate 110B will be described.
  • FIG. 3A is a longitudinal sectional view showing a schematic configuration of the solid-state imaging device 1a in which the first substrate 110A and the second substrate 110B are bonded together by FtoF
  • FIG. 3B is a longitudinal sectional view showing a schematic configuration of the solid-state imaging device 1 in which the first substrate 110A and the second substrate 110B are bonded together by FtoB, similarly to the configuration example shown in FIG.
  • the configuration of the solid-state imaging device 1a is the same as that of the solid-state imaging device 1 shown in FIG. 1 except that the direction of the second substrate 110B is opposite.
  • the function (signal wiring, GND wiring, or power supply wiring) of each wiring included in the multilayer wiring layers 105, 125, 135 is represented by hatching shown in the legend, and these hatching representing the function of each wiring. Is superimposed on the hatching of the wiring shown in FIG.
  • terminals corresponding to the above-described pads 151 for leading out signal wiring, GND wiring, and power supply wiring are provided along the outer periphery of the chip. .
  • Each of these terminals is provided in pairs at a position sandwiching the pixel portion 206 in the horizontal plane. Therefore, in the solid-state imaging device 1, 1a, the signal wiring, the GND wiring, and the power supply wiring are extended so as to connect these terminals, and are stretched in a horizontal plane.
  • the photodiode provided in each pixel of the pixel portion is a photodiode in which an N-type diffusion region is formed in PWELL in order to photoelectrically convert incident light and extract electrons.
  • the transistor provided in each pixel is an N-type MOS transistor in order to read out electrons generated by the photodiode. For this reason, the WELL of the pixel portion is PWELL.
  • the logic circuit and the memory circuit provided on the second substrate 110B and the third substrate 110C are configured by CMOS circuits, PMOS and NMOS may be mixed. For this reason, PWELL and NWELL exist, for example, in the same area. Therefore, in the illustrated configuration example, the area of the PWELL is larger in the first substrate 110A than in the second substrate 110B and the third substrate 110C.
  • a GND potential can be applied to PWELL. Therefore, when there is a configuration in which the PWELL and the power supply wiring face each other with an insulator interposed therebetween, a parasitic capacitance is formed between them.
  • FIG. 4A is a diagram for describing a parasitic capacitance between the PWELL and the power supply wiring in the solid-state imaging device 1a illustrated in FIG. 3A.
  • 4A shows the solid-state imaging device 1a shown in FIG. 3A in a simplified manner, and similarly to FIG. 3A, the function of each wiring is shown by hatching superimposed on the hatching of the wiring shown in FIG. As shown in FIG.
  • FIG. 4B is a diagram for explaining the parasitic capacitance between the PWELL and the power supply wiring in the solid-state imaging device 1 shown in FIG. 3B.
  • the solid-state imaging device 1 shown in FIG. 3B is simplified, and the function of each wiring is shown by hatching superimposed on the wiring hatching shown in FIG.
  • the logic circuit or the memory circuit PWELL of the third substrate 110C and the second substrate 110B The power supply wiring in the multilayer wiring layer 125 is opposed to the insulating film 123, 133 with an insulator interposed therebetween. Therefore, a parasitic capacitance can be formed between the two (in FIG. 4B, the parasitic capacitance is schematically shown by a two-dot chain line).
  • the parasitic capacitance is considered to increase as the PWELL area increases. Therefore, in the configuration example shown in FIGS. 4A and 4B, the configuration in which the first substrate 110A and the second substrate 110B shown in FIG. 4A are bonded to each other by FtoF is the same as the second substrate 110B and the second substrate shown in FIG. 4B.
  • the parasitic capacitance is larger than the configuration in which the three substrates 110C are bonded to each other with FtoF.
  • the parasitic capacitance related to the power supply wiring in the second substrate 110B is large, the impedance of the current path of the power supply-GND in the second substrate 110B decreases. Therefore, the power supply system in the second substrate 110B can be further stabilized. Specifically, for example, even when the power consumption fluctuates with fluctuations in the operation of the circuit in the second substrate 110B, fluctuations in the power supply level due to fluctuations in the power consumption can be suppressed. Therefore, even when the circuit related to the second substrate 110B is operated at high speed, the operation can be further stabilized, and the performance of the entire solid-state imaging device 1a can be improved.
  • the solid-state imaging device 1a in which the first substrate 110A and the second substrate 110B are bonded to each other with FtoF is used.
  • a larger parasitic capacitance is formed in the power supply wiring of the second substrate 110B, and high stability can be obtained when operating at high speed. That is, it can be said that the solid-state imaging device 1a is a more preferable configuration.
  • the third substrate 110C may have a larger PWELL area than the first substrate 110A.
  • the configuration of the solid-state imaging device 1 in which a larger parasitic capacitance is formed between the power supply wiring of the second substrate 110B and the PWELL of the third substrate 110C is faster than the solid-state imaging device 1a. It is considered that high stability can be obtained when it is used.
  • the solid-state imaging device 1a is configured so that the side faces the front surface side of the first substrate 110A, that is, the first substrate 110A and the second substrate 110B are bonded together by FtoF.
  • the surface side of the second substrate 110B faces the surface side of the third substrate 110C, that is, the first substrate.
  • the solid-state imaging device 1 is configured such that 110A and the second substrate 110B are bonded together by FtoB.
  • the direction of the second substrate 110B may be determined from the viewpoint based on the area of the PWELL.
  • the solid-state imaging devices 1 to 15E according to this embodiment shown in FIG. 1 and FIGS. 6A to 15E to be described later are configured such that, for example, the area of the PWELL of the first substrate 110A is smaller than the area of the PWELL of the third substrate 110C. Accordingly, the first substrate 110A and the second substrate 110B are configured to be bonded together by FtoB. Therefore, according to the solid-state imaging devices 1 to 15E, it is possible to obtain high operational stability even during high-speed operation.
  • the first substrate 110A includes a photodiode that photoelectrically converts incident light and extracts electrons, and Only a pixel portion having an NMOS transistor for reading electrons from the photodiode in the PWELL is mounted, and various circuits (pixel signal processing circuit, logic circuit, memory circuit, etc.) are provided on the second substrate 110B and the third substrate 110C. May be installed.
  • the PWELL area of the third substrate 110C is larger than the PWELL area of the first substrate 110A, for example, both the pixel portion and various circuits are mounted on the first substrate 110A. It is conceivable that the area occupied by the various circuits is relatively large.
  • FIG. 5A is a diagram schematically showing the arrangement of power supply wiring and GND wiring in the solid-state imaging device 1a shown in FIG. 3A.
  • FIG. 5B is a diagram schematically showing the arrangement of the power supply wiring and the GND wiring in the solid-state imaging device 1 shown in FIG. 3B.
  • 5A and 5B the structure of the solid-state imaging device 1 or 1a is illustrated in a simplified manner, and the schematic arrangement of the power supply wiring and the GND wiring is indicated by a two-dot chain line, and the GND wiring is indicated by a one-dot chain line. It is shown by showing.
  • the size of the arrow in the figure schematically represents the amount of current flowing through the power supply wiring and the GND wiring.
  • the power supply wiring is a vertical power supply wiring extending in the z-axis direction from a power supply terminal (VCC) provided on the upper surface of the first substrate 110A (that is, the upper surface of the solid-state imaging device 1, 1a).
  • VCC power supply terminal
  • the vertical power supply wiring 303 and the horizontal power supply wiring 304 are collectively referred to as power supply wirings 303 and 304.
  • the horizontal power supply wiring 304 may also exist in the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B. However, in FIG. 5A and FIG. The illustration is omitted, and only the horizontal power supply wiring 304 in the multilayer wiring layer 135 of the third substrate 110C is illustrated.
  • the GND wiring includes a vertical GND wiring 305 extending in the z-axis direction from a GND terminal provided on the upper surface of the first substrate 110A, a multilayer wiring layer 105 of the first substrate 110A, a multilayer wiring layer 125 of the second substrate 110B, And the horizontal GND wiring 306 extending in the horizontal direction in the multilayer wiring layer 135 of the third substrate 110C.
  • the vertical GND wiring 305 and the horizontal GND wiring 306 are collectively referred to as GND wirings 305 and 306.
  • the horizontal GND wiring 306 of the first substrate 110A is also referred to as a horizontal GND wiring 306a
  • the horizontal GND wiring 306 of the second substrate 110B is also referred to as a horizontal GND wiring 306b
  • 306 is also referred to as a horizontal GND wiring 306c.
  • the third substrate 110C is assumed to be a logic substrate.
  • the logic circuit is divided into a plurality of circuit blocks, and the circuit block that operates depends on the contents to be processed. That is, the place where the solid-state imaging device 1 or 1a mainly operates during a series of operations can vary. Therefore, there is a bias in the place where the power supply current flows in the logic circuit (for example, the power supply current is generated due to charging / discharging of the transistor gate capacitance and the wiring capacitance accompanying the operation of the circuit), and the location varies. Can do.
  • FIGS. 5A and 5B attention is paid to the two circuit blocks 301 and 302 in the logic circuit of the third substrate 110C.
  • a current path of power supply terminal-power supply wiring 303, 304-circuit block 301, 302-GND wiring 305, 306-GND terminal is formed.
  • the power consumption at a certain timing is larger in the circuit block 301 than in the circuit block 302.
  • the amount of current flowing through the vertical GND wiring 305 via the circuit blocks 301 and 302 is also described as a vertical GND wiring 305 near the circuit block 301 (for the sake of distinction, also referred to as a vertical GND wiring 305a).
  • Is larger than the vertical GND wiring 305 near the circuit block 302 also referred to as a vertical GND wiring 305b for the sake of distinction).
  • the imbalance in the amount of current between the vertical GND wirings 305a and 305b is directed to the GND terminal on the upper surface of the first substrate 110A.
  • the horizontal GND wirings 306a and 306b of the first substrate 110A and the second substrate 110B are eliminated. That is, current flows through the horizontal GND wirings 306a and 306b of the first substrate 110A and the second substrate 110B so as to eliminate the imbalance of the current amount between the vertical GND wirings 305a and 305b.
  • the solid-state imaging devices 1 and 1a include the horizontal power supply wiring 304, the circuit block 301, 302, the horizontal GND wiring 306c, the vertical GND wiring 305a, and the horizontal GND wiring 306a as shown by solid arrows in FIGS. 5A and 5B.
  • 306b is formed as a loop current path.
  • the horizontal GND wirings 306a and 306b of the first substrate 110A and the second substrate 110B are In either case, the third substrate 110C is disposed relatively far from the horizontal power supply wiring 304. Accordingly, since the opening width of the loop is increased in the loop-shaped current path, the inductance of the loop-shaped current path is increased. That is, the impedance is increased. Therefore, the stability of the power supply current is lowered, and the performance of the solid-state imaging device 1a as a whole may be lowered.
  • the horizontal GND wiring 306a of the first substrate 110A is the horizontal power supply wiring of the third substrate 110C.
  • the horizontal GND wiring 306b of the second substrate 110B is disposed relatively close to the horizontal power supply wiring 304 of the third substrate 110C. Therefore, the opening width of the loop is reduced in the loop-shaped current path, so that the inductance of the loop-shaped current path is decreased. That is, the impedance is lowered. Therefore, the power supply current can be further stabilized, and the performance of the solid-state imaging device 1 as a whole can be further improved.
  • the horizontal GND wiring 306b of the second substrate 110B can be disposed on the first substrate 110A and the second substrate 110B. It is considered that more stable operation can be realized than the solid-state imaging device 1a in which and are bonded by FtoF. That is, it can be said that the solid-state imaging device 1 is a more preferable configuration.
  • the first substrate 110A may consume more power than the third substrate 110C.
  • the configuration of the solid-state imaging device 1a that can make the distance between the horizontal power supply wiring of the first substrate 110A and the horizontal GND wiring 306b of the second substrate 110B closer than the solid-state imaging device 1. It is considered that more stable operation can be expected.
  • the solid-state imaging device 1a is configured so that the front surface side of the first substrate 110A faces the front surface side of the first substrate 110A, that is, the first substrate 110A and the second substrate 110B are bonded together by FtoF.
  • the surface side of the second substrate 110B faces the surface side of the third substrate 110C, that is, the first substrate 110A and
  • the solid-state imaging device 1 is preferably configured such that the second substrate 110B is bonded to the second substrate 110B by FtoB.
  • the direction of the second substrate 110B may be determined from the viewpoint based on the power consumption and the arrangement of the GND wiring.
  • the solid-state imaging devices 1 to 15E according to the present embodiment illustrated in FIG. 1 and FIGS. 6A to 15E described later are configured such that, for example, the power consumption of the first substrate 110A is smaller than the power consumption of the third substrate 110C. Accordingly, the first substrate 110A and the second substrate 110B are configured to be bonded together by FtoB. Therefore, according to the solid-state imaging devices 1 to 15E, more stable operation can be realized.
  • the power consumption of the third substrate 110C is larger than the power consumption of the first substrate 110A
  • only the pixel portion is mounted on the first substrate 110A, and more on the second substrate 110B and the third substrate 110C.
  • these circuits for example, a pixel signal processing circuit, a logic circuit, and a memory circuit
  • the pixel portion is mounted on the first substrate 110A
  • the pixel signal processing circuit and the memory circuit are mounted on the second substrate 110B
  • the logic is mounted on the third substrate 110C.
  • a configuration in which a circuit is mounted can be considered.
  • a digital circuit for example, a digital circuit that generates a reference voltage for AD conversion
  • a memory circuit with high access frequency for example, a memory circuit in which pixel signals are written or read multiple times in one frame
  • the power consumption of the third substrate 110C is expected to grow.
  • the power consumption of the first substrate 110A is larger than the power consumption of the third substrate 110C
  • both the pixel portion and various circuits are mounted on the first substrate 110A. It can be considered that the area occupied by the circuit is relatively large.
  • a memory circuit with low access frequency for example, a memory circuit in which a pixel signal is written or read out once per frame
  • the power consumption of the third substrate 110C is relatively increased.
  • the power consumption itself may be compared, or another index that may represent the magnitude of the power consumption may be compared.
  • the other indicators include the number of gates (for example, 100 gates and 1M gates) mounted on the circuit of each substrate, the operating frequencies of the circuits of each substrate (for example, 100 MHz and 1 GHz), and the like.
  • FIG. 5C is a diagram illustrating a configuration example for reducing the impedance in the solid-state imaging device 1a illustrated in FIG. 5A. 5C is different from the solid-state imaging device 1a shown in FIG.
  • the other configuration is the same as that of the solid-state imaging device 1a.
  • the horizontal GND wirings 306a and 306b can be strengthened, and the impedance in the loop-shaped current path can be lowered, so that the solid-state imaging device 1b is more comprehensive than the solid-state imaging device 1a. It is considered possible to further improve the performance.
  • FIG. 5C the horizontal GND wirings 306a and 306b can be strengthened, and the impedance in the loop-shaped current path can be lowered, so that the solid-state imaging device 1b is more comprehensive than the solid-state imaging device 1a. It is considered possible to further improve the performance.
  • the power consumption of the third substrate 110C is larger than the power consumption of the first substrate 110A and the first substrate 110A and the second substrate 110B are bonded to each other by FtoF
  • the configuration can reduce the impedance of the loop-shaped current path
  • the power consumption of the first substrate 110A is larger than the power consumption of the third substrate 110C
  • the first substrate 110A and the second substrate 110B are In the case of bonding by FtoB, in order to reduce the impedance of the loop-shaped current path, a plurality of gaps between the horizontal GND wiring 306b of the second substrate 110B and the horizontal GND wiring 306c of the third substrate 110C are provided. What is necessary is just to connect with a vertical GND wiring.
  • the connection structure for connecting the GND wirings to the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B.
  • the arrangement of the GND wiring in the multilayer wiring layers 105 and 125 and the arrangement of the other wiring are subject to restrictions considering that the connection structure is provided.
  • the vertical GND wiring and the connection structure for connecting them between the substrates are only in the outer peripheral portion of the chip in the horizontal plane. In other words, the distribution is more distributed in the central portion of the chip, and it is necessary to arrange each wiring in consideration of this fact. That is, the degree of freedom in designing each wiring in the multilayer wiring layers 105 and 125 is lowered.
  • the impedance of the loop current path is reduced by adjusting the direction of the second substrate 110B. Therefore, unlike the configuration shown in FIG. 5C, the vertical GND wirings can be arranged so that the vertical GND wirings are distributed more in the outer periphery of the chip in the horizontal plane. Therefore, the impedance in the current path can be reduced, that is, the operation of the solid-state imaging device 1 or 1a can be stabilized without reducing the degree of freedom of design of each wiring in the multilayer wiring layers 105 and 125.
  • the density of the arrangement of the vertical GND wirings in the outer peripheral portion of the chip in the horizontal plane and the central portion of the chip can be determined as follows, for example. For example, in nine areas in which the chip is equally divided into 3 ⁇ 3 areas in the horizontal plane, the number of vertical GND wirings existing in one central area is larger than the number of vertical GND wirings existing in the eight surrounding areas. If there are too many, it can be determined that the number of vertical GND wirings in the center of the chip is large (that is, it can be determined that the configuration of the solid-state imaging device 1b shown in FIG. 5C may be applied).
  • the number of vertical GND wirings existing in one central region is smaller than the number of vertical GND wirings existing in the eight surrounding regions, the number of vertical GND wirings in the outer peripheral portion of the chip is large. (That is, it can be determined that the configuration of the solid-state imaging device 1 or 1a shown in FIGS. 5A and 5B may be applied).
  • the case where the chip is equally divided into nine regions in the horizontal plane has been described as an example, but the number of regions to be divided is not limited to this example, and 4 ⁇ 4 16 regions or 5 ⁇ 5 25
  • the number of areas may be changed as appropriate.
  • the density may be determined by the number of vertical GND wirings in the four central regions and the 12 surrounding regions.
  • the chip is divided into 25 regions of 5 ⁇ 5, one central region and 24 surrounding regions, or nine central regions and 16 surrounding regions, The density may be determined by the number of vertical GND wirings in FIG.
  • the configuration of the solid-state imaging device 1 illustrated in FIG. 1 is an example of a solid-state imaging device according to the present embodiment.
  • the solid-state imaging device according to the present embodiment may be configured to have a connection structure different from that shown in FIG.
  • FIG. 1 another configuration example of the solid-state imaging device according to the present embodiment having a different connection structure will be described.
  • each solid-state imaging device described below corresponds to a part of the configuration of the solid-state imaging device 1 shown in FIG. Therefore, the detailed description of the configuration already described with reference to FIG. 1 is omitted.
  • some reference numerals given in FIG. 1 are omitted in order to avoid the drawing becoming complicated.
  • the members having the same type of hatching are formed of the same material.
  • Each configuration example described below is a bonding structure in which the signal lines and the power supply lines of the first substrate 110A and the second substrate 110B are electrically connected to each other, and the first substrate 110A and the second substrate 110B are attached.
  • the common point is that the connection structure via the mating surface is not included.
  • the wiring of the second substrate 110B, the connection structure that electrically connects the signal lines and the power supply lines of the third substrate 110C, and the first substrate 110A and the third substrate 110C are connected.
  • a connection structure that electrically connects signal lines and power lines is provided, a connection structure that electrically connects signal lines and power lines of the first substrate 110A and the second substrate 110B is not provided. There can be.
  • connection structure via the bonding surface of the first substrate 110A and the second substrate 110B is not only the electrode bonding structure existing on the bonding surface of the first substrate 110A and the second substrate 110B, Also included is a TSV that penetrates the bonding surface of the first substrate 110A and the second substrate 110B.
  • TSV that penetrates the bonding surface of the first substrate 110A and the second substrate 110B.
  • FIGS. 6A to 6B are longitudinal sectional views showing examples of the solid-state imaging devices 6A to 6B according to the first configuration example.
  • a pad 151 is provided on the back side of the first substrate 110A with respect to the solid-state imaging device 1 shown in FIG. 1, and lead line openings 155a, 155b, 155c. This is different in that it is electrically connected to the wirings in the multilayer wiring layers 105, 125, and 135 via the conductive material layer 510 formed on the inner wall of the wiring layer.
  • the lead line opening 155a penetrates the semiconductor substrate 101 from the back side of the first substrate 110A and exposes the wiring in the multilayer wiring layer 105 of the first substrate 110A. Formed.
  • the lead line opening 155b is formed so as to penetrate the first substrate 110A from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the lead line opening 155c is formed so as to penetrate the first substrate 110A and the second substrate 110B from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a, 155b, and 155c, and the conductive material layer 510 is insulated from the back side of the first substrate 110A.
  • the film 109 is stretched up.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A.
  • the pad 151 may be formed by being embedded in the insulating film 109.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a, 155b, and 155c. Further, the pad 151 may be provided for each of the lead line openings 155a, 155b, and 155c, or a plurality of pads 151 may be provided for each lead line opening 155a, 155b, and 155c.
  • FIGS. 7A to 7E are longitudinal sectional views showing examples of the solid-state imaging devices 7A to 7E according to the second configuration example.
  • the wiring in the multilayer wiring layer 125 of the second substrate 110B is exposed from either the back side of the second substrate 110B or the back side of the third substrate 110C.
  • a TSV 157 having a twin contact structure in which a conductive material is embedded in the first through hole and the second through hole exposing the wiring in the multilayer wiring layer 135 of the third substrate 110C is provided.
  • the TSV 157 is provided through the third substrate 110C from the back side of the third substrate 110C.
  • the TSV 157 penetrates through the third substrate 110C to expose the wiring in the multilayer wiring layer 125 of the second substrate 110B and the semiconductor substrate 131, and the multilayer wiring layer of the third substrate 110C.
  • a conductive material is embedded in the second through hole exposing the wiring in 135.
  • the TSV 157 can be connected to a wiring formed of a second metal similar to the pad 151.
  • the pad 151 is provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B, and the pad 151 is exposed by the pad openings 153a and 153b.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C are electrically connected to each other via the TSV 157, the pad 151, and the pad openings 153a and 153b. Is done.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and a multilayer of the first substrate 110A is formed by the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b. You may electrically connect with the wiring in the wiring layer 105, and the wiring in the multilayer wiring layer 125 of the 2nd board
  • the TSV 157 may be connected to a wiring formed of the same first metal as a normal wiring.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the lead line opening 155b is formed from the back side of the first substrate 110A so as to penetrate the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 7B.
  • the TSV 157 may be provided through the second substrate from the back side of the second substrate 110B. Specifically, the TSV 157 penetrates the semiconductor substrate 121 from the back side of the second substrate 110B, and exposes the wiring in the multilayer wiring layer 125 of the second substrate 110B, and the second substrate 110B. A conductive material may be embedded in the second through hole that penetrates the third substrate 110C from the back surface side and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the TSV 157 can electrically connect the signal line and the power supply line of the second substrate 110B and the signal line and the power supply line of the third substrate 110C, so that the first substrate 110A, the second substrate 110B, and the second substrate 110B can be electrically connected.
  • the signal lines and power lines of the three substrates 110C can be electrically connected to each other.
  • the pad 151 may be provided on the insulating film 109 or may be provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B.
  • the pad 151 may be embedded in the insulating film 109 in the structure of the solid-state imaging device 7D.
  • the pad 151 may be provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 135 of the third substrate 110C. . Further, the conductive material layer 510 may be provided to be electrically separated for each of the lead wire openings 155a and 155b. Furthermore, the pad 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • FIGS. 8A to 8G are longitudinal sectional views showing examples of the solid-state imaging devices 8A to 8G according to the third configuration example.
  • the first through hole exposing the wiring in the multilayer wiring layer 125 of the second substrate 110B from the back surface side of the first substrate 110A, and the first substrate 110A A TSV 157 having a twin contact structure in which a conductive material is embedded in the second through hole exposing the wiring in the multilayer wiring layer 135 of the third substrate 110C from the back surface side is provided.
  • the TSV 157 penetrates the first substrate 110A from the back side of the first substrate 110A and exposes the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material is embedded in the hole and the second through hole that penetrates the first substrate 110A and the second substrate 110B and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the pad 151 is provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B, and the pad 151 is exposed by the pad openings 153a and 153b.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C are electrically connected to each other via the TSV 157, the pad 151, and the pad openings 153a and 153b. Is done.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring layer 105 of the first substrate 110A is formed by the conductive material layer 510 formed on the inner wall of the lead line opening 155. It may be electrically connected to the internal wiring.
  • the lead line opening 155 is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner wall of the lead line opening 155, and the conductive material layer 510 includes the insulating film 109 on the back surface side of the first substrate 110A and the TSV 157. Stretched to the top. Further, a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. The pad 151 is connected to the signal line and the power line of the second substrate 110B and the signal line and the power line of the third substrate 110C through the conductive material layer 510 extended on the TSV 157 exposed on the back surface of the first substrate 110A. You may connect electrically.
  • the pad 151 may be embedded in the insulating film 109 in the structure of the solid-state imaging device 8B.
  • the TSV157 is different from the structure of the solid-state imaging device 8C in that the first through hole is replaced with a structure in which a conductive material is embedded in the first through hole and the second through hole.
  • a conductive material may be formed on the inner wall of the second through hole.
  • the conductive material layer 510 is formed in the first through hole and the second through hole of the TSV 157 (that is, the lead line openings 155b and 155a), and the conductive material layer 510 forms the second substrate 110B.
  • the wiring in the multilayer wiring layer 125 and the wiring in the multilayer wiring layer 135 of the third substrate 110C are electrically connected.
  • the TSV 157 uses the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b to electrically connect the pad 151 and the wiring in the multilayer wiring layer of each substrate.
  • a structure similar to the structure can be taken. Therefore, the TSV 157 can also function as a pad lead structure and can be formed at the same time as the pad lead structure including the lead line opening 155c.
  • the pad 151 may be provided on the insulating film 109 so as to protrude from the back surface of the first substrate 110A.
  • the conductive material layer 510 may be connected to a wiring formed of a second metal similar to the pad 151 with respect to the structure of the solid-state imaging devices 8D and 8E. Alternatively, it may be connected to a wiring formed of the same first metal as a normal wiring.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a, 155b, and 155c. Further, the pad 151 may be provided for each of the lead line openings 155a, 155b, and 155c, or a plurality of pads 151 may be provided for each lead line opening 155a, 155b, and 155c.
  • FIGS. 9A to 9F are longitudinal sectional views showing examples of the solid-state imaging devices 9A to 9F according to the fourth configuration example.
  • the wiring in the multilayer wiring layer 125 of the second substrate 110B and the wiring in the multilayer wiring layer 135 of the third substrate 110C are connected to one through hole.
  • a TSV157 having a shared contact structure embedded with a conductive material is provided.
  • the TSV 157 is provided through the third substrate 110C from the back side of the third substrate 110C, and is in contact with the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the conductive material is embedded in one through hole exposing the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the TSV 157 may be formed in a structure in which at least a side surface of the wiring included in the multilayer wiring layer 135 is exposed and a through hole that exposes the upper surface of the wiring included in the multilayer wiring layer 125 is embedded with the conductive material.
  • the TSV 157 having the shared contact structure may be in contact with a plurality of wirings in the multilayer wiring layer 135 of the third substrate 110C on both sides, or may be in contact with one wiring in the multilayer wiring layer 135 of the third substrate 110C on one side. Also good. Similarly, TSV157 of other shared contact structures described below may be in contact with the wiring in multilayer wiring layers 105, 125, 135 on either side or one side. Note that the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • a pad 151 is provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B, and the pad 151 is exposed by the pad openings 153a and 153b.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C are electrically connected to each other via the TSV 157, the pad 151, and the pad openings 153a and 153b. Is done.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring of the first substrate 110A is formed by the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b.
  • the wiring in the layer 105 and the wiring in the multilayer wiring layer 125 of the second substrate 110B may be electrically connected.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the portion 155b is formed so as to penetrate the first substrate 110A from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 9B.
  • the TSV 157 is provided through the second substrate 110B from the back surface side of the second substrate 110B, and contacts the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the conductive material may be embedded in one through hole that exposes the wiring in the multilayer wiring layer 135 of 110C.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the TSV 157 can electrically connect the wiring of the second substrate 110B and the wiring of the third substrate 110C, so that the signal lines and power supply of the first substrate 110A, the second substrate 110B, and the third substrate 110C The lines can be electrically connected to each other.
  • the pad 151 may be provided on the back surface side of the first substrate 110A with respect to the structure of the solid-state imaging device 9D.
  • the pad 151 is connected to the wiring in the multilayer wiring layer 105 of the first substrate 110A and the second substrate 110B via the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b.
  • the wiring in the multilayer wiring layer 125 may be electrically connected.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 9E.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a and 155b. Further, the pads 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • FIGS. 10A to 10E are longitudinal sectional views showing examples of the solid-state imaging devices 10A to 10E according to the fifth configuration example.
  • the conductive material is embedded in one through hole provided through the first substrate 110A and the second substrate 110B from the back surface side of the first substrate 110A.
  • a TSV157 having a shared contact structure is provided.
  • the TSV 157 is provided through the first substrate 110A and the second substrate 110B from the back side of the first substrate 110A, and is provided in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material is embedded in one through-hole that is in contact with the wiring and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the pad 151 is provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B, and the pad 151 is exposed by the pad openings 153a and 153b.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C are electrically connected to each other via the TSV 157, the pad 151, and the pad openings 153a and 153b. Is done.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring layer 105 of the first substrate 110A is formed by the conductive material layer 510 formed on the inner wall of the lead line opening 155. It may be electrically connected to the internal wiring.
  • the lead line opening 155 is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner wall of the lead line opening 155, and the conductive material layer 510 includes the insulating film 109 on the back surface side of the first substrate 110A and the TSV 157. Stretched to the top. Further, a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. The pad 151 is electrically connected to the signal line and the power line of the second substrate 110B and the third substrate 110C through the conductive material layer 510 extended on the TSV 157 exposed on the back surface of the first substrate 110A. Also good.
  • the pad 151 may be embedded in the insulating film 109.
  • the TSV157 is different from the structure of the solid-state imaging device 10C in that the conductive material is embedded in one through hole, and the conductive material is formed on the inner wall of one through hole. It may be provided in the structure. Specifically, a conductive material layer 510 is formed on the inner wall of the through hole (that is, the lead line opening 155a) of the TSV 157, and the conductive material layer 510 allows the wiring in the multilayer wiring layer 125 of the second substrate 110B, and The wiring in the multilayer wiring layer 135 of the third substrate 110C is electrically connected.
  • the TSV 157 has a pad lead structure that electrically connects the pad 151 and the wiring in the multilayer wiring layer of each substrate by the conductive material layer 510 formed on the inner wall of the lead line opening 155a.
  • the TSV 157 can also function as a pad lead structure and can be formed simultaneously with the pad lead structure including the lead line opening 155b.
  • the pad 151 may be embedded in the insulating film 109 in the structure of the solid-state imaging device 10D.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a and 155b. Further, the pads 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • FIGS. 11A to 11C are longitudinal sectional views showing examples of the solid-state imaging devices 11A to 11C according to the sixth configuration example.
  • an electrode bonding structure 159 is provided in which the electrodes provided on the bonding surfaces of the second substrate 110B and the third substrate 110C are bonded in a direct contact state.
  • the electrode bonding structure 159 is formed on the uppermost layer of the multilayer wiring layer 135 of the third substrate 110C and the electrode formed on the uppermost layer of the multilayer wiring layer 125 of the second substrate 110B. It is formed by joining the formed electrodes in direct contact with each other. Note that the electrode bonding structure 159 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring. .
  • a pad 151 is provided inside the multilayer wiring layer 105 of the first substrate 110A and the multilayer wiring layer 125 of the second substrate 110B, and the pad 151 is exposed by the pad openings 153a and 153b.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C are electrically connected to each other through the electrode bonding structure 159, the pad 151, and the pad openings 153a and 153b. Connected.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring of the first substrate 110A is formed by the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b.
  • the wiring in the layer 105 and the wiring in the multilayer wiring layer 125 of the second substrate 110B may be electrically connected.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the portion 155b is formed so as to penetrate the first substrate 110A from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the wiring in the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 11B.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a and 155b. Further, the pads 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • FIGS. 12A to 12F are longitudinal sectional views showing examples of the solid-state imaging devices 12A to 12F according to the seventh configuration example.
  • the first through hole exposing the wiring in the multilayer wiring layer 125 of the second substrate 110B and the wiring in the multilayer wiring layer 135 of the third substrate 110C are connected.
  • a structure 159 is provided.
  • the TSV 157 penetrates the third substrate 110C from the back side of the third substrate 110C and exposes the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material is embedded in the hole and the second through hole that penetrates the semiconductor substrate 131 and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the electrode bonding structure 159 is in a state where the electrode provided on the uppermost layer of the multilayer wiring layer 125 of the second substrate 110B and the electrode provided on the uppermost layer of the multilayer wiring layer 135 of the third substrate 110C are in direct contact with each other. It is formed by joining with.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C via the TSV 157, the electrode bonding structure 159, the pad 151, and the pad openings 153a and 153b. are electrically connected to each other.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring of the first substrate 110A is formed by the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b.
  • the wiring in the layer 105 and the wiring in the multilayer wiring layer 125 of the second substrate 110B may be electrically connected.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the portion 155b is formed so as to penetrate the first substrate 110A from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the wiring in the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 12B.
  • the TSV 157 may be provided through the second substrate from the back side of the second substrate 110B. Specifically, the TSV 157 penetrates the semiconductor substrate 121 from the back side of the second substrate 110B, and exposes the wiring in the multilayer wiring layer 125 of the second substrate 110B, and the second substrate 110B. A conductive material may be embedded in the second through hole that penetrates the third substrate 110C from the back surface side and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the TSV 157 can electrically connect the wiring of the second substrate 110B and the wiring of the third substrate 110C, so that the signal lines and power supply of the first substrate 110A, the second substrate 110B, and the third substrate 110C The lines can be electrically connected to each other.
  • the pad 151 is provided on the back surface side of the first substrate 110A and is formed on the inner wall of the lead line openings 155a and 155b.
  • the layer 510 may be electrically connected to the wiring in the multilayer wiring layer 105 of the first substrate 110A and the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the portion 155b is formed so as to penetrate the first substrate 110A from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the wiring in the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 12E.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a and 155b.
  • the pads 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • the TSV 157 and the electrode bonding structure 159 may be connected to a wiring formed of a second metal similar to the pad 151, or connected to a wiring formed of a first metal similar to a normal wiring. Also good.
  • FIGS. 13A to 13E are longitudinal sectional views showing examples of the solid-state imaging devices 13A to 13E according to the eighth configuration example.
  • the first through hole exposing the wiring in the multilayer wiring layer 125 of the second substrate 110B from the back surface side of the first substrate 110A, and the first substrate 110A
  • the TSV157 having a twin contact structure in which a conductive material is embedded in the second through hole exposing the wiring in the multilayer wiring layer 135 of the third substrate 110C from the back side, and the bonding of the second substrate 110B and the third substrate 110C
  • An electrode bonding structure 159 is provided in which the electrodes provided on the surfaces are bonded in a contact state.
  • the TSV 157 penetrates the first substrate 110A from the back side of the first substrate 110A and exposes the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material is embedded in the hole and the second through hole that penetrates the first substrate 110A and the second substrate 110B and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the electrode bonding structure 159 is in a state where the electrode provided on the uppermost layer of the multilayer wiring layer 125 of the second substrate 110B and the electrode provided on the uppermost layer of the multilayer wiring layer 135 of the third substrate 110C are in direct contact with each other. It is formed by joining with.
  • the signal lines and power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C via the TSV 157, the electrode bonding structure 159, the pad 151, and the pad openings 153a and 153b. Are electrically connected to each other.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring layer 105 of the first substrate 110A is formed by the conductive material layer 510 formed on the inner wall of the lead line opening 155. It may be electrically connected to the internal wiring.
  • the lead line opening 155 is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner wall of the lead line opening 155, and the conductive material layer 510 includes the insulating film 109 on the back surface side of the first substrate 110A and the TSV 157. Stretched to the top. Further, a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the wiring in the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • W tungsten
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 13B.
  • the TSV157 is different from the structure of the solid-state imaging device 13C in that the first through hole is replaced with a structure in which a conductive material is embedded in the first through hole and the second through hole.
  • a conductive material may be formed on the inner wall of the second through hole.
  • a conductive material layer 510 is formed on the inner wall of the first through hole and the second through hole (that is, the lead wire openings 155b and 155a) of the TSV 157, and the second substrate is formed by the conductive material layer 510.
  • the wiring in the multilayer wiring layer 125 of 110B and the wiring in the multilayer wiring layer 135 of the third substrate 110C are electrically connected.
  • the TSV 157 uses the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b to electrically connect the pad 151 and the wiring in the multilayer wiring layer of each substrate.
  • a structure similar to the structure can be taken. Therefore, the TSV 157 can also function as a pad lead structure and can be formed at the same time as the pad lead structure including the lead line opening 155c.
  • the pad 151 may be embedded in the insulating film 109 in the structure of the solid-state imaging device 13D.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a, 155b, and 155c.
  • the pad 151 may be provided for each of the lead line openings 155a, 155b, and 155c, or a plurality of pads 151 may be provided for each lead line opening 155a, 155b, and 155c.
  • FIGS. 14A to 14F are longitudinal sectional views showing examples of the solid-state imaging devices 14A to 14F according to the ninth configuration example.
  • the wiring in the multilayer wiring layer 125 of the second substrate 110B and the wiring in the multilayer wiring layer 135 of the third substrate 110C are connected to one through hole.
  • a TSV 157 having a shared contact structure embedded with a conductive material, and an electrode bonding structure 159 in which the electrodes provided on the bonding surfaces of the second substrate 110B and the third substrate 110C are bonded in a contact state are provided.
  • the TSV 157 is provided through the third substrate 110C from the back side of the third substrate 110C, and is in contact with the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • a conductive material is embedded in one through hole exposing the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the electrode bonding structure 159 is in a state where the electrode provided on the uppermost layer of the multilayer wiring layer 125 of the second substrate 110B and the electrode provided on the uppermost layer of the multilayer wiring layer 135 of the third substrate 110C are in direct contact with each other. It is formed by joining with. Thereby, in the solid-state imaging device 14A, the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C via the TSV 157, the electrode bonding structure 159, the pad 151, and the pad openings 153a and 153b. Are electrically connected to each other.
  • the pad 151 is provided on the back side of the first substrate 110A, and the multilayer wiring of the first substrate 110A is formed by the conductive material layer 510 formed on the inner walls of the lead line openings 155a and 155b.
  • the wiring in the layer 105 and the wiring in the multilayer wiring layer 125 of the second substrate 110B may be electrically connected.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the portion 155b is formed so as to penetrate the first substrate 110A from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top. Further, a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the wiring in the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 in the structure of the solid-state imaging device 14B.
  • the TSV 157 is provided through the second substrate 110B from the back surface side of the second substrate 110B, and comes into contact with the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the conductive material may be embedded in one through hole that exposes the wiring in the multilayer wiring layer 135 of 110C.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the TSV 157 can electrically connect the wiring of the second substrate 110B and the wiring of the third substrate 110C, so that the signal lines and power supply of the first substrate 110A, the second substrate 110B, and the third substrate 110C The lines can be electrically connected to each other.
  • the pad 151 is provided on the back side of the first substrate 110A and is formed on the inner wall of the lead line openings 155a and 155b.
  • the layer 510 may be electrically connected to the wiring in the multilayer wiring layer 105 of the first substrate 110A and the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • the lead line opening 155a is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • the portion 155b is formed so as to penetrate the first substrate 110A from the back surface side of the first substrate 110A and expose the wiring in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner walls of the lead line openings 155a and 155b, and the conductive material layer 510 is formed on the insulating film 109 on the back surface side of the first substrate 110A. Stretched to the top.
  • a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. That is, the pad 151 may be provided on the back surface of the first substrate 110A and electrically connected to the wiring in the multilayer wiring layers 105, 125, and 135 of each substrate through the conductive material layer 510.
  • the pad 151 may be embedded in the insulating film 109 in the structure of the solid-state imaging device 14E.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a and 155b. Further, the pads 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • FIGS. 15A to 15E are longitudinal sectional views showing examples of the solid-state imaging devices 15A to 15E according to the tenth configuration example.
  • the conductive material is embedded in one through hole provided through the first substrate 110A and the second substrate 110B from the back surface side of the first substrate 110A.
  • a TSV 157 having a shared contact structure and an electrode bonding structure 159 in which the electrodes provided on the bonding surfaces of the second substrate 110B and the third substrate 110C are bonded in a contact state are provided.
  • the TSV 157 is provided through the first substrate 110A and the second substrate 110B from the back surface side of the first substrate 110A, and is provided in the multilayer wiring layer 125 of the second substrate 110B.
  • a conductive material is embedded in one through-hole that is in contact with the wiring and exposes the wiring in the multilayer wiring layer 135 of the third substrate 110C.
  • the TSV 157 may be connected to a wiring formed of a second metal similar to the pad 151, or may be connected to a wiring formed of a first metal similar to a normal wiring.
  • the electrode bonding structure 159 is in a state where the electrode provided on the uppermost layer of the multilayer wiring layer 125 of the second substrate 110B and the electrode provided on the uppermost layer of the multilayer wiring layer 135 of the third substrate 110C are in direct contact with each other. It is formed by joining with.
  • the signal lines and the power lines of the first substrate 110A, the second substrate 110B, and the third substrate 110C via the TSV 157, the electrode bonding structure 159, the pad 151, and the pad openings 153a and 153b. Are electrically connected to each other.
  • the pad 151 is provided on the back surface side of the first substrate 110A, and the multilayer wiring layer 105 of the first substrate 110A is formed by the conductive material layer 510 formed on the inner wall of the lead line opening 155. It may be electrically connected to the internal wiring.
  • the lead line opening 155 is formed so as to penetrate the semiconductor substrate 101 from the back side of the first substrate 110A and expose the wiring in the multilayer wiring layer 105 of the first substrate 110A.
  • a conductive material layer 510 made of tungsten (W) or the like is formed on the inner wall of the lead line opening 155, and the conductive material layer 510 includes the insulating film 109 on the back surface side of the first substrate 110A and the TSV 157. Stretched to the top. Further, a pad 151 is provided on the conductive material layer 510 extended on the insulating film 109 on the back surface side of the first substrate 110A. The pad 151 is electrically connected to the signal line and the power line of the second substrate 110B and the third substrate 110C through the conductive material layer 510 extended on the TSV 157 exposed on the back surface of the first substrate 110A. Also good.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 15B.
  • the TSV 157 has a structure in which a conductive material is formed on the inner wall of one through-hole instead of the structure in which the conductive material is embedded in one through-hole in the structure of the solid-state imaging device 15C. It may be provided in the structure. Specifically, a conductive material layer 510 is formed on the inner wall of the through hole (that is, the lead line opening 155a) of the TSV 157, and the conductive material layer 510 allows the wiring in the multilayer wiring layer 125 of the second substrate 110B, and The wiring in the multilayer wiring layer 135 of the third substrate 110C is electrically connected.
  • the TSV 157 has a pad lead structure that electrically connects the pad 151 and the wiring in the multilayer wiring layer of each substrate by the conductive material layer 510 formed on the inner wall of the lead line opening 155.
  • the TSV 157 can also function as a pad lead structure and can be formed simultaneously with the pad lead structure including the lead line opening 155b.
  • the pad 151 may be embedded in the insulating film 109 with respect to the structure of the solid-state imaging device 15D.
  • the conductive material layer 510 may be provided electrically separated for each of the lead line openings 155a and 155b. Further, the pads 151 may be provided for each of the lead line openings 155a and 155b, or a plurality of pads 151 may be provided for each of the lead line openings 155a and 155b.
  • FIG. 16A is a diagram illustrating an appearance of a smartphone as an example of an electronic apparatus to which the solid-state imaging devices 1 to 15E according to the present embodiment can be applied.
  • the smartphone 901 includes buttons, an operation unit 903 that accepts an operation input by a user, a display unit 905 that displays various types of information, and a housing, and electronically captures an observation target.
  • an imaging unit (not shown). The imaging unit can be configured by the solid-state imaging devices 1 to 15E.
  • FIGS. 16B and 16C are views showing the appearance of a digital camera, which is another example of an electronic apparatus to which the solid-state imaging devices 1 to 15E according to this embodiment can be applied.
  • FIG. 16B shows an appearance of the digital camera 911 viewed from the front (subject side)
  • FIG. 16C shows an appearance of the digital camera 911 viewed from the rear.
  • the digital camera 911 displays a main body (camera body) 913, an interchangeable lens unit 915, a grip portion 917 held by the user during shooting, and various types of information.
  • the imaging unit can be configured by the solid-state imaging devices 1 to 15E.
  • the electronic devices to which the solid-state imaging devices 1 to 15E according to the present embodiment can be applied are not limited to those exemplified above.
  • the solid-state imaging devices 1 to 15E include a video camera, a glasses-type wearable device, an HMD (Head Mounted Display),
  • the present invention can be applied as an imaging unit mounted on any electronic device such as a tablet PC or a game device.
  • FIG. 17A is a cross-sectional view illustrating a configuration example of a solid-state imaging device to which the technology according to the present disclosure can be applied.
  • a PD (photodiode) 20019 receives incident light 20001 incident from the back surface (upper surface in the drawing) side of the semiconductor substrate 20018.
  • a planarizing film 20013, a CF (color filter) 20012, and a microlens 20011 are provided above the PD 20019, and incident light 20001 incident through each part is received by the light receiving surface 20017 to perform photoelectric conversion. Is called.
  • the n-type semiconductor region 20020 is formed as a charge accumulation region for accumulating charges (electrons).
  • the n-type semiconductor region 20020 is provided inside the p-type semiconductor regions 20016 and 20041 of the semiconductor substrate 20018.
  • a p-type semiconductor region 20009 having a higher impurity concentration than the back surface (upper surface) side is provided on the front surface (lower surface) side of the semiconductor substrate 20018 in the n-type semiconductor region 20020.
  • the PD 20019 has a HAD (Hole-Accumulation-Diode) structure, and a p-type semiconductor is used to suppress the generation of dark current at each interface between the upper surface side and the lower surface side of the n-type semiconductor region 20020. Regions 20061 and 20041 are formed.
  • HAD Hole-Accumulation-Diode
  • a pixel separation unit 20030 for electrically separating a plurality of pixels 20010 is provided, and a PD 20019 is provided in a region partitioned by the pixel separation unit 20030.
  • the pixel separation unit 20030 is formed in a lattice shape so as to be interposed between a plurality of pixels 20010, for example, and the PD 20001 includes the pixel separation unit 20030. It is formed in a region partitioned by
  • each PD20019 the anode is grounded, and in the solid-state imaging device, signal charges (for example, electrons) accumulated in the PD20019 are read out via a transfer Tr (MOS FET) (not shown) and the like as an electrical signal. It is output to a VSL (vertical signal line) (not shown).
  • MOS FET transfer Tr
  • VSL vertical signal line
  • the wiring layer 20050 is provided on the surface (lower surface) opposite to the back surface (upper surface) on which each part such as the light shielding film 20014, CF20012, and microlens 20011 is provided in the semiconductor substrate 20018.
  • the wiring layer 20050 includes a wiring 20051 and an insulating layer 20052, and the wiring 20051 is formed in the insulating layer 20052 so as to be electrically connected to each element.
  • the wiring layer 20050 is a so-called multilayer wiring layer, and is formed by alternately stacking an interlayer insulating film constituting the insulating layer 20052 and the wiring 20051 a plurality of times.
  • wiring 20051 wiring to the Tr for reading out charges from the PD 20019 such as the transfer Tr and wirings such as VSL are stacked via the insulating layer 20052.
  • a support substrate 20061 is provided on the surface of the wiring layer 20050 opposite to the side on which the PD 20019 is provided.
  • a substrate made of a silicon semiconductor having a thickness of several hundred ⁇ m is provided as the support substrate 20061.
  • the light shielding film 20014 is provided on the back surface (upper surface in the drawing) side of the semiconductor substrate 20018.
  • the light shielding film 20014 is configured to shield a part of incident light 20001 from the upper side of the semiconductor substrate 20018 toward the back surface of the semiconductor substrate 20018.
  • the light shielding film 20014 is provided above the pixel separation unit 20030 provided inside the semiconductor substrate 20018.
  • the light shielding film 20014 is provided on the back surface (upper surface) of the semiconductor substrate 20018 so as to protrude in a convex shape through an insulating film 20015 such as a silicon oxide film.
  • the light shielding film 20014 is not provided and is opened so that the incident light 20001 enters the PD 20019.
  • the planar shape of the light shielding film 20014 is a lattice shape, and an opening through which incident light 20001 passes to the light receiving surface 20017 is formed.
  • the light shielding film 20014 is formed of a light shielding material that shields light.
  • a light shielding film 20014 is formed by sequentially stacking a titanium (Ti) film and a tungsten (W) film.
  • the light-shielding film 20014 can be formed by sequentially stacking a titanium nitride (TiN) film and a tungsten (W) film, for example.
  • the light shielding film 20014 is covered with a planarizing film 20013.
  • the planarization film 20013 is formed using an insulating material that transmits light.
  • the pixel separation portion 20030 includes a groove portion 20031, a fixed charge film 20032, and an insulating film 20033.
  • the fixed charge film 20032 is formed on the back surface (upper surface) side of the semiconductor substrate 20018 so as to cover the groove portions 20031 partitioning the plurality of pixels 20010.
  • the fixed charge film 20032 is provided so as to cover the inner surface of the groove portion 20031 formed on the back surface (upper surface) side of the semiconductor substrate 20018 with a certain thickness. Then, an insulating film 20003 is provided (filled) so as to fill the inside of the groove part 20031 covered with the fixed charge film 20032.
  • the fixed charge film 20032 is made of a high dielectric material having a negative fixed charge so that a positive charge (hole) accumulation region is formed at the interface with the semiconductor substrate 20018 and generation of dark current is suppressed. Is formed.
  • the fixed charge film 20032 By forming the fixed charge film 20032 to have a negative fixed charge, an electric field is applied to the interface with the semiconductor substrate 20018 by the negative fixed charge, and a positive charge (hole) accumulation region is formed.
  • the fixed charge film 20032 can be formed of, for example, a hafnium oxide film (HfO 2 film).
  • the fixed charge film 20032 can be formed to include at least one of oxides such as hafnium, zirconium, aluminum, tantalum, titanium, magnesium, yttrium, and a lanthanoid element.
  • FIG. 17B shows a schematic configuration of a solid-state imaging device to which the technology according to the present disclosure can be applied.
  • the solid-state imaging device 30001 includes an imaging unit (so-called pixel unit) 30003 in which a plurality of pixels 30002 are two-dimensionally arranged with regularity, and peripheral circuits arranged around the imaging unit 30003, that is, a vertical driving unit 30004, a horizontal transfer unit. 30005 and an output unit 30006.
  • the pixel 30002 includes a photodiode 30021 that is one photoelectric conversion element and a plurality of pixel transistors (MOS transistors) Tr1, Tr2, Tr3, and Tr4.
  • the photodiode 30021 has a region for photoelectrically converting light incident and accumulating signal charges generated by the photoelectric conversion.
  • the plurality of pixel transistors include four MOS transistors, that is, a transfer transistor Tr1, a reset transistor Tr2, an amplification transistor Tr3, and a selection transistor Tr4.
  • the transfer transistor Tr1 is a transistor that reads out signal charges accumulated in the photodiode 30021 to a floating diffusion (FD) region 30022 described later.
  • the reset transistor Tr2 is a transistor for setting the potential of the FD region 30022 to a specified value.
  • the amplification transistor Tr3 is a transistor for electrically amplifying the signal charge read to the FD region 30022.
  • the selection transistor Tr4 is a transistor for selecting one row of pixels and reading out a pixel signal to the vertical signal line 30008.
  • the source of the transfer transistor Tr1 is connected to the photodiode 30021, and the drain thereof is connected to the source of the reset transistor Tr2.
  • An FD region 30022 (corresponding to a drain region of the transfer transistor and a source region of the reset transistor) serving as charge-voltage conversion means between the transfer transistor Tr1 and the reset transistor Tr2 is connected to the gate of the amplification transistor Tr3.
  • the source of the amplification transistor Tr3 is connected to the drain of the selection transistor Tr4.
  • the drain of the reset transistor Tr2 and the drain of the amplification transistor Tr3 are connected to the power supply voltage supply unit.
  • the source of the selection transistor Tr4 is connected to the vertical signal line 30008.
  • a row reset signal ⁇ RST applied in common to the gates of the reset transistors Tr2 of the pixels arranged in one row from the vertical drive unit 30004 is also applied in common to the gates of the transfer transistors Tr1 of the pixels in one row.
  • a row selection signal ⁇ SEL, to which the transfer signal ⁇ TRG is applied in common to the gates of the selection transistors Tr4 in one row, is supplied.
  • the horizontal transfer unit 30005 includes an amplifier or an analog / digital converter (ADC) connected to the vertical signal line 30008 of each column, in this example, an analog / digital converter 30009, a column selection circuit (switch means) 30007, a horizontal And a transfer line (for example, a bus line composed of the same number of lines as the data bit lines) 30010.
  • the output unit 30006 includes an amplifier, an analog / digital converter and / or a signal processing circuit, in this example, a signal processing circuit 30011 for processing an output from the horizontal transfer line 30010, and an output buffer 30012. .
  • the signals of the pixels 30002 in each row are subjected to analog / digital conversion by the analog / digital converters 30009, read out to the horizontal transfer line 30010 through the sequentially selected column selection circuit 30007, and sequentially horizontal. Transferred.
  • the image data read to the horizontal transfer line 30010 is output from the output buffer 30012 through the signal processing circuit 30011.
  • the gate of the transfer transistor Tr1 and the gate of the reset transistor Tr2 are turned on to empty all the charges of the photodiode 30021.
  • the gate of the transfer transistor Tr1 and the gate of the reset transistor Tr2 are turned off to perform charge accumulation.
  • the gate of the reset transistor Tr2 is turned on to reset the potential of the FD region 30022.
  • the gate of the reset transistor Tr2 is turned off and the gate of the transfer transistor Tr1 is turned on to transfer the charge from the photodiode 30021 to the FD region 30022.
  • the amplification transistor Tr3 electrically amplifies the signal charge in response to the charge being applied to the gate.
  • the selection transistor Tr4 is turned on only for the pixel to be read from the time of FD reset immediately before the reading, and the charge-voltage converted image signal from the corresponding intra-pixel amplification transistor Tr3 is read to the vertical signal line 30008. .
  • FIG. 17C is an explanatory diagram illustrating a configuration example of a video camera to which the technology according to the present disclosure can be applied.
  • the camera 10000 in this example includes a solid-state imaging device 10001, an optical system 10002 that guides incident light to a light receiving sensor unit of the solid-state imaging device 10001, a shutter device 10003 provided between the solid-state imaging device 10001 and the optical system 10002, and a solid-state imaging device.
  • the camera 10000 further includes a signal processing circuit 10005 that processes an output signal of the solid-state imaging device 10001.
  • the optical system (optical lens) 10002 forms image light (incident light) from a subject on an imaging surface (not shown) of the solid-state imaging device 10001. As a result, signal charges are accumulated in the solid-state imaging device 10001 for a certain period.
  • the optical system 10002 may be configured by an optical lens group including a plurality of optical lenses.
  • the shutter device 10003 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 10001.
  • the drive circuit 10004 supplies drive signals to the solid-state imaging device 10001 and the shutter device 10003.
  • the drive circuit 10004 controls the signal output operation to the signal processing circuit 10005 of the solid-state imaging device 10001 and the shutter operation of the shutter device 10003 based on the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 10001 to the signal processing circuit 10005 is performed by a drive signal (timing signal) supplied from the drive circuit 10004.
  • the signal processing circuit 10005 performs various types of signal processing on the signal transferred from the solid-state imaging device 10001.
  • the signal (AV-SIGNAL) subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).
  • the technology according to the present disclosure may be applied to an endoscopic surgery system.
  • FIG. 17D is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology (present technology) according to the present disclosure can be applied.
  • FIG. 17D shows a situation where an operator (doctor) 11131 is performing an operation on a patient 11132 on a patient bed 11133 using an endoscopic operation system 11000.
  • an endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, and a support arm device 11120 that supports the endoscope 11100. And a cart 11200 on which various devices for endoscopic surgery are mounted.
  • the endoscope 11100 includes a lens barrel 11101 in which a region having a predetermined length from the distal end is inserted into the body cavity of the patient 11132, and a camera head 11102 connected to the proximal end of the lens barrel 11101.
  • a lens barrel 11101 in which a region having a predetermined length from the distal end is inserted into the body cavity of the patient 11132, and a camera head 11102 connected to the proximal end of the lens barrel 11101.
  • an endoscope 11100 configured as a so-called rigid mirror having a rigid lens barrel 11101 is illustrated, but the endoscope 11100 may be configured as a so-called flexible mirror having a flexible lens barrel. Good.
  • An opening into which the objective lens is fitted is provided at the tip of the lens barrel 11101.
  • a light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101. Irradiation is performed toward the observation target in the body cavity of the patient 11132 through the lens.
  • the endoscope 11100 may be a direct endoscope, a perspective mirror, or a side endoscope.
  • An optical system and an image sensor are provided inside the camera head 11102, and reflected light (observation light) from the observation target is condensed on the image sensor by the optical system. Observation light is photoelectrically converted by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image is generated.
  • the image signal is transmitted to a camera control unit (CCU: “Camera Control Unit”) 11201 as RAW data.
  • the CCU 11201 is a CPU (Central Processing Unit) or GPU (Graphics). Processing Unit) and the like, and comprehensively control operations of the endoscope 11100 and the display device 11202. Further, the CCU 11201 receives an image signal from the camera head 11102 and performs various kinds of image processing for displaying an image based on the image signal, such as development processing (demosaic processing), for example.
  • image processing for example, development processing (demosaic processing), for example.
  • the display device 11202 displays an image based on an image signal subjected to image processing by the CCU 11201 under the control of the CCU 11201.
  • the light source device 11203 includes a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing a surgical site or the like.
  • a light source such as an LED (light emitting diode)
  • the input device 11204 is an input interface for the endoscopic surgery system 11000.
  • a user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204.
  • the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) by the endoscope 11100.
  • the treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for tissue ablation, incision, blood vessel sealing, or the like.
  • the pneumoperitoneum device 11206 passes gas into the body cavity via the pneumoperitoneum tube 11111.
  • the recorder 11207 is an apparatus capable of recording various types of information related to surgery.
  • the printer 11208 is a device that can print various types of information related to surgery in various formats such as text, images, or graphs.
  • the light source device 11203 that supplies the irradiation light when the surgical site is imaged to the endoscope 11100 can be configured by, for example, a white light source configured by an LED, a laser light source, or a combination thereof.
  • a white light source is configured by a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high accuracy. Therefore, the light source device 11203 adjusts the white balance of the captured image. It can be carried out.
  • the driving of the light source device 11203 may be controlled so as to change the intensity of the output light every predetermined time. Synchronously with the timing of changing the intensity of the light, the drive of the image sensor of the camera head 11102 is controlled to acquire an image in a time-sharing manner, and the image is synthesized, so that high dynamic without so-called blackout and overexposure A range image can be generated.
  • the light source device 11203 may be configured to be able to supply light of a predetermined wavelength band corresponding to special light observation.
  • special light observation for example, by utilizing the wavelength dependence of light absorption in body tissue, the surface of the mucous membrane is irradiated by irradiating light in a narrow band compared to irradiation light (ie, white light) during normal observation.
  • a so-called narrow-band light observation (Narrow Band Imaging) is performed in which a predetermined tissue such as a blood vessel is imaged with high contrast.
  • fluorescence observation may be performed in which an image is obtained by fluorescence generated by irradiating excitation light.
  • the body tissue is irradiated with excitation light to observe fluorescence from the body tissue (autofluorescence observation), or a reagent such as indocyanine green (ICG) is locally administered to the body tissue and applied to the body tissue. It is possible to obtain a fluorescence image by irradiating excitation light corresponding to the fluorescence wavelength of the reagent.
  • the light source device 11203 can be configured to be able to supply narrowband light and / or excitation light corresponding to such special light observation.
  • FIG. 17E is a block diagram illustrating an example of a functional configuration of the camera head 11102 and the CCU 11201 illustrated in FIG. 17D.
  • the camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405.
  • the CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413.
  • the camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.
  • the lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401.
  • the lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.
  • the imaging device constituting the imaging unit 11402 may be one (so-called single plate type) or plural (so-called multi-plate type).
  • image signals corresponding to RGB may be generated by each imaging element, and a color image may be obtained by combining them.
  • the imaging unit 11402 may be configured to include a pair of imaging elements for acquiring right-eye and left-eye image signals corresponding to 3D (dimensional) display. By performing the 3D display, the operator 11131 can more accurately grasp the depth of the living tissue in the surgical site.
  • a plurality of lens units 11401 can be provided corresponding to each imaging element.
  • the imaging unit 11402 is not necessarily provided in the camera head 11102.
  • the imaging unit 11402 may be provided inside the lens barrel 11101 immediately after the objective lens.
  • the driving unit 11403 is configured by an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. Thereby, the magnification and the focus of the image captured by the imaging unit 11402 can be adjusted as appropriate.
  • the communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201.
  • the communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.
  • the communication unit 11404 receives a control signal for controlling driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405.
  • the control signal includes, for example, information for designating the frame rate of the captured image, information for designating the exposure value at the time of imaging, and / or information for designating the magnification and focus of the captured image. Contains information about the condition.
  • the imaging conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. Good.
  • a so-called AE (Auto-Exposure) function, AF (Auto-Focus) function, and AWB (Auto-White Balance) function are mounted on the endoscope 11100.
  • the camera head control unit 11405 controls driving of the camera head 11102 based on a control signal from the CCU 11201 received via the communication unit 11404.
  • the communication unit 11411 is configured by a communication device for transmitting and receiving various types of information to and from the camera head 11102.
  • the communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.
  • the communication unit 11411 transmits a control signal for controlling driving of the camera head 11102 to the camera head 11102.
  • the image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.
  • the image processing unit 11412 performs various types of image processing on the image signal that is RAW data transmitted from the camera head 11102.
  • the control unit 11413 performs various types of control related to imaging of the surgical site by the endoscope 11100 and display of a captured image obtained by imaging of the surgical site. For example, the control unit 11413 generates a control signal for controlling driving of the camera head 11102.
  • control unit 11413 causes the display device 11202 to display a picked-up image showing the surgical part or the like based on the image signal subjected to the image processing by the image processing unit 11412.
  • the control unit 11413 may recognize various objects in the captured image using various image recognition techniques.
  • the control unit 11413 detects surgical tools such as forceps, specific biological parts, bleeding, mist when using the energy treatment tool 11112, and the like by detecting the shape and color of the edge of the object included in the captured image. Can be recognized.
  • the control unit 11413 may display various types of surgery support information superimposed on the image of the surgical unit using the recognition result. Surgery support information is displayed in a superimposed manner and presented to the operator 11131, thereby reducing the burden on the operator 11131 and allowing the operator 11131 to proceed with surgery reliably.
  • the transmission cable 11400 for connecting the camera head 11102 and the CCU 11201 is an electric signal cable corresponding to electric signal communication, an optical fiber corresponding to optical communication, or a composite cable thereof.
  • communication is performed by wire using the transmission cable 11400.
  • communication between the camera head 11102 and the CCU 11201 may be performed wirelessly.
  • the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.
  • FIG. 17F is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, a sound image output unit 12052, and an in-vehicle network I / F (Interface) 12053 are illustrated as a functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp.
  • the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted.
  • the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image.
  • the vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light.
  • the imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
  • the vehicle interior information detection unit 12040 detects vehicle interior information.
  • a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
  • the microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, following traveling based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
  • the sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 17G is a diagram illustrating an example of an installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100.
  • the imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100.
  • the imaging unit 12105 provided on the upper part of the windshield in the passenger compartment is mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 1022 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100).
  • a solid object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100, particularly the closest three-dimensional object on the traveling path of the vehicle 12100. it can.
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
  • the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles.
  • the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining.
  • the audio image output unit 12052 When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to be superimposed and displayed.
  • voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above.
  • the technique according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, and thus it is possible to reduce driver fatigue.
  • the accuracy of driving support can be improved.
  • the various wirings included in the solid-state imaging devices 1 to 15E may be connected to each other in a cross section (not shown) in order to realize the functions of the solid-state imaging devices 1 to 15E according to the present embodiment. Yes.
  • the first substrate and the second substrate are bonded so that the first multilayer wiring layer and the second semiconductor substrate face each other,
  • the first connection structure for electrically connecting the circuit of the first substrate and the circuit of the second substrate includes: the first substrate formed from the first substrate; and the second substrate.
  • the first connection structure includes an opening provided from the back surface side of the first substrate so as to expose a predetermined wiring in the first multilayer wiring layer, and a predetermined wiring in the second multilayer wiring layer. Including an opening provided at least through the first substrate from the back side of the first substrate so as to be exposed, The solid-state imaging device according to (1).
  • a second connection structure for electrically connecting the circuit of the second substrate and the circuit of the third substrate includes an opening provided at least through the first substrate from the back surface side of the second substrate so as to expose a predetermined wiring in the second multilayer wiring layer, and the third An opening provided at least through the first substrate and the second substrate from the back surface side of the first substrate so as to expose a predetermined wiring in the multilayer wiring layer;
  • the solid-state imaging device according to (2) The predetermined wiring in the second multilayer wiring layer and the predetermined wiring in the third multilayer wiring layer exposed by the opening are pads functioning as I / O portions;
  • the solid-state imaging device according to (3) is
  • a conductive material is formed on the inner wall of the opening, The predetermined wiring in the second multilayer wiring layer and the predetermined wiring in the third multilayer wiring layer exposed by the opening are electrically connected to the pad by the conductive material.
  • the predetermined wiring in the second multilayer wiring layer and the predetermined wiring in the third multilayer wiring layer are electrically connected to the same pad by the conductive material;
  • the predetermined wiring in the second multilayer wiring layer and the predetermined wiring in the third multilayer wiring layer are electrically connected to different pads by the conductive material, respectively.
  • the second substrate and the third substrate are bonded so that the second multilayer wiring layer and the third multilayer wiring layer face each other,
  • the second connection structure is provided through the second substrate or the third substrate, a predetermined wiring in the second multilayer wiring layer, a predetermined wiring in the third multilayer wiring layer, Including electrically connecting vias, including The solid-state imaging device according to (1).
  • the via is different from the first through hole exposing the predetermined wiring in the second multilayer wiring layer and the first through hole exposing the predetermined wiring in the third multilayer wiring layer.
  • the solid-state imaging device is one through-hole provided so as to contact the predetermined wiring in the second multilayer wiring layer and expose the predetermined wiring in the third multilayer wiring layer, or the third multilayer wiring A structure in which a conductive material is embedded in one through hole provided so as to expose the predetermined wiring in the second multilayer wiring layer in contact with the predetermined wiring in the layer, or the one through hole Having a structure in which a conductive material is deposited on the inner wall of The solid-state imaging device according to (8).
  • the second substrate and the third substrate are bonded so that the second multilayer wiring layer and the third multilayer wiring layer face each other,
  • the third connection structure is provided penetrating at least the second substrate from the back surface side of the first substrate or the back surface side of the third substrate, and the predetermined wiring in the first multilayer wiring layer, A via that electrically connects the predetermined wiring in the third multilayer wiring layer;
  • the solid-state imaging device according to (1).
  • the via is different from the first through hole exposing the predetermined wiring in the first multilayer wiring layer and the first through hole exposing the predetermined wiring in the third multilayer wiring layer.
  • the via is provided as one through hole provided so as to be in contact with the predetermined wiring in the third multilayer wiring layer to expose the predetermined wiring in the first multilayer wiring layer, or the third multilayer wiring.
  • the via is electrically connected to a predetermined wiring in the second multilayer wiring layer;
  • the second substrate and the third substrate temporarily hold a pixel circuit acquired by each of the logic circuit that executes various signal processing related to the operation of the solid-state imaging device and the pixels of the first substrate.
  • a memory circuit having at least one of The solid-state imaging device according to any one of (1) to (15).
  • the second substrate has a pixel signal processing circuit that AD converts a pixel signal acquired by each of the pixels of the first substrate,
  • the first connection structure exists corresponding to each of the pixels in order to transmit the pixel signal to the pixel signal processing circuit.
  • a solid-state imaging device that electronically captures an observation target;
  • the solid-state imaging device A first substrate having a first semiconductor substrate on which a pixel portion in which pixels are arranged is formed, and a first multilayer wiring layer stacked on the first semiconductor substrate;
  • a second substrate having a second semiconductor substrate on which a circuit having a predetermined function is formed, and a second multilayer wiring layer stacked on the second semiconductor substrate;
  • a third substrate having a third semiconductor substrate on which a circuit having a predetermined function is formed, and a third multilayer wiring layer stacked on the third semiconductor substrate;
  • the first connection structure for electrically connecting the circuit of the first substrate and the circuit of the second substrate includes: the first substrate formed from the first substrate; and the second substrate. Does not include a connection structure through a bonding surface, or the first connection structure does not exist, Electronics.
  • Electrode bonding structure 510 Conductive material layer 901 Smartphone (electronic device) 911 Digital camera (electronic equipment)

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention vise à améliorer les performances d'un dispositif d'imagerie à semi-conducteurs et d'un appareil électronique. Plus spécifiquement, l'invention concerne un dispositif d'imagerie à semi-conducteurs constitué, stratifiés dans l'ordre suivant: d'un premier substrat dans lequel est formée une partie pixels dans laquelle des pixels sont alignés, et lequel substrat est constitué à son tour d'un premier substrat à semi-conducteurs et d'une première couche de câblage multicouche stratifiés; d'un deuxième substrat dans lequel est formé un circuit avec une fonction prédéterminée, et lequel substrat est constitué à son tour d'un deuxième substrat à semi-conducteurs et d'une deuxième couche de câblage multicouche stratifiés; et d'un troisième substrat dans lequel est formé un circuit avec une fonction prédéterminée, et lequel substrat est constitué à son tour d'un troisième substrat à semi-conducteurs et d'une troisième couche de câblage multicouche stratifiés. Les premier substrat et deuxième substrat susmentionnés sont collés de façon que la première couche de câblage multicouche et la deuxième couche de câblage multicouche soient opposées l'une à l'autre. Le dispositif d'imagerie à semi-conducteurs possède première une structure de connexion pour la connexion électrique du circuit du premier substrat et du circuit du deuxième substrat. Cette première structure de connexion ne contient pas de structure de connexion formée en tant que base du premier substrat et mettant en oeuvre une surface d'adhésion entre le premier substrat et le deuxième substrat susmentionnés, ou alternativement, le dispositif d'imagerie à semi-conducteurs ne contient pas de première structure de connexion.
PCT/JP2018/011569 2017-04-04 2018-03-23 Dispositif d'imagerie à semi-conducteurs et appareil électronique WO2018186196A1 (fr)

Priority Applications (2)

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US16/497,497 US11411037B2 (en) 2017-04-04 2018-03-23 Solid-state imaging device and electronic apparatus including coupling structures for electrically interconnecting stacked semiconductor substrates
US17/869,659 US11948961B2 (en) 2017-04-04 2022-07-20 Solid-state imaging device and electronic device including coupling structures for electrically interconnecting stacked semiconductor substrates

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JP2017074806 2017-04-04
JP2017-074806 2017-04-04
JP2017156586 2017-08-14
JP2017-156586 2017-08-14

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US17/869,659 Continuation US11948961B2 (en) 2017-04-04 2022-07-20 Solid-state imaging device and electronic device including coupling structures for electrically interconnecting stacked semiconductor substrates

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US11948961B2 (en) 2024-04-02
US11411037B2 (en) 2022-08-09
US20220359605A1 (en) 2022-11-10
US20200105813A1 (en) 2020-04-02

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