WO2018176968A1 - 一种具有串并联结构的包络线跟踪电源、芯片及通信终端 - Google Patents

一种具有串并联结构的包络线跟踪电源、芯片及通信终端 Download PDF

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WO2018176968A1
WO2018176968A1 PCT/CN2017/120457 CN2017120457W WO2018176968A1 WO 2018176968 A1 WO2018176968 A1 WO 2018176968A1 CN 2017120457 W CN2017120457 W CN 2017120457W WO 2018176968 A1 WO2018176968 A1 WO 2018176968A1
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Prior art keywords
pmos transistor
power supply
output
transistor
drain
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PCT/CN2017/120457
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English (en)
French (fr)
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白云芳
林升
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唯捷创芯(天津)电子技术股份有限公司
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Publication of WO2018176968A1 publication Critical patent/WO2018176968A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Definitions

  • the present invention relates to an envelope tracking power supply, and more particularly to an envelope tracking power supply for a radio frequency power amplifier having a series-parallel structure, and also relates to an integrated circuit chip including the envelope tracking power supply and corresponding communication.
  • the terminal belongs to the technical field of radio frequency integrated circuits.
  • PAPR peak-to-average power ratio
  • PAPR signals force the power amplifier to operate in a large power supply back-off state. Although this allows the power amplifier to achieve better linearity, it can result in greater power loss.
  • the power amplifier's operating efficiency is reduced.
  • one of the methods is to use a variable dynamic bias voltage. As shown in Figure 1, the power amplifier itself is used to amplify the input signal, while the RF input signal provides a bias voltage to the power amplifier through an envelope amplifier. . In this way, the power supply voltage of the power amplifier can be continuously adjusted according to the envelope of the baseband signal, which is equivalent to making the power amplifier always biased to a state close to saturation, thereby improving the working efficiency.
  • SMPS switch mode power supply
  • the existing envelope tracking power supply consists of a linear amplifier in parallel with a switching amplifier.
  • the RF input signal envelope is connected to the forward input of the linear amplifier, and its output is fed back to the inverting input through a loop with a feedback coefficient of ⁇ .
  • the switching amplifier consists of a control circuit and an output stage.
  • the output stage is connected to an inductor L.
  • the output of the amplifier is also applied to the input through a feedback loop.
  • the output signal of the linear amplifier acts as the input signal to the switching amplifier, and the input signal provides the RF power amplifier with a power supply bias that varies according to the envelope.
  • the instantaneous efficiency of the linear amplifier is proportional to the ratio of the peak output to the supply voltage. This phenomenon causes power loss in the output stage of the linear amplifier, which is also the main reason for the inefficiency of this structure.
  • the linear amplifier has a high probability of operating in the low efficiency region.
  • the method of modulating the bias of the linear amplifier by an additional switching power supply to improve its operating efficiency is effective, but the circuit is very complicated, and the introduction of additional inductance components causes a huge waste in power consumption, area, and the like.
  • the primary technical problem to be solved by the present invention is to provide an envelope tracking power supply having a series-parallel structure.
  • Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the envelope tracking power supply and a corresponding communication terminal.
  • an envelope tracking power supply having a series-parallel structure, comprising a linear modulator and a switching power supply;
  • An input end of the linear modulator is connected to an input signal envelope, and an output end is connected to a first input end of the switching power supply;
  • the second input end of the switching power supply is connected to the input signal envelope, the first output end of the switching power supply is connected to the first input end of the switching power supply, and the second output end of the switching power supply is a linear modulator Provide bias.
  • the linear modulator employs a linear amplifier
  • the forward input of the linear amplifier is connected to the input signal envelope
  • the output of the linear amplifier is fed back through a loop with a feedback coefficient of ⁇ .
  • the output of the linear amplifier is respectively connected to a radio frequency power amplifier and a first input end of the switching power supply, and the received input signal envelope is performed by the linear amplifier Amplifying and outputting a voltage corresponding to the amplitude of the envelope of the input signal.
  • the input stage of the linear amplifier adopts a folded cascode circuit
  • the folded cascode circuit is composed of a plurality of PMOS transistors and NMOS transistors stacked, wherein the fourth PMOS transistor The source is connected to the power supply voltage, the gate of the fourth PMOS transistor is connected to the first bias voltage, and the drain of the fourth PMOS transistor is respectively connected to the sources of the fifth PMOS transistor and the sixth PMOS transistor.
  • the gates of the fifth PMOS transistor and the sixth PMOS transistor are input terminals for receiving the input signal envelope, and the drains of the fifth PMOS transistors and the drains of the second NMOS transistors and the fourth a source of the NMOS transistor is connected, a drain of the sixth PMOS transistor is respectively connected to a drain of the third NMOS transistor, a source of the fifth NMOS transistor, and a source of the second NMOS transistor and the third NMOS transistor The poles are respectively grounded, the second NMOS transistor is connected to the gate of the third NMOS transistor and connected to a second bias voltage, and the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor Connected together, connected to a third bias voltage, the drains of the fourth NMOS transistors being respectively connected to the drains of the seventh PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor, a drain of the fifth NMOS transistor is coupled to a drain of the eighth PMOS transistor to form an output
  • the intermediate stage of the linear amplifier adopts a transconductance stage composed of a plurality of PMOS transistors and NMOS transistors, wherein sources of the eleventh PMOS transistor and the twelfth PMOS transistor are respectively connected to the power supply voltage a gate of the eleventh PMOS transistor is connected to an output end of the linear amplifier, a drain of the eleventh PMOS transistor is connected to a source of the thirteenth PMOS transistor, and the twelfth PMOS transistor is a gate is connected to a gate of the ninth PMOS transistor, a drain of the twelfth PMOS transistor is connected to a source of the fourteenth PMOS transistor, and a gate of the thirteenth PMOS transistor is respectively connected to the first a gate of the seventh PMOS transistor, a gate of the eighth PMOS transistor, a gate of the fourteenth PMOS transistor, a drain of the thirteenth PMOS transistor and a drain of the eighth NMOS transistor, a drain of the fourteenth PMOS transistor is connected to a drain of the sixth
  • the output stage of the linear amplifier is composed of a plurality of PMOS transistors and NMOS transistors, wherein the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, and the second The sources of the ten PMOS transistors are respectively connected to the second output end of the switching power supply, and the gates of the fifteenth PMOS transistor, the sixteenth PMOS transistor, and the seventeenth PMOS transistor are respectively connected together Connected to the drain of the fifteenth PMOS transistor and the drain of the ninth NMOS transistor, and the gate of the ninth NMOS transistor is respectively connected to the drain of the sixth NMOS transistor and the gate of the seventh NMOS transistor.
  • the sources of the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the fourteenth NMOS transistor are respectively grounded, and the tenth NMOS transistor and the eleventh NMOS transistor are gated
  • the poles are respectively connected to the gates of the eighth NMOS transistors, the drains of the tenth NMOS transistors and the drains of the sixteenth PMOS transistors, the drains of the nineteenth PMOS transistors, and the eighteenth PMOS a gate of the transistor, a gate of the twentieth PMOS transistor, a drain of the eleventh NMOS transistor and a drain of the seventeenth PMOS transistor, a drain of the thirteenth NMOS transistor, and a drain a gate of the twelfth NMOS transistor, a gate of the fourteenth NMOS transistor, and a drain of the twelfth NMOS transistor connected to a source of the thirteenth NMOS transistor, the thirteenth a gate of
  • the ninth NMOS transistor and the fifteenth PMOS transistor are configured to mirror a current outputted by a transconductance stage of the linear amplifier to the output stage of the linear amplifier and pass through a second output of the switching power supply The voltage output from the terminal supplies power to the output stage of the linear amplifier.
  • the switching power supply includes a control circuit and an output stage, and an output end of the control circuit is connected to the output stage; a first input end of the control circuit receives a voltage from the linear modulator output, And generating a control signal according to the voltage, the second input end of the control circuit receives the bandwidth-limited input signal envelope, and the control circuit controls the output stage to provide a bias voltage for the linear modulator,
  • the control circuit controls the output stage to be a low frequency power of the RF power amplifier.
  • the output stage includes an inverter and a switching stage, the inverter and the switching stage are connected in series by an inductor, and an input end of the inverter and an output end of the control circuit a connection for amplifying a control signal output by the control circuit, and outputting a current corresponding to an amplitude of the input signal envelope according to the control signal; the switch stage is implemented by the control circuit to flow through The current of the inductor is distributed to the first output and the second output.
  • the inverter is composed of a complementary form of a first PMOS transistor and a first NMOS transistor, and a gate of the first PMOS transistor is coupled with a gate of the first NMOS transistor to form the opposite An input end of the phase transistor, a drain of the first PMOS transistor and a drain of the first NMOS transistor are connected together to form an output end of the inverter, and a source of the first PMOS transistor is connected to a power supply voltage The source of the first NMOS transistor M2 is grounded.
  • the switch stage is composed of two switches connected in parallel, the switch adopting a second PMOS transistor and a third PMOS transistor, respectively, a source of the second PMOS transistor and the third PMOS transistor The source is connected to the inductor, and the gate of the second PMOS transistor and the gate of the third PMOS transistor are respectively connected to the control circuit, and the second PMOS transistor and the first A drain of the three PMOS transistor is coupled to the first output terminal and the second output terminal.
  • the first output provides low frequency power to the radio frequency power amplifier, and the switching ripple of the first output is absorbed by the linear modulator, and the second output is the linear
  • the modulator provides an envelope dependent variable for reducing power loss of the linear modulator output stage; the first output end is coupled to the second output end to be coupled to one end of an output filter, the output filter The capacitor is combined with the resistor in parallel, and the other end of the output filter is grounded.
  • the control circuit includes a first error amplifier, a second error amplifier, a first comparator, a second comparator, and a triangular wave generator, and the first error amplifier is reversed from the second error amplifier.
  • the input terminals are respectively connected to corresponding output filters, the positive input terminal of the first error amplifier receives the current output from the second output terminal, and the forward input terminal of the second error amplifier and the bandwidth limited input signal Envelope connection, the first error amplifier and the output end of the second error amplifier are connected to one input end of the first comparator and the second comparator, the first comparator, the first comparator
  • the other input end of the second comparator is respectively connected to the triangular wave generator, and the output end of the first comparator is respectively connected to the gate of the second PMOS transistor and the gate of the third PMOS transistor, the second The output of the comparator is connected to the input of the inverter.
  • an integrated circuit chip including the above-described envelope tracking power supply having a series-parallel structure.
  • a communication terminal including the above-described envelope tracking power supply having a series-parallel structure.
  • the envelope tracking power supply provided by the invention combines a linear modulator with a switching power supply, and can not only change the output voltage to track the change of the envelope of the RF input signal, but also provide a variable amplitude power supply for the RF power amplifier.
  • the voltage, and also the switching power supply modulates the bias of the linear modulator to reduce its power loss, improving the efficiency of the linear modulator and the entire envelope tracking power supply.
  • the use of high-precision switching modulators and inductors and other components is avoided, saving chip area.
  • FIG. 1 is a schematic structural diagram of an envelope modulation amplifier in the prior art
  • FIG. 2 is a schematic structural diagram of an envelope tracking power supply in the prior art
  • FIG. 3 is a schematic structural diagram of an envelope tracking power supply provided by the present invention.
  • FIG. 4 is a schematic structural diagram of a linear modulator using a class AB amplifier in an envelope tracking power supply according to the present invention
  • FIG. 5 is a schematic structural diagram of a single-inductance dual-output switching power supply in a switching power supply of the envelope tracking power supply provided by the present invention.
  • the envelope tracking power supply provided by the invention comprises a linear modulator and a switching power supply, the input end of the linear modulator is connected to the input signal envelope, the output end of the linear modulator is connected to the first input end of the switching power supply, and the switching power supply is The second input is coupled to the bandwidth limited input signal envelope, the first output of the switching power supply is coupled to the first input of the switching power supply, and the second output of the switching power supply is biased to the linear modulator.
  • the envelope tracking power supply with the series-parallel structure can not only change the output voltage tracking RF input signal envelope, but also provide a variable amplitude power supply voltage for the RF power amplifier (RF PA), and also through the switch
  • the power supply modulates the bias of the linear modulator to reduce its power loss, improving the efficiency of the linear modulator.
  • the linear modulator can use a linear amplifier.
  • the forward input of the linear amplifier is connected to the input signal envelope, and the output of the linear amplifier is fed back to its reverse through a loop with a feedback coefficient of ⁇ .
  • the output of the linear amplifier is respectively connected to the RF power amplifier and the first input of the switching power supply.
  • the switching power supply may include a control circuit and an output stage, and an output end of the control circuit is connected to the output stage.
  • the first input of the control circuit can receive the voltage from the output of the linear modulator and generate a control signal according to the output voltage, the control signal is related to the magnitude of the output voltage;
  • the second input of the control circuit can receive the bandwidth Limited input signal envelope.
  • the output stage can include an inverter and a switching stage, and the inverter and the switching stage are connected in series by an inductor L.
  • the control signal outputted by the amplification control circuit can be realized by connecting the input end of the inverter to the output end of the control circuit, and the inverter can output a current corresponding to the amplitude of the input signal envelope according to the control signal, the current It is stored by the inductor L and output through the switching stage.
  • the inverter is composed of a complementary form of the first PMOS transistor M1 ⁇ and the first NMOS transistor M2 , wherein the gate of the first PMOS transistor M1 ⁇ is connected to the gate of the first NMOS transistor M2 ⁇ to form an input end of the inverter
  • the drain of the first PMOS transistor M1 ⁇ is connected to the drain of the first NMOS transistor M2 ⁇ to form an output terminal of the inverter.
  • the source of the first PMOS transistor M1 ⁇ is connected to the power supply voltage VDD, and the source of the first NMOS transistor M2 ⁇ Ground.
  • the switching stage can be composed of two switches connected in parallel.
  • the two switches can respectively adopt the second PMOS transistor M3 ⁇ and the third PMOS transistor M4 ⁇ , and the source of the second PMOS transistor M3 ⁇ is connected to the source of the third PMOS transistor M4 ⁇ After being connected together with the inductor L; the gate of the second PMOS transistor M3 ⁇ and the gate of the third PMOS transistor M4 ⁇ are respectively connected to the control circuit, and the second PMOS transistor M3 ⁇ and the third PMOS transistor M4 ⁇ are adjusted by the control circuit to complete the current distribution To two different outputs, and in order to track the signal envelope of LTE, a fast switching between the two switches can be achieved by the control circuit.
  • the drain of the third PMOS transistor M4 is fed back to the first input of the control circuit, and the drain of the second PMOS transistor M3 is fed back to the linear modulator by the second output Vout2 of the switching power supply. Provides bias to the linear modulator to improve the efficiency of the linear modulator.
  • the output current of the switching power supply can be calculated by weighting the error signals ERR1 and ERR2.
  • the linear modulator supplies high-frequency current to the RF power amplifier and makes the current value as small as possible through the surrounding feedback structure.
  • the output of the linear modulator has a low impedance characteristic, so the switching ripple of the first output terminal Vout1 of the switching power supply can be absorbed.
  • the second output of the switching power supply, Vout2 provides an envelope dependent variable for the linear modulator, reducing the loss of power in the linear modulator output stage.
  • the following is a linear amplifier with a Class AB amplifier with three stages and with nested Miller compensation.
  • the switching power supply uses a single inductor dual output switching power supply as a typical embodiment, and the envelope provided by the present invention is combined with FIG. 4 and FIG. Line tracking power supply is described.
  • the input stage of the linear amplifier may employ a folded cascode circuit composed of a plurality of PMOS transistors and NMOS transistors.
  • the source of the fourth PMOS transistor M0 is connected to the power supply voltage VDD
  • the gate of the fourth PMOS transistor M0 is connected to the bias voltage VB1
  • the drain of the fourth PMOS transistor M0 is respectively connected to the fifth PMOS transistor M1 and the sixth PMOS.
  • the source of the transistor M2 is connected, the gates of the fifth PMOS transistor M1 and the sixth PMOS transistor M2 are input terminals (Vip and Vin), and can be used for receiving an input signal envelope; the drains of the fifth PMOS transistor M1 are respectively and the second The drain of the NMOS transistor M3 and the source of the fourth NMOS transistor M5 are connected, and the drain of the sixth PMOS transistor M2 is respectively connected to the drain of the third NMOS transistor M4 and the source of the fifth NMOS transistor M6, and the second NMOS transistor M3 and the source of the third NMOS transistor M4 are respectively grounded, the second NMOS transistor M3 is connected to the gate of the third NMOS transistor M4 and connected to the bias voltage VB2; the fourth NMOS transistor M5 and the fifth NMOS transistor M6 The gates are connected together and connected to the bias voltage VB3, and the drains of the fourth NMOS transistors M5 are respectively connected to the drains of the seventh PMOS transistor M7, the gate of the ninth PMOS
  • the fifth NMOS transistor M6 The drain is connected to the drain of the eighth PMOS transistor M8 to form an output terminal of the linear amplifier input stage; the seventh PMOS transistor M7 is connected to the gate of the eighth PMOS transistor M8, and the source of the seventh PMOS transistor M7 Connected to the drain of the ninth PMOS transistor M9, the source of the eighth PMOS transistor M8 is connected to the drain of the tenth PMOS transistor M10, and the sources of the ninth PMOS transistor M9 and the tenth PMOS transistor M1 are respectively connected to the power supply voltage VDD. connection.
  • the gain of the linear amplifier is increased by the folded cascode circuit.
  • the intermediate stage of the linear amplifier can employ a transconductance stage composed of a plurality of PMOS transistors and NMOS transistors. As shown in FIG. 4, the sources of the eleventh PMOS transistor M11 and the twelfth PMOS transistor M12 are respectively connected to the power supply voltage VDD, and the gate of the eleventh PMOS transistor M11 is connected to the output end of the linear amplifier.
  • the drain of a PMOS transistor M11 is connected to the source of the thirteenth PMOS transistor M13, the gate of the twelfth PMOS transistor M12 is connected to the gate of the ninth PMOS transistor M9, and the drain of the twelfth PMOS transistor M12 is The source of the fourteenth PMOS transistor M14 is connected; the gate of the thirteenth PMOS transistor M13 is respectively connected to the gate of the seventh PMOS transistor M7, the gate of the eighth PMOS transistor M8, and the gate of the fourteenth PMOS transistor M14.
  • the drain of the thirteenth PMOS transistor M13 is connected to the drain of the eighth NMOS transistor M16, the drain of the fourteenth PMOS transistor M14 is connected to the drain of the sixth NMOS transistor M15, and the gate of the sixth NMOS transistor M15 is biased
  • the voltage VB5 is connected, the source of the sixth NMOS transistor M15 is connected to the drain of the seventh NMOS transistor M17, and the sources of the seventh NMOS transistor M17 and the eighth NMOS transistor M16 are grounded.
  • the voltage output from the input stage of the linear amplifier can be converted to current by the transconductance stage.
  • the output stage of the linear amplifier can be composed of a plurality of PMOS transistors and NMOS transistors. As shown in FIG. 4, the sources of the fifteenth PMOS transistor M19, the sixteenth PMOS transistor M20, the seventeenth PMOS transistor M23, the eighteenth PMOS transistor M24, and the twentieth PMOS transistor PM1 are respectively connected to the switching power supply.
  • the second output terminal Vout2 is connected, and the gates of the fifteenth PMOS transistor M19, the sixteenth PMOS transistor M20, and the seventeenth PMOS transistor M23 are connected together and are respectively connected to the drain of the fifteenth PMOS transistor M19 and the ninth NMOS transistor.
  • the drain of the M18 is connected, and the gate of the ninth NMOS transistor M18 is respectively connected to the drain of the sixth NMOS transistor M15 and the gate of the seventh NMOS transistor M17, and the ninth NMOS transistor M18, the tenth NMOS transistor M21, and the eleventh
  • the sources of the NMOS transistor M22, the twelfth NMOS transistor M27, and the fourteenth NMOS transistor PM2 are respectively grounded;
  • the gates of the tenth NMOS transistor M21 and the eleventh NMOS transistor M22 are respectively connected to the gate of the eighth NMOS transistor M16,
  • the drain of the tenth NMOS transistor M21 is respectively connected to the drain of the sixteenth PMOS transistor M20, the drain of the nineteenth PMOS transistor M25, the gate of the eighteenth PMOS transistor M24, and the gate of the twentieth PMOS transistor PM1.
  • eleventh N a drain of the MOS transistor M22 is connected to a drain of the seventeenth PMOS transistor M23, a drain of the thirteenth NMOS transistor M26, a gate of the twelfth NMOS transistor M27, and a gate of the fourteenth NMOS transistor PM2;
  • the drain of the twelve NMOS transistor M27 is connected to the source of the thirteenth NMOS transistor M26, the gate of the thirteenth NMOS transistor M26 is connected to the bias voltage VB6;
  • the drain of the transistor M24 is connected, the gate of the nineteenth PMOS transistor M25 is connected to the bias voltage VB7, and the drain of the twentieth PMOS transistor PM1 is connected to the drain of the fourteenth NMOS transistor PM2.
  • the current output from the transconductance stage of the linear amplifier can be mirrored to the output stage of the linear amplifier through the ninth NMOS transistor M18 and the fifteenth PMOS transistor M19, and the output voltage of the linear amplifier is output through the second output terminal Vout2 of the switching power supply. Power is supplied.
  • the linear amplifier When the supply voltage VDD reaches VT+2VDSsat, the linear amplifier still operates in the saturation region, where VT is the threshold voltage of the transistor and VDSsat is the minimum drain-source voltage of the transistor.
  • the linear amplifier can adjust the gain bandwidth of the linear amplifier by serially connecting the compensation capacitor Cc with the output terminal of the linear amplifier input stage, and through the parasitic capacitance of the output element twentieth PMOS transistor PM1 and the fourteenth NMOS transistor PM2. Compensate the output stage of the linear amplifier.
  • the linear amplifier not only achieves high gain, but also adjusts the gain bandwidth, provides a variable amplitude supply voltage for the RF power amplifier, and also modulates the linear modulator bias through a switching power supply to reduce its power loss. Achieve improved linear modulator efficiency.
  • the single-inductance dual-output switching power supply is also composed of a control circuit and an output stage, and the output end of the control circuit is connected to the output stage.
  • the control circuit may include a first error amplifier AMP1, a second error amplifier AMP2, a first comparator CMP1, a second comparator CMP2, and a triangular wave generator.
  • the output stage can include an inverter and a switching stage, and the inverter and the switching stage are connected in series by an inductor L.
  • the inverter is composed of a complementary form of the first PMOS transistor M1 ⁇ and the first NMOS transistor M2 ,, and the connection relationship is the same as that described above, and details are not described herein again.
  • the switching stage includes two switching and output filters, each of which is connected to a corresponding output filter to achieve a stable output voltage.
  • the two PMOS transistors M3 ⁇ and the third PMOS transistor M4 ⁇ can be respectively used, and the source of the second PMOS transistor M3 ⁇ is connected to the source of the third PMOS transistor M4 ⁇ and then connected to the inductor L; the second PMOS transistor M3 ⁇
  • the gates of the gate and the third PMOS transistor M4 ⁇ are respectively connected to the output end of the first comparator CMP1, the drain of the third PMOS transistor M4 ⁇ is the first output terminal Vout1 of the switching power supply, and the drain of the second PMOS transistor M3 ⁇ is the switching power supply.
  • the output filter is composed of a capacitor and a resistor connected in parallel. One end of the output filter is respectively connected with the first output terminal Vout1 and the second output terminal Vout2, and the other end of the output filter is grounded, and is received by the output filter respectively.
  • the current outputted by the output terminal Vout1 and the second output terminal Vout2 is filtered and outputted as a voltage.
  • the bandwidth-limited input signal envelope is connected to the forward input terminal of the second error amplifier AMP2, and the reverse of the first error amplifier AMP1 and the second error amplifier AMP2
  • the input ends are respectively connected to the corresponding output filters, and the forward input end of the first error amplifier AMP1 receives the current output from the second output terminal Vout2, and the output ends of the first error amplifier AMP1 and the second error amplifier AMP2 correspond to the first One input end of the comparator CMP1 and the second comparator CMP2 are connected, and the other input ends of the first comparator CMP1 and the second comparator CMP2 are respectively connected to the triangular wave generator, and the output ends of the first comparator CMP1 are respectively connected with the second
  • the gate of the PMOS transistor M3 is connected to the gate of the third PMOS transistor M4, and the output of the second comparator CMP2 is connected to the input of the inverter.
  • Two pulse width modulation (PWM) signals (S1 and S2) are generated by the first error amplifier AMP1, the second error amplifier AMP2, the first comparator CMP1, the second comparator CMP2, and the triangular wave generator, and the pulse width modulation signal S1
  • the amplification by the inverter, the pulse width modulation signal S2 and the reverse signal S2b of the pulse width modulation signal S2 correspondingly control the second PMOS transistor M3 ⁇ switch and the third PMOS transistor M4 ⁇ switch are in an on or off state, and according to the error signal
  • the ERR1 and ERR2 weighted calculations distribute the inductor current to both outputs.
  • the first output terminal Vout1 supplies current to the RF power amplifier
  • the second output terminal Vout2 is used to drive the output stage of the linear amplifier
  • the two feedback loops drawn from the output of the switching power supply regulate the behavior of the switching power supply.
  • the envelope tracking power supply provided by the present invention is preferably implemented in a 14 nm HV process and can provide accurate envelope tracking under a 20 MHz LTE envelope signal with a peak output power of 30.5 dBm.
  • the envelope tracking power supply provided by the present invention combines a linear modulator with a switching power supply to not only change the output voltage to track changes in the envelope of the RF input signal, but also provides a variable amplitude for the RF power amplifier.
  • the supply voltage, and also the switching power supply to modulate the bias of the linear modulator to reduce its power loss improves the efficiency of the linear modulator and the entire envelope tracking power supply. At the same time, it also avoids the use of high-precision components such as switching modulators and inductors, saving chip area.
  • the envelope tracking power supply provided by the present invention can be used in an integrated circuit chip (e.g., a radio frequency front end chip).
  • an integrated circuit chip e.g., a radio frequency front end chip.
  • the specific structure of the RF power amplifier in the RF front-end chip will not be detailed here.
  • the above-described envelope tracking power supply having a series-parallel structure can also be used in a communication terminal as an important component of the radio frequency circuit.
  • the term "communication terminal” as used herein refers to a computer device that can be used in a mobile environment and supports various communication systems such as GSM, EDGE, TD_SCDMA, TDD_LTE, and FDD_LTE, including mobile phones, notebook computers, tablet computers, and on-board computers.
  • the technical solution provided by the present invention is also applicable to other RF circuit applications, such as a communication base station.

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Abstract

一种具有串并联结构的包络线跟踪电源、芯片及通信终端。该包络线跟踪电源包括线性调制器和开关电源，其中线性调制器的输入端与输入信号包络连接，线性调制器的输出端与开关电源的第一输入端连接，开关电源的第二输入端与带宽限制的输入信号包络连接，开关电源的第一输出端与开关电源的第一输入端连接，开关电源的第二输出端为线性调制器提供偏置。该包络线跟踪电源通过将线性调制器与开关电源组合在一起，不仅为射频功率放大器提供可变幅值的电源电压，而且还通过开关电源来调制线性调制器的偏置以减小其功率损耗，提高了线性调制器及整个包络线跟踪电源的工作效率。

Description

一种具有串并联结构的包络线跟踪电源、芯片及通信终端 技术领域
本发明涉及一种包络线跟踪电源，尤其涉及一种用于射频功率放大器、具有串并联结构的包络线跟踪电源，同时也涉及包括该包络线跟踪电源的集成电路芯片及相应的通信终端，属于射频集成电路技术领域。
背景技术
随着移动宽带技术的日益发展，对无线传输的数据速率提出了更高的要求，然而实际用于传输的频谱资源却是有限的。所以，4G以及更高级的通信服务应运而生，这些新型通信技术的一个重要特点就是采用更高的峰值平均功率比(PAPR)来发送信号。
对于传统的功率放大器(PA)而言，高PAPR信号会迫使功率放大器工作在大电源功率回退状态，虽然这样能使功率放大器实现较好的线性度，但会导致较大的功率损耗，使功率放大器的工作效率降低。为了解决这个问题，其中一种方法是采用可变的动态偏置电压，如图1所示,功率放大器本身用于放大输入信号，同时射频输入信号通过一个包络放大器为功率放大器提供偏置电压。通过这种方法，能够根据基带信号的包络连续调整功率放大器的电源电压，相当于使功率放大器一直偏置在接近饱和的状态，提高了其工作效率。如果需要处理的是一个宽带信号，那么就需要一个高效率的开关模式电源(SMPS)以提供大部分在直流偏置附近的功率。与此同时，还需要一个高带宽、低效率的线性稳压器提供较远端频率点的剩余功率。
另一种方法是通过包络跟踪电源提高功率放大器的效率。如图2所示，现有的包络跟踪电源由一个线性放大器与一个开关放大器并联构成。射频输入信号包络连接到线性放大器的正向输入端，其输出端通过一个反馈系数为β的环路反馈回到反向输入端。开关放大器由控制电路和输出级构成，输出级连接一个电感L，放大器的输出同样通过一个反馈环路作用于输入端。线性放大器的输出信号作为开关放大器的输入信号，同时该输入信号为射频功率放大器提供根据包络变化 的电源偏置。在这种结构中，线性放大器的瞬时效率与峰值输出和电源电压的比例成正比。这个现象引起了线性放大器输出级的功率损耗，也是这种结构效率低下的主要原因。
如果LTE信号具有高峰值平均功率比和功率谱密度，那么线性放大器有很大可能性工作在低效率区。通过额外增加的开关电源来调制线性放大器的偏置以提高其工作效率的方法虽然有效，但是其电路非常复杂，而且引入了额外的电感元件，在功耗、面积等方面造成了巨大的浪费。
发明内容
本发明所要解决的首要技术问题在于提供一种具有串并联结构的包络线跟踪电源。
本发明所要解决的另一技术问题在于提供一种包括该包络线跟踪电源的集成电路芯片及相应的通信终端。
为了实现上述发明目的，本发明采用下述的技术方案：
根据本发明实施例的第一方面，提供一种具有串并联结构的包络线跟踪电源，包括线性调制器和开关电源；
所述线性调制器的输入端与输入信号包络连接，输出端与所述开关电源的第一输入端连接；
所述开关电源的第二输入端与输入信号包络连接，所述开关电源的第一输出端与所述开关电源的第一输入端连接，所述开关电源的第二输出端为线性调制器提供偏置。
其中较优地，所述线性调制器采用线性放大器，所述线性放大器的正向输入端与所述输入信号包络连接，所述线性放大器的输出端通过一个反馈系数为β的环路反馈回到所述线性放大器的反向输入端，所述线性放大器的输出端分别与射频功率放大器以及所述开关电源的第一输入端连接，通过所述线性放大器对接收的所述输入信号包络进行放大，并输出与所述输入信号包络的幅值相应的电压。
其中较优地，所述线性放大器的输入级采用折叠式共源共栅电路，所述折叠式共源共栅电路由多个PMOS晶体管与NMOS晶体管叠连在一起组成，其中，第四PMOS晶体管的源极与电源电压连接，所述第四PMOS晶体管的栅极与第一偏置电压连接，所述第四PMOS晶体管的漏 极分别与第五PMOS晶体管、第六PMOS晶体管的源极连接，所述第五PMOS晶体管与所述第六PMOS晶体管的栅极为输入端，用于接收所述输入信号包络，所述第五PMOS晶体管的漏极分别与第二NMOS晶体管的漏极、第四NMOS晶体管的源极连接，所述第六PMOS晶体管的漏极分别与第三NMOS晶体管的漏极、第五NMOS晶体管的源极连接，所述第二NMOS晶体管与所述第三NMOS晶体管的源极分别接地，所述第二NMOS晶体管与所述第三NMOS晶体管的栅极连接在一起后与第二偏置电压连接，所述第四NMOS晶体管与所述第五NMOS晶体管的栅极连接在一起后与第三偏置电压连接，所述第四NMOS晶体管的漏极分别与第七PMOS晶体管的漏极、第九PMOS晶体管的栅极、第十PMOS晶体管的栅极连接，所述第五NMOS晶体管的漏极与第八PMOS晶体管的漏极连接在一起组成所述线性放大器输入级的输出端，所述第七PMOS晶体管与所述第八PMOS晶体管的栅极连接在一起，所述第七PMOS晶体管的源极与所述第九PMOS晶体管的漏极连接，所述第八PMOS晶体管的源极与所述第十PMOS晶体管的漏极连接，所述第九PMOS晶体管与第十PMOS晶体管的源极分别与所述电源电压连接。
其中较优地，所述线性放大器的中间级采用由多个PMOS晶体管与NMOS晶体管组成的跨导级，其中，第十一PMOS晶体管与第十二PMOS晶体管的源极分别与所述电源电压连接，所述第十一PMOS晶体管的栅极与所述线性放大器的输出端连接，所述第十一PMOS晶体管的漏极与第十三PMOS晶体管的源极连接，所述第十二PMOS晶体管的栅极与所述第九PMOS晶体管的栅极连接，所述第十二PMOS晶体管的漏极与第十四PMOS晶体管的源极连接，所述第十三PMOS晶体管的栅极分别与所述第七PMOS晶体管的栅极、所述第八PMOS晶体管的栅极、所述第十四PMOS晶体管的栅极连接，所述第十三PMOS晶体管的漏极与第八NMOS晶体管的漏极，所述第十四PMOS晶体管的漏极与第六NMOS晶体管的漏极连接，所述第六NMOS晶体管的栅极与第四偏置电压连接，所述第六NMOS晶体管的源极与第七NMOS晶体管的漏极连接，所述第七NMOS晶体管与所述第八NMOS晶体管的源极接地。
其中较优地，所述线性放大器的输出级由多个PMOS晶体管与NMOS晶体管组成，其中，第十五PMOS晶体管、第十六PMOS晶体管、第十 七PMOS晶体管、第十八PMOS晶体管、第二十PMOS晶体管的源极分别与所述开关电源的第二输出端连接，所述第十五PMOS晶体管、所述第十六PMOS晶体管、所述第十七PMOS晶体管的栅极连接在一起后分别与所述第十五PMOS晶体管的漏极、第九NMOS晶体管的漏极连接，所述第九NMOS晶体管的栅极分别与第六NMOS晶体管的漏极、第七NMOS晶体管的栅极连接，所述第九NMOS晶体管、第十NMOS晶体管、第十一NMOS晶体管、第十二NMOS晶体管、第十四NMOS晶体管的源极分别接地，所述第十NMOS晶体管、所述第十一NMOS晶体管的栅极分别与第八NMOS晶体管的栅极连接，所述第十NMOS晶体管的漏极分别与所述第十六PMOS晶体管的漏极、第十九PMOS晶体管的漏极、所述第十八PMOS晶体管的栅极、所述第二十PMOS晶体管的栅极连接，所述第十一NMOS晶体管的漏极分别与所述第十七PMOS晶体管的漏极、第十三NMOS晶体管的漏极、所述第十二NMOS晶体管的栅极、所述第十四NMOS晶体管的栅极连接，所述第十二NMOS晶体管的漏极与所述第十三NMOS晶体管的源极连接，所述第十三NMOS晶体管的栅极与第五偏置电压连接，所述第十九PMOS晶体管的源极与所述第十八PMOS晶体管的漏极连接，所述第十九PMOS晶体管的栅极与第六偏置电压连接，所述第二十PMOS晶体管的漏极与所述第十四NMOS晶体管的漏极连接；
所述第九NMOS晶体管、所述第十五PMOS晶体管用于将所述线性放大器的跨导级输出的电流镜像到所述线性放大器的所述输出级，并通过所述开关电源的第二输出端输出的电压为所述线性放大器的输出级进行供电。
其中较优地，所述开关电源包括控制电路与输出级，所述控制电路的输出端与所述输出级连接；所述控制电路的第一输入端接收来自所述线性调制器输出的电压，并根据所述电压产生控制信号，所述控制电路的第二输入端接收所述带宽限制的输入信号包络，所述控制电路控制所述输出级为所述线性调制器提供偏置电压，所述控制电路控制所述输出级为射频功率放大器低频功率。
其中较优地，所述输出级包括反相器与开关级，所述反相器与所述开关级通过电感串接在一起，所述反相器的输入端与所述控制电路的输出端连接，用于实现放大所述控制电路输出的控制信号，并根据 所述控制信号输出与所述输入信号包络的幅值相应的电流；所述开关级通过所述控制电路实现将流过所述电感的电流分配给第一输出端与第二输出端。
其中较优地，所述反相器由第一PMOS晶体管与第一NMOS晶体管二者互补形式组成，所述第一PMOS晶体管的栅极与第一NMOS晶体管的栅极连接在一起组成所述反相器的输入端，所述第一PMOS晶体管的漏极与所述第一NMOS晶体管的漏极连接在一起组成所述反相器的输出端，所述第一PMOS晶体管的源极接电源电压，所述第一NMOS晶体管M2的源极接地。
其中较优地，所述开关级由两个并联在一起的开关组成，所述开关分别采用第二PMOS晶体管和第三PMOS晶体管，所述第二PMOS晶体管的源极与所述第三PMOS晶体管的源极连接在一起后与所述电感连接，所述第二PMOS晶体管的栅极与所述第三PMOS晶体管的栅极分别与所述控制电路连接，所述第二PMOS晶体管与所述第三PMOS晶体管的漏极对应与所述第一输出端与所述第二输出端连接。
其中较优地，所述第一输出端将低频功率提供给所述射频功率放大器，并通过所述线性调制器吸收所述第一输出端的开关纹波，所述第二输出端为所述线性调制器提供一个包络因变量，用于减少所述线性调制器输出级的功率损失；所述第一输出端与所述第二输出端对应与输出滤波器的一端连接，所述输出滤波器由电容与电阻并联组成，所述输出滤波器的另一端接地。
其中较优地，所述控制电路包括第一误差放大器、第二误差放大器、第一比较器、第二比较器以及三角波发生器，所述第一误差放大器与所述第二误差放大器的反向输入端分别与对应输出滤波器连接，所述第一误差放大器的正向输入端接收来自第二输出端输出的电流，所述第二误差放大器的正向输入端与所述带宽限制的输入信号包络连接，所述第一误差放大器与所述第二误差放大器的输出端对应与所述第一比较器、所述第二比较器的一个输入端连接，所述第一比较器、所述第二比较器的另一个输入端分别与所述三角波发生器连接，所述第一比较器的输出端分别与第二PMOS晶体管的栅极与第三PMOS晶体管的栅极连接，所述第二比较器的输出端与反相器的输入端连接。
根据本发明实施例的第二方面，提供一种集成电路芯片，其中包括有上述具有串并联结构的包络线跟踪电源。
根据本发明实施例的第三方面，提供一种通信终端，其中包括有上述具有串并联结构的包络线跟踪电源。
本发明所提供的包络线跟踪电源通过将线性调制器与开关电源组合在一起，不仅能够使输出的电压跟踪射频输入信号包络的变化而变化，为射频功率放大器提供可变幅值的电源电压，而且还通过开关电源来调制线性调制器的偏置以减小其功率损耗，提高线性调制器及整个包络线跟踪电源的工作效率。同时，还避免了使用高精度的开关调制器和电感等元件，节约了芯片面积。
附图说明
图1为现有技术中的包络调制放大器的结构示意图；
图2为现有技术中的包络跟踪电源的结构示意图；
图3为本发明所提供的包络线跟踪电源的结构示意图；
图4为本发明所提供的包络线跟踪电源中，线性调制器采用AB类放大器的结构示意图；
图5为本发明所提供的包络线跟踪电源中，开关电源采用单电感双输出开关电源的结构示意图。
具体实施方式
下面结合附图和具体实施例对本发明的技术内容做进一步的详细说明。
本发明所提供的包络线跟踪电源包括线性调制器和开关电源，线性调制器的输入端与输入信号包络连接，线性调制器的输出端与开关电源的第一输入端连接，开关电源的第二输入端与带宽限制的输入信号包络连接，开关电源的第一输出端与开关电源的第一输入端连接，开关电源的第二输出端为线性调制器提供偏置。通过本具有串并联结构的包络线跟踪电源不仅能够实现输出的电压跟踪射频输入信号包络的变化而变化，为射频功率放大器(RF PA)提供可变幅值的电源电压，而且还通过开关电源来调制线性调制器的偏置以减小其功率损耗，实现提高线性调制器的工作效率。
其中，如图3所示，线性调制器可以采用线性放大器，线性放大 器的正向输入端与输入信号包络连接，线性放大器的输出端通过一个反馈系数为β的环路反馈回到其反向输入端，线性放大器的输出端分别与射频功率放大器以及开关电源的第一输入端连接。通过线性放大器对接收的输入信号包络进行放大，并输出与输入信号包络的幅值相应的电压，该输出的电压与输入信号包络的幅值之间呈线性变化，即，当输入信号包络的幅值增大时，线性放大器输出的电压值也随之增大；当输入信号包络的幅值减小时，线性放大器输出的电压值也随之减小。线性放大器输出的电压将分别提供给射频功率放大器作为其电源电压。线性放大器的效率可以表示为：
Figure PCTCN2017120457-appb-000001
由公式(1)可以得出：线性放大器的效率在输出电压较低时会急剧下降，为了尽量减少功率损耗，线性放大器的输出需要密切跟踪其电源电压。
在本发明所提供的包络线跟踪电源中，如图3所示，开关电源可以包括控制电路、输出级，控制电路的输出端与输出级连接。其中，控制电路的第一输入端可以接收来自线性调制器输出的电压，并根据该输出的电压产生控制信号，控制信号与该输出的电压的大小有关；控制电路的第二输入端可以接收带宽限制的输入信号包络。输出级可以包括反相器与开关级，反相器与开关级通过电感L串接在一起。通过将反相器的输入端与控制电路的输出端连接，可以实现放大控制电路输出的控制信号，并且反相器可以根据该控制信号输出与输入信号包络的幅值相应的电流，该电流通过电感L进行储存，并通过开关级进行输出。反相器由第一PMOS晶体管M1ˊ与第一NMOS晶体管M2ˊ二者互补形式组成，其中，第一PMOS晶体管M1ˊ的栅极与第一NMOS晶体管M2ˊ的栅极连接在一起组成反相器的输入端，第一PMOS晶体管M1ˊ的漏极与第一NMOS晶体管M2ˊ的漏极连接在一起组成反相器的输出端，第一PMOS晶体管M1ˊ的源极接电源电压VDD，第一NMOS晶体管M2ˊ的源极接地。开关级可以由两个并联在一起的开关组成，两个开关可以分别采用第二PMOS晶体管M3ˊ和第三PMOS晶体管M4ˊ，第二PMOS晶体管M3ˊ的源极与第三PMOS晶体管M4ˊ的源极连接在一 起后与电感L连接；第二PMOS晶体管M3ˊ的栅极与第三PMOS晶体管M4ˊ的栅极分别与控制电路连接，通过控制电路调节第二PMOS晶体管M3ˊ与第三PMOS晶体管M4ˊ，完成将电流分配到两个不同的输出端，并且，为了跟踪LTE的信号包络，可以通过控制电路实现两个开关之间的快速切换。第三PMOS晶体管M4ˊ的漏极为开关电源的第一输出端Vout1反馈回到控制电路的第一输入端，第二PMOS晶体管M3ˊ的漏极为开关电源的第二输出端Vout2反馈给线性调制器，用于给线性调制器提供偏置，提高线性调制器的工作效率。开关电源的输出电流可以根据误差信号ERR1和ERR2加权计算得到。
开关电源大部分的低频功率通过开关电源的第一输出端Vout1提供给射频功率放大器，并通过检测流出线性调制器的电流实现对功率的调节。线性调制器为射频功率放大器提供高频电流，并通过周边的反馈结构使电流值尽可能地小。此外，线性调制器的输出具有低阻抗的特性，所以开关电源的第一输出端Vout1的开关纹波能够被吸收掉。开关电源的第二输出端Vout2为线性调制器提供了一个包络因变量，减少了线性调制器输出级的功率的损失。
下面以线性放大器采用一个具有三级并带有嵌套密勒补偿的AB类放大器，开关电源采用单电感双输出开关电源为典型实施例，并结合图4和图5对本发明所提供的包络线跟踪电源进行说明。
如图4所示，线性放大器的输入级可以采用折叠式共源共栅电路，该折叠式共源共栅电路由多个PMOS晶体管与NMOS晶体管组成。其中，第四PMOS晶体管M0的源极与电源电压VDD连接，第四PMOS晶体管M0的栅极与偏置电压VB1连接，第四PMOS晶体管M0的漏极分别与第五PMOS晶体管M1、第六PMOS晶体管M2的源极连接，第五PMOS晶体管M1与第六PMOS晶体管M2的栅极为输入端(Vip与Vin)，可以用于接收输入信号包络；第五PMOS晶体管M1的漏极分别与第二NMOS晶体管M3的漏极、第四NMOS晶体管M5的源极连接，第六PMOS晶体管M2的漏极分别与第三NMOS晶体管M4的漏极、第五NMOS晶体管M6的源极连接，第二NMOS晶体管M3与第三NMOS晶体管M4的源极分别接地，第二NMOS晶体管M3与第三NMOS晶体管M4的栅极连接在一起后与偏置电压VB2连接；第四NMOS晶体管M5与第五NMOS晶体管M6的栅极 连接在一起后与偏置电压VB3连接，第四NMOS晶体管M5的漏极分别与第七PMOS晶体管M7的漏极、第九PMOS晶体管M9的栅极、第十PMOS晶体管M10的栅极连接，第五NMOS晶体管M6的漏极与第八PMOS晶体管M8的漏极连接在一起组成线性放大器输入级的输出端；第七PMOS晶体管M7与第八PMOS晶体管M8的栅极连接在一起，第七PMOS晶体管M7的源极与第九PMOS晶体管M9的漏极连接，第八PMOS晶体管M8的源极与第十PMOS晶体管M10的的漏极连接，第九PMOS晶体管M9与第十PMOS晶体管M1的源极分别与电源电压VDD连接。通过该折叠式共源共栅电路提高线性放大器的增益。
线性放大器的中间级可以采用由多个PMOS晶体管与NMOS晶体管组成的跨导级。其中，如图4所示，第十一PMOS晶体管M11与第十二PMOS晶体管M12的源极分别与电源电压VDD连接，第十一PMOS晶体管M11的栅极与线性放大器的输出端连接，第十一PMOS晶体管M11的漏极与第十三PMOS晶体管M13的源极连接，第十二PMOS晶体管M12的栅极与第九PMOS晶体管M9的栅极连接，第十二PMOS晶体管M12的漏极与第十四PMOS晶体管M14的源极连接；第十三PMOS晶体管M13的栅极分别与第七PMOS晶体管M7的栅极、第八PMOS晶体管M8的栅极、第十四PMOS晶体管M14的栅极连接，第十三PMOS晶体管M13的漏极与第八NMOS晶体管M16的漏极，第十四PMOS晶体管M14的漏极与第六NMOS晶体管M15的漏极连接；第六NMOS晶体管M15的栅极与偏置电压VB5连接，第六NMOS晶体管M15的源极与第七NMOS晶体管M17的漏极连接；第七NMOS晶体管M17与第八NMOS晶体管M16的源极接地。通过该跨导级可以实现将线性放大器的输入级输出的电压转换成电流。
线性放大器的输出级可以采用由多个PMOS晶体管与NMOS晶体管组成。其中，如图4所示，第十五PMOS晶体管M19、第十六PMOS晶体管M20、第十七PMOS晶体管M23、第十八PMOS晶体管M24、第二十PMOS晶体管PM1的源极分别与开关电源的第二输出端Vout2连接，第十五PMOS晶体管M19、第十六PMOS晶体管M20、第十七PMOS晶体管M23的栅极连接在一起后分别与第十五PMOS晶体管M19的漏极、第九NMOS晶体管M18的漏极连接，第九NMOS晶体管M18的栅极分别与第 六NMOS晶体管M15的漏极、第七NMOS晶体管M17的栅极连接，第九NMOS晶体管M18、第十NMOS晶体管M21、第十一NMOS晶体管M22、第十二NMOS晶体管M27、第十四NMOS晶体管PM2的源极分别接地；第十NMOS晶体管M21、第十一NMOS晶体管M22的栅极分别与第八NMOS晶体管M16的栅极连接，第十NMOS晶体管M21的漏极分别与第十六PMOS晶体管M20的漏极、第十九PMOS晶体管M25的漏极、第十八PMOS晶体管M24的栅极、第二十PMOS晶体管PM1的栅极连接；第十一NMOS晶体管M22的漏极分别与第十七PMOS晶体管M23的漏极、第十三NMOS晶体管M26的漏极、第十二NMOS晶体管M27的栅极、第十四NMOS晶体管PM2的栅极连接；第十二NMOS晶体管M27的漏极与第十三NMOS晶体管M26的源极连接，第十三NMOS晶体管M26的栅极与偏置电压VB6连接；第十九PMOS晶体管M25的源极与第十八PMOS晶体管M24的漏极连接，第十九PMOS晶体管M25的栅极与偏置电压VB7连接；第二十PMOS晶体管PM1的漏极与第十四NMOS晶体管PM2的漏极连接。通过第九NMOS晶体管M18、第十五PMOS晶体管M19可以将线性放大器的跨导级输出的电流镜像到线性放大器的输出级，通过开关电源的第二输出端Vout2输出的电压为线性放大器的输出级进行供电。
当电源电压VDD达到VT+2VDSsat电压时，线性放大器仍然工作在饱和区，其中VT是晶体管的阈值电压，VDSsat是晶体管的最小漏源电压。线性放大器通过将补偿电容Cc与线性放大器输入级的输出端串接在一起，可以实现调整线性放大器的增益带宽，并通过输出元件第二十PMOS晶体管PM1和第十四NMOS晶体管PM2的寄生电容来对线性放大器的输出级进行补偿。通过该线性放大器不仅能够实现高增益，还能实现调整增益带宽，为射频功率放大器提供可变幅值的电源电压，同时还通过开关电源来调制线性调制器的偏置以减小其功率损耗，实现提高线性调制器的工作效率。
单电感双输出开关电源也是由控制电路与输出级组成，控制电路的输出端与输出级连接。如图5所示，控制电路可以包括第一误差放大器AMP1、第二误差放大器AMP2、第一比较器CMP1、第二比较器CMP2以及三角波发生器。输出级可以包括反相器与开关级，反相器与开关级通过电感L串接在一起。其中，反相器由第一PMOS晶体管M1ˊ与 第一NMOS晶体管M2ˊ二者互补形式组成，其连接关系同上所述，在此不再赘述。开关级包括两个开关与输出滤波器，每一个开关与对应的输出滤波器连接，实现输出稳定的电压。两个开关可以分别采用第二PMOS晶体管M3ˊ和第三PMOS晶体管M4ˊ，第二PMOS晶体管M3ˊ的源极与第三PMOS晶体管M4ˊ的源极连接在一起后与电感L连接；第二PMOS晶体管M3ˊ的栅极与第三PMOS晶体管M4ˊ的栅极分别与第一比较器CMP1的输出端连接，第三PMOS晶体管M4ˊ的漏极为开关电源的第一输出端Vout1，第二PMOS晶体管M3ˊ的漏极为开关电源的第二输出端Vout2。输出滤波器由电容与电阻并联在一起组成的，输出滤波器的一端分别与第一输出端Vout1、第二输出端Vout2连接，输出滤波器的另一端接地，通过输出滤波器分别接收来自第一输出端Vout1、第二输出端Vout2输出的电流，并对该电流进行滤波并以电压形式进行输出。
单电感双输出开关电源各部分之间的连接关系描述如下：带宽限制的输入信号包络与第二误差放大器AMP2的正向输入端连接，第一误差放大器AMP1与第二误差放大器AMP2的反向输入端分别与对应的输出滤波器连接，第一误差放大器AMP1的正向输入端接收来自第二输出端Vout2输出的电流，第一误差放大器AMP1与第二误差放大器AMP2的输出端对应与第一比较器CMP1、第二比较器CMP2的一个输入端连接，第一比较器CMP1、第二比较器CMP2的另一个输入端分别与三角波发生器连接，第一比较器CMP1的输出端分别与第二PMOS晶体管M3ˊ的栅极与第三PMOS晶体管M4ˊ的栅极连接，第二比较器CMP2的输出端与反相器的输入端连接。由第一误差放大器AMP1、第二误差放大器AMP2、第一比较器CMP1、第二比较器CMP2以及三角波发生器共同产生两个脉冲宽度调制(PWM)信号(S1和S2)，脉冲宽度调制信号S1通过反相器进行放大，脉冲宽度调制信号S2以及脉冲宽度调制信号S2的反向信号S2b对应控制第二PMOS晶体管M3ˊ开关和第三PMOS晶体管M4ˊ开关处于导通或关断状态，并根据误差信号ERR1和ERR2加权后的计算结果分配电感电流到两个输出端。第一输出端Vout1为射频功率放大器提供电流，第二输出端Vout2用于驱动线性放大器的输出级，并通过开关电源的输出端引出的两路反馈环路对开关电源的 行为起调节作用。
需要强调的是，本发明所提供的包络线跟踪电源优选在14nm HV工艺下实现，并能够提供20MHz LTE包络信号下的精确包络跟踪，其峰值输出功率达到30.5dBm。
本发明所提供的包络线跟踪电源通过将线性调制器与开关电源组合在一起，不仅能够使输出的电压跟踪射频输入信号包络的变化而变化，为射频功率放大器提供了可变幅值的电源电压，而且还通过开关电源来调制线性调制器的偏置以减小其功率损耗，提高了线性调制器及整个包络线跟踪电源的工作效率。同时，还避免使用高精度的开关调制器和电感等元件，节约了芯片面积。
本发明所提供的包络线跟踪电源可以被用在集成电路芯片(例如射频前端芯片)中。对于该射频前端芯片中的射频功率放大器的具体结构，在此就不再一一详述了。
另外，上述具有串并联结构的包络线跟踪电源还可以被用在通信终端中，作为射频电路的重要组成部分。这里所说的通信终端是指可以在移动环境中使用，支持GSM、EDGE、TD_SCDMA、TDD_LTE、FDD_LTE等多种通信制式的计算机设备，包括移动电话、笔记本电脑、平板电脑、车载电脑等。此外，本发明所提供的技术方案也适用于其他射频电路应用的场合，例如通信基站等。
以上对本发明所提供的包络线跟踪电源、芯片及通信终端进行了详细的说明。对本领域的一般技术人员而言，在不背离本发明实质精神的前提下对它所做的任何显而易见的改动，都将属于本发明专利权的保护范围。

Claims (13)

  1. 一种具有串并联结构的包络线跟踪电源，其特征在于包括线性调制器和开关电源；
    所述线性调制器的输入端与输入信号包络连接，输出端与所述开关电源的第一输入端连接；
    所述开关电源的第二输入端与输入信号包络连接，所述开关电源的第一输出端与所述开关电源的第一输入端连接，所述开关电源的第二输出端为线性调制器提供偏置。
  2. 如权利要求1所述的包络线跟踪电源，其特征在于：
    所述线性调制器采用线性放大器；所述线性放大器的正向输入端与所述输入信号包络连接，所述线性放大器的输出端通过一个环路反馈回到所述线性放大器的反向输入端，所述线性放大器的输出端分别与射频功率放大器以及所述开关电源的第一输入端连接，通过所述线性放大器对接收的所述输入信号包络进行放大，并输出与所述输入信号包络的幅值相应的电压。
  3. 如权利要求2所述的包络线跟踪电源，其特征在于：
    所述线性放大器的输入级采用折叠式共源共栅电路；所述折叠式共源共栅电路由多个PMOS晶体管与NMOS晶体管叠连在一起组成，其中，第四PMOS晶体管的源极与电源电压连接，所述第四PMOS晶体管的栅极与第一偏置电压连接，所述第四PMOS晶体管的漏极分别与第五PMOS晶体管、第六PMOS晶体管的源极连接，所述第五PMOS晶体管与所述第六PMOS晶体管的栅极为输入端，用于接收所述输入信号包络，所述第五PMOS晶体管的漏极分别与第二NMOS晶体管的漏极、第四NMOS晶体管的源极连接，所述第六PMOS晶体管的漏极分别与第三NMOS晶体管的漏极、第五NMOS晶体管的源极连接，所述第二NMOS晶体管与所述第三NMOS晶体管的源极分别接地，所述第二NMOS晶体管与所述第三NMOS晶体管的栅极连接在一起后与第二偏置电压连接，所述第四NMOS晶体管与所述第五NMOS晶体管的栅极连接在一起后与第三偏置电压连接，所述第四NMOS晶体管的漏极分别与第七PMOS晶体管的漏极、第九PMOS晶体管的栅极、第十PMOS晶体管的栅极连接，所述第 五NMOS晶体管的漏极与第八PMOS晶体管的漏极连接在一起组成所述线性放大器输入级的输出端，所述第七PMOS晶体管与所述第八PMOS晶体管的栅极连接在一起，所述第七PMOS晶体管的源极与所述第九PMOS晶体管的漏极连接，所述第八PMOS晶体管的源极与所述第十PMOS晶体管的漏极连接，所述第九PMOS晶体管与第十PMOS晶体管的源极分别与所述电源电压连接。
  4. 如权利要求3所述的包络线跟踪电源，其特征在于：
    所述线性放大器的中间级采用由多个PMOS晶体管与NMOS晶体管组成的跨导级；其中，第十一PMOS晶体管与第十二PMOS晶体管的源极分别与所述电源电压连接，所述第十一PMOS晶体管的栅极与所述线性放大器的输出端连接，所述第十一PMOS晶体管的漏极与第十三PMOS晶体管的源极连接，所述第十二PMOS晶体管的栅极与所述第九PMOS晶体管的栅极连接，所述第十二PMOS晶体管的漏极与第十四PMOS晶体管的源极连接，所述第十三PMOS晶体管的栅极分别与所述第七PMOS晶体管的栅极、所述第八PMOS晶体管的栅极、所述第十四PMOS晶体管的栅极连接，所述第十三PMOS晶体管的漏极与第八NMOS晶体管的漏极，所述第十四PMOS晶体管的漏极与第六NMOS晶体管的漏极连接，所述第六NMOS晶体管的栅极与第四偏置电压连接，所述第六NMOS晶体管的源极与第七NMOS晶体管的漏极连接，所述第七NMOS晶体管与所述第八NMOS晶体管的源极接地。
  5. 如权利要求3所述的包络线跟踪电源，其特征在于：
    所述线性放大器的输出级由多个PMOS晶体管与NMOS晶体管组成；其中，第十五PMOS晶体管、第十六PMOS晶体管、第十七PMOS晶体管、第十八PMOS晶体管、第二十PMOS晶体管的源极分别与所述开关电源的第二输出端连接，所述第十五PMOS晶体管、所述第十六PMOS晶体管、所述第十七PMOS晶体管的栅极连接在一起后分别与所述第十五PMOS晶体管的漏极、第九NMOS晶体管的漏极连接，所述第九NMOS晶体管的栅极分别与第六NMOS晶体管的漏极、第七NMOS晶体管的栅极连接，所述第九NMOS晶体管、第十NMOS晶体管、第十一NMOS晶体管、第十二NMOS晶体管、第十四NMOS晶体管的源极分别接地，所述第十NMOS晶体管、所述第十一NMOS晶体管的栅极分别与第八NMOS晶体管 的栅极连接，所述第十NMOS晶体管的漏极分别与所述第十六PMOS晶体管的漏极、第十九PMOS晶体管的漏极、所述第十八PMOS晶体管的栅极、所述第二十PMOS晶体管的栅极连接，所述第十一NMOS晶体管的漏极分别与所述第十七PMOS晶体管的漏极、第十三NMOS晶体管的漏极、所述第十二NMOS晶体管的栅极、所述第十四NMOS晶体管的栅极连接，所述第十二NMOS晶体管的漏极与所述第十三NMOS晶体管的源极连接，所述第十三NMOS晶体管的栅极与第五偏置电压连接，所述第十九PMOS晶体管的源极与所述第十八PMOS晶体管的漏极连接，所述第十九PMOS晶体管的栅极与第六偏置电压连接，所述第二十PMOS晶体管的漏极与所述第十四NMOS晶体管的漏极连接；
    所述第九NMOS晶体管、所述第十五PMOS晶体管用于将所述线性放大器的跨导级输出的电流镜像到所述线性放大器的所述输出级，并通过所述开关电源的第二输出端输出的电压为所述线性放大器的输出级进行供电。
  6. 如权利要求1所述的包络线跟踪电源，其特征在于：
    所述开关电源包括控制电路与输出级；所述控制电路的输出端与所述输出级连接，所述控制电路的第一输入端接收来自所述线性调制器输出的电压，并根据所述电压产生控制信号，所述控制电路的第二输入端接收所述带宽限制的输入信号包络，所述控制电路控制所述输出级为所述线性调制器提供偏置电压，所述控制电路控制所述输出级为射频功率放大器低频功率。
  7. 如权利要求6所述的包络线跟踪电源，其特征在于：
    所述输出级包括反相器与开关级，所述反相器与所述开关级通过电感串接在一起，所述反相器的输入端与所述控制电路的输出端连接，用于放大所述控制电路输出的控制信号，并根据所述控制信号输出与所述输入信号包络的幅值相应的电流；所述开关级通过所述控制电路将流过所述电感的电流分配给第一输出端与第二输出端。
  8. 如权利要求7所述的包络线跟踪电源，其特征在于：
    所述反相器由第一PMOS晶体管与第一NMOS晶体管二者互补形式组成，所述第一PMOS晶体管的栅极与第一NMOS晶体管的栅极连接在一起组成所述反相器的输入端，所述第一PMOS晶体管的漏极与所述第 一NMOS晶体管的漏极连接在一起组成所述反相器的输出端，所述第一PMOS晶体管的源极接电源电压，所述第一NMOS晶体管的源极接地。
  9. 如权利要求7所述的包络线跟踪电源，其特征在于：
    所述开关级由两个并联在一起的开关组成，所述开关分别采用第二PMOS晶体管和第三PMOS晶体管，所述第二PMOS晶体管的源极与所述第三PMOS晶体管的源极连接在一起后与所述电感连接，所述第二PMOS晶体管的栅极与所述第三PMOS晶体管的栅极分别与所述控制电路连接，所述第二PMOS晶体管与所述第三PMOS晶体管的漏极对应与所述第一输出端与所述第二输出端连接。
  10. 如权利要求7所述的包络线跟踪电源，其特征在于：
    所述第一输出端将低频功率提供给所述射频功率放大器，并通过所述线性调制器吸收所述第一输出端的开关纹波，所述第二输出端为所述线性调制器提供一个包络因变量，用于减少所述线性调制器输出级的功率损失；
    所述第一输出端与所述第二输出端对应与输出滤波器的一端连接，所述输出滤波器由电容与电阻并联组成，所述输出滤波器的另一端接地。
  11. 如权利要求6所述的包络线跟踪电源，其特征在于：
    所述控制电路包括第一误差放大器、第二误差放大器、第一比较器、第二比较器以及三角波发生器，所述第一误差放大器与所述第二误差放大器的反向输入端分别与对应输出滤波器连接，所述第一误差放大器的正向输入端接收来自第二输出端输出的电流，所述第二误差放大器的正向输入端与所述带宽限制的输入信号包络连接，所述第一误差放大器与所述第二误差放大器的输出端对应与所述第一比较器、所述第二比较器的一个输入端连接，所述第一比较器、所述第二比较器的另一个输入端分别与所述三角波发生器连接，所述第一比较器的输出端分别与第二PMOS晶体管的栅极与第三PMOS晶体管的栅极连接，所述第二比较器的输出端与反相器的输入端连接。
  12. 一种集成电路芯片，其特征在于所述集成电路芯片中包括有权利要求1～11中任意一项所述的包络线跟踪电源。
  13. 一种通信终端，其特征在于所述通信终端中包括有权利要求 1～11中任意一项所述的包络线跟踪电源。
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