WO2018171593A1 - 移位寄存器单元、移位寄存器电路及其驱动方法、显示面板 - Google Patents

移位寄存器单元、移位寄存器电路及其驱动方法、显示面板 Download PDF

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WO2018171593A1
WO2018171593A1 PCT/CN2018/079693 CN2018079693W WO2018171593A1 WO 2018171593 A1 WO2018171593 A1 WO 2018171593A1 CN 2018079693 W CN2018079693 W CN 2018079693W WO 2018171593 A1 WO2018171593 A1 WO 2018171593A1
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WIPO (PCT)
Prior art keywords
pull
node
shift register
control
signal
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PCT/CN2018/079693
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English (en)
French (fr)
Inventor
秦文文
王珍
孙建
詹小舟
王继国
乔赟
黄飞
张寒
王争奎
丛乐乐
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/098,831 priority Critical patent/US10825397B2/en
Publication of WO2018171593A1 publication Critical patent/WO2018171593A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register circuit, a driving method thereof, and a display panel.
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the GOA technology is used to integrate the gate drive circuit into the peripheral area of the array substrate, thereby effectively improving the integration of the display device while achieving a narrow bezel design. And reduce its manufacturing costs.
  • the output of each stage of the shift register unit in the GOA circuit is coupled to a corresponding gate line for outputting a gate scan signal to the gate line for implementing a progressive scan function.
  • the switching element of the shift register unit usually uses a thin film transistor (TFT), and the TFT itself has characteristics of leakage current and parasitic capacitance, the shift register circuit often has various defects, resulting in display abnormality.
  • TFT thin film transistor
  • a shift register unit comprising:
  • a first input module configured to transmit the first voltage signal to the pull-up node under the control of the first input signal
  • a pull-up module configured to transmit the first clock signal to the signal output end under the control of the voltage signal of the pull-up node
  • a first pull-down control module configured to transmit the second clock signal to the pull-down node under control of the second clock signal
  • a second pull-down control module configured to transmit a second voltage signal to the pull-down node under control of a voltage signal of the pull-up node
  • a pull-up control module configured to transmit the second voltage signal to the pull-up node under control of a voltage signal of the pull-down node
  • a pull-down module configured to transmit the second voltage signal to the signal output end under the control of a voltage signal of the pull-down node
  • a hold module for maintaining the pull-up node low and/or maintaining the pull-down node high under the control of the second input signal.
  • a shift register circuit comprising a plurality of cascaded shift register units as described above;
  • the output signal of the signal output end of the M-th stage shift register unit is the first input signal of the M+1-stage shift register unit.
  • a display panel including a display area and a peripheral area; wherein the peripheral area is provided with the shift register circuit described above.
  • a driving method of a shift register circuit for driving the shift register circuit described above includes:
  • the second input signal is used to control the pull-up node to remain low and/or to control the pull-down node to remain high.
  • 1 is a schematic structural view showing a shift register unit in the related art
  • FIG. 2 is a view schematically showing an operation timing chart of a shift register unit in the related art
  • FIG. 3 is a schematic block diagram showing a structure of a shift register unit in an exemplary embodiment of the present disclosure
  • FIG. 4 is a view schematically showing an operation timing chart of a shift register unit in an exemplary embodiment of the present disclosure
  • FIG. 5 schematically shows a cascade structure diagram of a shift register circuit in an exemplary embodiment of the present disclosure.
  • FIG. 1 and 2 illustrate a shift register unit and its operation timing diagram in the related art.
  • the pull-up node PU When the pull-up node PU is at a high level, the sixth transistor T6 is turned on to pull the level of the pull-down node PD low.
  • the fifth transistor T5 When the pull-down node PD is at a high level, the fifth transistor T5 is turned on to pull the level of the pull-up node PU low. In one frame time, the pull-down node PD remains high for most of the time, and the pull-up node PU remains low for most of the time.
  • the first clock signal CK and the second clock signal CKB are both low, and the pull-down node PD can only rely on the second capacitor C2.
  • the level of the pull-down node PD will be lowered, and the level of the pull-up node PU cannot be completely pulled down.
  • the first clock signal CK and the pull-up node PU are connected to the gate and the source of the same transistor, the parasitic capacitance between the two is large, so at the beginning of the next frame, the pull-up node PU will be coupled.
  • the waveform of a clock signal CK causes the third transistor T3 to be abnormally turned on, resulting in display abnormality.
  • the present example embodiment provides a shift register unit for providing a gate scan signal; as shown in FIG. 3, the shift register unit may include:
  • the first input module 101 is configured to transmit the first voltage signal CN to the pull-up node PU under the control of the first input signal Input1;
  • the pull-up module 20 is configured to transmit the first clock signal CK to the signal output terminal Output under the control of the voltage signal of the pull-up node PU;
  • the first pull-down control module 301 is configured to transmit the second clock signal CKB to the pull-down node PD under the control of the second clock signal CKB;
  • the second pull-down control module 302 is configured to transmit the second voltage signal VGL to the pull-down node PD under the control of the voltage signal of the pull-up node PU;
  • a third pull-down mode control block 303 for transmitting the second voltage signal VGL to the pull-down node PD under the control of the voltage signal of the signal output terminal Output;
  • Pull-up control module 40 for transmitting the second voltage signal VGL to the pull-up node PU under the control of the voltage signal of the pull-down node PD;
  • the pull-down module 50 is configured to transmit the second voltage signal VGL to the signal output terminal Output under the control of the voltage signal of the pull-down node PD;
  • the holding module 60 is configured to keep the pull-up node PU low and/or keep the pull-down node PD at a high level under the control of the second input signal Input2.
  • the shift register unit provided by the exemplary embodiment of the present disclosure adds a holding module 60 based on the structure of the conventional shift register unit, and can output a high level signal after the shift register unit of the last stage of each frame of the screen During the V-blank time, the second input signal Input2 is used to maintain the low state of the pull-up node PU and/or the high state of the pull-down node PD is maintained, thereby preventing abnormal output of the scan signal and avoiding the resulting display. bad.
  • the holding module 60 may specifically include a first holding unit and/or a second holding unit; wherein the first holding unit is configured to transmit the second voltage signal VGL under the control of the second input signal Input2 The node PU is pulled up to keep it low; the second holding unit is configured to transmit the second input signal Input2 to the pull-down node PD under the control of the second input signal Input2 to keep it high.
  • the holding module 60 may only include the first holding unit to keep the pull-up node PU in a low state; or the holding module 60 may only include the second holding unit to enable the pull-down node.
  • the PD remains in a high state, and then the second voltage signal VGL is transmitted to the pull-up node PU through the pull-up control module 40 to maintain the low state; of course, the holding module 60 can also include the first holding unit and The second holding unit simultaneously plays a limiting role on the pull-up node PU and the pull-down node PD. Therefore, the purpose of the present embodiment is to prevent the abnormal output of the scan signal.
  • the holding module 60 can be provided with one holding unit or multiple holding units. Specifically limited.
  • the shift register unit may further include: a second input module 102, configured to transmit the third voltage signal CNB to the pull-up node PU under the control of the third input signal Input3 .
  • the first voltage signal CN and the third voltage signal CNB are mutually opposite signals; that is, the first voltage signal CN is a high level signal, and the third voltage signal CNB is a low level signal; the first voltage signal CN is The low level signal and the third voltage signal CNB are high level signals.
  • both the first input module 101 and the second input module 102 function to transmit the input signal to the pull-up node PU, the only difference being the difference of the input signals.
  • the effect of controlling the scanning order can be achieved. Specifically, if the first voltage signal CN is at a high level and the third voltage signal CNB is at a low level, the scanning sequence is a positive sweep; conversely, if the first voltage signal CN is at a low level, the third voltage signal CNB When it is high, the scan order is reverse sweep.
  • one of the first input module 101 and the second input module 102 can serve as a trigger module, and the other can function as a reset module.
  • the shift register unit in the present exemplary embodiment will be described in detail below with reference to FIGS. 3 and 4.
  • the first input module 101 may include: a first switching element, the control end thereof receives the first input signal Input1, the first end receives the first voltage signal CN, and the second end is connected to the pull-up node PU.
  • the second input module 102 can include: an eighth switching component, the control terminal thereof receives the third input signal Input3, the first terminal receives the third voltage signal CNB, and the second terminal is coupled to the pull-up node PU.
  • the pull-up module 20 may include: a second switching component, the control end of which is connected to the pull-up node PU, the first end receives the first clock signal CK, the second end is connected to the signal output terminal Output; and the first capacitor C1 has a first end The pull-up node PU is connected, and the second end is connected to the signal output terminal Output.
  • the first pull-down control module 301 can include: a third switching component, the control terminal thereof receives the second clock signal CKB, the first terminal receives the second clock signal CKB, and the second terminal is coupled to the pull-down node PD.
  • the second pull-down control module 302 can include a fourth switching component, the control end of which is coupled to the pull-up node PU, the first terminal receives the second voltage signal VGL, and the second terminal is coupled to the pull-down node PD.
  • the third pull-down control module 303 may include: a fifth switching component whose control terminal is connected to the signal output terminal Output, the first terminal receives the second voltage signal VGL, and the second terminal is connected to the pull-down node PD.
  • the pull-up control module 40 may include: a sixth switching element, the control end of which is connected to the pull-down node PD, the first end receives the second voltage signal VGL, and the second end is connected to the pull-up node PU.
  • the pull-down module 50 may include: a seventh switching component, the control terminal is connected to the pull-down node PD, the first terminal receives the second voltage signal VGL, the second terminal is connected to the signal output terminal Output; and the second capacitor C2 is connected to the first terminal The node PD receives the second voltage signal VGL.
  • the retention module 60 can include a first retention unit and/or a second retention unit.
  • the first holding unit may include: a ninth switching element, the control end receives the second input signal Input2, the first end receives the second voltage signal VGL, and the second end is connected to the pull-up node PD;
  • the second holding unit may include:
  • the tenth switching element has a control end receiving the second input signal Input2, the first end receiving the second input signal Input2, and the second end being connected to the pull-down node PD.
  • all of the switching elements may be MOS transistors (Metal Oxide Semiconductor), and they may all be P-type MOS transistors or N-type MOS transistors. It should be noted that for different transistor types, the level signals of the respective signal terminals need corresponding adjustment changes.
  • the first voltage signal CN is a high level signal
  • the second voltage signal VGL is a DC low level signal
  • the third voltage signal CNB is a low level signal.
  • the working process of the shift register circuit may include the following stages:
  • the first stage t1 the first input signal Input1 is at a high level, and the first transistor T1 is turned on to transmit the first voltage signal CN to the pull-up node PU and charge the first capacitor C1, and the pull-up node PU is at a high level.
  • the fourth transistor T4 is turned on to pull the level of the pull-down node PD by the second voltage signal VGL under the high level of the pull-up node PU, and the sixth transistor T6 and the seventh transistor T7 are turned off; the first clock The signal CK is at a high level.
  • the second transistor T2 Under the high level of the pull-up node PU, the second transistor T2 is turned on to transmit the first clock signal CK to the signal output terminal Output, and at this time, a high level signal is output; Under the high level of the terminal Output, the fifth transistor T5 is turned on to pull down the level of the pull-down node PD by using the second voltage signal VGL.
  • the second stage t2 the first input signal Input1 is at a low level, and the first transistor T1 is turned off. At this time, the first capacitor C1 discharge keeps the pull-up node PU at a high level; the second clock signal CKB is at a high level, and the third The transistor T3 is turned on to transfer the second clock signal CKB to the pull-down node PD and charge the second capacitor C2, and the pull-down node PD is at a high level; under the high level of the pull-down node PD, the sixth transistor T6 is turned on.
  • the second transistor T2 and the fourth transistor T4 are turned off; meanwhile, the seventh transistor T7 is turned on, and the second voltage signal VGL is used to pull down the signal output terminal Output. Level.
  • the third stage t3 the first input signal Input1 is at a low level, the first transistor T1 is turned off; the second capacitor C2 is discharged to keep the pull-down node PD at a high level, and the sixth transistor T6 is turned on to continue to pull down the pull-up node PU Level, the second transistor T2 and the fourth transistor T4 are turned off, while the seventh transistor T7 is turned on to continue to pull down the signal output terminal
  • the level of Output, the fifth transistor T5 is turned off.
  • the fourth stage t4 the first input signal Input1 is at a low level, the first transistor T1 is turned off; the second clock signal CKB is at a high level, and the third transistor T3 is turned on to transmit the second clock signal CKB to the pull-down node PD and
  • the pull-down node PD is at a high level; under the high level of the pull-down node PD, the sixth transistor T6 is turned on to pull down the level of the pull-up node PU by using the second voltage signal VGL.
  • the second transistor T2 and the fourth transistor T4 are turned off; at the same time, the seventh transistor T7 is turned on, and the level of the signal output terminal Output is pulled down by the second voltage signal VGL.
  • the nth stage tn the first input signal Input1 is at a low level, and the first clock signal CK and the second clock signal CKB are both at a low level, that is, at V Blank (the first line is returned from the last line after each frame scan ends). Time); at this time, the second input signal Input2 is at a high level, the ninth transistor T9 and the tenth transistor T10 are turned on, and the second voltage signal VGL is transmitted to the pull-up node PU through the ninth transistor T9 to keep it low. In the level state, the second input signal Input2 is transmitted to the pull-down node PD through the tenth transistor T10 to maintain it in a high state.
  • the shift register units of the stages repeat the above-mentioned third stage t3 and the fourth stage t4 according to actual conditions until the signal of the last stage shift register unit.
  • the output terminal outputs a high level signal.
  • the holding module 60 starts to work in the V-blank time after the shift register unit outputs the high level signal in the last stage of each frame, and the second input signal Input2 holds the pull-up node PU.
  • the low state and the high state of the pull-down node PD are maintained, thereby preventing the second transistor T2 from being abnormally turned on and causing an abnormal output of the scan signal.
  • the example embodiment further provides a shift register circuit for use as a gate driving circuit; as shown in FIG. 5, the shift register circuit may include a plurality of cascaded shift register units; wherein, the Mth The output signal of the signal output terminal Output of the stage shift register unit is the first input signal Input1 of the M+1th stage shift register unit.
  • the scanning mode of the shift register circuit may include forward scanning or reverse scanning.
  • the first voltage signal CN may be a high level
  • the third voltage signal CNB may be a low level
  • the first input signal Input1 of the first stage shift register unit is a start signal.
  • the first voltage signal CN may be a low level
  • the third voltage signal CNB may be a high level
  • the third input signal Input3 of the last stage shift register unit is a start signal.
  • the present exemplary embodiment also proposes a display panel including a display area and a peripheral area, and the above-described shift register circuit is provided in the peripheral area.
  • the present embodiment utilizes the GOA technology to integrate the shift register circuit on the periphery of the display panel, thereby realizing the design of the narrow bezel panel and reducing the manufacturing cost of the display panel.
  • the display panel may be an LCD display panel, an OLED display panel, a PLED (Polymer Light-Emitting Diode) display panel, a PDP (Plasma Display Panel), or the like. Applicable without specific restrictions.
  • the example embodiment also provides a display device including the above display panel.
  • the display device may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.
  • modules or units of equipment for action execution are mentioned in the detailed description above, such division is not mandatory. Indeed, in accordance with embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one of the modules or units described above may be further divided into multiple modules or units.
  • the technical solution according to an embodiment of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network.
  • a non-volatile storage medium which may be a CD-ROM, a USB flash drive, a mobile hard disk, etc.
  • a number of instructions are included to cause a computing device (which may be a personal computer, server, mobile terminal, or network device, etc.) to perform a method in accordance with an embodiment of the present disclosure.

Abstract

一种移位寄存器单元、移位寄存器电路及其驱动方法、显示面板。该移位寄存器单元包括：第一输入模块（101），在第一输入信号（Input1）的控制下将第一电压信号（CN）传输至上拉节点（PU）；上拉模块（20），在上拉节点（PU）的控制下将第一时钟信号（CK）传输至信号输出端（Output）；第一下拉控制模块（301），在第二时钟信号（CKB）的控制下将第二时钟信号（CKB）传输至下拉节点（PD）；第二下拉控制模块（302），在上拉节点（PU）的控制下将第二电压信号（VGL）传输至下拉节点（PD）；上拉控制模块（40），在下拉节点（PD）的控制下将第二电压信号（VGL）传输至上拉节点（PU）；下拉模块（50），在下拉节点（PD）的控制下将第二电压信号（VGL）传输至信号输出端（Output）；保持模块（60），在第二输入信号（Input2）的控制下保持上拉节点（PU）为低电平和/或保持下拉节点（PD）为高电平。上述移位寄存器单元、移位寄存器电路及其驱动方法、显示面板可避免扫描信号的异常输出而导致的不良。

Description

移位寄存器单元、移位寄存器电路及其驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、移位寄存器电路及其驱动方法、显示面板。
背景技术
随着光学技术和半导体技术的发展，以液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管显示器(Organic Light Emitting Diode，OLED)为代表的平板显示器具有轻薄、能耗低、反应速度快、色纯度佳、以及对比度高等特点，在显示领域占据了主导地位。
近些年来显示装置呈现出了高集成度以及低成本的发展趋势。以阵列基板行驱动(Gate Driver on Array，GOA)技术为代表，利用GOA技术将栅极驱动电路集成于阵列基板的周边区域，从而在实现窄边框设计的同时，有效提高显示装置的集成度，并降低其制造成本。GOA电路中的每一级移位寄存器单元的输出端与一对应的栅线相连，用于向该栅线输出栅极扫描信号，以实现逐行扫描功能。但是，由于移位寄存器单元的开关元件通常采用薄膜晶体管(Thin Film Transistor，TFT)，而TFT自身存在漏电电流以及寄生电容的特性，因此移位寄存器电路常会出现各种不良，从而导致显示异常。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种移位寄存器单元、移位寄存器电路及其驱动方法、显示面板，进而至少在一定程度上克服由于相关技术的限制和缺陷而导致的一个或者多个问题。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的一个方面，提供一种移位寄存器单元，包括：
第一输入模块，用于在第一输入信号的控制下将第一电压信号传输至上拉节点；
上拉模块，用于在所述上拉节点的电压信号的控制下将第一时钟信号传输至信号输出端；
第一下拉控制模块，用于在第二时钟信号的控制下将所述第二时钟信号传输至下拉 节点；
第二下拉控制模块，用于在所述上拉节点的电压信号的控制下将第二电压信号传输至所述下拉节点；
上拉控制模块，用于在所述下拉节点的电压信号的控制下将所述第二电压信号传输至所述上拉节点；
下拉模块，用于在所述下拉节点的电压信号的控制下将所述第二电压信号传输至所述信号输出端；
保持模块，用于在第二输入信号的控制下保持所述上拉节点为低电平和/或保持所述下拉节点为高电平。
根据本公开的另一个方面，提供一种移位寄存器电路，包括多个级联的上述的移位寄存器单元；
其中，第M级移位寄存器单元的信号输出端的输出信号为第M+1级移位寄存器单元的第一输入信号。
根据本公开的再一个方面，提供一种显示面板，包括显示区域和周边区域；其中，所述周边区域设置有上述的移位寄存器电路。
根据本公开的又一个方面，提供一种移位寄存器电路的驱动方法，用于驱动上述的移位寄存器电路；所述驱动方法包括：
在每个帧周期最后一级移位寄存器单元的信号输出端输出高电平之后，利用第二输入信号控制上拉节点保持低电平和/或控制下拉节点保持高电平。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性示出相关技术中移位寄存器单元的结构示意图；
图2示意性示出相关技术中移位寄存器单元的工作时序图；
图3示意性示出本公开示例性实施例中移位寄存器单元的结构示意图；
图4示意性示出本公开示例性实施例中移位寄存器单元的工作时序图；
图5示意性示出本公开示例性实施例中移位寄存器电路的级联结构图。
附图标记：
T1-T10第一晶体管至第十晶体管
C1第一电容
C2第二电容
Input1第一输入信号
Input2第二输入信号
Input3第三输入信号
Output信号输出端
PU上拉节点
PD下拉节点
CK第一时钟信号
CKB第二时钟信号
CN第一电压信号
VGL第二电压信号
CNB第三电压信号
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。
此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
图1和图2示出了相关技术中的移位寄存器单元及其工作时序图，当上拉节点PU为高电平时，第六晶体管T6导通以将下拉节点PD的电平拉低，当下拉节点PD为高电平时，第五晶体管T5导通以将上拉节点PU的电平拉低。而在一帧时间内，下拉节点PD大部分时间保持高电平，上拉节点PU大部分时间保持低电平。在V Blank(每帧扫描结束后从最后一行返回第一行的时间)时间内，第一时钟信号CK和第二时钟信号CKB均为低电平，则下拉节点PD只能依靠第二电容C2保持高电平，当漏电流较大时，下拉节点PD的电平便会降低，此时上拉节点PU的电平便无法被完全拉低。这样一来，由于第一时钟信号CK和上拉节点PU连接同一晶体管的栅极和源极，二者之间的寄生电容较大，因此在 下一帧开始时，上拉节点PU便会耦合第一时钟信号CK的波形，使得第三晶体管T3异常打开，从而导致显示异常。
本示例实施方式提出了一种移位寄存器单元，用于提供栅极扫描信号；如图3所示，所述移位寄存器单元可以包括：
第一输入模块101，用于在第一输入信号Input1的控制下将第一电压信号CN传输至上拉节点PU；
上拉模块20，用于在上拉节点PU的电压信号的控制下将第一时钟信号CK传输至信号输出端Output；
第一下拉控制模块301，用于在第二时钟信号CKB的控制下将第二时钟信号CKB传输至下拉节点PD；
第二下拉控制模块302，用于在上拉节点PU的电压信号的控制下将第二电压信号VGL传输至下拉节点PD；
第三下拉模控制块303，用于在信号输出端Output的电压信号的控制下将第二电压信号VGL传输至下拉节点PD；
上拉控制模块40，用于在下拉节点PD的电压信号的控制下将第二电压信号VGL传输至上拉节点PU；
下拉模块50，用于在下拉节点PD的电压信号的控制下将第二电压信号VGL传输至信号输出端Output；
保持模块60，用于在第二输入信号Input2的控制下保持上拉节点PU为低电平和/或保持下拉节点PD为高电平。
本公开示例性实施方式所提供的移位寄存器单元，在传统移位寄存器单元结构的基础上增加了一保持模块60，可在每帧画面的最后一级移位寄存器单元输出高电平信号之后的V-blank时间内，利用第二输入信号Input2保持上拉节点PU的低电平状态和/或保持下拉节点PD的高电平状态，从而防止扫描信号的异常输出，避免由此产生的显示不良。
本示例实施方式中，所述保持模块60具体可以包括第一保持单元和/或第二保持单元；其中，第一保持单元用于在第二输入信号Input2的控制下将第二电压信号VGL传输至上拉节点PU以使其保持低电平；第二保持单元用于在第二输入信号Input2的控制下将第二输入信号Input2传输至下拉节点PD以使其保持高电平。
需要说明的是：所述保持模块60可以只包括第一保持单元，以使上拉节点PU保持低电平状态；或者，所述保持模块60也可以只包括第二保持单元，以使下拉节点PD保持高电平状态，再通过上拉控制模块40将第二电压信号VGL传输至上拉节点PU，使其 保持低电平状态；当然，所述保持模块60还可以同时包括第一保持单元和第二保持单元，以对上拉节点PU和下拉节点PD同时起到限制作用。由此可知，本示例实施方式设置所述保持模块60的目的在于防止扫描信号的异常输出，只要能够达到上述效果，所述保持模块60设置一个保持单元或者多个保持单元均可，这里不做具体限定。
本示例实施方式中，参考图3所示，所述移位寄存器单元还可以包括：第二输入模块102，用于在第三输入信号Input3的控制下将第三电压信号CNB传输至上拉节点PU。
其中，第一电压信号CN与第三电压信号CNB互为相反的信号；即，第一电压信号CN为高电平信号，第三电压信号CNB则为低电平信号；第一电压信号CN为低电平信号，第三电压信号CNB则为高电平信号。
基于此，第一输入模块101和第二输入模块102的作用均是将输入信号传输至上拉节点PU，其区别仅在于输入信号的差异。这样一来，通过控制第一电压信号CN和第三电压信号CNB的电平状态、以及起始信号脉冲，即可达到控制扫描顺序的效果。具体而言，若第一电压信号CN为高电平，第三电压信号CNB为低电平，则扫描顺序为正扫；反之，若第一电压信号CN为低电平，第三电压信号CNB为高电平，则扫描顺序为反扫。在此基础上，一旦确定了扫描顺序，第一输入模块101和第二输入模块102中的一个可以作为触发模块，另一个可以作为复位模块。
下面结合图3和图4对本示例实施方式中的移位寄存器单元进行详细的说明。
第一输入模块101可以包括：第一开关元件，其控制端接收第一输入信号Input1，第一端接收第一电压信号CN，第二端连接上拉节点PU。
第二输入模块102可以包括：第八开关元件，其控制端接收第三输入信号Input3，第一端接收第三电压信号CNB，第二端连接上拉节点PU。
上拉模块20可以包括：第二开关元件，其控制端连接上拉节点PU，第一端接收第一时钟信号CK，第二端连接信号输出端Output；以及第一电容C1，其第一端连接上拉节点PU，第二端连接信号输出端Output。
第一下拉控制模块301可以包括：第三开关元件，其控制端接收第二时钟信号CKB，第一端接收第二时钟信号CKB，第二端连接下拉节点PD。
第二下拉控制模块302可以包括：第四开关元件，其控制端连接上拉节点PU，第一端接收第二电压信号VGL，第二端连接下拉节点PD。
第三下拉控制模块303可以包括：第五开关元件，其控制端连接信号输出端Output，第一端接收第二电压信号VGL，第二端连接下拉节点PD。
上拉控制模块40可以包括：第六开关元件，其控制端连接下拉节点PD，第一端接收第二电压信号VGL，第二端连接上拉节点PU。
下拉模块50可以包括：第七开关元件，其控制端连接下拉节点PD，第一端接收第二电压信号VGL，第二端连接信号输出端Output；以及第二电容C2，其第一端连接下拉节点PD，第二端接收第二电压信号VGL。
保持模块60可以包括：第一保持单元和/或第二保持单元。其中，第一保持单元可以包括：第九开关元件，其控制端接收第二输入信号Input2，第一端接收第二电压信号VGL，第二端连接上拉节点PD；第二保持单元可以包括：第十开关元件，其控制端接收第二输入信号Input2，第一端接收第二输入信号Input2，第二端连接下拉节点PD。
在本示例实施方式中，所有开关元件可以采用MOS管(Metal Oxide Semiconductor，金属-氧化物-半导体场效应晶体)，其具体可以均采用P型MOS管或者均采用N型MOS管。需要说明的是：针对不同的晶体管类型，各个信号端的电平信号需要相应的调整变化。
下面以所有开关元件均为NMOS为例，结合图4所示的工作时序图对本实施例中的移位寄存器单元的工作原理进行具体的说明。其中，第一电压信号CN为高电平信号，第二电压信号VGL为直流低电平信号，第三电压信号CNB为低电平信号。
所述移位寄存器电路的工作过程可以包括以下阶段：
第一阶段t1：第一输入信号Input1为高电平，第一晶体管T1导通以将第一电压信号CN传输至上拉节点PU并对第一电容C1充电，则上拉节点PU为高电平；在上拉节点PU的高电平作用下，第四晶体管T4导通以利用第二电压信号VGL拉低下拉节点PD的电平，则第六晶体管T6和第七晶体管T7关闭；第一时钟信号CK为高电平，在上拉节点PU的高电平作用下，第二晶体管T2导通以将第一时钟信号CK传输至信号输出端Output，此时输出高电平信号；在信号输出端Output的高电平作用下，第五晶体管T5导通以利用第二电压信号VGL拉低下拉节点PD的电平。
第二阶段t2：第一输入信号Input1为低电平，第一晶体管T1关闭，此时第一电容C1放电保持上拉节点PU为高电平；第二时钟信号CKB为高电平，第三晶体管T3导通以将第二时钟信号CKB传输至下拉节点PD并对第二电容C2充电，则下拉节点PD为高电平；在下拉节点PD的高电平作用下，第六晶体管T6导通以利用第二电压信号VGL拉低上拉节点PU的电平，则第二晶体管T2和第四晶体管T4关闭；同时第七晶体管T7导通，利用第二电压信号VGL拉低信号输出端Output的电平。
第三阶段t3：第一输入信号Input1为低电平，第一晶体管T1关闭；第二电容C2放电保持下拉节点PD为高电平，第六晶体管T6导通以继续拉低上拉节点PU的电平，第二晶体管T2和第四晶体管T4关闭，同时第七晶体管T7导通以继续拉低信号输出端
Output的电平，第五晶体管T5关闭。
第四阶段t4：第一输入信号Input1为低电平，第一晶体管T1关闭；第二时钟信号CKB为高电平，第三晶体管T3导通以将第二时钟信号CKB传输至下拉节点PD并对第二电容C2充电，则下拉节点PD为高电平；在下拉节点PD的高电平作用下，第六晶体管T6导通以利用第二电压信号VGL拉低上拉节点PU的电平，则第二晶体管T2和第四晶体管T4关闭；同时第七晶体管T7导通，利用第二电压信号VGL拉低信号输出端Output的电平。
……
第n阶段tn：第一输入信号Input1为低电平，第一时钟信号CK和第二时钟信号CKB均为低电平，即处于V Blank(每帧扫描结束后从最后一行返回第一行的时间)时间段；此时，第二输入信号Input2为高电平，第九晶体管T9和第十晶体管T10导通，第二电压信号VGL通过第九晶体管T9传输至上拉节点PU以使其保持低电平状态，第二输入信号Input2通过第十晶体管T10传输至下拉节点PD以使其保持高电平状态。
需要说明的是，在上述第四阶段t4至第n阶段tn之间，各级移位寄存器单元根据实际情况重复上述第三阶段t3和第四阶段t4，直至最后一级移位寄存器单元的信号输出端Output输出高电平信号。
基于上述过程可知，在每帧画面的最后一级移位寄存器单元输出高电平信号之后的V-blank时间内，保持模块60即开始工作，其利用第二输入信号Input2保持上拉节点PU的低电平状态以及保持下拉节点PD的高电平状态，从而防止第二晶体管T2异常开启而导致扫描信号的异常输出。
本示例实施方式还提出了一种移位寄存器电路，用作栅极驱动电路；如图5所示，所述移位寄存器电路可以包括多个级联的上述移位寄存器单元；其中，第M级移位寄存器单元的信号输出端Output的输出信号为第M+1级移位寄存器单元的第一输入信号Input1。
在此基础上，所述移位寄存器电路的扫描方式可以包括正向扫描或者反向扫描。
当采用正向扫描时，第一电压信号CN可以为高电平，第三电压信号CNB可以为低电平，此时第一级移位寄存器单元的第一输入信号Input1为起始信号。
当采用反向扫描时，第一电压信号CN可以为低电平，第三电压信号CNB可以为高电平，此时最后一级移位寄存器单元的第三输入信号Input3为起始信号。
需要说明的是，所述移位寄存器电路中的各模块单元的具体细节已经在对应的移位寄存器单元中进行了详细的描述，这里不再赘述。
本示例实施方式还提出了一种显示面板，包括显示区域和周边区域，且在周边区域设置有上述的移位寄存器电路。
基于此可知，本实施例利用GOA技术将移位寄存器电路集成于显示面板的周边，从而实现窄边框面板的设计，同时还可降低显示面板的制造成本。
其中，所述显示面板具体可以为LCD显示面板、OLED显示面板、PLED(Polymer Light-Emitting Diode，高分子发光二极管)显示面板、PDP(Plasma Display Panel，等离子显示面板)等，这里对于显示面板的适用不做具体的限制。
本示例实施方式还提供一种显示装置，包括上述的显示面板。其中，所述显示装置例如可以包括手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
此外，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本公开实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、移动终端、或者网络设备等)执行根据本公开实施方式的方法。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (15)

  1. 一种移位寄存器单元，其中，包括：
    第一输入模块，用于在第一输入信号的控制下将第一电压信号传输至上拉节点；
    上拉模块，用于在所述上拉节点的电压信号的控制下将第一时钟信号传输至信号输出端；
    第一下拉控制模块，用于在第二时钟信号的控制下将所述第二时钟信号传输至下拉节点；
    第二下拉控制模块，用于在所述上拉节点的电压信号的控制下将第二电压信号传输至所述下拉节点；
    上拉控制模块，用于在所述下拉节点的电压信号的控制下将所述第二电压信号传输至所述上拉节点；
    下拉模块，用于在所述下拉节点的电压信号的控制下将所述第二电压信号传输至所述信号输出端；
    保持模块，用于在第二输入信号的控制下保持所述上拉节点为低电平和/或保持所述下拉节点为高电平。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述保持模块包括第一保持单元和/或第二保持单元；
    所述第一保持单元，用于在所述第二输入信号的控制下将所述第二电压信号传输至所述上拉节点；
    所述第二保持单元，用于在所述第二输入信号的控制下将所述第二输入信号传输至所述下拉节点。
  3. 根据权利要求1所述的移位寄存器单元，其中，还包括：
    第三下拉控制模块，用于在所述信号输出端的电压信号的控制下将所述第二电压信号传输至所述下拉节点。
  4. 根据权利要求1所述的移位寄存器单元，其中，还包括：
    第二输入模块，用于在第三输入信号的控制下将第三电压信号传输至所述上拉节点。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述第一输入模块包括：
    第一开关元件，其控制端接收所述第一输入信号，第一端接收所述第一电压信号，第二端连接所述上拉节点。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述上拉模块包括：
    第二开关元件，其控制端连接所述上拉节点，第一端接收所述第一时钟信号，第二端连接所述信号输出端；
    第一电容，其第一端连接所述上拉节点，第二端连接所述信号输出端。
  7. 根据权利要求3所述的移位寄存器单元，其中，所述第一下拉控制模块包括：
    第三开关元件，其控制端接收所述第二时钟信号，第一端接收所述第二时钟信号，第二端连接所述下拉节点；
    所述第二下拉控制模块包括：
    第四开关元件，其控制端连接所述上拉节点，第一端接收所述第二电压信号，第二端连接所述下拉节点；
    所述第三下拉控制模块包括：
    第五开关元件，其控制端连接所述信号输出端，第一端接收所述第二电压信号，第二端连接所述下拉节点。
  8. 根据权利要求1所述的移位寄存器单元，其中，所述上拉控制模块包括：
    第六开关元件，其控制端连接所述下拉节点，第一端接收所述第二电压信号，第二端连接所述上拉节点。
  9. 根据权利要求1所述的移位寄存器单元，其中，所述下拉模块包括：
    第七开关元件，其控制端连接所述下拉节点，第一端接收所述第二电压信号，第二端连接所述信号输出端；
    第二电容，其第一端连接所述下拉节点，第二端接收所述第二电压信号。
  10. 根据权利要求4所述的移位寄存器单元，其中，所述第二输入模块包括：
    第八开关元件，其控制端接收所述第三输入信号，第一端接收所述第三电压信号，第二端连接所述上拉节点。
  11. 根据权利要求2所述的移位寄存器单元，其中，所述第一保持单元包括：
    第九开关元件，其控制端接收所述第二输入信号，第一端接收所述第二电压信号，第二端连接所述上拉节点；
    所述第二保持单元包括：
    第十开关元件，其控制端接收所述第二输入信号，第一端接收所述第二输入信号，第二端连接所述下拉节点。
  12. 一种移位寄存器电路，其中，包括多个级联的权利要求1-11任一项所述的移位寄存器单元；
    其中，第M级移位寄存器单元的信号输出端的输出信号为第M+1级移位寄存 器单元的第一输入信号。
  13. 根据权利要求12所述的移位寄存器电路，其中，所述移位寄存器电路的扫描方式包括正向扫描或者反向扫描；
    正向扫描时，第一电压信号为高电平，第三电压信号为低电平；
    反向扫描时，第一电压信号为低电平，第三电压信号为高电平。
  14. 一种显示面板，其中，包括显示区域和周边区域；其中，所述周边区域设置有权利要求12或13所述的移位寄存器电路。
  15. 一种移位寄存器电路的驱动方法，用于驱动权利要求12或13所述的移位寄存器电路；其中，所述驱动方法包括：
    在每个帧周期最后一级移位寄存器单元的信号输出端输出高电平之后，利用第二输入信号控制上拉节点保持低电平和/或控制下拉节点保持高电平。
PCT/CN2018/079693 2017-03-22 2018-03-21 移位寄存器单元、移位寄存器电路及其驱动方法、显示面板 WO2018171593A1 (zh)

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